JP4175927B2 - Data processing apparatus, trace signal generation method, and trace signal generation program - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
(Background of the Invention)
The present invention relates to the generation of trace signals in a data processing apparatus having one or more components that track its behavior.
[0002]
[Prior art]
Tracking the movement of a data processing system and thereby generating a trace stream containing data representing the movement in the system step by step is a very useful tool in developing the system. However, since processing instructions tend to be embedded in the processor core in a complicated manner, it is extremely difficult to track the state of the processor core via a terminal accessible from the outside. Accordingly, not only the off-chip trace mechanism for collecting and analyzing the trace data but also more trace mechanisms are provided in the chip. An example of such an on-chip trace mechanism is the Embedded Trace Macrocell (ETM) provided by ARM, Cambridge, UK, for various ARM processors.
[0003]
Such a trace mechanism generates in real time a trace stream of data representing what the data processor is attempting to trace its movement. This trace stream is then used to enable debugging of the sequence of processing instructions executed by the data processing device.
[0004]
A trace mechanism is provided that incorporates a trigger point that is used to control trace operations that start and stop tracing due to access to a specific register, address, or data value. That is well known. Such a mechanism can be very useful in diagnosing certain parts of the system and certain types of movement.
[0005]
[Problems to be solved by the invention]
However, as data processing systems continue to increase in complexity, it is clear that there is potentially a very large amount of information to be traced. The stream of trace data generated by the ETM is usually stored temporarily prior to output for later processing, but this may cause the buffer to overflow with trace data, resulting in Trace data may be lost. For example, in a typical implementation, all ETM generated trace data is immediately written to an internal first-in first-out (FIFO) buffer and then transferred to the trace buffer via a relatively narrow bandwidth trace port. The When tracing a wide range of movement of the data processing apparatus, the FIFO overflows due to explosive generation of trace data, which may lead to loss of trace data.
[0006]
One known way to solve this problem is to configure the ETM to output a signal to the component whose operation is tracked when the FIFO occupancy reaches a predetermined level. Yes, this signal stops the component so that the contents of the FIFO can be eliminated before an overflow occurs. However, in order to avoid FIFO overflow, it is necessary to perform a search operation on the ETM from the outside (that is, depending on the component to be tracked). It turns out to be difficult. Since there is an inherent delay time between the ETM that generates such a signal and the signal generated by the component to be traced, such as a processor core, during this delay time, It can be seen that continuing to track other operations of the component will cause the FIFO to overflow anyway.
[0007]
In view of the foregoing, it would be desirable to provide a more improved method to reduce the possibility of trace data loss.
[0008]
[Means for Solving the Invention]
    (Summary of Invention)
  In a first aspect, the present invention receives a component whose operation is tracked and an input signal from the element indicating the operation, and receives a high priority from the input signal.Trace signalAnd generates a low-priority trace signal by generating a low-priority trace signal and outputting it to the trace receiver, and issuing a suppression signal from the trace receiver (assert "assert") The present invention provides a data processing apparatus including a trace generation unit that suppresses noise.
[0009]
According to the present invention, the trace signal generated by the trace generation unit is classified as being either a high priority trace signal or a low priority trace signal. The trace signal generated by the trace generation unit becomes an output to the trace reception device, and the trace generation unit receives the suppression signal from the trace reception device and suppresses the generation of the low priority trace signal. The present invention has been made based on the recognition that there are usually certain types of trace signals that are more important than other signals. For example, there are certain types of trace signals that need to be output to maintain instruction traces, such as trace signals for branch addresses, while losing synchronization, such as data trace signals. There are other trace signals that may be lost. The inventors of the present invention have also noted that the former type of trace signal often has a narrower bandwidth than the latter type of trace signal.
[0010]
With the above in mind, the data processing apparatus of the present invention is configured to suppress the low-priority trace signal when it is determined that the trace receiving apparatus is necessary. This solves the above-mentioned problem of the prior art that an arbitrary amount of trace data is lost due to overflow. On the other hand, according to the present invention, when the trace receiving apparatus determines that it is appropriate, it sends a suppression signal to the trace generation unit to ensure that only the high priority trace signal is output. Thus, the possibility that the trace receiving apparatus will overflow is suppressed as much as possible.
[0011]
Since this suppression occurs directly between the trace generation unit and the trace receiver, the above-mentioned problems in the prior art resulting from latency in returning signals to the component whose operation is being tracked are well solved, Thus, the present invention provides a more reliable method for preventing trace receiver overflow, and at the same time considers that the trace signal is lost only to the low priority trace signal. You can do it.
[0012]
  The trace receiving device can be installed at the location of the trace generation unit or away from the trace generation unit. In one embodiment, data processingapparatusA trace receiving device is provided inside, and preferably mounted on the same chip as the trace generating unit, so that the propagation of the suppression signal from the trace receiving device to the trace generating unit can be accelerated. When it becomes necessary to suppress the priority trace signal, the trace generation unit can respond at high speed. For this reason, issuing suppression signals(Occurrence " issuance ")Thus, in order to prevent the trace receiving apparatus from overflowing, the low-priority trace signal can be immediately suppressed, and the reliability is further improved.
[0013]
The trace receiving device can take various forms. However, in this embodiment, the trace receiving apparatus is a buffer having a predetermined capacity (for example, a FIFO buffer).
[0014]
In the preferred embodiment, the buffer is configured to issue a suppression signal when the amount of trace signal stored in the buffer reaches a predetermined suppression level. Accordingly, in these embodiments, a suppression signal is issued when the trace signal reaches a predetermined percentage of the buffer.
[0015]
The device that reads and analyzes the trace signal generated by the data processing device may be directly connected to the trace receiving device. However, in the embodiment, the trace receiving device includes an input port connected to the trace generation unit via the first bus having the first bandwidth, and a second configuration in which the trace signal is output to the trace buffer. An intermediate buffer having an output port connected to a second bus having a first bandwidth, the first bandwidth being wider than the second bandwidth. In these embodiments, the device for reading and analyzing the trace signal generated by the data processing device is typically configured to read the trace signal from the trace buffer.
[0016]
As can be seen from these embodiments, since the output bandwidth of the intermediate buffer is narrower than its input bandwidth, the intermediate buffer may overflow. However, by using the suppression signal of the present invention, the trace generation unit can respond quickly to the suppression signal so that the low priority trace signal is not generated excessively, thus reducing the possibility of such a situation. be able to.
[0017]
  As described above, the present invention classifies trace signals as either high priority trace signals or low priority trace signals.(By class " classification ")It is necessary to do. In the preferred embodiment, this classification is maintained within a trace generation unit that identifies whether the trace signal is a high priority trace signal or a low priority trace signal. For example, it is understood in the art that this classification can be predefined to indicate that the trace signal for instruction trace is high priority while the trace signal for data trace is low priority. It can be recognized by those who are familiar with. In addition, this classification is programmable.
[0018]
  In the preferred embodiment, when a suppression signal is issued, a suppressed low priority trace signal is used to indicate that suppression is occurring.forlocation information(Placeholder " placeholder ")The trace generation unit is configured to output to the trace receiver. Thereby, trace data can be analyzed by a tool used later, and it is possible to determine when the low-priority trace signal is suppressed.
[0019]
These location information is issued as each item of trace data is suppressed, but in the preferred embodiment the trace is generated so that only the location information for the initially suppressed low priority trace signal is output. Unit is configured. Therefore, this position information indicates that suppression has occurred first, and is sufficient for the trace analysis tool to determine that data suppression has occurred. The possibility of causing an overflow of is avoided.
[0020]
In a preferred embodiment, the trace receiver is configured to release the suppression signal when the amount of trace signal stored in the buffer has dropped to a predetermined restart level. The predetermined restart level may be determined to be the same as the predetermined suppression level, but if the predetermined restart level is determined in this way, in some situations, the And tend to cause a certain amount of vibration between the unsuppressed state. Therefore, in the preferred embodiment, the predetermined suppression level is set higher than the predetermined restart level so that when all traces are restarted, there is no need to reissue the suppression signal. A capacity capable of increasing the amount of the trace signal stored in the receiving apparatus can be secured.
[0021]
In the preferred embodiment, for the first low priority trace signal that leads to the de-issue of the suppression signal, the initial low priority trace signal, along with any necessary synchronization data, can be analyzed later. The trace generation unit is configured to output a priority trace signal. As a result, any synchronization information that is missing corresponding to a certain part of the trace stream to be suppressed is taken into the stream of the trace signal.
[0022]
Data processing systems are becoming more complex, for example due to increased integration levels in embedded systems, so that more functionality is included in each data processing device (eg, chip). Therefore, it is necessary to provide more trace blocks and modules in the data processing apparatus. In such future systems, a single trace module that includes such a single trace generation unit is no longer sufficient, as it includes multiple components whose operation is to be tracked. For example, a data processing device includes a plurality of processor cores, each of which needs to be traced, and further, various buses in the data processing device need to be traced. However, it can be seen that the cost of providing external pins and trace buffers for each trace module is very high. However, there are exchanges of signals and information between different parts of the data processing device, and in order to debug these, it is necessary to trace the relationship between these parts at the same time, so between the multiple trace modules, Simply sharing pins and trace buffers is not appropriate. Therefore, as another problem to be solved, it becomes a problem to be able to effectively trace signals from a plurality of trace modules of the data processing device.
[0023]
  Thus, in an embodiment of the present invention, the data processing apparatus further includes a plurality of trace modules for receiving input signals from one or more components to be traced, wherein each trace module is Generating a trace signal from the input signal and outputting the trace signal on a corresponding trace bus, wherein at least one of the trace modules includes the trace generation unit and a corresponding trace receiving device, and the corresponding trace bus receives the trace reception The data processing apparatus is further connected to the trace bus of the trace module, receives the trace signal output to each trace bus as an input trace signal, and receives the trace signal from the input trace signal. Configure to generate the resulting trace stream to the output port Comprises a funnel logic, wherein the output port, aggregation trace bus connected to the funnel logic(overall" collective ")The trace signal by the trace module has a maximum bandwidth that is narrower than the maximum bandwidth and the funnel logic ensures that the input trace signal is output from the output port so that the maximum bandwidth of the output port is not exceeded. It is characterized by being configured to control the issuance of.
[0024]
Accordingly, in these embodiments, funnel logic is provided that is connected to the trace bus of various trace modules and is configured to generate a trace stream derived from various input trace signals at the output port. The trace stream is sent, for example, to a pin that can send a signal to the chip or to a trace buffer. The funnel logic is also configured to control the issuance of trace signals by the various trace modules to ensure that the input trace signal is output from the output port so that the maximum bandwidth of the output port is not exceeded. ing. Thus, the funnel logic of these embodiments can effectively generate multiple trace sources as input and a single trace stream as output, where the output stream is that of the expected input stream. The total number is not exceeded.
[0025]
According to the first aspect of the present invention, this funnel logic is provided inside the data processing device regardless of whether any trace module can suppress the generation of low priority trace signals. Thus, according to a second aspect of the invention, the invention comprises a plurality of trace modules for receiving input signals from one or more components to be traced, wherein each trace module Is characterized by generating a trace signal from the input signal and outputting it on a corresponding trace bus, and receiving the trace signal output to each trace bus as an input trace signal. And a funnel logic configured to generate a trace stream derived from an input trace signal to an output port, wherein the output port is greater than an aggregate maximum bandwidth of the trace bus connected to the funnel logic. Has a narrow maximum bandwidth so that the funnel logic does not exceed the maximum bandwidth of the output port To ensure that the input trace signal is output from the output port, and characterized in that it is configured to control the issuance of the trace signal by trace module, there is provided a data processing apparatus.
[0026]
In a preferred embodiment, the trace module is configured to indicate to the trace module which trace module should send the trace signal to the funnel logic at any point in time, and only the trace signal from one trace module can be trace streamed at any point in time. Has come to include.
[0027]
The act of determining which trace module should send a trace signal to the funnel logic at any point in time can be implemented in various ways. However, in the preferred embodiment, the funnel logic receives a request signal from each trace module that is attempting to output a trace signal on the corresponding trace bus and applies the predetermined criteria to the received request signal. A request handler is included to determine which trace module is to output the trace signal to the funnel logic. Thus, in these embodiments, each trace module is configured to indicate to the funnel logic when the trace module is about to output a trace signal to the corresponding trace bus so that the funnel logic is received. Mediate between various requests.
[0028]
Here, the request handler is preferably configured to send a permission signal to a trace module that will send a trace signal to the funnel logic upon application of a predetermined criterion. Thus, in these embodiments, the trace module will continue to issue its request signal until it receives an enable signal indicating that the trace signal can be sent to the funnel logic.
[0029]
The predetermined criteria applied by the funnel logic request handler to determine which trace module issues a trace signal to the funnel logic at any given time can take a variety of forms. However, in the preferred embodiment, the predetermined criteria shall define the priority order of the various trace modules.
[0030]
The predetermined criteria can be either predetermined or programmable. For example, the predetermined criteria may be specified, for example, to identify the relative priority assigned to the various trace modules, by the component that the module contained in it is configured to trace its operation. It may be programmable for the implementation of. For example, if it is determined that the most important trace signal to be output relates to the operation of the memory bus, the highest priority is assigned to the trace module configured to track this memory bus operation. It is done.
[0031]
In a preferred embodiment, the funnel logic further includes a multiplexer whose output is connected to each of the trace buses, and the request handler issues a control signal to the multiplexer upon application of the predetermined criteria, It is configured to control which input of the multiplexer is to be output as a trace stream output from the multiplexer for transferring the stream to an output port of the funnel logic.
[0032]
In order to effectively analyze the trace stream output from the funnel logic, it is necessary to analyze using a tool in order to know which component corresponds to a specific part of the trace stream. Become. In the preferred embodiment, the funnel logic includes the logic required for such an identifier to be added to the trace stream. In particular, in the preferred embodiment, the funnel logic further includes wrapping logic for introducing an identifier into the trace stream that indicates which component a particular portion of the trace stream corresponds to. This identifier can be implemented in various ways. However, in some embodiments, the wrapping logic is configured to receive a control signal issued to the multiplexer, and this identifier is derived from the control signal. Another example is to configure each trace module to issue an identifier to the wrapping logic.
[0033]
It can be seen that there are various ways of assigning components to corresponding trace modules. For example, in one implementation, a single trace module can actually be configured to trace one or more components. However, in the preferred embodiment, one trace module may be provided for each component to be traced.
[0034]
In one embodiment, each trace module is configured to issue a request signal to the funnel logic, thereby allowing the funnel logic to control the issuance of trace signals by each trace module in each situation.
[0035]
However, in other embodiments, for example, the trace module may depend on the design of the past trace module, and may be configured to simply output the trace stream when the trace module determines that it is appropriate. Therefore, there is a case where one or more trace modules are not configured to issue such a request signal or respond to the permission signal. In such a situation, the issue of the trace signal by at least one of the trace modules cannot be controlled by funnel logic, and the data processing device further includes such trace modules and funnel logic. And includes a buffering buffer for each of the trace modules for temporarily storing trace signals output from the trace module.
[0036]
In such an embodiment, the stalling buffer is configured to issue a request signal for the corresponding trace module and respond to any grant signal issued by the request handler, temporarily Preferably, the stored trace signal is output to funnel logic. Thus, in practice, the stalling buffer is the “front end” for each module according to such a past design, and the trace module can be connected in an appropriate manner with funnel logic.
[0037]
In the preferred embodiment, the stalling buffer is configured to issue a request signal when the amount of trace signal stored in the stalling buffer reaches a predetermined level. The number of components connected to the funnel logic that determine which trace module provides the trace signal to the funnel logic at a particular time by appropriately selecting the predetermined criteria applied by the funnel logic By limiting the bandwidth, it is possible to ensure that the stalling buffer receives the grant signal before the stalling buffer overflows with the trace data output from the corresponding trace module.
[0038]
As described above, the funnel logic output port may be connected to the trace buffer of the data processing apparatus. Alternatively, the output port may include a plurality of pins that allow the trace stream to be output to the outside from the data processing device.
[0039]
According to a third aspect of the present invention, the present invention provides a method for generating a trace signal in a data processing apparatus having components for tracing its operation, the method comprising: (i) Receiving an input signal from an operational component; (ii) generating a high priority and low priority trace signal from the input signal for output to a trace receiver; (iii) During step (ii), in order to suppress the low-priority trace signal, a step including responding to issuance of the suppression signal from the trace receiving device is performed using the trace generation unit. Yes.
[0040]
In a fourth aspect of the present invention, the present invention provides a data processing apparatus having a plurality of trace modules for receiving input signals from one or more components that trace its operation. Each trace module is configured to generate a trace signal output via a corresponding trace bus from each input signal of the trace module, the method comprising: (A) receiving a trace signal output to each trace bus in the funnel logic as an input trace signal; and (b) generating a trace stream obtained from the input trace signal at an output port of the funnel logic. The output port is an aggregated maximum of trace buses connected to the funnel logic A step characterized by having a maximum bandwidth narrower than the bandwidth; and (c) a trace to ensure that the input trace signal is output from the output port so as not to exceed the maximum bandwidth of the output port. Controlling the issuance of trace signals from the module.
[0041]
Speaking from the fifth aspect of the present invention, the present invention provides a computer program product for executing a computer program for controlling an apparatus based on the method of the third or fourth aspect of the present invention.
[0042]
DETAILED DESCRIPTION OF THE INVENTION
Detailed Description of the Preferred Embodiment
The present invention will now be described, by way of example only, with reference to a preferred embodiment as illustrated in the accompanying drawings.
[0043]
FIG. 1 schematically illustrates a data processing system 2 that provides an on-chip trace mechanism. The integrated circuit 4 includes a microprocessor core 6, a cache memory 8, an on-chip trace module 10 and an on-chip trace buffer 12. The integrated circuit 4 is connected to an external memory 14 that is accessed when a cache miss occurs in the cache memory 8. The general-purpose computer 16 is connected to the on-chip trace module 10 and the on-chip trace buffer 12, and uses software executed by the general-purpose computer 16 to extract and analyze a stream of trace data from these components.
[0044]
During operation, the processor core 6 often needs to access more data processing instructions and data than the actual memory space for the external memory 14. For example, the external memory 14 has a capacity of 1 MB, while the processor core 16 can normally specify a 32-bit address, thereby specifying a 4 GB instruction and data. it can. Therefore, all the instructions and data required by the processor core 6 are stored in the external storage device 18 such as a hard disk, and this operation is performed when the processor core 6 tries to operate in a specific operation state. Instructions and data appropriate for the state are loaded into the external memory 14.
[0045]
FIG. 2 is a block diagram showing in more detail the components provided in the on-chip trace module of FIG. The on-chip trace module 10 is configured to receive data representing processing executed by the processor core 6 via the path 105. According to FIG. 1, this data (eg, instructions and / or data provided to the core 6 and data generated by the core) is received by other control-type data received directly from the core 6 via the bus 20. (For example, data indicating an indexed instruction address, data indicating that an instruction for some reason has failed to execute its condition code, etc.) and the bus 20 connected to the cache 8 and the on-chip trace module 10 . In one embodiment, both types of data are sent to trading module 10 via a single bus between trace module 10 and core 6 (rather than using two buses 20 and 22) It can be recognized by those skilled in the art.
[0046]
The synchronization logic 100 is configured to convert the input signal to an internal mode of signal that is more suitable for use in an on-chip trace module. These internal modes are sent to the trigger 110 and the trace generation block 120, but it can be seen that the trigger 110 and the trace generation block 120 are not necessarily required to receive the same signal. Basically, the trigger 110 is necessary to receive data related to triggerable events such as addresses, data values, register accesses, and the like. The trigger generation block 120 is necessary to receive any data that needs to be traced in response to the enable signal issued by the trigger 110. The on-chip trace module 10 further incorporates a register bank 180 configured to receive configuration information from the general-purpose computer 16 via the path 125, and the contents of the configuration information can be It is read by the components of the on-chip trace module 10.
[0047]
Whenever trigger 110 detects an event that causes generation of a trace stream, the trigger sends an enable signal to trace generation logic 120 via path 135 to turn the trace on and off. This causes the trace generation logic to respond by outputting the necessary trace data to the FIFO 130 via paths 145 and 155. Various enable signals are sent over path 135 to identify the type of signal to be traced, eg, instruction only trace, instruction and data trace.
[0048]
According to a preferred embodiment of the present invention, the trace signal generated by the trace generation unit is classified as being either a high priority trace signal or a low priority trace signal. This classification is preferably maintained in the trace generation block 120 and may be predefined or programmable by the user. In the embodiment shown in FIG. 2, the high priority trace signal indicates a signal related to an instruction trace, such as a trace signal related to a branch address, while the low priority trace signal indicates a signal related to a data trace. This low priority trace signal can be lost without loss of synchronization. In the absence of any signal received from the FIFO 130 by the trace generation logic 120, the trace generation logic may output appropriate trace data to the FIFO 130 in response to an enable signal received from the trigger 110 via path 135. It is configured. With this configuration, for example, both an instruction trace signal issued via the path 145 and a data trace signal issued via the path 155 are issued. Although two independent paths are shown in FIG. 2, it is known in the art that both instruction trace signals and data trace signals typically share a connection between trace generation logic 120 and FIFO 130. It can be recognized by those familiar with the field.
[0049]
In addition to tracing instructions, it can be seen that when tracing data, the data trace signal via path 155 occupies most of the bandwidth of the trace port from trace generation signal 120 to FIFO 130. Further, the trace signal is exhausted through path 150 from FIFO 130 to trace buffer 12 via a narrowband output trace port. In general, any trace signal issued to the trace buffer via path 150 is accompanied by a trace valid signal that indicates whether the output trace is valid on path 140. The trace valid signal is normally set to be invalid when the corresponding trace module has no trace data to be issued during the clock cycle.
[0050]
Since the output bandwidth from the FIFO 130 is typically narrower than its input bandwidth, for example, if trace data is issued suddenly by the trace generation block 120, the FIFO 130 may overflow. For example, the input trace port has a bandwidth four to five times that of the output trace port to the trace buffer.
[0051]
Prior to the present invention, as a method of solving this problem, a signal indicating that the FIFO is full is sent from the on-chip trace module 10 to the core 6, and the core 6 is temporarily stopped, and the data in the FIFO is There was something that could reduce the amount. However, due to the inherent delay time and other problems, it is in operation before the core 6 is stopped between the signal generation time indicating that the FIFO is full and the processor core stop time. It has been found that this method is unreliable because a trace signal is issued to indicate that the FIFO 130 tends to cause an overflow anyway.
[0052]
According to an embodiment of the present invention, this problem can be solved by providing a suppression signal (hereinafter referred to as a DSup signal) issued by the FIFO 130 and sent directly to the trace generation block 120 via the path 160. In the present embodiment, the FIFO 130 is configured to issue a DSup signal from the FIFO 130 toward the trace generation block 120 when the content of the FIFO reaches a predetermined suppression level, whereby the trace generation block While the DSup signal is issued, the issuance of an arbitrary data trace signal via the path 155 is stopped. This means that data trace signals are lost, but these signals are considered low priority trace signals and may be lost without loss of synchronization information. In addition, since data traces typically use a wider bandwidth than high priority instruction traces, suppressing data traces may be sufficient to prevent FIFO 130 from becoming full. I know it.
[0053]
When the amount of data trace in the FIFO 130 substantially settles to a predetermined restart level, the FIFO 130 is configured to stop issuing the DSup signal so that the trace generation block 120 is on the path 155. The data trace signal is issued again.
[0054]
The predetermined suppression level and the predetermined restart level are selected according to the mounting state. However, for example, in a 60-byte FIFO, a predetermined suppression level is set to be 45 bytes (that is, a state that occupies 75% of the total capacity of the FIFO), whereas a predetermined suppression level is predetermined. The restart level is normally set to a value slightly less than 45 bytes, and after the suppression signal issuance is stopped, the trace signal stored in the FIFO is not required immediately after the suppression signal is issued again. To ensure that there is room to increase the amount of
[0055]
Since the operation of simply discarding the data trace signal by issuing the DSup signal cannot prevent the FIFO 130 from overflowing in all situations, the FIFO 130 overflows on the path 170 when it becomes full. A signal can be issued, so that the generation of an arbitrary trace signal can be stopped by the trace generation block 120 until the generation of the overflow signal stops. Such a procedure results in the loss of both the high priority trace signal and the low priority trace signal, but by appropriately selecting a predetermined suppression level for generating the DSup signal, the overflow signal is reduced. The scenes that need to be published are extremely rare.
[0056]
In other embodiments, in addition to issuing the DSup signal to the trace generation block 120, the FIFO 130 may take an internal step of storing only the instruction trace signal after the DSup signal is issued (thus, DSup The delay time between the signal issuance and the response to the DSup signal by the trace generation block can be eliminated).
[0057]
FIG. 3 is a flow diagram illustrating processing steps for determining a trace signal output to the FIFO 130 via paths 145 and 155, which is performed by the trace generation block 120 of the present embodiment. In step 300, it is determined whether there is any trace data to be generated. If it is determined that there is new trace data to be generated, the process proceeds to step 310 where it is determined whether the trace data is instruction trace data. If so, proceed to step 380 where trace data that does not include data synchronization information is issued on path 145. However, it may be recognized by those skilled in the art that sometimes other instruction synchronization information may be required for instruction tracing.
[0058]
  If it is determined in step 310 that the trace data to be generated is not instruction data, the trace data becomes a data trace, and the process proceeds to processing step 320 where it is determined whether a DSup signal has been issued. If a DSup signal is issued, proceed to step 330 where the data trace entry to be generated is the first following the DSup signal issue.(the first)Determine if it is an item. If not, the process proceeds to step 340 and no data trace item is output. However, if the data trace entry is the first to follow the DSup signal issue(the first)If it is an item, the process proceeds to step 350, and a position information signal is output to the FIFO via the path 155 instead of the entire data trace signal. This position information signal is a unique signal (for example, a 1-byte signal that specifies the start position of data suppression) and can be identified later by any tool that analyzes the trace data. Used to indicate that suppression has occurred. The position information is issued for each item of the suppressed data trace. In this embodiment, the position information is issued only for the first item of the data trace to be suppressed, and the FIFO is obtained by issuing the position information. To prevent the risk of overflow. Furthermore, it is usually more important for the trace analysis tool to know that suppression has occurred rather than knowing how many data trace items have been suppressed.
[0059]
  If it is determined in step 320 that the DSup signal has not been issued, then the process proceeds to step 360 where the DSup signal issuance is stopped, so that the data trace item to be traced is the first trace item.(the first)Determine if it is a data trace item. If so, proceed to step 370 to issue the data trace signal along with any data synchronization information needed to allow the data trace signal to be analyzed later. For example, when the address in the output data trace is compressed, the data synchronization information includes the output of the uncompressed address.
[0060]
However, assuming that it is determined in step 360 that the data trace item to be issued is not the first data trace item because issuance of the DSup signal has been stopped, then the process proceeds to step 380 where the corresponding data The data trace item is output without synchronization information.
[0061]
Thus, according to the position embodiment of the present invention, the method used here can dynamically avoid FIFO overflow without stopping the core 36. Thus, instead of taking time for the user to narrow down the trace data in order to avoid such overflow, the method can provide low priority trace data when it reaches a level where the FIFO is likely to overflow. It ensures that only as much trace data as possible is traced in such a way that only is lost.
[0062]
FIG. 4 is a block diagram of a data processing system provided with a plurality of on-chip trace modules 400, 405 and 410. In this example, the integrated circuit 4 has two processor cores 402 and 407 that are connected to corresponding caches 404 and 409. The caches 404 and 409 are both connected to the external memory 14 via the memory bus 420. Although not explicitly shown in FIG. 4, the external memory 14 is connected to the external storage device shown in FIG. In the system of this example, it may be desirable to be able to trace the operation of both the processor cores 402 and 407 and the memory bus 420. Accordingly, independent on-chip trace modules 400, 405 and 410 are each provided to trace these different components of the integrated circuit 4.
[0063]
However, the cost of providing external pins or independent trace buffers corresponding to each trace module is usually very high. Therefore, in the example shown in FIG. 4, a single trace buffer 12 is provided to store trace signals output from the plurality of trace modules 400, 405, and 410. Further, to mediate between multiple on-chip trace modules, convert the trace signals from these multiple on-chip trace modules into a single trace stream, and output to trace buffer 12 via path 470, Funnel logic 460 is provided. Such mediation is required because the total amount of bandwidth on the input trace paths 440, 442 and 444 is typically wider than the bandwidth on the path 470 to the trace buffer 12.
[0064]
In this embodiment, each of the on-chip modules 400, 405, and 410 issues a request signal to funnel logic via paths 430, 432, and 434 when the on-chip trace module requires output trace data. It is configured as follows. In practice, this request signal is given by the trace valid signal shown in FIG. Further, based on predetermined criteria, funnel logic 460 mediates between multiple request signals and determines which trace module should issue trace data to funnel logic as an output to trace buffer 12. In response, funnel logic issues grant signals 452, 454, and 450 accordingly. Any suitable mediation procedure can be used, but it is possible to use a mediation procedure similar to that typically used to mediate accesses required by multiple processor cores over a memory bus, for example. It will be understood that there is. When a particular trace module receives an issued grant signal, it outputs its trace data via each trace path 440, 442 and 444 between the trace module and funnel logic 460. Details of the operation of the funnel logic 460 will be described in detail later with reference to FIG.
[0065]
Request handler 500 is provided within funnel logic 460 for receiving a plurality of request signals via paths 430, 432 and 434. Further, the request handler 500 is configured in a reference storage device 510 that stores predetermined priority information, and issues a permission signal to which trace module when one or more request signals are issued at a specific time. Decide what to do. The priority information stored in the memory 510 may be predetermined or may be programmable by the user. In the example shown in FIG. 4, it is assumed that the operation of the memory bus 420 is the most important thing to be traced, followed by the operation of the core 1, and then the operation of the core 2. Yes. Therefore, when the memory bus trace module 410 issues a request on the path 434, the permission signal is issued on the path 450 regardless of the presence of the request signal on the paths 430 and 432. Similarly, when request signals are simultaneously received from the on-chip trace modules 400 and 405 on the paths 430 and 432, a permission signal to the trace module 400 is issued on the path 452 in preference to the trace module 405. The
[0066]
Multiplexer 520 is provided within funnel logic 460 for receiving a plurality of trace signals received on paths 440, 442 and 444 from three trace modules. When request handler 550 issues a grant signal, it simultaneously issues an identification signal on path 525 and sends it to multiplexer 520, which routes the trace signal issued by the trace module to which the grant signal was given. 535. Thus, by way of example, if a permission signal is issued to memory bus trace module 410, multiplexer 520 is configured to issue a signal received via input path 444 on path 535.
[0067]
In addition, since a single trace stream is output to trace buffer 12 via path 470, identification of which trace module corresponds to generating a particular portion of the trace stream is within the trace stream. It is important for use in later analysis by a trace tool operating on the computer 16 (see FIG. 1). Therefore, in this embodiment, the trace signal output from the multiplexer 520 is received and inserted into a trace identifier indicating which component (or trace module) corresponds to a specific part of the trace stream. And wrapping protocol logic 530 is provided. In this embodiment, this identifier is determined from the identification signal issued via path 525 by wrapping protocol logic 530. The trace stream obtained in this way is output to the trace buffer 12 via the path 470.
[0068]
FIG. 5 shows an overview of the operation of funnel logic 460, and some actual implementations require many registers in the control path, in which case some input to multiplexer 520 is required. The need to provide a buffer can be recognized by those skilled in the art.
[0069]
FIG. 7 is a diagram schematically showing logic provided in the request handler 500 in order to issue an appropriate permission signal and identifier signal. As described above, in this embodiment, the operation of the memory bus is considered to be the most important thing to be traced, so the configuration request signal (ie, logic logic) sent from the memory bus trace module 410 onto path 434. A signal having a value of 1 level) is output as a permission signal on the path 450. In such a situation, AND gates 700 and 710 ensure that the other two grant signals 452 and 454 are at a logic zero level regardless of the request signal received via paths 430 and 432. It is. Further, since the ID signal is “00”, the generation source of the corresponding trace signal is specified as the memory bus trace module 410.
[0070]
If the request signal on path 434 is not set (i.e., has a logic zero level), AND gates 700 and 710 will send the set request signal from on-chip trace module 1 400 It is guaranteed that the priority is higher than the setting request signal from the module 2 405. Further, from FIG. 7, if the permission signal is issued on the path 452, the ID signal is “01”, so that the corresponding trace signal is generated from the on-chip trace module 1 400. Identified. Similarly, when the permission signal is issued on the path 454, the ID signal is “10”, and therefore the generation source of the corresponding trace signal is specified as the on-chip trace module 2405.
[0071]
According to one embodiment, each trace module is configured to issue a request signal and can output the trace signal to funnel logic 460 only when a corresponding grant signal is received. However, in the present embodiment, each trace module is configured to issue a request signal and to stop outputting the trace signal if issuance of the permission signal is stopped. In an integrated circuit such as that shown in FIG. 4, there may be one or more past trace module designs that are not designed to respond to a grant signal. Such a trace module based on a past design is hereinafter referred to as an unstoppable device.
[0072]
In FIG. 6, one stoppable device 600 and two non-stoppable devices 610 and 620 are schematically shown as being connected to funnel logic 460. Corresponding buffers 630 and 640 are placed between each non-stoppable device and funnel logic 460 and are referred to below as stoppable buffers.
[0073]
As previously described with reference to FIG. 5, when a stoppable device attempts to issue trace data, it first issues a request signal on path 604 and the corresponding grant signal. Is also received on the path 604 from the funnel logic 460, the device further issues trace data on the path 602. In this example, it is assumed that the trace data has a 32-bit bandwidth.
[0074]
However, in contrast, each non-stoppable device 610 and 620 issues a data trace entry as it is generated, which is routed via paths 612 and 622 to the corresponding stoppable buffers 630 and 640. Sent to. At the same time, trace valid signals are issued on paths 614 and 624, which can be considered similar to request signals. For convenience of illustration, in FIG. 6, the unstoppable device 610 issues trace data with a bandwidth of 8 bits, whereas the unstoppable device 620 issues trace data with a bandwidth of 16 bits. Yes.
[0075]
Each of the stoppable buffers 630 and 640 is configured to wait until it has 32 bits of trace data to issue, and further issues a request signal to funnel logic 460 via paths 634 and 644, respectively. Is configured to do. When each buffer receives the permission signal, it outputs corresponding trace data via paths 632 and 643, respectively.
[0076]
Stoppable buffers 630 and 640 are ideally relatively small in capacity, so that non-stoppable devices 610 and 630 and 640 and 640 do not require a long wait before receiving a grant signal. 620 is preferably assigned a relatively high priority from the priority information stored in the memory 510 of the funnel logic 460. In the example shown in FIG. 6, assuming that the non-stoppable device is assigned a higher priority than the stoppable device 600, each buffer 630 and 640 has 64 It only needs to have a bit capacity.
[0077]
Within a single cycle time, since only a single device needs an output trace, the total bandwidth of the unstoppable device preferably does not exceed the bandwidth of the output stream from the funnel logic. In the example shown in FIG. 6, the total bandwidth of the non-stoppable device is 24 bits, whereas the output bandwidth is 32 bits.
[0078]
As described above with reference to FIG. 5, by issuing an appropriate grant signal by funnel logic 460, a single stream of trace data is output, in this example a trace having a bandwidth of 32 bits. It is guaranteed that the stream will be output. As described above, this trace stream goes through wrapping logic 530 where a device identifier is added and then the modified trace stream is output to the trace buffer 12. In the example shown in FIG. 6, since there are three different devices, two bits of information are necessary to uniquely identify the device in the device ID. Accordingly, the 32-bit trace stream is modified to generate a 34-bit wide trace stream when the device ID is added by the wrapping logic 530.
[0079]
In FIG. 6, the wrapping logic 530 is outlined as being external to the funnel logic 460 in order to clearly show how much the bandwidth of the trace stream changes as a result of incorporating the device ID. The wrapping logic may be provided outside the funnel logic or inside the funnel logic, as desired, and it is well known in the art that this result does not affect processing operations. It can be recognized by the person.
[0080]
As described above for the embodiments of the present invention, an improved method for generating trace signals within a data processing apparatus has been described. In particular, by using a suppression signal inside the on-chip trace module, when a suppression signal is issued, low priority trace data can be suppressed and the amount of trace data entering the FIFO can be reduced. It is possible to more reliably guarantee that the FIFO of the suppression signal on-chip trace module does not overflow. Further, when a plurality of on-chip trace modules are provided, a plurality of trace signals issued by these trace modules are aggregated into a single trace stream and output to the trace buffer by the funnel logic described above. Therefore, a plurality of trace modules can be used without causing an unnecessary increase in the cost of providing the corresponding pins or trace buffers.
[0081]
While specific embodiments of the invention have been described above, it will be appreciated that the invention is not so limited and that many modifications and additions are possible within the scope of the invention. For example, it is possible to obtain a combination of the features of the dependent claims together with the features of the independent claims without departing from the scope of the present invention.
[Brief description of the drawings]
FIG. 1 is a diagram showing an outline of a data processing system provided with an on-chip trace mechanism.
FIG. 2 is a block diagram illustrating in more detail the on-chip trace module of FIG. 1 in one embodiment of the present invention.
FIG. 3 is a flow diagram illustrating a method for determining which trace signal the trace generation block of FIG. 2 issues in one embodiment of the present invention.
FIG. 4 is a diagram showing an outline of a data processing apparatus according to an embodiment of the present invention and showing a configuration in which a plurality of on-chip trace modules are provided.
5 is a block diagram illustrating in more detail components provided within the funnel logic of FIG. 4 in one embodiment of the present invention.
FIG. 6 illustrates how the funnel logic of an embodiment is configured to connect to both stable and unstable devices in one embodiment of the present invention.
FIG. 7 is a diagram illustrating logic used within the funnel logic of an embodiment to generate a grant signal and an identifier signal from a received request signal in an embodiment of the present invention.
[Explanation of symbols]
2 Data processing system
4 Integrated circuits
6 Microprocessor core
8 Cache memory
10 On-chip trace module
12 On-chip trace buffer
14 External memory
16 General-purpose computer
20, 22 bus

Claims (57)

Components whose behavior is traced;
A data generation device comprising: a high-priority trace signal for receiving an input signal from a component that indicates operation; and a trace generation unit for generating a low-priority trace signal from the input signal for output to the trace reception device,
The trace generation unit suppresses the generation of the low priority trace signal in response to the suppression signal asserted (“assertion”) from the trace receiver,
The trace receiving device is a buffer of a predetermined size for storing the trace signal output by the trace generation unit,
A data processing device characterized in that the buffer is configured to assert ("assert") the suppression signal when the amount of the trace signal stored in the buffer reaches a predetermined suppression level .   2. The data processing device according to claim 1, wherein the trace receiving device is provided inside the data processing device.   2. The data processing apparatus according to claim 1, wherein the trace receiving device includes an input port connected to the trace generation unit via a first bus having a first bandwidth, and a second bus having a second bandwidth. A data processing apparatus comprising: an intermediate buffer having an output port connected to the first buffer, wherein the first bandwidth is wider than the second bandwidth, and a trace signal is output to the trace buffer.   2. The data processing apparatus according to claim 1, further comprising: a class for identifying whether a specific trace signal is a high priority trace signal or a low priority trace signal, in the trace generation unit. A data processing apparatus.   5. A data processing apparatus according to claim 4, wherein each class is programmable.   5. The data processing apparatus according to claim 4, wherein the classes are predetermined.   7. The data processing apparatus according to claim 6, wherein, for each class, the instruction trace signal is defined as a high priority trace signal and the data trace signal is defined as a low priority trace signal.   The data processing device according to claim 1, wherein when the suppression signal is asserted, a placeholder for the low priority trace signal that is suppressed to indicate that the suppression has occurred is output to the trace receiving device. A data processing apparatus comprising a trace generation unit.   9. The data processing apparatus according to claim 8, wherein the trace generation unit is configured to output only a placeholder relating to the suppressed first low priority trace signal.   2. The data processing apparatus according to claim 1, wherein the buffer is configured to stop asserting the suppression signal when the amount of the trace signal stored in the buffer decreases to a predetermined restart level. A data processing apparatus.   11. The data processing apparatus according to claim 10, wherein the predetermined suppression level is higher than the predetermined restart level.   11. A data processing apparatus according to claim 10, wherein for the first low priority trace signal following the discontinuation of the suppression signal assertion, along with any synchronization data required for the first low priority trace signal to be analyzed later, A data processing apparatus, wherein the trace generation apparatus is configured to output an initial low priority trace signal. The data processing apparatus of claim 1, further comprising a plurality of trace modules that receive input signals from one or more components that trace their operation, each trace module including a corresponding trace. A trace signal to be output via a bus is generated from each input signal, and at least one of the trace modules includes the trace generation unit according to claim 1 and a trace receiving device corresponding thereto. And the trace signal output from the trace receiving device is output to the corresponding trace bus ,
Furthermore, it is connected to the trace bus of the trace module so as to receive the trace signal output on each trace bus as an input trace signal, and is configured to generate a trace stream obtained from the input trace signal at the output port. The output port has a maximum bandwidth that is narrower than the maximum bandwidth of the entire trace bus connected to the funnel logic;
The funnel logic is configured to control the generation of trace signals by multiple trace modules to ensure that the input trace signal is output from the output port so that the maximum bandwidth of the output port is not exceeded A data processing device.   14. A data processing apparatus according to claim 13, wherein at any point in time a trace module should send a trace signal to the funnel logic so that the trace stream contains only trace signals from one trace module. A data processing apparatus comprising funnel logic as shown in the module.   14. The data processing apparatus according to claim 13, wherein the funnel logic receives a request signal from each trace module that attempts to output a trace signal on a corresponding trace bus, and which trace module receives the funnel logic from the received request signal. A data processing apparatus comprising: a request handler for applying a predetermined criterion to determine whether a trace signal should be sent to   16. The data processing apparatus according to claim 15, wherein the request handler is configured to generate a permission signal to a trace module that sends a trace signal to the funnel logic when a predetermined standard is applied. apparatus.   16. The data processing apparatus according to claim 15, wherein the predetermined criterion defines a priority between a plurality of trace modules.   16. A data processing apparatus according to claim 15, wherein the predetermined criteria are programmable.   16. The data processing apparatus according to claim 15, wherein the funnel logic further includes a multiplexer having a plurality of inputs connected to each of the trace buses, and the request handler outputs the funnel logic when a predetermined criterion is applied. A data processing apparatus for generating, in a multiplexer, a control signal for controlling which input of a multiplexer is to be output from the multiplexer as a trace stream to be sent to a port.   20. The data processing apparatus according to claim 19, wherein the funnel logic further includes wrapping logic for introducing an identifier into the trace stream indicating which component corresponds to a particular portion of the trace stream. Data processing device.   21. The data processing apparatus of claim 20, wherein the wrapping logic is configured to receive a control signal generated for the multiplexer and the identifier is derived from the control signal.   14. The data processing apparatus according to claim 13, wherein one trace module is provided for each component to be traced.   14. The data processing apparatus according to claim 13, wherein the funnel logic can control generation of a trace signal by each trace module.   14. The data processing apparatus according to claim 13, wherein generation of a trace signal by at least one of the trace modules is not controllable by funnel logic, and is further connected between the trace module and funnel logic. A data processing apparatus comprising a stalling buffer for each such trace module for temporarily storing output trace signals.   17. The data processing apparatus according to claim 16, wherein generation of a trace signal by at least one of the trace modules is not controllable by funnel logic, and is further connected between the trace module and funnel logic, A temporary buffer is included for each such trace module to temporarily store the output trace signal, which generates a request signal for the associated trace module and is generated by the request handler A data processing apparatus configured to output the temporarily stored trace signal to the funnel logic in response to the given permission signal.   26. The data processing apparatus according to claim 25, wherein the stalling buffer is configured to generate a request signal when the amount of the trace signal stored in the stalling buffer reaches a predetermined level. A data processing apparatus characterized by comprising:   14. The data processing apparatus according to claim 13, wherein the output port is connected to a trace buffer of the data processing apparatus.   14. The data processing apparatus according to claim 13, wherein the output port includes a plurality of pins for outputting a trace stream from the data processing apparatus. A method for generating a trace signal in a data processing apparatus having components for tracing its operation, comprising:
(I) receiving an input signal from a component indicating operation;
(Ii) generating a high priority trace signal and a low priority trace signal for output to the trace receiver from the input signal;
(Iii) during the step (ii), the trace generation unit performs a step comprising: suppressing a low priority trace signal in response to assertion of the suppression signal from the trace receiving device;
The trace receiving device is a buffer having a predetermined size for storing the trace signal generated in the step (ii),
The method further includes the step of causing the buffer to assert a suppression signal when the amount of trace signal stored in the buffer reaches a predetermined suppression level.   30. The method of claim 29, wherein the trace receiving device is provided within the data processing device.   30. The method of claim 29, wherein the trace receiver is connected to an input port connected to the trace generation unit via a first bus having a first bandwidth and to a second bus having a second bandwidth. An intermediate buffer having an output port, wherein the first bandwidth is wider than the second bandwidth and the trace signal is output to the trace buffer.   30. The method of claim 29, further comprising the step of maintaining within the trace generation unit a class for identifying whether a particular trace signal is a high priority trace signal or a low priority trace signal. Feature method.   33. The method of claim 32, wherein the classes are programmable.   33. The method according to claim 32, wherein the classification is predetermined.   35. The method of claim 34, wherein by class, the instruction trace signal is defined as a high priority trace signal and the data trace signal is defined as a low priority trace signal.   30. The method of claim 29, wherein during step (ii), when a suppression signal is asserted, a trace receive placeholder for a suppressed low priority trace signal to indicate that suppression has occurred. A method wherein a trace generation unit is configured to output to a device.   37. The method of claim 36, wherein the trace generation unit is configured to output only placeholders for the first suppressed low priority trace signal.   30. The method of claim 29, further comprising causing the buffer to de-assert the suppression signal when the amount of trace signal stored in the buffer has decreased to a predetermined restart level. A method characterized by.   40. The method of claim 38, wherein the predetermined suppression level is higher than the predetermined restart level.   39. The method of claim 38, with respect to the first low priority trace signal following discontinuation of the suppression signal assertion, along with any synchronization data required for the initial low priority trace signal to be analyzed later. A method wherein the trace generator is configured to output a low priority trace signal. 30. The method of claim 29, wherein the data processing apparatus further includes a plurality of trace modules for receiving input signals from one or more components that trace its operation, each trace module comprising: 30. The trace generation unit according to claim 29 and the trace reception unit corresponding thereto, wherein the trace generation unit is configured to generate a trace signal output via a corresponding trace bus from a respective input signal. A trace signal output from the trace receiving device is output to the corresponding trace bus,
The method
(A) In funnel logic, receiving a trace signal output to each trace bus as an input trace signal;
(B) generating a trace stream obtained from an input trace signal at an output port of the funnel logic, the output port being a maximum bandwidth narrower than a maximum bandwidth of the entire trace bus connected to the funnel logic; Comprising the steps of:
(C) controlling the generation of the trace signal from the trace module to ensure that the input trace signal is output from the output port so as not to exceed the maximum bandwidth of the output port;
A method comprising the steps of:   42. The method of claim 41, wherein the trace stream shows only trace signals from one trace module at any time by indicating to the trace module which trace module should send the trace signal to funnel logic at any time. A method characterized in that the funnel logic is configured to include. 42. The method of claim 41, wherein step (c) comprises:
Receiving a request signal from each trace module attempting to output an output trace signal on a corresponding trace bus;
Determining from the received request signal which trace module should send the trace signal to the funnel logic.   44. The method of claim 43, further comprising generating a grant signal to a trace module that sends a trace signal to funnel logic upon application of a predetermined criterion.   44. The method of claim 43, wherein the predetermined criteria defines a priority among the plurality of trace modules.   44. The method of claim 43, wherein the predetermined criteria is programmable.   44. The method of claim 43, wherein the funnel logic includes a multiplexer having a plurality of inputs connected to each of the trace buses, the method further comprising: providing a funnel logic output port upon application of a predetermined criterion. Generating a control signal to the multiplexer for controlling which input of the multiplexer is to be output from the multiplexer as a trace stream for transmission.   48. The method of claim 47, further comprising introducing an identifier into the trace stream indicating which component corresponds to a particular portion of the trace stream.   49. The method of claim 48, wherein the identifier is determined from a control signal generated by the multiplexer.   42. The method of claim 41, wherein one trace module is provided for each component to be traced.   42. The method of claim 41, wherein funnel logic is capable of controlling the generation of trace signals by each trace module.   42. The method of claim 41, wherein the generation of a trace signal by at least one of the trace modules is not controllable by funnel logic and is further connected between and output by the trace module and funnel logic. A method comprising a stalling buffer for each such trace module for temporarily storing trace signals.   45. The method of claim 44, wherein generation of a trace signal by at least one of the trace modules is not controllable by funnel logic, and is further connected between and output by the trace module and funnel logic. A temporary buffer for each such trace module to temporarily store the trace signal generated by the request handler and generated by the request handler for the corresponding trace module. A method configured to cause a funnel logic to output a temporarily stored trace signal in response to an arbitrary enable signal.   54. The method of claim 53, wherein the stalling buffer is configured to generate a request signal when the amount of trace signal stored in the stalling buffer reaches a predetermined level. A method characterized by that.   42. The method of claim 41, wherein the output port is connected to a trace buffer of the data processing device.   42. The method of claim 41, wherein the output port includes a plurality of pins for the trace stream to be output from the data processing device. A computer program for generating a trace signal in a data processing apparatus having components for tracing its operation,
(I) receiving an input signal from a component indicating operation;
(Ii) generating a high-priority trace signal and a low-priority trace signal to be output to the trace reception device from the input signal, and the trace reception device stores the trace signal output by the trace generation unit. A buffer of a predetermined size for
(Iii) suppressing the low-priority trace signal in response to assertion of the suppression signal from the trace receiver during the step (ii), and the amount of the trace signal stored in the buffer Is configured to assert the suppression signal when a predetermined suppression level is reached,
A computer program for causing to perform the steps in the trace generation unit including.

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