JP4172278B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a reference potential generation technique at the time of data reading.
[0002]
[Prior art]
Along with miniaturization of semiconductor processing dimensions, a bit line is not directly driven by a memory cell, but a weak signal generated from a small memory cell is once received by the gate of the FET as a gain transistor, and then the bit line is generated by the FET. Attention has been focused on gain-type semiconductor memories that drive the memory.
[0003]
Since such a gain-type memory has excellent scaling properties, its application to DRAMs and FeRAMs is being studied, but the same technique can be applied to other memories such as flash memory and magnetic memory (MRAM).
For example, in the following document, the present applicant has proposed a semiconductor memory device in which a plurality of ferroelectric capacitors are shared by one gain FET, and there is almost no area overhead due to gain circuit installation.
[Patent Document 1]
JP 2002-197857 A
[0004]
An example of a semiconductor memory device as the gain type memory is shown in FIG.
The memory unit MU is composed of a plurality of ferroelectric capacitors C1, C2,... Cn connected to the common node electrode NE. Each of the capacitors C, C2,... Cn is a memory cell that stores different data.
The gain transistor T1 is a depletion N-channel MOS-FET, and its gate is connected to the common node electrode NE. Further, one of the source / drain is connected to a power supply line such as Vcc or ground, and the other is connected to the bit line BL via a read switch T2 made of FET.
The gate of the read switch T2 is connected to the read word line WLr.
Further, a write switch T3 by FET is provided, the gate of the write switch T3 is connected to the write word line WLw, one of the source / drain is connected to the common node electrode NE, and the other is connected to the bit line BL. ing.
[0005]
Each of the capacitors C1, C2,... Cn has one end connected to the common node electrode NE. The other ends are connected to plate lines PL1, PL2,.
[0006]
When 1 bit is stored in one memory cell in such a gain-type memory, the reading requires some reference means for data determination.
An example of a conventional reference method will be described with reference to FIG.
[0007]
FIG. 10 shows a memory array in which memory units MU as shown in FIG. 9 are repeatedly arranged in the bit line BL direction and the word line WL direction.
Each of the memory units MU11, MU12,... Has four ferroelectric capacitors C1 to C4 as an example.
[0008]
In each memory unit arranged in the word line WL direction, the read word line WLr and the write word line WLw are shared.
For example, in the memory units MU11, MU12, MU13, and MU14, the read word line WLr1 is connected to the gate of the read switch T2 of each of these memory units (MU11 to MU14), and the write word line WLw1 is connected to each memory unit (MU11 to MU11). MU14) is connected to the gate of the write switch T3.
Each word line WL is applied with a voltage according to an address to be accessed and write / read by a word line driving circuit (not shown).
[0009]
The bit lines BL are shared by the memory units arranged in the bit line BL direction.
For example, the bit line BL1 is connected to the memory units MU11 and MU21 via the read switch T2 and the write switch T3.
Each bit line BL (BL1, BL2,...) Is applied with a voltage during writing by the sense amplifier 2 (2-1, 2-2.
[0010]
As also shown in FIG. 9, each of the capacitors C1 to C4 in the memory unit MU is connected to the plate line PL.
For example, in the memory units MU11, MU12, MU13, and MU14, the capacitors C1 to C4 are connected to the plate lines PL11 to PL14, respectively.
A predetermined voltage is applied to each plate line PL by a plate line drive circuit (not shown).
[0011]
A reference potential generating circuit 1 for generating a reference potential Vref is provided. The generated reference potential Vref is supplied as a reference signal to each of the sense amplifiers 2-1, 2-2,.
The sense amplifier 2 (2-1, 2-2,...) Is a circuit that determines the read value by comparing the potential of the bit line BL to be read with the reference potential Vref.
[0012]
In such a gain-type memory, data reading is performed as follows.
For example, when reading data from the capacitor C1 of the memory unit MU11, the plate line PL11 is driven in a state where the plate lines PL12 to PL14 are fixed to 0V. Then, a signal corresponding to the polarization direction of the ferroelectric film constituting the capacitor C1 is applied to the gate of the gain transistor T1.
Further, when the read word line WLr1 is selected and turned on, the read switch T2 becomes conductive and the gain transistor T1 is connected to the bit line BL1. Thereby, the gain transistor T1 drives the bit line BL1 previously equalized to the Vcc potential toward the ground. The driving capability depends on the gate potential, and varies depending on the storage state of the cell capacitor C1, that is, the polarization direction of the ferroelectric film. Therefore, the bit line potential changes depending on the storage state. The sense amplifier 2-1 compares the potential of the bit line BL1 with the reference potential Vref to determine the storage state of the cell capacitor C1, that is, whether the read value is “1” or “0”. it can.
[0013]
In such a gain-type memory, the selected capacitor does not need to directly drive the bit line BL when reading data. Therefore, a large signal can be obtained with a small capacitor, which is suitable for miniaturization.
[0014]
[Problems to be solved by the invention]
Normally, as shown in FIG. 10, a fixed potential generated by the reference potential generation circuit 1 outside the cell array is used as the reference potential Vref.
However, in that case, the following problems occur.
[0015]
The threshold value of the gain transistor T1 has a distribution with a width of about several tens of mV in the chip due to various factors in the manufacturing process.
Further, if the variation between different chips in the wafer is included, the width becomes about 100 mV, and if the variation between wafers and lots is included, the distribution width ranges from 200 to 300 mV.
Accordingly, the driving capability of the bit line BL of the gain transistor T1 varies greatly, and even if the reference potential Vref is accurately generated, the read margin is greatly deteriorated.
[0016]
Furthermore, the signal itself from the memory cell also varies within a chip, between chips, between wafers, and between lots, and the signal level also has temperature dependence, and each causes deterioration of the read margin.
Furthermore, if the memory unit MU to be accessed changes due to the difference in the ROW address of the memory cell to be accessed and the distance between the sense amplifier 2 and the gain transistor T1 changes, the amount of voltage drop due to the bit line resistance changes, and the sense amplifier 2 The input potential varies.
Depending on the memory element used for the memory cell, the signal may have access frequency dependency due to fatigue. Furthermore, the read signal level may change depending on the elapsed time from writing, that is, the data holding time. All of these are directly related to deterioration of the read margin.
[0017]
As described above, as long as a fixed potential or a fixed current is used as the reference potential Vref, there is an unavoidable problem that various variation factors generated in the potential or current of the read bit line greatly deteriorate the read margin.
[0018]
[Means for Solving the Problems]
Therefore, the present invention proposes a method of generating a reference potential or a reference current that effectively cancels each variation factor.
[0019]
  Therefore, the semiconductor memory device of the present invention isA memory unit having one or a plurality of memory cells that generate a read potential corresponding to a stored value at a predetermined node and a gain transistor that drives a corresponding bit line based on the read potential generated at the node; A semiconductor memory device including a memory array arranged corresponding to each of a plurality of bit lines includes the following reference drive means, short-circuit means, and read value determination means.
The reference driving means is provided corresponding to each of the plurality of bit lines, a dummy transistor having the same size as the gain transistor for driving the corresponding bit line based on the potential generated at the gate node, and the memory It has the same structure as the cell, and has one or a plurality of dummy cells that generate a potential corresponding to the stored value at the gate node.
The short-circuit means short-circuits the gate nodes of the dummy transistors of the reference drive means provided corresponding to the two bit lines paired among the plurality of bit lines.
When one of the two bit lines paired is driven by the gain transistor of the memory unit and the other is driven by the dummy transistor of the reference driving means, the read value determining means The value of the data read from the memory unit is determined by comparing both currents flowing through the two bit lines, or both potentials of the two bit lines.
[0020]
In addition, the short-circuit means has the same number of the gate nodes to which the first value signal read from the dummy cell is applied and the gate nodes to which the second value signal read from the dummy cell is applied, or Short-circuit approximately the same number.
[0025]
  That is, in the present invention as described above, in order to cancel the influence of the variation in the threshold value of the gain transistor, a dummy transistor having the same size as that of the gain transistor of the read cell is provided in the vicinity and the bit is set by the dummy transistor.Line (the other bit line)To drive. ThisTWire(The other bit line)Generates a reference signal as a reference potential or reference current and reads it with the read bitLine (one bit line)The read value is determined by directly or indirectly comparing the states.
  Specifically, the dummy transistor is provided in a cell array that is the same as or adjacent to the gain transistor connected to the memory cell to be accessed. Alternatively, a gain transistor and a dummy transistor may be arranged in pairs in each memory unit, and memory units arranged in pairs in the vicinity may provide a reference potential to each other.
  In general, the threshold value of a transistor (FET) has a lot-to-lot and wafer-to-wafer dependency, and also has a strong chip-to-chip dependency in a wafer and also a location dependency in a chip. Accordingly, there is almost no threshold difference between FETs arranged close to each other in the same chip.
  Therefore, a dummy transistor is arranged in the vicinity of the gain transistor connected to the memory cell to be accessed, thereby driving a reference bit line and using the potential or current of the bit line as a reference for reading determination. By doing so, it is possible to cancel the influence of the threshold variation of the gain transistor.
[0026]
Furthermore, in order to cancel the variation in the generated signal from the memory cell and the temperature dependence, it is preferable to apply a read signal from the dummy cell having the same structure as the memory cell to the gate of the dummy transistor.
Further, in order to level the variation in signals from the dummy cells, the gate nodes of the plurality of dummy transistors are once short-circuited, and then the reference bit line is driven. Alternatively, the potentials or currents for the plurality of second bit lines are combined to generate a read determination potential or current.
In particular, a signal from a dummy cell in which a first value (for example, “1”) is written and a second value (for example, “0”) are written using a pair or a plurality of pairs of dummy transistors or reference bit lines. The same number of signals from the dummy cell are short-circuited and applied to the gate of the dummy transistor, or the second bit line potential or current corresponding to the first value and another second bit line potential corresponding to the second value Alternatively, the leveling can be appropriately performed by combining the same number of currents.
[0027]
Further, in order to offset the dependency between the sense potential of the sense amplifier (read value determination means) between the memory cell and the sense amplifier, the dependency on the data retention time of the generated signal from the memory, and the dependency on the number of accesses, A dummy cell may be arranged for each row address, a dummy cell corresponding to the row address of the accessed memory cell may be accessed, and a read signal thereof may be given to the dummy transistor.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
The first and second embodiments of the semiconductor memory device of the present invention will be described below.
1 to 5 show the configurations of the first to fifth embodiments as semiconductor memory devices using ferroelectric capacitors, and FIGS. 6 to 8 similarly show the present invention. Fig. 2 shows another memory cell structure that can be adopted.
In each figure, a word line is shown as a code including “WL” (for example, WLw1, WLr1, etc.), and similarly, a bit line is used as a code including “BL”, and a plate line is used as a code including “PL”. Show.
As for the word lines WL and the plate lines PL, the circuit portions for driving these lines are not shown. However, the word lines WL are separately accessed by a word line driving circuit (not shown) by an address and write / read. The corresponding voltage is applied. A dummy word line (dWL) is also provided as a characteristic configuration of the embodiment, and this dummy word line dWL is also driven by a word line driving circuit.
The plate line PL (and the dummy plate line dPL) is applied with a voltage according to an address and a write / read type accessed by a plate line driving circuit (not shown) in a predetermined manner.
[0029]
<First Embodiment>
The present embodiment is a semiconductor memory device as a ferroelectric memory. FIG. 1 shows a configuration example.
As shown in FIG. 1, a plurality of memory units MU are repeatedly arranged in the bit line BL direction and the word line WL direction to form a memory array.
Each of the memory units MU11, MU12,... Has four ferroelectric capacitors C as an example. For example, the memory unit MU11 includes capacitors C11 to C14. Of course, the number of capacitors in one memory unit MU is not limited to four. In particular, when the purpose is high integration, a larger number of capacitors are provided.
[0030]
Since the configuration in each memory unit MU is the same, the configuration will be described using the memory unit MU11.
In the memory unit MU11, the plurality of ferroelectric capacitors C11 to C14 are memory cells that store different data. One end of each of the capacitors C11 to C14 is connected to the common node electrode NE.
Further, a gain transistor T11, a read switch T12, and a write switch T13 are provided by FETs.
The gain transistor T11 is an N-channel MOS-FET in a depletion state, and its gate is connected to the common node electrode NE. Further, one of the sources / drains is connected to the ground (or a power supply line such as Vcc), and the other is connected to the bit line BL1 via the read switch T12 made of FET.
The gate of the read switch T12 is connected to the read word line WLr1.
The gate of the FET write switch T13 is connected to the write word line WLw1, and one of the source / drain is connected to the common node electrode NE and the other is connected to the bit line BL1.
The other ends of the capacitors C11 to C14 are connected to plate lines PL1, PL2, PL3, and PL4, respectively.
[0031]
The other memory units MU have the same internal configuration, but the word lines WL, bit lines BL, and plate lines PL to be connected are in accordance with their arrangement positions.
[0032]
In each memory unit arranged in the word line WL direction, the read word line WLr and the write word line WLw are alternately shared.
For example, in the memory units MU11 and MU13, the read word line WLr1 is connected to the gates of the read switches (T12 and the like) of the memory units MU11 and MU13, and the write word line WLw1 is written to the memory units MU11 and MU13. Connected to the gate of a switch (T13 etc.).
Further, for example, in the memory units MU12 and MU14, the read word line WLr2 is connected to the gate of the read switch (such as T22) of each memory unit MU12 and MU14, and the write word line WLw2 is written to each memory unit MU12 and MU14. Connected to the gate of a switch (T23, etc.).
[0033]
The bit lines BL are shared by the memory units arranged in the bit line BL direction.
For example, the bit line BL1 is connected to the memory units MU11 and MU21 via the read switch T2 and the write switch T3.
Each bit line BL (BL1, BL2,...) Is applied with a voltage during writing by the sense amplifier 2 (2-1, 2-2.
The sense amplifier 2 is a circuit that determines the read value by comparing the potential of the bit line BL to be read with a reference signal.
[0034]
In the memory array in which a plurality of memory units MU are arranged in this manner, dummy unit rows 10 are provided in the word line direction.
In the dummy unit row 10, dummy units dU (dU1, dU2,...) Are formed corresponding to the bit lines BL1, BL2,.
Each dummy unit dU is provided with dummy transistors dT11, dT21... By FETs having the same structure and size as the gain transistors (T11, T21...) In the memory unit MU, and dummy read switches. dT12, dT22... are provided.
[0035]
Each gate of the dummy transistors dT11, dT21... Is connected to the reference potential line Lref. Further, one of the source / drains is connected to the ground (or a power supply line such as Vcc), and the other is connected to the corresponding bit lines BL1, BL2,... Via the dummy read switches dT12, dT22. It is connected.
A pair of dummy word lines dWL1 and dWL2 are arranged for the dummy unit row 10, and the respective dummy units are connected alternately.
For example, in the dummy units dU1 and dU3, the gate of the dummy read switch (dT12, etc.) is connected to the dummy word line dWL1, and in the dummy units dU2, dU4, the gate of the dummy read switch (dT22, etc.) is connected to the dummy word line dWL2. The
[0036]
A reference potential generating circuit 1 for generating a reference potential Vref is provided. The generated reference potential Vref is applied to the gates of the dummy transistors dT11, dT21,... Of each dummy unit dU via the reference potential line Lref.
The generated reference potential Vref is set to a potential set to an intermediate level of a signal generated from the memory cell (capacitor C) holding data “1” and data “0” to the node NE.
[0037]
In this example, dummy units dU having dummy transistors dT11, dT21,... Are arranged in a memory array in which a plurality of memory units MU are arranged in this way.
Data reading in this case is performed as follows.
In this example, a plurality of sense amplifiers 2-1, 2-2,... Are arranged in the memory array, but for each sense-up 2, a pair of memory units MU and a dummy unit dU are selected. Accessed form.
[0038]
For example, a case where data is read from the capacitor C11 of the memory unit MU11 and the capacitor C21 of the memory unit MU12 is taken as an example.
In this case, the plate line PL11 is selected and driven to a high level. Then, different signals depending on the storage states of the capacitors C11 and C21 are applied to the gates of the gain transistors T11 and T21, respectively.
[0039]
Here, since the read switch T12 and the dummy read switch dT22 are turned on by simultaneously turning on the read word line WLr1 and the dummy word line dWL2, the gain transistor T11 drives the bit line BL1, and the dummy transistor dT21 is turned on. The bit line BL2 is driven. Accordingly, a read current corresponding to the data of the capacitor C11 flows through the bit line BL1, and a reference current based on the reference potential Vref flows through the bit line BL2, and the potentials of both vary.
By comparing and sensing this with the sense amplifier 2-1, the stored value of the memory cell (capacitor C11) is determined.
[0040]
Subsequently, both bit lines BL1 and BL2 are equalized, and this time the read word line WLr2 and the dummy word line dWL1 are turned on simultaneously. Then, since the read switch T22 and the dummy read switch dT12 are turned on, the gain transistor T21 drives the bit line BL2, and the dummy transistor dT11 drives the bit line BL1. Accordingly, a read current corresponding to the data of the capacitor C21 flows through the bit line BL2, and a reference current based on the reference potential Vref flows through the bit line BL1, and the potentials of both vary.
By comparing and sensing this with the sense amplifier 2-1, the stored value of the memory cell (capacitor C21) is determined.
[0041]
Thus, in the case of this example, in the case of reading data from a memory unit on a certain bit line BL, the reference signal is obtained by the dummy unit dU on the other bit line BL corresponding to the same sense amplifier 2. Is.
Here, the gain transistors T11, T21... And the dummy transistors dT11, dT21... Exist in the same cell array and are close to each other. For this reason, the difference between the threshold values is not affected by variations among chips, wafers, and lots, and the influence of variations within a chip is extremely small. Therefore, these variations hardly affect the determination of the read value by the sense amplifier 2. That is, there is almost no deterioration in the read margin.
[0042]
In order to make the memory unit MU to be accessed and the dummy unit dU as close as possible, a plurality of dummy unit rows 10 may be provided in the same cell array, and the dummy unit row close to the access unit may drive the reference bit line. .
[0043]
<Second Embodiment>
FIG. 2 shows a configuration example of the second embodiment.
The first embodiment has a so-called folded bit line configuration, but the second embodiment in FIG. 2 is an example of an open bit line configuration.
[0044]
Bit lines BL1-1 and BL1-2 are provided as bit lines for the sense amplifier 2-1, and bit lines BL2-1 and BL2-2 are provided as bit lines for the sense amplifier 2-2. In this structure, a pair of bit lines BL are formed in an adjacent cell array across the sense amplifier 2.
[0045]
The illustrated memory units MU11, MU12, MU21, and MU22 are memory units disposed on the bit lines BL1-1, BL1-2, BL2-1, and BL2-2, respectively.
Also, dummy units dU11, dU12, dU21, and dU22 are provided on the bit lines BL1-1, BL1-2, BL2-1, and BL2-2, respectively.
The configuration in each memory unit MU and the configuration in the dummy unit dU are the same as those in FIG.
The reference potential line Lref is provided as reference potential lines Lref1 and Lref2 for each cell array, and the reference potential generation circuit 1 applies the reference potential Vref.
[0046]
In the case of this configuration, the dummy unit dU for obtaining the reference signal corresponding to the memory unit MU to be accessed during the read operation is arranged in the adjacent cell array with the sense amplifier 2 interposed therebetween.
[0047]
For example, when data is read from the capacitor C11 of the memory unit MU11, when the plate line PL11 is selected and driven to a high level, a different signal is applied to the gate of the gain transistor T11 depending on the storage state of the capacitor C11. The
Here, the read word line WLr1 and the dummy word line dWL2 are simultaneously turned on, whereby the gain transistor T11 drives the bit line BL1-1 and the dummy transistor dT21 drives the bit line BL1-2. Accordingly, since a read current corresponding to the data of the capacitor C11 flows through the bit line BL1-1 and a reference current based on the reference potential Vref flows through the bit line BL1-2, the sense amplifier 2-1 performs comparison and sensing. The stored value of the capacitor C11 is determined.
[0048]
When reading data from the capacitor C21 of the memory unit MU12,
The plate line PL21 is driven to a high level, and a signal that varies depending on the storage state of the capacitor C21 is applied to the gate of the gain transistor T21.
Here, when the read word line WLr2 and the dummy word line dWL1 are turned on simultaneously, the gain transistor T21 drives the bit line BL1-2, and the dummy transistor dT11 drives the bit line BL1-1. Accordingly, since a read current corresponding to the data of the capacitor C21 flows through the bit line BL1-2 and a reference current based on the reference potential Vref flows through the bit line BL1-1, the sense amplifier 2-1 performs comparison and sensing. Then, the stored value of the capacitor C21 is determined.
According to this embodiment, the same effect as that of the first embodiment can be obtained.
[0049]
<Third Embodiment>
The configuration of the third embodiment is shown in FIG. This is a configuration example in which the dummy unit dU is provided in the memory unit MU.
[0050]
As in FIG. 1, for example, in a pair of bit lines BL1, BL2 corresponding to the sense amplifier 2-1, memory units MU11, MU21,... Are arranged on the bit line BL1, and a memory is provided on the bit line BL2. Units MU12, MU22,... Are arranged.
In each memory unit MU, a dummy unit dU (dU11, dU12, dU21, dU22) having a dummy transistor (dT11, dT21, etc.) and a dummy read switch (dT12, dT22, etc.) is provided. Yes.
That is, the memory unit MU and the dummy unit dU are provided at 1: 1.
The reference potential generation circuit 1 supplies the reference potential Vref to the gates of the dummy transistors (dT11, dT21, etc.) of each dummy unit dU, as in the above-described embodiments.
[0051]
Write word line WLw and read word line WLr are alternately shared by memory units MU arranged in the word line direction (memory units MU adjacent in the word line direction are connected to another word line WL). Is similar to FIG. 1, but the dummy word line dWL is not provided for the dummy unit dU in each memory unit MU, and the read word line WLr is shared as a dummy word line.
For example, the gate of the dummy read switch dT12 of the memory unit MU11 is connected to the read word line WLr2 corresponding to the adjacent memory unit (for example, MU12), and the gate of the dummy read switch dT22 of the memory unit MU12 is connected to the adjacent memory unit. Read word line WLr1 corresponding to (for example, MU11) is connected.
[0052]
In such a configuration, for example, a pair of memory units arranged on a pair of bit lines, for example, the memory units MU11 and MU12, are arranged adjacent to each other or in extremely close proximity to each other.
Then, at the time of read access to the memory cell, the dummy units dU operate in correspondence with each other.
[0053]
For example, a case where data is read from the capacitor C11 of the memory unit MU11 and the capacitor C21 of the memory unit MU12 is taken as an example.
In this case, the plate line PL11 is selected and driven to a high level. Then, different signals depending on the storage states of the capacitors C11 and C21 are applied to the gates of the gain transistors T11 and T21, respectively.
[0054]
When the read word line WLr1 is turned on, the gain transistor T11 drives the bit line BL1, and the dummy transistor dT21 drives the bit line BL2. Accordingly, a read current corresponding to the data of the capacitor C11 flows through the bit line BL1, and a reference current based on the reference potential Vref flows through the bit line BL2, and the potentials of both vary. By comparing and sensing this with the sense amplifier 2-1, the stored value of the memory cell (capacitor C11) is determined.
[0055]
Subsequently, both bit lines BL1 and BL2 are equalized, and this time the read word line WLr2 is turned on. Then, the gain transistor T21 drives the bit line BL2, and the dummy transistor dT11 drives the bit line BL1. Accordingly, a read current corresponding to the data of the capacitor C21 flows through the bit line BL2, and a reference current based on the reference potential Vref flows through the bit line BL1, and the potentials of both vary. By comparing and sensing this with the sense amplifier 2-1, the stored value of the memory cell (capacitor C21) is determined.
[0056]
In this example, the memory units MU paired in this way provide a reference potential to each other. The gain transistor and the dummy transistor (for example, T11 and dT21, or T21 and dT11, etc.) operating at the same time are located in close proximity to each other. 10 mV or less. Accordingly, the threshold variation of the gain transistor (T11 or the like) does not deteriorate the read margin.
[0057]
<Fourth embodiment>
In order to secure a sufficient read margin, it is also important to adjust the reference voltage Vref applied to the gates of the dummy transistors dT11, dT21.
Many memory devices, including ferroelectric capacitors, have temperature dependence on their read signal levels. In addition, since the characteristics of the memory element itself vary within a chip, between chips, between wafers, and between lots, when the reference potential Vref is supplied as a fixed potential by the reference potential generation circuit 1, all of the above variations lead to margin degradation.
[0058]
Considering this, it is desirable that the reference voltage Vref applied to the gates of the dummy transistors dT11, dT21...
As a countermeasure, it is effective to use a dummy cell having the same structure as the memory cell as means for generating the reference potential Vref as seen in a DRAM or FeRAM which is not a gain type memory.
That is, if the reference potential Vref is generated using a dummy cell, the reference potential also has characteristic variations and temperature dependence between memory chips, wafers, and lots as in the case of a read signal from the memory cell. Therefore, these are offset.
[0059]
However, as a result of examination, it has become clear that the following two points need to be noted when combining a gain-type memory and a dummy cell.
First, in a gain type memory, a minute signal from a very small memory element is amplified by a gain FET, and therefore, variation in the characteristics of the dummy cell itself on the chip becomes an important margin deterioration factor.
[0060]
Next, in general, in a gain type memory, the load capacity driven by the memory cell is very small, so that the parasitic capacity of the memory cell itself greatly contributes to the overall load capacity. Therefore, like a normal memory, the signal from the memory cell does not depend linearly on the size of the memory cell.
For example, in a ferroelectric memory, when the area is A, the polarization amount per unit area is P, the paraelectric component (parasitic capacitance of the cell) per unit area is Cs, and the load capacity to be driven is Cb, the data is read from the memory cell. Signal S is
S = A · P / (A · Cs + Cb)
It is.
[0061]
In a normal ferroelectric memory, the load capacity Cb to be driven is sufficiently large with respect to “A · Cs”.
S = A · P / Cb
That is, the signal S is approximately proportional to the area A. Therefore, an intermediate signal of “1” and “0” can be easily generated by adjusting the area of the dummy cell, and the method is almost adopted in actual products. However, on the contrary, Cb is very small in gain type memory.
S = A · P / (A · Cs)
That is, the area dependence of the signal S is almost eliminated. Here, a simple one-capacitor connection type is taken as an example, but the same applies even if the memory unit is configured with a plurality of capacitors as in the above-described embodiment. That is, in the gain type memory, it is very difficult to adjust the signal level by changing the cell area. For this reason, it is not appropriate to generate a reference potential using a memory cell in the same manner as a normal memory.
[0062]
In view of this point, a fourth embodiment in which a dummy cell is used to generate the reference potential Vref will be described with reference to FIG.
In FIG. 4, only MU11 to MU14 are shown as the memory units MU. However, the configuration of these memory units MU and the memory units MU (not shown) (for example, the memory units MU21 to MU24 in FIG. 1), The connection state of the memory unit MU and the word lines WL, bit lines BL, and plate lines PL is the same as that in FIG.
In the example of FIG. 1, the dummy unit row 10 is shown. As a portion corresponding to the dummy unit row 10, in the case of FIG. dU1, dU2, dU3, dU4... are provided.
That is, each dummy unit dU includes a dummy capacitor dC having the same size as the capacitor C of the memory unit MU.
[0063]
For example, the dummy unit dU1 will be described. The dummy unit dU1 has four dummy capacitors dC11 to dC14. These are capacitors of the same size as the capacitor C of the memory unit MU.
One end of each of the dummy capacitors dC11 to dC14 is connected to the common node electrode dNE.
Dummy plate lines dPL1 to dPL4 are arranged, and the other ends of the dummy capacitors dC11 to dC14 are connected to the dummy plate lines dPL1 to dPL4, respectively.
Similarly, dummy capacitors dC are provided for the other dummy units dU2, dU3,. Each dummy capacitor dC has one end connected to the common node electrode dNE in the dummy unit dU and the other end connected to the dummy plate lines dPL1 to dPL4.
[0064]
In each dummy unit dU, dummy transistors dT11, dT21... Are formed of FETs having the same structure and size as the gain transistors (T11, T21...) In the memory unit MU. Dummy read switches dT12, dT22,... Are provided. Further, dummy write switches dT13, dT23... Are provided.
[0065]
In each dummy unit dU, the gates of the dummy transistors dT11, dT21,... Are connected to the common node electrode dNE. One of the sources / drains is connected to the ground (or a power supply line such as Vcc), and the other is connected to the corresponding bit lines BL1, BL2,... Via the dummy read switches dT12, dT22. It is connected.
[0066]
A pair of dummy read word lines dWLr1 and dWLr2 and a pair of dummy write word lines dWLw1 and dWLw2 are arranged for the dummy unit row in which such dummy units dU are arranged. Connected alternately.
For example, in the dummy units dU1, dU3, the gate of the dummy read switch (dT12, etc.) is connected to the dummy read word line dWLr1, and the gate of the dummy write switch (dT13, etc.) is connected to the dummy write word line dWLw1.
On the other hand, in dummy units dU2 and dU4, the gate of the dummy read switch (dT22, etc.) is connected to dummy read word line dWLr2, and the gate of the dummy write switch (dT23, etc.) is connected to dummy write word line dWLw2. .
[0067]
Further, an equalize transistor Teq for short-circuiting each common node electrode dNE is provided between dummy units dU arranged on a pair of bit lines (for example, bit lines BL1 and BL2) corresponding to the same sense amplifier 2.
For example, the equalizing transistor Teq1 serves as a switch for short-circuiting the common node electrodes dNE of the dummy units dU1 and dU2 in the bit lines BL1 and BL2, and the equalizing transistor Teq2 is used for each of the dummy units dU3 and dU4 in the bit lines BL3 and BL4. It becomes a switch for short-circuiting the common node electrode dNE.
An equalize signal dEQ is supplied from the equalization control unit 11 to the gate of each equalize transistor Teq.
[0068]
As described above, in the configuration of FIG. 4, the dummy unit dU has the same configuration as the memory unit MU including the capacitor size.
A dummy unit pair that can be short-circuited by the equalizing transistor Teq is connected to the same bit line pair as the memory unit MU (a pair of bit lines corresponding to the same sense amplifier 2).
In the dummy unit pair, that is, two dummy units connected by the equalizing transistor Teq, in the dummy capacitor pair sharing the dummy plate line dPL, data “0” is stored on one side and data “1” is stored on the other side. Has been.
For example, in the dummy unit pair of the dummy units dU1 and dU2, the dummy capacitors dC11 and dC21 share the dummy plate line dPL1, but one of the dummy capacitor pair (dC11 and dC21) is “0” and the other is “1”. Is done.
Similarly, the other dummy capacitor pairs (dC12 and dC22, dC13 and dC23, dC14 and dC24) are set to "0" and the other to "1".
[0069]
In such a configuration, for example, data reading from the capacitor C11 of the memory unit MU11 and the capacitor C21 of the memory unit MU12 is performed as follows.
First, when the plate line PL11 is selected and becomes high level, different signals are applied to the gates of the gain transistors T11 and T21 depending on the storage states of the capacitors C11 and C21.
At the same time, the dummy plate line dPL1 is selected, and signals read from the dummy capacitors dC11 and dC21 are applied to the gates of the dummy transistors dT11 and dT21, respectively. At this time, one of the signals applied to the gates of the dummy transistors dT11 and dT21 is a signal corresponding to “0” and the other is a signal corresponding to “1”.
[0070]
Here, the equalization control unit 11 applies the equalization control signal dEQ to the gate of the equalization transistor Teq. Then, the equalizing transistor Teq1 is turned on, so that the common node electrode dNE of the dummy unit dU1 and the common node electrode dNE of the dummy unit dU2 are short-circuited. That is, the gate nodes of the dummy transistors dT11 and dT21 are short-circuited.
As a result, an intermediate value of the cell signals “0” and “1” is applied to the gates of both dummy transistors dT11 and dT21.
[0071]
Here, by turning on the read word line WLr1 and the dummy read word line dWLr2 at the same time, the gain transistor T11 drives the bit line BL1, and the dummy transistor dT21 drives the bit line BL2, and each bit line BL1, A read current and a reference current flow through BL2, and both potentials fluctuate. By comparing and sensing this with the sense amplifier 2-1, the stored value of the memory cell (capacitor C11) is determined.
[0072]
Further, after equalizing both the bit lines BL1 and BL2, the read word line WLr2 and the dummy read word line dWLr1 are simultaneously turned on, whereby the gain transistor T21 drives the bit line BL2, and the dummy transistor dT11 is driven by the bit line BL1. And the read current and the reference current flow through the respective bit lines BL2 and BL1, and the potentials of both of them change. By comparing and sensing this with the sense amplifier 2-1, the stored value of the memory cell (capacitor C21) is determined.
[0073]
In other capacitor pairs (capacitor C12 and capacitor C22, capacitor C13 and capacitor C23, capacitor C14 and capacitor C24), dummy capacitor pairs (dummy capacitor dC12 and dummy capacitor dC22, dummy capacitor dC13) in which data are complementarily stored, respectively. And dummy capacitor dC23, dummy capacitor dC14, and dummy capacitor dC24).
[0074]
In the fourth embodiment, an intermediate reference potential between “0” and “1” can be accurately generated in the gain memory. In addition to the same effects as those of the first to third embodiments, the temperature dependency of the memory cell itself and the marginal deterioration due to the variation of the characteristics within the chip, between chips, between wafers, and between lots are also prevented. It will be possible.
[0075]
In this example, the gates of a pair of dummy transistors (for example, dT11 and dT21) are short-circuited, but it is desirable to further short-circuit the gates of a plurality of pairs of dummy transistors. That is, the gate of the dummy transistor receiving the signal from the dummy capacitor storing “0” and the signal from the dummy capacitor storing “1” and the gate of the received dummy transistor are short-circuited. In this case, the potential applied to the gates of the dummy transistors is leveled, and variations in the reference potential due to variations in the characteristics of the dummy capacitors dC can be greatly reduced.
[0076]
By the way, as described above, in a normal DRAM or FeRAM which is not a gain type memory, an example of using a dummy cell as means for generating the reference potential Vref has been proposed. In these cases, the reference potential Vref is set to an appropriate value by adjusting the area of the dummy capacitor. However, as described above, in the gain-type memory as in this example, the adjustment of the area of the dummy capacitor dC does not have a significant advantage over the generation of the reference potential Vref. That is, in the gain type memory, it is difficult to set Vref to an appropriate value by adjusting the dummy capacitor area, and a technique similar to that of a normal DRAM or FeRAM is not appropriate.
Therefore, as in the configuration example of FIG. 4, it is appropriate to adopt a reference potential generation method based on “0” and “1” synthesis in the gain type memory. Therefore, a synergistic effect is achieved for realizing a highly reliable ultra-high integrated memory.
[0077]
In this embodiment, as in the first embodiment, a reference potential generation method is described by taking a so-called folded bit line configuration as an example. However, an open bit line configuration as in the second embodiment is described. Needless to say, the same method is effective.
[0078]
On the contrary, in the gain type memory, if the area of the ferroelectric capacitor as the dummy capacitor dC is made larger than that of the capacitor C as a normal memory cell by taking advantage of the fact that the dependence on the area is very small, the dummy capacitor The influence of dC variation can be further reduced.
[0079]
<Fifth embodiment>
In the fourth embodiment, the combination of “0” and “1” is realized by short-circuiting the gate node of the dummy transistor. This is a technique that facilitates assembly of an access sequence, but it is necessary to embed an equalizing transistor Teq in a fine cell array in terms of layout, which is disadvantageous.
On the other hand, the same effect can be obtained by generating reference potentials of “0” and “1” or reference currents on individual reference bit lines and combining them to generate an intermediate reference potential.
Further, FIG. 5 shows a fifth embodiment of the present invention in consideration of the data holding time and the rewrite frequency dependency of the read signal from the capacitor C (and dummy capacitor dC) as a memory cell.
[0080]
In the example of FIG. 5, each memory unit MU is arranged in the word line direction and the bit line direction as in FIGS.
In this example, a pair of reference bit lines dBL1 and dBL2 are arranged, and each dummy unit dU is arranged on the reference bit lines dBL1 and dBL2.
That is, dummy units dU11, dU21... Are arranged on the reference bit line dBL1, and dummy units dU12, dU22.
Each dummy unit dU has the same configuration as in FIG. For example, the dummy unit dU11 includes dummy capacitors dC11 to dC14, a dummy transistor dT11, a dummy read switch dT12, and a dummy write switch dT13.
[0081]
Each dummy unit dU shares the word line WL with the memory units MU arranged in the word line direction.
For example, in the dummy units dU11 and dU12, the gates of the dummy read switches dT12 and dT22 are connected to the read word line WLr1 connected to the gates of the read switches (T12 and the like) of the memory units MU11, MU12, and MU13.
For example, in the dummy units dU11 and dU12, the write word line WLw1 connected to the gates of the write switches (T13 and the like) of the memory units MU11, MU12 and MU13 is connected to the gates of the dummy write switches dT13 and dT23. Connected.
[0082]
Each dummy unit dU shares the plate line PL with the memory units MU arranged in the word line direction.
For example, in dummy units dU11, dU12, plate lines PL11, PL12, PL13, PL14 for each capacitor C of memory units MU11, MU12, MU13 are connected to each dummy capacitor dC.
[0083]
In this case, two dummy units dU arranged in the word line direction form a pair of dummy units.
In the two dummy units as the dummy unit pair, data “0” is stored on one side and data “1” is stored on the other side in the dummy capacitor pair sharing the plate line PL with each other.
For example, in the dummy unit pair of the dummy units dU11 and dU12, the dummy capacitors dC11 and dC21 share the plate line PL11. One of the dummy capacitor pairs (dC11 and dC21) is “0” and the other is “1”. The
Similarly, the other dummy capacitor pairs (dC12 and dC22, dC13 and dC23, dC14 and dC24) are set to "0" and the other to "1".
[0084]
Further, since each dummy capacitor dC shares the plate line PL with the capacitor C of the memory unit MU, a dummy capacitor pair is provided for each ROW address, “0” on one side and “0” on the other side. 1 "is stored.
[0085]
The pair of reference bit lines dbL1, dBL2 can be short-circuited by the equalizing transistor Teq2. Further, when the equalizing transistor Teq1 is turned on, a combined signal of the reference bit lines dBL1, dBL2 is supplied to the sense amplifiers 2-1, 2-2,.
[0086]
The read operation in such a configuration will be described by taking data read from the capacitor C connected to the plate line PL11 such as the capacitor C11 of the memory unit MU11 as an example.
When the plate line PL11 is selected and set to the high level, a different signal according to the storage state of each cell capacitor connected thereto is applied to the gate of the gain transistor of the corresponding memory unit MU. For example, a signal from the capacitor C11 is applied to the gate of the gain transistor T11.
At the same time, signals read from the dummy capacitors dC11 and dC21 are applied to the gates of the dummy transistors dT11 and dT21. In this case, one of the signals applied to the gates of the dummy transistors dT11 and dT21 is a signal corresponding to “0”, and the other is a signal corresponding to “1”.
[0087]
Next, when the read word line WLr1 is turned on, the gain transistors (T11 and the like) of the memory units MU11, MU12, and MU13 drive the bit lines BL1, BL2, and BL3, respectively. Further, the dummy transistors dT11 and dT21 of the dummy units dU11 and dU12 drive the reference bit lines dBL1 and dBL2, respectively.
Here, if the equalizing control unit 11 turns on the equalizing transistors Teq1 and Teq2 by the equalizing control signal dEQ to short-circuit the reference bit lines dBL1 and dBL2, the potentials of both are combined and the shorted reference bit lines dbL1 and dbL2 are placed on the shorted reference bit lines dbL1 and dbL2. A reference potential intermediate between “1” and “0” is generated. The current flowing through both is the sum of the read currents of “1” and “0”.
This potential is distributed as a reference potential to adjacent sense amplifier groups 2-1, 2-2, 2-3. Each sense amplifier 2-1, 2-2, 2-3 compares the read potentials of the bit lines BL 1, BL 2, BL 3 connected thereto with the reference potential distributed from the reference bit line pair dBL 1, dBL 2, The read value is determined.
In this manner, the data of the memory cell such as the capacitor C11 is determined by the sense amplifier 2.
[0088]
In such an embodiment, the same effect as in the fourth embodiment can be obtained, and the read margin can be improved.
Further, according to this example, a dummy cell (dummy capacitor dC) is provided for each row address, and a dummy cell (dummy capacitor dC) corresponding to the row address of the accessed memory cell (capacitor C) is simultaneously accessed. Become. That is, each dummy capacitor dC is always accessed simultaneously with the capacitor C row of the corresponding ROW address. Accordingly, the data holding time can be set to be equivalent to the corresponding capacitor C in the same row (on the same plate line PL), and the number of accesses is the same.
Further, the distance between the sense amplifier 2 and the gain transistor (T11, etc.) is the same as the distance between the sense amplifier 2 and the dummy transistor (dT11, etc.).
Therefore, the data retention dependency, the access frequency dependency, and the voltage drop of the bit line are all canceled out, and the read margin improvement effect becomes more remarkable.
[0089]
Here, the reference signal is distributed as a voltage to each sense amplifier 2-1, 2-2..., However, the current is mirrored to 1/2 and distributed as a reference current. A configuration may be adopted in which read determination is performed by comparing the current flowing through the bit line BL with a reference current.
[0090]
Although the pair of reference bit lines dbL1 and dBL2 are short-circuited here, a plurality of pairs of reference bit lines dbL may be arranged at equal intervals every other fixed number of sense amplifiers 2, and they may be short-circuited together. That is, the same number or substantially the same number of the reference bit line signals from which “0” data has been read and the reference bit line signals from which “1” data has been read are short-circuited. In this way, the reference potential or current is leveled, and the variation in the reference potential or reference current caused by the variation in the characteristics of the dummy capacitor can be greatly reduced.
[0091]
It should be noted that such an arrangement of dummy units is not appropriate in a normal ferroelectric memory that is not a gain type.
When the reference potential and current are distributed from the reference bit line dbL to the plurality of sense amplifiers 2 in this way, the wiring pattern is greatly different between the allocation access bit line BL and the allocation reference bit line dbL.
Therefore, a certain amount of load capacity imbalance is inevitable. Even if unbalance is adjusted by adding a capacitor or the like to the bit line BL, it is difficult to achieve perfect balance, and it is necessary to align the values on the side where the load capacitance is large. This is because if it is directly driven by a fine signal of the memory cell, a large margin deterioration occurs on the contrary. This tendency is conspicuous particularly in the case where a signal is generated on the bit line BL with a constant charge amount from the capacitor, such as a DRAM or a ferroelectric memory.
On the other hand, in the case of a gain type memory in which the bit line BL is driven by a gain transistor as in this example, the driving capability is much higher than that of direct drive from a memory cell, so the capacity of the bit line BL is larger than that of a normal memory. Can be set, and the influence of unbalanced bit line capacitance can be relatively reduced.
[0092]
In this case, it is desirable to set the bit line capacitance larger than the load capacitance of the gate node of the gain transistor (such as T11) directly driven by the memory cell.
Further, when an appropriate MOS capacitor or the like is connected to the bit line BL for adjusting the capacitance imbalance, more stable reading can be performed.
[0093]
If the drain side of the gain transistor is connected to the power source and the source side is connected to the bit line BL, the potential Vb of the bit line BL is independent of the bit line capacitance,
Vb = Vg−Vth
Converge to. Vg is a signal level applied to the gate of the gain FET, and Vth is a threshold value of the gain transistor.
Therefore, it is not easily affected by the unbalance of the bit line capacitance.
[0094]
Thus, in the gain type memory, the influence of the unbalance of the bit line pattern can be greatly reduced, and the above-described dummy unit configuration can be effectively utilized.
However, if the reference voltage and the reference current are distributed to an excessive number of sense amplifiers 2, an imbalance such as a wiring length cannot be ignored. Therefore, the distribution should be made in consideration of the trade-off between the area overhead due to the dummy units and the unbalance of the bit line capacity. Specifically, the dummy unit pairs are arranged every 4 to 64 sense amplifiers. It is desirable to provide a pair of reference bit lines dbL.
[0095]
Furthermore, it is desirable to combine the potentials or currents of a plurality of pairs of reference bit lines dbL. For example, if 1024 sense amplifiers 2 are arranged in a cell array, reference bit line pairs are arranged every 32. At that time, 32 pairs of reference bit lines are inserted, but if they are all short-circuited, the potentials of a total of 64 reference bit lines are synthesized. At this time, the fluctuation range of the reference potential due to the characteristic variation of the dummy capacitor dC is reduced to (1/8) which is the square root of (1/64) as compared with the case where a single reference bit line is used. Is done. Therefore, it is more advantageous for improving the reading margin.
[0096]
<Examples of other gain-type memories to which the present invention can be applied>
In each of the above embodiments, the case where the memory cell is formed of a ferroelectric capacitor is taken as an example. In this type of gain memory, the load capacitance driven by the selected cell capacitor is dominated by the characteristics of itself and the non-selected ferroelectric capacitor, which contains some weakly inverted ferroelectric component, The value also has temperature dependence. Therefore, as in the fourth and fifth embodiments, if a dummy unit having the same structure as that of the memory unit is provided, the reference signal is generated by the dummy capacitor, and the dummy capacitor is also used for the driving load, the temperature of the driving load is increased. The effect that can offset the dependency can also be obtained.
[0097]
However, the scope of application of the present invention is not limited to a memory in which a memory cell is composed of a ferroelectric capacitor, but a signal generated from a minute memory cell is applied to the gate of a FET (gain transistor), and the bit line is formed by the FET. The present invention can be applied to any gain type memory that reads data by driving BL.
6 to 8 show examples of other gain-type memories to which the present invention can be applied. In each figure, the gain transistor is indicated by T1, the read switch is T2, and the write switch is T3 as the same reference numerals as in FIG.
[0098]
FIG. 6 shows a DRAM in which the paraelectric capacitor C30 is a memory cell. The input signal to the node NE connected to the gate of the gain transistor T1 changes depending on the presence or absence of the accumulated charge in the capacitor C30.
Also in this case, since the parasitic capacitance of the memory cell itself occupies a large proportion of the load capacitance, it is difficult to generate an appropriate reference potential Vref by adjusting the size. Further, there is a problem that the signal level changes depending on the data holding time. Therefore, it is very effective to adopt the configuration of the same method as that of the above-described embodiment and obtain an intermediate reference signal by combining “1” and “0”, or to provide a dummy cell for each ROW address.
[0099]
In addition to the type in which the gate of the gain transistor is driven by the capacitor as described above, the gain type memory includes a type in which a signal potential is applied to the gate of the gain transistor using a memory resistor element. An example is shown in FIG.
The resistance element R1 is a memory cell that exhibits different resistance values depending on the data storage state. On the other hand, the resistance element R2 is a reference resistance element having a fixed resistance value, and is formed by a MOS transistor operated in a linear region, a diffusion layer, a polysilicon layer, or the like.
The input signal Vg to the node NE connected to the gate of the gain transistor T1 is determined by resistance division of the resistance elements R1 and R2. If the resistance value of both is r1 and r2, the value is
Vg = Vcc · r1 / (r1 + r2)
It is.
In this example, the memory resistive element R1 is connected to the ground side and the reference resistive element R2 is connected to the Vcc side, but both may be interchanged.
[0100]
For example, a magnetic junction can be used for the resistance element R1. A magnetic junction is an element in which a tunnel barrier is sandwiched between a magnetic film for storing data by changing the spin direction and a magnetic film having a fixed spin direction, and the resistance value changes according to the spin direction of the magnetic film for storage. Examples of memory using this are listed in Articles 7.2 (R. Scheuerlein, P.128) and 7.3 (M. Durlam, P.130) of ISSCC (IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE) 2000. is described.
[0101]
Further, for example, a chalcogenide film resistor can be used for the resistance element R1. Since the resistivity of the chalcogenide film changes when the crystal state changes between polycrystalline and amorphous, the resistor may be formed by sandwiching the film between electrodes. An example of a memory using this is described in ISSCC 2002 paper number 12.4 (M. Gill, p. 202).
[0102]
In addition, a stacked gate transistor or a nitride gate transistor can be used as the resistance element R1. These transistors are used as EPROMs, and their resistance values change as the threshold value changes according to the storage state. Furthermore, if these are connected in series, independent data can be stored in each.
[0103]
In the example of such a resistance type memory, there is a problem that the temperature characteristic of the reference resistance element R2 is different from the temperature characteristic of the resistance memory element R1 which is a memory cell. Therefore, it is difficult to obtain an appropriate reference potential Vref in a wide temperature range by the method of adjusting the resistance value by adjusting the cell size. In addition, there is a problem that the signal resistance changes due to the data retention time and the signal level changes. Therefore, the method of the present invention in which “1” and “0” are combined to obtain an intermediate reference signal or a dummy cell is provided for each ROW address is effective as in the case of using a capacitor for the cell.
[0104]
A constant current source may be used instead of the reference resistance element. An example is shown in FIG. An N-channel MOS (T30) operating as a constant current source is connected to the memory resistive element R1. The gate is supplied with a fixed potential so as to operate in a saturation region as a constant current source. At this time, the signal Vg applied to the node NE connected to the gate of the gain transistor T1 has a resistance value of R1 as r1 and a current flowing through T1 as i1.
Vg = Vcc- (r1 · i1)
It is.
In the case of such a memory as well, in order to cope with variations in the resistance value of the cells, the method of the present invention is obtained by synthesizing “1” and “0” to obtain an intermediate reference signal, or providing a dummy cell for each ROW address Is valid.
[0105]
The embodiments and examples of the gain-type memory to which the present invention can be applied have been described above, but the present invention can be further applied.
For example, in the above embodiment, a case has been assumed in which each memory cell stores 1 bit, that is, binary of “0” and “1”. However, the present invention can be similarly applied to the case of storing so-called multivalues. For example, when each cell stores 2 bits, the first to fourth four-level signals are given to the gate of the gain transistor in order from the lowest level, and it is necessary to make the determination.
Also in this case, a dummy cell and a dummy transistor are used, for example, the first reference potential is generated from the synthesis of the second signal and the third signal, and the read cell is first used as the first and second lower groups, Alternatively, it is determined whether it belongs to the third or fourth upper group.
Next, a second reference potential is generated by combining the first signal and the second signal, and a third reference potential is generated by combining the third signal and the fourth signal. Then, level determination in the lower group is performed using the second reference potential, and level determination in the upper group is performed using the third reference potential. In this way, the read value of each cell can be uniquely determined.
[0106]
【The invention's effect】
As can be seen from the above description, the present invention provides the following effects.
Generally, the threshold value of the gain transistor (FET) has a lot-to-lot and wafer-to-wafer dependency, and also has a strong chip-to-chip dependency in the wafer, and further a location dependency in the chip. Accordingly, there is almost no threshold difference between FETs arranged close to each other in the same chip. Therefore, as in the present invention, a dummy transistor of the same size is arranged in the vicinity of the gain transistor connected to the memory cell to be accessed, thereby driving the second bit line for reference, If the potential or current of the second bit line is used as a reference signal for read determination, it is possible to cancel the influence of threshold variation of the gain transistor, and as a result, the read margin can be greatly improved.
[0107]
In addition, by supplying a signal to the dummy transistor from a dummy cell having the same structure as the memory cell of the memory unit, it is possible to cancel the characteristic variation that occurs between chips of the memory element, between wafers, and between lots. Further, the temperature dependence similar to that of the read signal from the memory cell is generated in the gate potential of the dummy transistor. Accordingly, it is possible to prevent margin deterioration due to temperature dependency. This also improves the read margin.
[0108]
Further, by driving the bit line for reference after short-circuiting the gate nodes of the plurality of dummy transistors, the reference potential generated by the variation in the chip of the signal from the dummy cell, the variation in the remaining of the dummy transistor, or the like Variation on the reference current side can be reduced by statistical leveling.
A similar effect can be achieved by combining the potentials or currents of the plurality of second bit lines and using them as reference signals.
In particular, a signal from a dummy cell in which a first value (for example, “1”) is written using a pair or a plurality of pairs of dummy transistors or a plurality of second bit lines for reference, and a second value (for example, “ 0 ”) is short-circuited and applied to the gate of the dummy transistor, or the bit line potential or current corresponding to the first value and the bit line potential or current corresponding to the second value By combining these, it is possible to accurately generate an intermediate reference signal level when reading the first value and when reading the second value, and the above leveling can be realized appropriately. As a result, the read margin can be improved.
This is particularly effective in a gain type memory in which it is difficult to adjust the capacitor size to generate an appropriate intermediate signal.
Further, if the area of the ferroelectric capacitor of the dummy cell is made larger than that of a normal memory cell, the influence of the variation of the dummy capacitor can be further reduced.
[0109]
Further, by connecting a bit line to the source side of the gain transistor, the final bit line potential is defined only by the gain transistor, the threshold value, and the signal potential from the cell applied to the gate, and the influence of the bit line capacitance. Not receive. Therefore, the influence of the difference in bit line capacitance due to the pattern difference between the second bit line for reference and the first bit line for reading can be reduced. Alternatively, the influence of the pattern difference can be relatively reduced by increasing the bit line capacitance itself, that is, by making the bit line capacitance larger than the capacity of the node driven by the memory cell.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a configuration example of a first embodiment of the present invention.
FIG. 2 is an explanatory diagram of a configuration example of a second embodiment of the present invention.
FIG. 3 is an explanatory diagram of a configuration example of a third embodiment of the present invention.
FIG. 4 is an explanatory diagram of a configuration example of a fourth embodiment of the present invention.
FIG. 5 is an explanatory diagram of a configuration example of a fifth embodiment of the present invention.
FIG. 6 is an explanatory diagram of an example of a gain type memory that can employ the present invention;
FIG. 7 is an explanatory diagram of an example of a gain-type memory that can employ the present invention;
FIG. 8 is an explanatory diagram of an example of a gain type memory that can employ the present invention;
FIG. 9 is an explanatory diagram of a configuration of a gain type memory.
FIG. 10 is an explanatory diagram of a configuration of a gain-type memory that performs reading using a reference potential;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Reference potential generation circuit, 2, 2-1, 2-2 ... Sense amplifier, 10 Dummy unit row, 11 Equalize control part, MU, MU11, MU12 ... Memory unit, WL Word line, WLw1, WLw2,. .. Write word line, WLr1, WLr2 ... Read word line, BL, BL1, BL2 ... Bit line, PL, PL11, PL12 ... Plate line, T11, T21 Gain transistor, T12, T22 Read Switch, T13, T23 Write switch, dT11, dt12 Dummy transistor, dU, dU1, dU2 Dummy unit

Claims (2)

Multiple bit lines,
One or a plurality of memory cells to generate a read potential corresponding to the storage value in the predetermined node, a memory unit having a gain transistor that drives the bit line corresponding based on the read potential generated in the node In a semiconductor memory device including a memory array arranged corresponding to each of the plurality of bit lines ,
A dummy transistor having the same size as the gain transistor for driving the corresponding bit line based on the potential generated at the gate node, and having the same structure as the memory cell. Reference driving means having one or a plurality of dummy cells for generating a potential corresponding to a stored value at the gate node ;
Among the plurality of bit lines, a short-circuit means for short-circuiting the gate nodes of the dummy transistors of the reference driving means provided corresponding to two bit lines paired with each other;
When one of the paired two bit lines is driven by the gain transistor of the memory unit and the other is driven by the dummy transistor of the reference driving means, each of the two bit lines is A read value determination means for determining a value of data read from the memory unit by comparing both flowing currents or both potentials of the two bit lines ;
A semiconductor memory device. The short-circuit means has the same or substantially the same number of the gate nodes to which the first value signal read from the dummy cell is applied and the gate nodes to which the second value signal read from the dummy cell is applied. The semiconductor memory device according to claim 1 , wherein the same number is short-circuited.

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