JP4167343B2 - Drive element split drive control device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a divided drive control method and a divided drive control apparatus for driving a drive element such as a heating element in a thermal head and a capacitive element in an inkjet head in a divided manner.
[0002]
[Prior art]
As this type of drive control device, for example, there is a thermal head drive device that divides and drives a drive element of a thermal head constituted by arranging a plurality of drive elements such as heating elements.
FIGS. 19 and 20 show a circuit diagram and a timing diagram of four-division drive having a print data buffer of one line in such a conventional thermal head driving device, respectively.
[0003]
This device comprises a plurality of driving elements 1, a transistor array 2, a 3-input AND gate 3, a latch circuit 4, and a shift register 5. In such a device, when driving the thermal head, serial data (SD) is transferred to the shift register 5 by a shift clock (SCK). When the transfer is completed, the data on the shift register 5 is transferred to the latch circuit 4 by the latch signal (LT).
[0004]
The data latched by the latch circuit 4 has a one-to-one correspondence with the driving element 1. In order to drive the heating element 1 in such a way as to divide into four parts, the period between the latch signals (LT) is divided into four parts, and a division enable (G1 to G4) for driving each group. Is supplied from the outside.
[0005]
The division enable (G1 to G4) is input to the 3-input AND gate 3, and the driving element 1 can be driven for each group by validating the data corresponding to the group.
[0006]
Further, a strobe signal (STB) is input to all of the three-input AND gates 3 to control the energization time. The data of the selected group is input to the transistor array 2 and drives the drive element 1 according to the energization time of the strobe signal (STB).
[0007]
Since the above is for four-division driving, four division enables are required. However, for three-division driving, three division enables are required.
[0008]
FIG. 21 and FIG. 22 show circuit diagrams and timing diagrams of other thermal head driving devices, respectively. When division driving is performed with such an apparatus, the print data buffer composed of a shift register and a latch can be driven as 1 / division number. Since the case shown in FIG. 21 is a case where four-division driving is performed, the print data buffer is set to ¼.
[0009]
21 differs from that shown in FIG. 19 in that the print data buffer is composed of a combination of the ¼ shift register 6 and the ¼ latch circuit 7. This reduces the number of circuits. Further, the latch signal (LT), the division enable (G1 to G4), and the strobe signal (STB) are sequentially supplied in units of this division drive.
[0010]
In the two thermal head driving devices shown in FIGS. 19 and 21, in order to drive the drive element in a divided manner, serial data (SD) and shift clock (SCK) as drive information necessary for driving the head. In addition to the signals of the latch signal (LT) and the strobe signal (STB), the division enable (G1 to G4) is necessary, so that the total number of signal lines is eight. Here, the case of four-division driving has been described, but the number of signal lines increases as the number of divisions increases. Thus, in order to divide and drive the head, many control lines are required, and there is a problem that a connector for connection is required to have a multi-pin.
[0011]
In order to avoid such an increase in the number of signal lines, there is a technique disclosed in Japanese Patent Laid-Open No. 7-290707 as an apparatus that performs division driving while reducing the number of signal lines. A circuit diagram and a timing diagram of this thermal head driving device are shown in FIGS. 23 and 24, respectively.
[0012]
This apparatus is provided with a controller 8, inputs a shift clock (SCK), and generates a split enable (G 1 to G 4) and a latch signal (LT) by a counter built in the controller 8, thereby externally. The division enable (G1 to G4) signals need not be input, and the number of signal lines is reduced.
[0013]
This controller 8 has a reset signal (RST) for initialization, and performs a reset operation before printing. Note that the control timing shown in FIG. 24 is the same as the control timing shown in FIG. 22 except that a reset is required and the divided drive cycle is not used.
[0014]
[Problems to be solved by the invention]
However, in the apparatus shown in FIG. 23 as described above, the number of signal lines can be certainly reduced, but a shift clock (SCK) is input and division enable (G1 to G4) is performed by the counter of the controller 8. Since the latch signal (LT) is generated, there is a problem that the divided drive cycle cannot be changed.
[0015]
Therefore, in such an apparatus, for example, when printing is performed by driving the head in the main scanning direction, the operation of the head in the main scanning direction is detected by an encoder pulse, and this is used to print in the main scanning direction. Since the timing cannot be adjusted, the printing timing is shifted and a good printing result cannot be obtained.
[0016]
Further, if the division drive cycle cannot be changed, a good print result may not be obtained in the same manner even when the heads are configured by shifting the drive element groups provided in the division units.
[0017]
In addition, since the order of division enable (G1 to G4) cannot be changed, the order of division driving is fixed, and there is a problem that it can be applied only to printing in a specific direction. This lacks flexibility and is disadvantageous in terms of performance and cost.
[0018]
However, since the apparatus shown in FIGS. 19 and 21 has a configuration in which the division enable (G1 to G4) is separately supplied from the outside, it is possible to change the division driving cycle or arbitrarily change the order of the division driving. However, as described above, an increase in the number of signal lines is inevitable. This is disadvantageous particularly when used with a plurality of driving devices.
[0019]
Accordingly, the present invention is intended to provide a drive element split drive control device that can arbitrarily change the drive cycle and the order of drive division with a small number of signal lines.
[0020]
[Means for Solving the Problems]
The present invention of claim 1 divides a plurality of drive elements into a plurality of groups, and in a drive drive divided drive control apparatus that drives each group, the activation information for taking drive timing for each group of drive elements includes: Control means including a function for generating a group selection signal based on timing obtained by detecting the activation information when it is input in synchronization with drive information for driving each drive element, and drive information is stored And a drive unit that selects a group of drive elements to be driven based on a group selection signal from the control unit and drives the drive element based on drive information stored in the storage unit. This is a split drive control device for a drive element characterized by the following.
[0021]
According to a second aspect of the present invention, in the driving element according to the first aspect, the control means generates a group selection signal for selecting a group in order at each timing obtained by detecting the activation information. This is a split drive control device.
[0022]
According to a third aspect of the present invention, the control means inputs the drive information and the group designation information for designating and selecting the group of the drive elements in a time-division manner and configured by one signal line, and detects the group designation information. 2. The divided drive control device for a drive element according to claim 1, wherein a group selection signal for selecting a group designated by the group designation information is generated every time.
[0023]
According to a fourth aspect of the present invention, there is provided the drive element split drive control apparatus according to the first aspect, wherein the drive information and the activation information are constituted by separate and independent signal lines.
[0024]
According to a fifth aspect of the present invention, in the drive element divided drive control device according to the first aspect of the present invention, the drive information and the activation information are constituted by one time-divided signal line.
[0025]
According to a sixth aspect of the present invention, the control means is configured to generate a group selection signal for sequentially selecting a group at each timing obtained by detecting the activation information, and to select the drive information and the group of drive elements. 2. The drive according to claim 1, wherein initialization information for initializing is input in a time-sharing manner and configured by one signal line, and group selection is initialized each time the initialization information is detected. It is an element split drive control device.
[0026]
According to a seventh aspect of the present invention, in the drive element split drive control apparatus that divides a plurality of drive elements into a plurality of groups and drives each group, the selection control information includes drive information and time for driving each drive element. Control means including a function for generating a group selection signal based on the selection control signal when inputted through one division multiplexed signal line, storage means for storing drive information, and group selection signal from the control means A drive element split drive control device comprising: a drive unit that selects a group of drive elements to be driven based on the drive information; and a drive unit that drives the drive element based on drive information stored in the storage unit is there.
[0027]
According to the present invention of claim 8, when the selection control information including the activation information is input, the control means generates a group selection signal for selecting a group in order at each timing obtained by detecting the activation information. 8. The divided drive control device for a drive element according to claim 7, wherein
[0028]
In the present invention of claim 9, the control means inputs selection control information including group designation information for selecting a group of drive elements, and each time the group designation information is detected, the group designated by the group designation information is selected. 8. The divided drive control apparatus for a drive element according to claim 7, wherein a group selection signal to be selected is generated.
[0029]
The present invention of claim 10 is configured such that the control means generates a group selection signal for selecting a group in order for each timing obtained by detecting the activation information included in the selection control information. 8. The divided drive control device for a drive element according to claim 7, wherein the group selection is initialized every time detection information included in the control information and initialization information for initializing group selection of the drive elements are detected. .
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
[0031]
FIG. 1 is a circuit diagram showing a configuration of a divided drive control apparatus according to the present embodiment, in which 11 is a plurality of drive elements such as heat generation elements and capacitive elements connected to a power supply Vcc, and 12 is a drive for each drive element 11. A transistor array including transistors to be operated, 13 is a three-input AND gate that drives the transistor array 12 of the corresponding drive element 11, and 14 is data that drives a group of one drive element 11, that is, 1 / division of data for one line A latch circuit as a latch means for latching a number of data (in this case, 1/4 because it is divided into four), and 15 is a 1/4 as a storage means for storing 1/4 of the data for one line. A shift register 16 is a controller as control means.
The transistor array 12 and the 3-input AND gate 13 apply a drive signal based on the serial data (SD) to the drive elements of the group selected by the division enable (G1 to G4) according to the timing of the strobe signal (STB). The drive means for driving this is configured.
[0032]
The controller 16 is activated by receiving a control signal (STBI) as activation information input in units of divisions in order to switch the group of driving elements 11 to be driven. The group of driving elements 11 to be driven is driven. The division enable (G1 to G4) as the group selection signal for selecting the data, the latch signal (LT) as the control signal for latching data in the latch circuit 14, and the serial data (SD) as the drive information in the shift register 15 A data transfer enable (DSE) as a control signal for transfer and a strobe signal (STB) as a control signal for driving the drive element 11 are generated and supplied. The control signal (STBI) is input in synchronization with serial data (SD) as drive information.
Conventionally, data is transferred to the shift register 5 or 7 by the shift clock (SCK) as shown in FIGS. 19, 21, and 23. In this embodiment, data is transferred to the shift register 15. Data is transferred during a period when the transfer enable (DSE) is valid.
[0033]
23, the shift clock (SCK) is input to the controller 8 and the shift register 7. In the present embodiment, the shift to the controller 16 and the shift register 15 is performed. Instead of the clock (SCK), the system clock (MCK) is always input. Further, the reset signal (RST) is input for the initialization of the controller 16 as in the case shown in FIG.
[0034]
Next, the print drive control timing of this apparatus will be described with reference to FIG.
When the control signal (STBI) is input to the controller 16 after the controller 16 is reset by supplying the reset signal (RST), the data transfer enable (DSE) is transferred from the controller 16 to the shift register 15. It is generated according to the length and is input to the shift register 15. The serial data (STBI) is synchronized with the control signal (STBI) in a predetermined time after the control signal (STBI) is input, that is, in a period when the data transfer enable (DSE) is valid (in FIG. 2, when it is H level). When SD) is input, data transfer to the shift register 15 is performed. This eliminates the need to input a signal from the outside of the apparatus according to the data transfer length.
[0035]
The data transferred to the shift register 15 is latched by the latch circuit 14 in response to a latch signal (LT) from the controller 16, and the latched data is divided and enabled (G1 to G4) and strobe from the controller 16. The signal (STB) is input to the 3-input AND gate 13 and the output from the 3-input AND gate 13 drives the transistor array 12 to drive the corresponding drive element 11.
[0036]
As a result, the control signal (STBI) as the activation information and the serial data (SD) as the drive information are synchronously input to the apparatus at a specific time interval, thereby driving the drive element 11. Divided drive control can be performed. That is, since the input cycle of the control signal (STBI) and serial data (SD) corresponds to the divided drive cycle, the divided drive cycle can be easily set by changing the input cycle of the control signal (STBI) and serial data (SD). Can be changed.
[0037]
Next, the circuit configuration of the controller 16 will be described with reference to FIG.
The controller 16 includes a circuit 21 that detects the rise of the control signal (STBI), a circuit 22 that generates a data transfer enable (DSE), a circuit 23 that generates a latch signal (LT), and a division enable (G1 to G4). It comprises a circuit 24 for generating and a circuit 25 for generating a strobe signal (STB).
[0038]
The rise detection circuit 21 includes two D flip-flops 26 and 27 and a two-input AND gate 28. When the control signal (STBI) is input, the rise detection circuit 21 detects the rise and outputs a detection signal T from the 2-input AND gate 28.
[0039]
The transfer enable generation circuit 22 includes a JK flip-flop 31 and a data transfer length counter 32 that counts the data transfer length. When the transfer enable generation circuit 22 receives the detection signal T from the rise detection circuit 21, the output Q of the JK flip-flop 31 changes from the L level to the H level, and this output directly changes to the data transfer enable (DSE). The data transfer length counter 32 is activated. When the data transfer length counter 32 counts up, the output of the JK flip-flop 31 changes from H level to L level. As a result, the data transfer enable (DSE) becomes L level.
[0040]
The latch generation circuit 23 includes a JK flip-flop 33, a 2-input AND gate 34, and a NOT gate 35. When the first detection signal T from the rising detection circuit 21 is input to the latch generation circuit 23, the Q output of the JK flip-flop 33 is at the L level, so the output of the 2-input AND gate 34 remains at the L level. is there.
[0041]
At this time, since the Q output of the JK flip-flop 33 becomes H level, when the second and subsequent detection signals T are input, an internal activation signal (ST) serving as a starting point for driving the drive element is generated from the 2-input AND gate 34. To do. This internal activation signal (ST) is output as a latch signal (LT) via the NOT gate 35.
[0042]
The division enable generation circuit 24 includes a group switching counter 36 and a decoder 37. The division enable generation circuit 24 counts the internal activation signal (ST) from the two-input AND gate 34 of the latch signal generation circuit 23 by the group switching counter 36, so that the number of divisions (in this embodiment, four-division driving). Since there are 1 to 4). The output from the group switching counter 36 is decoded by the decoder 37, and any one of the division enables G1 to G4 corresponding to this is selected and output. Thereby, the division enables G1 to G4 are sequentially switched and outputted in the order in which the internal activation signal (ST) is generated, that is, in the order in which the detection signal T from the rising detection circuit 21 is detected.
[0043]
The strobe signal generation circuit 25 includes a JK flip-flop 38, a strobe counter 39, and a strobe decoder 40. When the strobe signal generation circuit 25 receives the internal activation signal (ST) from the 2-input AND gate 34 of the latch signal generation circuit 23, STBE is output from the JK flip-flop 38. The output counted by the strobe counter 39 is converted by the strobe decoder 40 and output as a strobe signal (STB).
[0044]
FIG. 4 shows the operation timing of such a controller 16.
First, when the control signal (STBI) is input to the rising detection circuit 21, the rising of the control signal (STBI) is detected, and the detection signal T is output from the 2-input AND gate 28.
[0045]
When this detection signal T is input to the JK flip-flop 31 of the transfer enable generation circuit 22, the output Q of the JK flip-flop 31 changes from L level to H level. As a result, the data transfer length counter 32 is started from the detection signal T as a starting point, and a data transfer enable (DSE) is output (in this case, it is in the H level state).
[0046]
Next, the second and subsequent rises in the control signal (STBI) become a latch signal (LT) via the NOT gate 35 as an internal activation signal (ST) and activate the strobe counter 39. The value of the strobe counter 39 is converted by the strobe decoder 40 to generate a strobe signal (STB).
[0047]
Further, this internal activation signal (ST) causes the operation of this counter as an enable of the group switching counter 36. The output QG of the group switching counter 36 is decoded by the decoder 37 to generate division enable (G1 to G4). In this case, the division enable (G1 to G4) is sequentially generated according to the count of the group switching counter 36.
[0048]
As described above, when the control signal (STBI) is input, the drive elements are sequentially driven for each group starting from the rising edge, and a series of drive control within the division cycle is performed.
[0049]
As described above, when the control signal (STBI) as the activation information is input in synchronization with the serial data (SD) as the drive information in the controller 16, the rise of the control signal (STBI) is detected. Since the division enable (G1 to G4) is generated based on the above, the division driving cycle can be easily changed by changing the input cycle of the control signal (STBI) and the serial data (SD).
[0050]
Thereby, for example, when printing is performed by driving the head in the main scanning direction, the operation of the head in the main scanning direction is detected by the pulse of the encoder, and this is used to adjust the print timing in the main scanning direction. Therefore, a good printing result can be obtained. In addition, even when the heads are configured by shifting each drive element group provided in divided units, the print timing can be easily adjusted, so that a good print result can always be obtained.
[0051]
In addition, the controller 16 generates not only the division enable (G1 to G4) but also the latch signal (LT) and the strobe signal (STB) in division units by the rising of the control signal (STBI). ) And serial data (SD) alone are input to the division unit, so that the drive element can be divided and controlled. Thereby, the total number of signal lines can be reduced.
[0052]
When a control signal (STBI) is input to the controller 16, a data transfer enable (DSE) is generated, and serial data (SD) is input during a period in which the data transfer enable (DSE) is valid, and shift is performed. Data transfer to the register 15 is performed. As a result, it is not necessary to input a signal from the outside of the apparatus according to the data transfer length, and this can also reduce the number of signal lines.
[0053]
Next, a second embodiment of the present invention will be described with reference to FIGS. In addition, the same code | symbol is attached | subjected to the part same as the part in the said embodiment, and the detailed description is abbreviate | omitted. The device in the first embodiment can change the division drive cycle, but the device in the present embodiment can change not only the division drive cycle but also the division drive order. .
[0054]
FIG. 5 is a circuit diagram showing the configuration of the divided drive control apparatus according to the present embodiment. The difference from that shown in FIG. 1 is that serial data (SD) is not directly supplied to the shift register 15, but serial data The serial data (SDA1) provided with a division flag as group designation information indicating the division order at the beginning of (SD) is supplied to the controller 41 and then supplied to the shift register 15. That is, unlike the one shown in FIG. 1, the controller 41 as the control means in the present embodiment selects and outputs the division enable (G1 to G4) designated by the division flag of the serial data (SDA1). It has become.
[0055]
As shown in FIG. 6, the printing drive control timing of this apparatus is substantially the same as the timing shown in FIG. 2, but differs in that the division enable (G1 to G4) is arbitrarily switched depending on the contents of the division flag.
[0056]
Next, the circuit configuration of the controller 41 will be described with reference to FIG.
The controller 41 inputs serial data (SDA1) having a division flag and supplies it to the shift register 15 as serial data (SDA2), and division of the serial data (SDA2) from the D flip-flop 42 A 2-bit shift register 43 that detects the flag and outputs it as divided data (DVFD), a circuit 44 that detects the rising edge of the control signal (STBI), and only when the dividing flag is detected when the rising edge of the control signal is detected A circuit 45 that delays subsequent operations such as data transfer, a circuit 46 that generates a transfer enable, a circuit 47 that generates a latch signal (LT), a circuit 48 that generates a division enable (G1 to G4), and a strobe signal (STB) Is constituted by a circuit 49 for generating.
[0057]
The rise detection circuit 44 includes two D flip-flops 51 and 52 and a 2-input AND gate 53, detects the rise of the control signal (STBI), and outputs a detection signal T. The rise detection circuit 44 performs the same operation as the rise detection circuit 21 shown in FIG.
[0058]
The delay circuit 45 includes a JK flip-flop 54, a 2-input AND gate 55, and a D flip-flop 56. When the detection signal T from the rise detection circuit 44 is output, the delay circuit 45 shifts the timing only while the 2-bit shift register 43 detects the division flag of the serial data (SDA2), and the D flip-flop 56 Output from the Q terminal.
[0059]
That is, the timing of the control signal (STBI) and the serial data (SDA1) is adjusted by the delay circuit 45.
The output from the Q terminal of the JK flip-flop 54 is an internal signal (DVFE) indicating the division flag enable. Since the internal signal (DVFE) is at the H level while the division flag is detected, the delay circuit 45 uses the internal signal (DVFE) to determine the division flag and data in the serial data (SDA2). It can be said that the discrimination is performed.
[0060]
The transfer enable generation circuit 46 includes a JK flip-flop 57 and a data transfer length counter 58 that counts the data transfer length, and generates a transfer enable (DSE) from the output from the D flip-flop 56 of the delay circuit 45 as a starting point. . As a result, since transfer enable (DSE) is generated with a delay only during detection of the division flag, only the drive data portion excluding the division flag of the serial data (SDA2) is transferred to the shift register 15.
[0061]
The latch signal generation circuit 47 is composed of a JK flip-flop 59, a two-input AND gate 60, and a NOT gate 61. The output from the D flip-flop 56 of the delay circuit 45 is the same as the latch generation circuit 23 shown in FIG. A start signal (ST) is output. This internal activation signal (ST) is output as a latch signal (LT) via the NOT gate 61.
[0062]
The division enable generation circuit 48 includes a 2-bit latch 62 and a decoder 63. The 2-bit latch 62 inputs the internal activation signal (ST) from the 2-input AND gate 60 of the latch signal generation circuit 47 to the LD terminal, thereby latching the divided data (DVFD) from the 2-bit shift register 43. . The decoder 63 decodes the divided data latched by the 2-bit latch 62, and selects and outputs one of the division enables (G1 to G4) according to the decoded data.
[0063]
The strobe signal generation circuit 49 includes a JK flip-flop 64, a strobe counter 65, and a strobe decoder 66. The operation is the same as that of the strobe signal generation circuit 25 shown in FIG. 3, and the internal activation signal (ST) is input. Then, a strobe signal (STB) is output.
[0064]
The operation timing of the circuit of the controller 41 will be described with reference to FIG. First, a control signal (STBI) is input, and after a specific time interval, a 2-bit division flag (DVF) as shown by the hatched portion in FIG. 8 and subsequent data are synchronized with the control signal (STBI). Serial data (SDA1) consisting of
[0065]
The serial data (SDA2) is supplied to the shift register 15 through the D flip-flop 42 as serial data (SDA1).
Further, when the control signal (STBI) is input to the rise detection circuit 44, the rise of the control signal (STBI) is detected, and the division flag enable (DVFE) is generated (H level) for 2 bits in the delay circuit 45. After that, the latch signal generation circuit 47 generates an internal activation signal (ST).
[0066]
During the 2 bits in which the division flag enable (DVFE) is generated, the serial data (SDA2) is supplied to the 2-bit shift register 43, the division flag is detected, and is output as the division data (DVFD).
[0067]
Then, the internal activation signal (ST) is latched by the 2-bit latch 62 of the division enable generation circuit 48, which is decoded by the decoder 63 to generate division enables (G1 to G4). At this point, the group switching counter 36 counts the detection signal T at the rise of the control signal (STBI) and decodes the value to generate the division enable (G1 to G4) in the first embodiment shown in FIG. Different from the circuit shown in.
[0068]
The circuit according to the present embodiment is activated by the rise of the control signal (STBI) and generates the data transfer enable (DSE), the latch signal (LT), and the strobe signal (STB). In the circuit shown in FIG. 3, the circuit shown in FIG. 3 generates a data transfer enable (DSE), a latch signal (LT), and a strobe signal (STB) based on the detection signal T. In the circuit shown in FIG. 7 in the present embodiment, only after the detection signal T from the rise detection circuit 44 is output, the delay circuit 45 detects the division flag of the serial data (SDA2) by the delay circuit 45. After the delay, the data transfer enable (DSE) is generated and latched by the internal start signal (ST) delayed similarly. No. (LT), the strobe signal (STB), divided enable (G1 to G4) is generated.
[0069]
As described above, when the control signal (STBI) is input, the drive elements of the group specified by the division data in the division flag of the serial data (SDA1) are driven from the rising edge, and a series within the division cycle is driven. The drive control is performed.
[0070]
As described above, when the control signal (STBI) as the start signal and the serial data (SDA1) as the drive information are input in synchronization in the controller 41, the rise of the control signal (STBI) is detected. Since the division enable (G1 to G4) is generated based on the above, the division drive cycle can be easily set by changing the input cycle of the control signal (STBI) and the serial data (SDA1) as in the first embodiment. Can be changed.
[0071]
In addition to this, in the present embodiment, the drive elements of the group specified by the division data in the division flag of the serial data (SDA1) can be driven. Can also be changed arbitrarily. As a result, the present invention can be applied regardless of the direction of printing, which is advantageous in terms of flexibility, performance, and cost as compared with the prior art.
[0072]
Moreover, in the same manner as in the first embodiment, the controller 41 generates not only the division enable (G1 to G4) but also the latch signal (LT) and strobe signal (STB) in units of division by the rise of the control signal (STBI). Therefore, the drive element can be divided and controlled by inputting only the control signal (STBI) and the serial data (SD) to the division unit. Thereby, the total number of signal lines can be reduced.
[0073]
Next, a third embodiment of the present invention will be described with reference to FIGS. The same reference numerals are given to the same parts as those in the above embodiment, and the detailed description thereof is omitted.
The devices in the first and second embodiments perform split driving at the rising edge of the control signal (STBI) as activation information. However, the device in the present embodiment replaces this control signal (STBI). Serial data (SDB1) as selection control information provided with a start flag (solid solid portion) as start information as shown in FIG. 10 or FIG. Is input to the controller 71, and the controller 71 is activated based on the activation flag to perform drive control in which the division cycle can be arbitrarily changed.
[0074]
FIG. 9 is a circuit diagram showing the configuration of the split drive control apparatus according to the present embodiment. The difference from FIG. 1 is that the control signal (STBI) is not input to the controller 71, and the controller 71 is that serial data (SDB1) provided with a start flag as start information is input to 71 instead of serial data (SD).
[0075]
FIG. 10 shows the print drive control timing in such a divided drive control apparatus. In this embodiment, since the control signal (STBI) is not used, the control signal (STBI) is deleted as compared with that shown in FIG. Further, the timing is substantially the same as the timing shown in FIG. 2 except that the controller 71 is activated based on the activation flag instead of the rise of the control signal (STBI).
[0076]
Next, the circuit configuration of the controller 71 will be described with reference to FIG.
The controller 71 includes a circuit 72 for detecting a start flag (first 1 bit) of serial data (SDB1), a circuit 22 for generating a data transfer enable (DSE), and a NOT gate 73 for disabling the detection of the start flag. , A circuit 23 for generating a latch signal (LT), a circuit 24 for generating a division enable (G1 to G4), and a circuit 25 for generating a strobe signal (STB).
[0077]
3 differs from the circuit shown in FIG. 3 in that an activation flag detection circuit 72 composed of two D flip-flops 74 and 75 and a three-input AND gate 76 is provided in place of the rise detection circuit 21. The serial data (SDB1) provided with the start flag is input, the start flag is detected and the detection signal T is output, and the data transfer enable (DSE) which is the output Q of the JK flip-flop 31 in the data transfer enable generation circuit 22 ) Is input to the 3-input AND gate 76 via the NOT gate 73 to disable the detection of the start flag while the data transfer enable (DSE) is being output. The serial data (SDB1) is converted to D The data is output as serial data (SDB2) via the flip-flop 74 and is shifted. Is a point to be supplied to the static 15.
[0078]
FIG. 12 shows the operation timing of such a controller 71.
The serial data (SDB1) is composed of a 1-bit activation flag and data, and the other stationary parts are at the L level. This activation flag is at a level opposite to that of the steady portion, and is at the H level in the present embodiment. The activation flag is detected by the two-stage D flip-flops 74 and 75 and the 3-input AND gate 76, and the data transfer length counter 32 is activated by the detection signal T to perform data transfer control.
[0079]
At this time, the data transfer enable (DSE) is inverted by the NOT gate 73 and fed back to the 3-input AND gate 76 as a mask signal (MSK). As a result, the activation flag detection circuit 72 disables the detection of the activation flag during data transfer.
[0080]
When the serial data transfer to the shift register 15 is completed, the data transfer enable (DSE) becomes L level, so that the mask signal (MSK) becomes H level, and the activation flag detection circuit 72 re-enables detection of the activation flag. To do. In this way, the activation flag and data are discriminated.
[0081]
When the second and subsequent activation flags are input, an internal activation signal (ST) is generated this time, and by driving the internal circuit, a strobe signal (STB), a division enable (G1 to G4), a latch signal (LT) ) Is generated and output.
[0082]
As described above, when the serial data (SDB1) provided with the activation flag is input, the drive elements are sequentially driven for each group starting from the detection of the activation flag, and a series of drive control within the division cycle is performed. Done.
Thus, when the serial data (SDB1) provided with the activation flag as the activation information is input in the controller 71, the activation flag is detected, and the division enable (G1 to G4) is generated based on the detected activation flag. Therefore, by changing the input period of the serial data (SDB1), the division drive period can be easily changed, the control signal (STBI) can be made unnecessary, and the number of signal lines of the entire apparatus is further reduced. Can be made.
[0083]
The fourth embodiment of the present invention will be described below with reference to FIGS. In addition, the same code | symbol is attached | subjected to the part same as the part in the said embodiment, and the detailed description is abbreviate | omitted. Further, the circuit diagram of the split drive control device in the present embodiment is the same except that SDB1 and SDB2 shown in FIG. 9 are changed to SDC1 and SDC2, respectively, and thus detailed description thereof is omitted.
[0084]
In the third embodiment, by providing a start flag in the serial data (SD), it becomes possible to control the drive of the apparatus while changing the division drive cycle. As in the first embodiment, the group switching counter 36 is used. On the other hand, in the present embodiment, as the selection control information provided with the division flag as the group designation information for designating the division enable (G1 to G4) following the activation flag as the activation information in the serial data (SD). By performing drive control based on the serial data (SDC1), not only the control signal (STBI) is required, but also the division drive order can be arbitrarily changed.
[0085]
The circuit configuration of the controller 71 as the control means in the present embodiment will be described with reference to FIG.
The controller 71 detects a start flag (first 1 bit) of the serial data (SDC1), detects a division flag (next 2 bits of the start flag) of the serial data (SDC1) and detects it. 2-bit shift register 43 that outputs as divided data (DVFD), circuit 45 that delays subsequent operations such as data transfer only when the activation flag is detected, circuit 46 that generates transfer enable, activation A 2-input NOR gate 80 for disabling flag detection, a circuit 47 for generating a latch signal (LT), a circuit 48 for generating a division enable (G1 to G4), and a circuit 49 for generating a strobe signal (STB) Is done.
[0086]
7 differs from the circuit shown in FIG. 7 in that an activation flag detection circuit 72 composed of two D flip-flops 74 and 75 and a three-input AND gate 76 is provided in place of the rise detection circuit 44. Serial data (SDC1) provided with a start flag is input, the start flag is detected and a detection signal T is output, and data transfer enable (DSE) and division flag enable (DVFE) in the data transfer enable generation circuit 46 are set. The detection of the activation flag is disabled while transferring the division flag and data by inputting to the 3-input AND gate 76 via the 2-input NOR gate 80, and the D flip-flop 42 is eliminated. Serial data (SDC1) is converted to serial data via D flip-flop 74. Is that supplies the output to the shift register 15 as SDC2).
[0087]
FIG. 14 shows the operation timing of such a controller 71.
The serial data (SDC1) is composed of a 1-bit activation flag that is time-division multiplexed, followed by a 2-bit division flag (DVF), and further data, and the other stationary portions are at the L level. This activation flag is at a level opposite to that of the steady portion, and is at the H level in the present embodiment. The operation timing after detecting the activation flag is substantially the same as that shown in FIG.
[0088]
However, the present embodiment is different in that the division flag enable (DVFE) and the data transfer enable (DSE) are NORed by the NOR gate 80 and fed back to the 3AND gate 76 as a mask signal (MSK). As a result, the activation flag detection circuit 72 disables detection of the division flag and the activation flag during data transfer. When the transfer is completed, the mask signal (MSK) becomes H level, and the detection of the activation flag is enabled again. In this way, the activation flag and the division flag are distinguished from the data. This is because, in this embodiment, since not only the start flag but also the division flag is put on the serial data (SDC1), it is necessary to delay the data transfer and the subsequent control drive.
[0089]
As described above, in this embodiment, when the controller 71 receives the serial data (SDC1) provided with the activation flag and the division flag as the activation information, the division enable (G1 to G4) is performed based on the serial data (SDC1). Since it is generated, the divided drive cycle can be easily changed by changing the input cycle of serial data (SDC1) as in the third embodiment, and the control signal (STBI) is not required. And the number of signal lines in the entire apparatus can be further reduced.
[0090]
In addition, in the present embodiment, as in the second embodiment, the drive elements of the group specified by the divided data in the divided flag of the serial data (SDC1) can be driven, so that the divided drive cycle Not only that, the order of division driving can be arbitrarily changed.
[0091]
Hereinafter, a fifth embodiment of the present invention will be described with reference to FIGS. In addition, the same code | symbol is attached | subjected to the part same as the part in the said embodiment, and the detailed description is abbreviate | omitted. Further, the circuit diagram of the divided drive control device in the present embodiment is the same except that SDA1 and SDA2 shown in FIG. 5 are changed to SDD1 and SDD2, respectively, and detailed description thereof will be omitted.
[0092]
In the case where the divided signals (G1 to G4) are generated by the count of the group switching counter 36 as in the first embodiment, if the group switching counter 36 is shifted due to noise or the like, the subsequent division is performed. There is a possibility that the driving result is shifted and the printing result becomes poor. On the other hand, in this embodiment, the group switching counter 36 is periodically initialized (initial value load or reset) to minimize the influence of the division counter due to noise or the like.
[0093]
FIG. 15 is a diagram showing a circuit configuration of the controller 71 as the control means in the present embodiment, which differs from that shown in FIG. 3 in the first embodiment in that the initialization information is converted into serial data (SD). The serial data (SDD1) provided with the initialization flag is input, and a 2-input NAND gate 81 is provided for periodically initializing the group switching counter 36 before driving each group of drive elements. The serial data (SDD1) and the internal start signal (ST) output from the 2-input AND gate 34 are input to the 2-input NAND gate 81, and the output of the 2-input NAND gate 81 is input to the group switching counter 36. The point connected to the reset terminal is that the serial data (SDD1) is supplied to the shift register 15 as (SDD2).
[0094]
FIG. 16 shows the print drive control timing in such a divided drive control apparatus. Serial data (SDD1) and a control signal (STBI) synchronized therewith are input to the controller 71, the rise of the control signal (STBI) is detected, and the detection signal T (H level) is output from the rise detection circuit 21. If the initialization flag of the serial data (SDD1) is at the H level, the output of the 2-input NAND gate 81 becomes the L level, and the group switching counter 36 is initialized.
[0095]
Even if detection signal T (H level) is output from rising detection circuit 21, if the initialization flag of serial data (SDD1) is at L level, the output of 2-input NAND gate 81 is at H level. The group switching counter 36 is not initialized.
[0096]
As described above, the 2-input NAND gate 81 is provided, and the group switching counter 36 can be periodically initialized by the initialization flag of the serial data (SDD1). Thereby, in addition to having the same effect as that of the first embodiment, it is possible to prevent the count of the group switching counter 36 from being shifted due to noise or the like. Therefore, even if there is noise or the like, the influence on the group switching counter 36 can be minimized, and printing defects can be minimized.
[0097]
In this embodiment, the case where the first embodiment is modified has been described. However, the third embodiment also uses the group switching counter 36 and may be applied to this.
[0098]
FIG. 17 shows a circuit diagram when applied to the circuit of the controller 71 in the third embodiment, and FIG. 18 shows the operation timing thereof.
In the serial data (SDB1) in the third embodiment, it is necessary to put a start flag at the head. Therefore, in this embodiment, the start flag and the drive information as the start information are set as the initialization flag as the start information. Serial data (SDE1) as selection control information configured to be time-division multiplexed between the data and the data is input to the controller 71.
[0099]
In the present embodiment, the serial data (SDE1) and the detection signal T output when the activation flag is detected by the activation flag detection circuit 72 are input to the two-input NAND gate 81. The output of the input NAND gate 82 is connected to the reset terminal of the group switching counter 36.
[0100]
Thus, if the initialization flag of the serial data (SDE1) is H level at the timing immediately before the data transfer enable (DSE) is output from the data transfer enable generation circuit 22, the output of the 2-input NAND gate 82 is output. At the L level, the group switching counter 36 is initialized.
[0101]
Even if detection signal T (H level) is output from activation flag detection circuit 72, if the initialization flag of serial data (SDE1) is at L level, the output of 2-input NAND gate 82 is at H level. The group switching counter 36 is not initialized.
[0102]
By doing in this way, in addition to having the same effect as the third embodiment, it is possible to prevent the count of the group switching counter 36 from being shifted due to noise or the like. Therefore, even if there is noise or the like, the influence on the group switching counter 36 can be minimized, and printing defects can be minimized.
[0103]
【The invention's effect】
As described above in detail, according to the present invention, the activation information and the drive information are input in synchronization from one signal line or an independent separate signal line, so that the activation information is detected at the timing obtained. Since the group switching signal for selecting the group to be driven is generated based on this, the divided drive cycle can be easily changed by changing the input cycle of the activation information and the drive information.
[0104]
Thereby, for example, when printing is performed by driving the head in the main scanning direction, the operation of the head in the main scanning direction is detected by the pulse of the encoder, and this is used to adjust the print timing in the main scanning direction. Therefore, a good printing result can be obtained. In addition, even when the heads are configured by shifting each drive element group provided in divided units, the print timing can be easily adjusted, so that a good print result can always be obtained.
[0105]
In addition to the group selection signal, control signals such as a transfer enable signal, a latch signal, and a strobe signal necessary for driving are generated in units of division based on the timing obtained by detecting the activation information. By driving only the drive information into the division unit, the drive element can be divided and controlled. Thereby, the total number of signal lines can be reduced.
[0106]
Further, the number of signal lines as a whole can be further reduced by configuring the start information and drive information with one signal line obtained by time division.
[0107]
Further, the selection control information including the division information is configured by one signal line that is time-division multiplexed together with the drive information, and the drive elements of the group specified by the division information are driven by performing the division drive based on the signal line. Therefore, not only the division drive cycle but also the division drive order can be arbitrarily changed. As a result, the present invention can be applied regardless of the direction of printing, which is advantageous in terms of flexibility, performance, and cost as compared with the prior art.
[0108]
That is, according to the present invention, it is possible to arbitrarily change the division drive cycle and the order of division drive while reducing the total number of signal lines.
[0109]
In addition, it is configured to generate a group selection signal that switches the group in order for each timing obtained by detecting the activation information, and inputs selection control information including initialization information, and detects this initialization information. Then, the group selection can be periodically initialized by initializing the group selection. Thereby, for example, when the group selection signal is generated in order every time the activation information is counted by the counter, it is possible to prevent the counter from being shifted due to noise or the like. Therefore, even if there is noise or the like, the influence on the counter can be minimized, and printing defects can be minimized.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a divided drive control apparatus according to a first embodiment of the present invention.
FIG. 2 is a diagram showing an operation timing of the circuit shown in FIG.
FIG. 3 is a circuit diagram showing a configuration of a controller shown in FIG. 1;
4 is a diagram showing an operation timing of the circuit shown in FIG. 3;
FIG. 5 is a circuit diagram showing a configuration of a split drive control device according to a second embodiment of the present invention.
6 is a diagram showing operation timing of the circuit shown in FIG. 5. FIG.
7 is a circuit diagram showing a configuration of a controller shown in FIG. 5. FIG.
8 is a diagram showing operation timing of the circuit shown in FIG.
FIG. 9 is a circuit diagram showing a configuration of a split drive control device according to a third embodiment of the present invention.
10 is a diagram showing an operation timing of the circuit shown in FIG. 9;
11 is a circuit diagram showing a configuration of a controller shown in FIG. 9;
12 is a diagram showing operation timing of the circuit shown in FIG.
FIG. 13 is a circuit diagram showing a configuration of a controller in a split drive control apparatus according to a fourth embodiment of the present invention.
14 is a diagram showing operation timing of the circuit shown in FIG. 13;
FIG. 15 is a circuit diagram showing a configuration of a controller in a split drive control device according to a fifth embodiment of the present invention.
16 is a diagram showing operation timing of the circuit shown in FIG.
FIG. 17 is a circuit diagram showing a configuration of another controller according to the sixth embodiment of the present invention.
18 is a diagram showing operation timing of the circuit shown in FIG.
FIG. 19 is a circuit diagram showing a configuration of a conventional split drive control device.
20 is a diagram showing operation timing of the circuit shown in FIG. 19;
FIG. 21 is a circuit diagram showing a configuration of another conventional divided drive control device.
FIG. 22 is a diagram showing operation timing of the circuit shown in FIG. 21;
FIG. 23 is a circuit diagram showing a configuration of another conventional divided drive control device.
24 is a diagram showing operation timing of the circuit shown in FIG. 23;
[Explanation of symbols]
11 ... Drive element
12 ... Transistor array
13 ... 3 input AND gate
14 ... Latch circuit
15 ... Shift register
16 ... Controller
21, 44 ... Rise detection circuit
22, 46 ... Transfer enable generation circuit
23, 47 ... Latch generation circuit
24, 48 ... division enable generation circuit
25, 49 ... Strobe signal generation circuit
36 ... Group switching counter
41. Controller
43 ... 2-bit shift register
45. Delay circuit
72... Start flag detection circuit
81, 82 ... 2-input NAND gate

Claims (10)

In a divided drive control device for drive elements that divides a plurality of drive elements into a plurality of groups and drives each group,
When activation information for taking drive timing for each group of drive elements is input in synchronization with drive information for driving each drive element, based on the timing obtained by detecting the activation information Control means including a function of generating a group selection signal;
Storage means for storing the drive information;
Drive means for selecting a group of drive elements to be driven based on a group selection signal from the control means and driving the drive elements based on drive information stored in the storage means; A drive control device for driving elements. 2. The drive drive divided drive control apparatus according to claim 1, wherein the control means generates a group selection signal for selecting a group in order at each timing obtained by detecting the activation information. The control means inputs the drive information and group designation information for designating and selecting a group of drive elements in a time-sharing manner and configured as one signal line, and each time the group designation information is detected, the group designation information is detected. 2. The divided drive control device for a drive element according to claim 1, wherein a group selection signal for selecting the group specified in (1) is generated. 2. The drive element split drive control apparatus according to claim 1, wherein the drive information and the activation information are configured by independent and separate signal lines. 2. The drive element division drive control device according to claim 1, wherein the drive information and the activation information are configured by one signal line that is time-divided. The control means is configured to generate a group selection signal for selecting a group in order at each timing obtained by detecting activation information, and initialization for initializing the drive information and group selection of drive elements 2. The divided drive control device for a drive element according to claim 1, wherein information is time-divided and configured by one signal line and input, and group selection is initialized each time this initialization information is detected. . In a divided drive control device for drive elements that divides a plurality of drive elements into a plurality of groups and drives each group,
Control means including a function for generating a group selection signal based on the selection control signal when the selection control information is input by one signal line time-division multiplexed with drive information for driving each drive element;
Storage means for storing the drive information;
Drive means for selecting a group of drive elements to be driven based on a group selection signal from the control means and driving the drive elements based on drive information stored in the storage means; A drive control device for driving elements. When the selection control information including activation information is input, the control means generates a group selection signal for selecting a group in order at each timing obtained by detecting the activation information. 8. A split drive control device for a drive element according to claim 7. The control means inputs the selection control information including group designation information for selecting a group of drive elements, and outputs a group selection signal for selecting a group designated by the group designation information every time the group designation information is detected. The divided drive control apparatus for a drive element according to claim 7, wherein the drive element is divided. The control means is configured to generate a group selection signal for selecting a group in order for each timing obtained by detecting activation information included in the selection control information, and the control means includes the control information included in the selection control information. 8. The drive element split drive control device according to claim 7, wherein the group selection is initialized each time detection information for initializing drive information and group selection of the drive elements is detected.

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