JP4164943B2 - ATM cell assembling apparatus and ATM cell disassembling apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an existing STM (Synchronous Transfer Mode) network and an ATM (Asynchronous Transfer Mode) cell that constitute a backbone communication network using SDH (Synchronous Digital Hierarchy), which is a synchronous multiplexing stacking technology, as a hierarchy of multiplexing stacks. The present invention relates to an ATM cell assembling / disassembling apparatus using a multiplexing interface used for mutual connection with a future ATM network based on a transfer technology.
[0002]
In particular, in the present invention, when the STM network side multiplexing interface is multiplexed with 64 kbps information centered on voice and multi-rate data that is an integral multiple of 64 kbps, the generation of a call from an arbitrary time point is prevented. In addition, it automatically avoids mutual collision between cells when assembling ATM cells, and at the same time, distributes the load of ATM cell transmission timing for multi-rate data, realizes high-speed device and diminishing memory scale, and is suitable for LSI implementation The present invention also relates to an ATM cell assembling / disassembling apparatus using a multiplexing interface for connection between an STM network and an ATM network.
[0003]
An image applied to the ATM cell assembling / disassembling apparatus for interconnecting the STM network and the ATM network of FIG. 29 is shown.
[0004]
As shown in FIG. 29, the ATM cell assembling / disassembling apparatus is disposed between the TDM switch on the STM network side and the ATM switch on the ATM network side. Usually, the communication service on the STM network side in the same station. It is used as a format conversion apparatus between necessary communication data between a TDM exchange that performs exchange connection in units of channels and an ATM exchange that exchanges ATM cells in communication services.
[0005]
Further, as shown in the correspondence between the ATM cell assembling / disassembling apparatus of the present invention and the application field of FIG. 30, the ATM cell assembling / disassembling apparatus is an SAR (Segmentation and Disassembly) that occupies the lower layer portion of the AAL (ATM Adaptation Layer) of FIG. The reassembly function is performed in coordination with the CS (Convergence Sublayer) function, which performs cell connection management, error control, frame start position pointer information transmission of higher layer information transmission frames, etc. One.
[0006]
According to the international standard classification of the interface of the AAL layer, four types of classification from AAL1 to AAL5 are defined according to the type of communication data put on the ATM, but the data from the STM network side in the present invention is Targeted at constant rate information called CBR (Constant Bit Rate), that is, synchronous multi-rate data of 64 kbps or an integral multiple thereof, classified as a device that realizes an ATM cell assembling / disassembling interface equivalent to AAL1 in a multiplexing interface Is done.
[0007]
[Prior art]
Communication technology is advancing rapidly, and in the process of shifting from an existing communication network based on the old technology to a new communication network based on the new technology, in addition to utilizing existing facilities, Interconnection between them is an essential issue.
[0008]
The current backbone communication network employs a method of stacking multiplexed frames at a rate that is an integral multiple of 64 kbps equivalent to voice 1CH, and the higher-order group is based on STM1 of 155.520 Mbps or STM0 of 51.840 Mbps. A network is being constructed by hierarchical multiplexing hierarchy based on SDH (Synchronous Digital Hierarchy) based on STM (Synchronous Transfer Mode) technology based on network synchronization, which is stacked at an integral multiple of STM1.
[0009]
FIG. 31 shows the SDH multiplexing hierarchy, and FIG. 32 shows the STM1 frame structure.
[0010]
As shown in FIG. 31, SDH absorbs the hierarchy of low-order group PDH (Pleciochronous Digital Hierarchy) networks by synchronizing existing staff in each country, and is also aware of the shift to ATM networks that will provide broadband services in the future. It has a configuration.
[0011]
Of these, the STM1 speed is the most basic multiplexing speed in the SDH network, such as when stacking higher-order groups or when connecting internationally. In the case of Hierarchy in Japan and North America, it is 24 × 4 in terms of 64 kbps. × 21, that is, 2016CH can be multiplexed, and in the future, it is expected as a basic speed when the B-ISDN service is introduced to the home.
[0012]
Further, the basic frame of STM1 (hereinafter referred to as STM frame) has a configuration based on a sampling period of 8 kHz (125 μs), which is twice the bandwidth of the voice, which has been the center of traffic so far, as shown in FIG. In the virtual container VC1, 260 × 9 = 2340 bytes of information can be loaded on one frame and sent. The basic time width in bytes in this STM frame is hereinafter referred to as a time slot.
[0013]
This includes the 28.8 kbps and 56 kbps data transfer services commonly used for Internet connection, the ISDN 64 kbps service, and the high-efficiency compressed voice communication service of 5.6 kbps to 8 kbps used for mobile phones and the Internet. It is sent after being converted to a communication speed of 64 kbps. Also, high-speed digital leased lines and the like are provided on the basis of a speed that is an integral multiple of 64 kbps.
[0014]
As a result of progress in circuit / device technologies such as high-speed memory and processing LSI, the number of STM1 multiplexed frames is generally used as a basic bundle of TDM exchange in the current TDM exchange.
[0015]
On the other hand, with the aim of providing high-quality and flexible multimedia services in addition to voice, it is based on ATM (Asynchronous Transfer Mode) technology based on cell transfer with a main transfer rate of 155.520 Mbps equivalent to STM1. The construction of ATM networks is currently being introduced in the form of intranets using ATM dedicated networks, and in the future, full-scale introduction to public mobile communication networks and general subscribers is expected. Yes.
[0016]
In this case, in the transition period, in order to allow users connected to each network to freely receive communication services across the network, the existing STM network and the newly established ATM network Interconnection is required.
[0017]
In other words, the existing STM network with 64 kbps as the basic speed of service accumulation and the ATM network with the basic technology of 53-byte ATM cell transfer at the speed of 155.520 Mbps as well as for future service development. There is a need for a technology for economically interconnecting with a simple circuit configuration while keeping communication quality in mind, and an ATM cell assembling / disassembling device that realizes high-speed and economical equipment suitable for LSI implementation. .
[0018]
In the following, an outline of the basic mechanism of ATM cell assembly / disassembly will be described, and a conventional ATM cell assembly / disassembly apparatus will be described in more detail. First, the cell assembling apparatus will be described in the order of the cell disassembling apparatus.
[0019]
An explanatory diagram of a basic cell configuration including details of the header portion of the ATM cell is shown in the configuration of the ATM cell corresponding to AAL1 for communication within the ATM network of FIG. Also, FIG. 34 illustrates a mechanism for assembling and disassembling an AAL1 ATM cell for a 64 kbps call, a configuration of a conventional ATM cell assembling apparatus of FIG. 35, and an explanatory diagram of cell assembling in the conventional ATM cell assembling apparatus of FIG. A basic configuration diagram of a conventional ATM device and a state of ATM cell assembly / disassembly are shown.
[0020]
In FIG. 33, the first 5 bytes are a well-known ATM header part, and each function is as shown in the figure. The VPI (Virtual Path Identifier) is a logical bundle of virtual communication bundles or paths in the connection between switching nodes. VCI (Virtual Channel Identifier) is a logical identification number indicating which channel in this path is used, and PTI (Payload Type Identifier) is the type of data in the payload portion, CLP ( Cell Loss Priority) is a control bit for instructing the network that cells may be discarded preferentially when an overflow occurs in the formation of a congestion queue in an exchange connection. HEC (Header Error Control) is an error in the header part. Means error control bits for detection and correction.
[0021]
As shown in FIG. 33, in the ATM cell of AAL1, one byte in 48 bytes of the ATM payload is for fulfilling the CS function described in the correspondence between the ATM cell assembling / disassembling apparatus of the present invention of FIG. . That is, when assembling on the ATM cell receiving side, 1 bit is set for CSI (Convergence Sublayer Indication) for instructing periodic transmission of the STM frame synchronization pointer, and the sequence of ATM cells is secured to ensure the continuity of ATM cell sequence numbers. SAR PDU with 3 bits for SC (Sequence Count) for performing SAR PDU, 4 bits for SNP (Sequence Number Protection) for transmission error correction of SN (Sequence Number) defined as a set of CSI and SC Always used as a header. Therefore, it is always a payload part indicated by 47-byte SAR PDU (Protocol Data Unit) that can be actually sent with data from the STM side.
[0022]
Actually, in order to reduce redundancy in transmitting an STM frame on an ATM cell, section overhead information of the STM frame is not sent on the ATM cell.
[0023]
As a result, STM frame information is lost for a communication call based on a multi-rate call (hereinafter referred to as multi-party call) of an integral multiple of 64 kbps that performs ATM cell assembly and transmission without maintaining the synchronization relationship between the STM frame and the time position. End up.
[0024]
Therefore, for such multiple calls, a function for ensuring frame synchronization of the STM frame is required to return from the ATM cell to the STM frame as part of the CS (Convergence Sublayer) function, which is indicated by SN. It is necessary to send pointer information for indicating the head position of the STM frame every 8 cell periods. As a result, the payload information is further consumed by 1 byte every 8 cells, and the SAR PDU portion is 46 bytes periodically.
[0025]
As a result, in actual ATM cell assembly / disassembly, it is necessary to be aware of this periodic structure. However, in order to simplify the explanation, in the description of the present invention, basically, assembly / disassembly of ATM cells is not performed. All are described as a 47-byte payload.
[0026]
It will be finally described that even when a 46-byte payload periodically enters, it can be easily handled without changing the circuit or the like only by periodically changing the designation of the control parameter in the present invention.
[0027]
As shown in the mechanism of assembling / disassembling AAL1 ATM cells for a 64 kbps call in FIG. 34, in the case of 64 kbps data mainly composed of voice, it is always sent as 1-byte data at a period of 125 μs. In order to assemble the ATM cell, 64 kbps data for 47 bytes is required. Therefore, until the 64 kbps data arrives for 47 bytes, it is stored in the cellized buffer of the cellization unit shown in the configuration of the conventional ATM cell assembling apparatus in FIG. The 64 kbps data that arrives is stored in units of bytes each time.
[0028]
In FIG. 35, the DMUX unit separates a 64 kbps call that has been multiplexed and sent in an STM frame, and accumulates data in a cellized buffer corresponding to each channel. When 47 bytes of audio data is accumulated, the buffer control unit of the cellization unit places the 47 bytes of data accumulated in the payload portion of the ATM cell, and includes 5 bytes of ATM header portion + 1 byte for CS function + ATM. For example, 1 byte, a total of 7 bytes header is attached to the switch inside the switch, and it is assembled into a 54-byte ATM cell, and then notified to the controller. The controller selects the ATM cell in the MUX section, and ATM is multiplexed as ATM. Send to the ATM switch on the network side.
[0029]
In the above description, the additional byte for internal processing of the exchange is 1 byte. However, this is only an example, and there are cases where a larger number of additional bytes is used for internal processing of the exchange. In this case, the ATM cell size for internal processing of the exchange also changes.
[0030]
On the contrary, since the communication data for 47 bytes is stored in the payload part of the ATM cell arriving from the ATM network side, the payload is once decomposed and stored in the cell disassembly buffer one by one, and then the STM every 125 μs. It is periodically read and sent out in the corresponding time slot of the frame.
[0031]
This ATM cell disassembly function is also required for ATM voice terminals. As shown in FIG. 34, 47 bytes of voice data sent together in an ATM cell are reproduced as 1-byte data every 125 μs. The sound is decoded.
[0032]
From the above description, when 64 kbps information centered on voice is targeted, a delay time of cell assembly waiting, Tc = 47 × 125 μs = 5.875 ms, is always required in the process of ATM cell assembly.
[0033]
This ATM cell assembly waiting time, that is, a frame in which 47 basic frames of STM1 are bundled is hereinafter referred to as a cellized basic frame.
[0034]
Next, based on the explanatory diagram of cell assembly in the configuration of the conventional ATM cell assembly apparatus shown in FIG. 35, the state of ATM cell assembly by the multiplexing interface for the basic 64 kbps data will be described first.
[0035]
In FIG. 35, from the STM network side to the ATM network side, one byte corresponding to a speed of 64 kbps is set as a basic time slot on one frame of STM1, and in the standard hierarchy example of Japan and the United States, Thus, data corresponding to a maximum of 2016 64 kbps channels flows.
[0036]
In response to the occurrence of a 64 kbps channel call (hereinafter referred to as 64 kbps call) from the STM network side, one empty time slot is allocated to the channel. The ATM cell assembling apparatus sequentially accumulates 64 kbps data in bytes transmitted through the time slot of STM1 for each STM frame in the cellized buffer assigned to the time slot. At the time after the 47 STM frame in which the 47-byte data is accumulated, the data is read out, added with 7-byte ATM header information, assembled into an ATM cell, and sent to the ATM switch on the ATM network side.
[0037]
If another 64 kbps call occurs during this call, 64 kbps data assigned to another free STM1 time slot is sent periodically, but this newly assigned STM1 time slot Similarly, an ATM cell assembly of 64 kbps data is performed using an empty cellization buffer associated with.
[0038]
When a service call is generated is completely random, as shown in FIG. 36, when communication is started on the adjacent STM1 channel almost simultaneously, the ATM cell assembly time after 47 frames overlaps. However, mutual collision between ATM cells occurs, and it is necessary to rearrange the ATM cells. For this purpose, complicated control according to the assembly situation of a plurality of ATM cell-ized buffers is required.
[0039]
Next, in the case of a multi-factor call, that is, a call with an integer multiple of 64 kbps, a plurality of STM1 time slots are required. For this reason, in the prior art based on the interconnection interface based on byte multiplexing by the multiplexing interface, a plurality of empty time slots that are not used for 64 kbps calls are combined to secure the necessary N time slots. Call communication is taking place.
[0040]
In this case, as shown in the assembly of ATM cells for conventional multi-call data in FIG. 37, the cell assembling waiting time in the case of a multi-speed call with a communication speed of an integer multiple N of 64 kbps is [47 / N] × 125 μs. . Here, [x] means an integer obtained by rounding up a numerical value below the decimal point of x. In FIG. 37, the case of the multinary number N = 3 is illustrated together with the 64 kbps information channel.
[0041]
In a multiple call, as the multiple number, that is, the multiple rate increases, the number of bytes sent per STM frame also increases, so the waiting time required for cell conversion is shortened, and the multiple number N is 47 (transmission rate 3 .008 Mbps) or more, the cell assembly waiting time is less than the STM frame.
[0042]
In the case of a multi-call, as shown in the flow chart for writing multi-call data into the cellized buffer according to the prior art of FIG. 38, in the process of writing into the cellized buffer, it is distributed over a plurality of time slots of the STM frame. It is necessary to write the data of the same channel sent to the cell buffer of the address associated with the channel, and whenever the data of one time slot arrives, the data is sent to the channel to which the time slot is assigned. You need to know the address of the corresponding cellized buffer.
[0043]
Therefore, as shown in the writing mechanism of the cellized buffer according to the conventional configuration of FIG. 37, when the data of the time slot arrives and is stored in the write control unit and is written in the cellized buffer, Channel number for the multiple call assigned to the time slot number from the TS / CH conversion memory provided corresponding to the slot, and then the cellized buffer allocated to this channel number by the cellized address control memory Know the address.
[0044]
Based on the cellized buffer address known in this way, the reception information of the time slot is written into the cellized buffer.
[0045]
The TS / CH conversion memory and the cell address control memory constitute a single control memory, and the cell buffer information and cell header information necessary for ATM cell assembly are held as table values for each channel number. ing.
[0046]
Therefore, in practice, reading of the cellized buffer address for the time slot is performed in one cycle.
[0047]
As a result, two cycles of reading of the cellized buffer address corresponding to the time slot number and writing to the cellized buffer corresponding to this cellized buffer address are required.
[0048]
The time slot time length in STM1 is 8 / 155.520 Mbps = 51 ns. During this time length, the flow of the flow chart of the procedure for writing STM data into the cell buffer according to the prior art of FIG. 38 is shown in FIG. Therefore, two access cycles of reading the address of the cellized buffer memory and writing to the cellized buffer memory with respect to the assigned time slot are required. .
[0049]
This speed is severe even in the current CMOS memory, and in a cell assembly apparatus that requires a large number of buffer memories such as a multiplexing interface, it becomes a factor of increase in LSI scale, memory cost, and power consumption.
[0050]
Next, a conventional ATM cell disassembling apparatus will be described.
[0051]
A specific example of a conventional ATM cell disassembly apparatus is shown in FIG. 40 as a conventional ATM cell disassembly apparatus configuration example.
[0052]
In the ATM cell disassembling apparatus of FIG. 40, the cell writing control unit also serves as a payload extraction buffer, and writes the payload portion of the ATM cell to the cell disassembly buffer having an address corresponding to the time slot number of the STM frame in bytes. At the time of writing. The write control table unit stores control information for write address designation control necessary for the cell write control unit to perform the write control.
[0053]
The cell disassembling buffer disassembles the payload data into multiples of the address of the time slot assigned for each STM frame and temporarily stores it.
[0054]
The STM data read control unit reads the STM time slot data from the cell disassembly buffer in the order of addresses, adds predetermined data such as a section overhead shown in the STM1 frame configuration of FIG. 32, and sends it out as an STM frame.
[0055]
When a multi-call ATM cell arrives, the address to which the ATM cell corresponding to the multi-degree of the ATM cell is to be disassembled by referring to the write control table of the address corresponding to the channel number VPI / VCI of the ATM cell The time slot number of STM1 is known, and the data of the payload portion of the ATM cell is stored in the cell disassembly buffer at the address corresponding to each channel number of the STM1 frame.
[0056]
For example, in the case of a multiple number 3, before storing the cell data in the STM data read control unit composed of the buffer memory arranged in the time slot order of the STM frame, as the corresponding time slot number TS # of the STM frame to be stored, TS # 5, TS # 90, and TS # 150 are obtained from the write control table, and are sequentially written to addresses corresponding to the time slots of the cell decomposition buffer.
[0057]
Thereafter, by periodically reading the cell disassembly buffer in the order of TS # addresses, the data multiplexed in the STM frame is sent to the STM network side.
[0058]
The STM data reading unit performs necessary addition processing such as section overhead of the STM frame and sends it out as STM data while reading the cell disassembly buffer unit in the order of addresses in the order of STM channel numbers.
[0059]
As a result, the original data repeated in the STM frame period is restored and sent to the TDM exchange on the STM network side.
[0060]
That is, in the conventional ATM cell disassembling apparatus, the time allowed for reading and writing data to the buffer memory in order to decompose the buffer memory used for ATM cell disassembly into a predetermined STM frame in byte units is The time corresponding to 1 byte of the STM1 frame, that is, 51 ns, requires processing of two cycles of reading and writing to different memories at this time. As in the case of ATM cell assembly, a high-speed memory is used as the memory. This is necessary, which increases the memory scale, power consumption, and increases the cost of the apparatus.
[0061]
[Problems to be solved by the invention]
As described above, in the ATM cell assembling / disassembling apparatus according to the conventional configuration necessary for connection between the STM network and the ATM network according to the conventional configuration technique,
1). In the process of assembling ATM cells using a multiplexed interface of 64 kbps call data and multi-rate data centered on voice that occurs and disappears at an arbitrary time, it is possible to avoid collision between ATM cells on an ATM frame. Complex control was required.
[0062]
2). Also, when multiple calls are multiplexed, the write address at the time of assembling the ATM cell is used to make correspondence between the allocated time slot for the multiple call and the address of the cellization buffer or cell disassembly buffer. It is necessary to perform two cycles of writing address reading and data writing in 51 ns for one time slot even at the time of reading and data writing and cell decomposition, and consumption for increasing the memory scale and memory speed. There were problems such as an increase in power.
[0063]
Therefore, an object of the present invention is to solve the following problems.
Problem (1): For multiple calls, it is not necessary to read and write data in two cycles during one time slot 51 ns of an STM frame, and a high-speed memory is not required.
Problem (2): Realize reduction of power consumption by reducing memory scale.
Problem (3): When connecting an STM network and an ATM network, collision between ATM cells at the time of ATM cell assembly is automatically avoided, and complicated control for collision avoidance is not required.
Problem (4): Burst of ATM cells for multi-way calls is suppressed, and the load on the ATM network is distributed.
[0064]
The present invention solves the above problems and provides an ATM cell assembling / disassembling apparatus suitable for LSI.
[0065]
In the ATM cell assembling apparatus, the means for solving the above problems (1) to (4), and in the ATM cell disassembling apparatus, the means for solving the problems (1) to (2) are required.
[0066]
[Means for Solving the Problems]
First, the basic idea point of the present invention will be briefly described.
[0067]
In order to solve Problem 1 to Problem 4, the problems of the prior art are rearranged again.
(1). In the case of a multi-call that requires a plurality of STM time slots, the prior art assumes a byte-multiplexed STM frame structure, so that data of the same channel is transmitted and transmitted using a plurality of discrete time slots in the STM frame. Reception is performed.
[0068]
As a result, in both the case of ATM cell assembly and ATM cell decomposition, the data buffer must be confirmed after confirming the address position of the data buffer (cellization buffer, cell decomposition buffer) corresponding to the discrete time slot positions. Cannot write to.
(2). In the case of ATM cell assembly, the ATM cell is assembled each time communication data sent from the STM frame side is accumulated by the number of payloads for ATM cell assembly.
[0069]
Therefore, the ATM cell assembly time is determined by the start time of the communication data, and the ATM cell collision avoidance operation for the adjacent STM data is inevitably required, and the avoidance processing is complicated.
[0070]
By solving the above problems (1) and (2), the problems 1 to 3 are solved. At that time, the problem including the problem 4 can be solved with the ATM network side of the ATM cell assembling apparatus. This is a basic requirement for maintaining the connection performance of the network.
[0071]
In order to solve the problem (1), in the ATM cell assembling / disassembling apparatus of the present invention, the STM based on the multiplex transmission interface as in the prior art is used as the connection interface for transmission / reception of multi-calls with the STM network. Instead of using discrete multiple-number time slots in bytes in a frame, we use multiple adjacent time slots in an STM frame.
[0072]
For a multi-call that requires multiple time slots in this way, the time slots used by the multi-call are continuous from the first time slot by determining to use continuous time slots in the STM frame. It is clear from the beginning that this is a multiple lot time lot.
[0073]
As a result, when the STM data is written into the cell buffer and the payload data is stored, the prior art requires the cell buffer address reference, and when the ATM cell is decomposed in units of multiple bytes and written to the cell decomposition buffer. The cell decomposition buffer address reference process is not required.
[0074]
As a result, data writing to the buffer memory can be performed in one cycle, a high-speed memory is unnecessary, the memory scale can be reduced, and the problems (1) to (2) can be solved.
[0075]
Next, in order to solve the problem (2), in the ATM cell assembling apparatus according to the present invention, as in the prior art, the ATM cell assembly is based on the start time of the communication call, and the payload data is converted into cells. Instead of passively waiting for an unspecified time stored in the buffer, a method of actively performing at a predetermined timing is adopted.
[0076]
That is, in the present invention, the STM frame payload number multiple, that is, 47 times the STM frame frame is used as a cellized basic frame for ATM cell assembly, and this cellized basic frame is time quantized with the time width of the ATM cell. A cell slot is determined, and ATM cell is assembled and transmitted using the timing of this cell slot.
[0077]
That is, the ATM cell assembling process is performed by reading the required number of data in the cell buffer corresponding to the cell slot in the time order of the cell slot using the time-quantized cell slot.
[0078]
The cell slot usage rule will be briefly described. For a communication call that requires real-time property such as voice, such as a 64 kbps call, the ATM cell assembly / transmission is repeated at the period of the cellized basic frame. This is performed using a cell slot having a number corresponding to the time slot number corresponding to the communication call.
[0079]
As a result, the ATM cell sent to the ATM network side can maintain the same time periodicity as the STM data sent from the STM network, and there is no delay fluctuation in the ATM cell assembly process. In the receiving terminal, it is possible to minimize the deterioration of the signal-to-noise ratio when returning to the original audio signal or the like.
[0080]
In addition, when assembling and sending ATM cells for multi-calls that are used for data communication that does not require real-time characteristics, the multi-call shares a cell slot that is not used by the communication call that requires real-time characteristics, and a payload is stored in the cellized buffer. Suppose that the rule is used by multiple calls in the time order in which data is accumulated.
[0081]
By adopting such a rule, ATM cells are not assembled / transmitted outside this cell slot, so mutual collision of ATM cells is automatically avoided, and complicated collision avoidance processing becomes unnecessary. The problem (3) can be solved.
[0082]
Also, cell slots allocated for multi-calls are shared and used by all multi-calls, and ATM cells are assembled and transmitted in the order of multi-calls in the order in which payload data has been stored in the cellization buffer. At the same time as collision avoidance is performed, the same decentralization at the time of generation of ATM cells for the multi-way call is realized. Thereby, the solution to the problem (4) is also achieved.
[0083]
Next, further detailed description will be given with reference to the explanatory drawings.
[0084]
First, an ATM cell assembling apparatus and then an ATM cell disassembling apparatus will be described in this order.
[0085]
The ATM cell assembling apparatus of the present invention relates to the principle configuration of the ATM cell assembling apparatus of the present invention of FIG. 1, the relationship between the STM frame of the present invention and the basic cell frame of FIG. 2, the time of the STM frame of the present invention of FIG. FIG. 4 shows the correspondence between slots, cellized buffers, and cell slots, and the basic procedure for assembling the ATM cell of FIG.
Regarding the ATM cell disassembling apparatus, the basic principle of the present invention is shown in the configuration of the ATM cell disassembling apparatus of the present invention in FIG. 5 and the basic procedure of ATM cell disassembling of the present invention in FIG.
[0086]
First, regarding each of FIGS. 1 to 6, a brief description of each outline will be given.
[0087]
In FIG. 1, the STM write control unit writes the time slot data of the payload portion to the corresponding addresses of the cellized buffer in the STM frame order and the time slot number order, excluding extra information such as section overhead from the STM data. I do.
[0088]
The cell buffer is a buffer memory in which addresses are given in the order of periodic numbers and time slot numbers in accordance with the STM frame counter, and temporarily stores a cell assembly payload.
[0089]
The ATM cell assembling unit reads ATM cell payload data from the cell buffer according to a certain reading rule, adds an ATM cell header, and assembles and sends out the ATM cell.
[0090]
The cellization table holds information such as communication start information, multi-element numbers, ATM header information for ATM assembly, etc. regarding the time slot of STM data corresponding to the cell slot targeted by the ATM cell assembly unit. The ATM cell assembly unit controls cell assembly based on this information.
[0091]
In the multi-factor table, the cellized buffer addresses in the order in which cell assembly preparation for multi-calls is completed constitute a logical first in first out (FIFO) queue, and cell slots are allocated for multi-calls. In addition, by using this multi-element table, the ATM cell assembling section can easily read out the data of the cellized buffer address at the head of the queue as the ATM payload.
[0092]
The μP INF unit receives necessary traffic information such as start and end of communication corresponding to each communication channel, used time slot, and multi-element information from the STM switch, and updates the cell table and multi-table update.
[0093]
The timing generator is necessary to realize the functions of each part, such as the STM frame counter clock, time slot counter clock, cellized basic frame clock, cell slot counter clock, and read clock required to read payload data from the cellized buffer. Various clocks are generated.
[0094]
Using these clocks, STM data is written into the cellized buffer, the ATM cell assembling unit reads out the cellized buffer based on the information in the cellized table and the multiple table, and ATM cell assembly is performed.
[0095]
Next, the relationship between the STM frame and the cellized basic frame of the present invention in FIG. 2 shows the relationship between the cell slot, the cellized basic frame, and the STM frame, and the cell slot allocation embodiment employed in the present invention. .
[0096]
From FIG. 2, it can be seen that the cellized basic frame has a cell slot corresponding to 9 × 270 × 47/54 = 2115. Further, as described above, in the STM1 frame, data for 2016 channels is sent in the STM multiplexing hierarchy of Japan and the United States in terms of 64 kbps.
[0097]
Therefore, as shown in FIG. 2, even if one vacant cell slot is provided per STM1 frame for the purpose of shared use of multiple calls, the remaining cell slots are used as shared free slots for multiple calls. The ATM cell assembly waiting time for multi-way calls can be shortened.
[0098]
The correspondence relationship between the time slot of the STM frame, cellized buffer, and cellized slot of the present invention shown in FIG. 3 is as follows: STM frame time slot number TS #, cellized buffer address number CB #, cellized basic frame cell slot number The correspondence with CS # is shown.
[0099]
As shown in FIG. 3, the time slot number TS # of the STM frame and the buffer address number CB # of the cellized buffer have a one-to-one correspondence, and in the case of a 64 kbps call in the cellized basic frame, the ATM cell slot The number CS # also has a one-to-one correspondence with the cellized buffer address number CB #.
[0100]
Further, the multi-call common cell slots C2 and C3 allocated for multi-call illustrated in FIG. 3 are shared by all multi-calls.
[0101]
Therefore, hereinafter, the time slot number of the STM frame is used in place of the cellized buffer address number.
[0102]
The basic procedure for assembling the ATM cell of the present invention in FIG. 4 shows the basic procedure from the start of communication to the assembly of the ATM cell.
[0103]
FIG. 4 shows a state in which the ATM cell assembling procedure is followed from the communication start to the end, focusing on a specific communication call. Further, in FIG. 4, in the case of a 64 kbps call, the cellization table is referred to, but the multi-component table is not referred to because it is unnecessary.
[0104]
The data periodically written to the cellized buffer for each time slot of each STM frame is referred to the cellized table and the multiple table according to the attribute of the data of the time lot corresponding to the cell slot in the order of the cell slot. However, payload data read control and ATM cell assembly / transmission are performed. Further detailed description will be given in the embodiment.
[0105]
In the configuration of the ATM cell disassembling apparatus of the present invention shown in FIG. 5, the ATM cell writing control unit decomposes the ATM cell into the address buffer in the time slot order of the STM frame according to the writing control table, and writes the data in units of multiples. Do. The STM data read controller is a part that sequentially reads out the written data in the STM frame period and the time slot period, and assembles it into an STM frame.
[0106]
The basic procedure of ATM cell disassembly of the present invention in FIG. 6 shows the basic procedure for performing ATM cell disassembly with the configuration of FIG.
[0107]
FIG. 6 shows a state in which the ATM cell disassembly procedure is followed from the start to the end of communication, focusing on a specific communication call. A more detailed description is given in the examples.
[0108]
The problem solving means will be described in detail below.
[0109]
First, means for solving the problems (1) and (2) by the cell assembling apparatus of the present invention will be described.
[0110]
FIG. 1 is a diagram illustrating the principle of the ATM cell assembling apparatus of the present invention shown in FIG. 1, in which an STM write control unit temporarily stores STM data, and stores information for each time slot of an STM frame in a cell buffer in the order of time slots in bytes. Store sequentially and periodically.
[0111]
At this time, as shown in the correspondence relationship between the time slot of the STM frame, the cell buffer, and the cell slot of the present invention in FIG. It shall be sent using several consecutive STM1 time slots.
[0112]
This means that, instead of the byte multiplex interface by the multiplex transmission of the prior art, the channel multiplex interface normally used for switching connection is used as the connection interface.
[0113]
As a result, even in the case of a multi-way call, data writing to the cellized buffer may be performed periodically for each STM frame in a continuous address area corresponding to the multi-way number. Thus, the writing speed can be increased, and at the same time, the address translation memory is not required, and the memory scale can be reduced.
[0114]
In addition, since the multi-call data is stored in the continuous buffer memory, the data can be read with a relatively simple read rule as detailed in the embodiment even when the cell is assembled.
[0115]
Next, a description will be given of solution means for automatically avoiding the mutual collision of ATM cells of the problem (3) in the cell assembling apparatus.
[0116]
As shown in FIG. 2, the timing of cell assembly is such that the ATM cell assembly time is quantized so as to be performed at the timing of the cell slot in the cellized basic frame. At timings other than the quantized cell slot, the ATM cell is Do not assemble / send.
[0117]
By forcibly setting the cell assembly timing in this way, the mutual collision of cells at the time of cell assembly, which has been a problem in the prior art, is automatically avoided, and for avoiding the collision of ATM cells. Complex control processing is not required.
[0118]
Finally, a description will be given of a means for solving the problem (4), in which the burst of ATM cells in response to the multi-source call is suppressed and the load is distributed to the ATM network.
[0119]
Since the solving means of the problem (3) and the solving means of the problem (4) are closely related, a detailed supplementary explanation will be given for the solving means of the problem (3).
[0120]
In the description of the means for solving the problem (3), in actuality, in order to assemble and transmit the ATM cell in each quantized cell slot of the cellized basic frame, the cell slot and the time slot of the STM frame are used. It is necessary to define the correspondence between cellized buffers and the rules for reading data from the cellized buffers.
[0121]
In the present invention, as shown in FIG. 2, the time slot, the cell buffer, and the cell slot of the STM frame are associated one by one in order.
[0122]
However, cell slot usage rules differ between 64 kbps calls and multi-way calls.
[0123]
That is, for 64 kbps calls that often use voices that require real-time characteristics, the data sent in the STM frame period using a specific time slot of the STM frame is the cellized basic frame. Assemble and send to the ATM cell using the corresponding specific cell slot.
[0124]
As a result, ATM cells can be assembled and transmitted without causing delay fluctuation while maintaining the same time periodicity as a 64 kbps call of an STM frame, and real-time characteristics can be maintained.
[0125]
In this case, immediately after the start of the call, it is necessary to read data from the cellized buffer in the first cell slot in a state where 47 bytes of data are not yet stored in the corresponding cellized buffer. Therefore, at the time of the first cell slot, read pointer information that indicates which address in the past should be read from the cellized buffer address is displayed immediately after the start of communication. In the principle configuration diagram of the assembling apparatus, it is written in the cell conversion table, and the read start point is determined by the pointer information from the cell conversion table.
[0126]
This processing is performed based on the signal information obtained from the exchange side by the μP INF unit in FIG.
[0127]
In recent years, with the development of multimedia applications on the Internet, the needs for digital video communication and the like are increasing. In the future, not only for 64 kbps calls centered on voice but also for multi-way calls, real-time performance is required. Applications may spread. Even in this case, the concept of control processing for a 64 kbps call in the present invention can be expanded and dealt with.
[0128]
In other words, for such a multi-call that requires real-time performance, the multi-call cell slot corresponding to the continuous multi-multiple time slots used by the multi-call is used continuously. It ’s fine.
[0129]
In this case, ATM cells for the same multi-call are generated continuously. However, even if the multi-element is increased to 2-3, the improvement effect in the video communication is remarkable as compared with the multi-element 1. While suppressing the occurrence of cell bursts to a relatively small range, it is possible to enhance the communication quality improvement effect for a real-time communication service that requires wide bandwidth such as video communication.
[0130]
On the other hand, when assembling multi-call data that is often used for data transmission and has a large amount of data and therefore a large multi-factor N in an ATM cell, in order to solve the problem (4), the cell slot usage rule is as follows: Two rules will be used.
(1) .Rule 1;
The next cell slot is used as a shared cell slot for multiple calls.
[0131]
(1). Empty slots, for example, empty slots between cell slot numbers CS # 43 and 44, 87 and 88 shown in the relationship between the STM frame of the present invention and the ATM cellized basic frame in FIG.
▲ 2 ▼. Cell slot without call when 64 kbps call is not used
(3). Corresponding cell slot with one-to-one allocation corresponding to the time slot allocated for multiple calls
That is, the cell slots (1), (2), and (3) are not used exclusively by multiple calls corresponding to a specific time slot as in the case of a 64 kbps call, but are shared by all multiple calls. To be used.
(2) .Rule 2;
Multi-call ATM cell assembly / sending uses the multi-call common cell slot defined in Rule 1 in the time order of multi-call when data of 47 bytes or more is accumulated for ATM cell payload and cell assembly preparation is completed. Do it.
[0132]
The reason for adopting rule 1 and rule 2 is as follows.
[0133]
That is, in the case of multi-call, using the same rules as in the case of 64 kbps call, the ATM cell corresponding to the cell slot corresponding to the cell slot corresponding to the time slot of the multi-call is directly corresponded to the cell slot. When assembled and transmitted, ATM cells for the same multi-element call are continuously generated in bursts in a number of consecutive cell slots corresponding to the multi-element number.
[0134]
For this reason, QOS (Quality Of Service) control on the ATM network side is likely to be subject to restrictions such as an increase in delay fluctuation due to shaping control and a forced cell discard at the time of traffic congestion.
[0135]
Further, when the concept of grouping cell slots for the same multi-call as described above is taken, as shown in the explanatory diagram of ATM cell assembly for the conventional multi-call data in FIG. The waiting time increases and the delay time due to assembly waiting increases.
[0136]
On the other hand, by performing ATM assembly for multi-calls using these rules 1 and 2, a specific multi-call does not occupy a continuous cell slot and ATM cells are not assembled and transmitted. ATM cells can be sent out sequentially using the shared cell slot of the multi-call in the order of the multi-call in which 47 bytes of data are stored.
[0137]
As a result, it is possible to distribute the generation timing of ATM cells even for a specific multi-way call having a large multi-way number. As a result, it is possible to assemble and send ATM cells without imposing a burden on the ATM network side.
[0138]
Next, how ATM cell assembly is performed for a multi-way call using rule 1 and rule 2 will be described.
[0139]
Referring to FIG. 1, the ATM cell assembling unit of the present invention has an address cell numbering table indicated by a cell slot clock counter in order for each cell slot in a cellized basic frame. To see what kind of data the time slot of the STM frame corresponding to this cell slot is used.
[0140]
That is, first, information such as whether or not the time slot corresponding to the cell slot is started, and if it is used, is used for a 64 kbps call or a multiple call. obtain.
[0141]
According to the information of this cellization table, in the case of a 64 kbps call, when the cell slot arrives, the above read pointer is used as a read start point, and the necessary payload data is read from the corresponding cellization buffer, and the ATM cell is read into the cell slot having a width of 54 bytes. Assemble the cell and send it out.
[0142]
In the case of a multi-call, as shown in the basic procedure of ATM cell assembly of the present invention in FIG. 4, the ATM cell assembly unit, in addition to referring to the cellization table, provides information on cellized buffer addresses ready for cellization. It also refers to the multi-component table held in the queue order.
[0143]
First, the ATM cell assembling unit looks at the cellization table address number corresponding to the cell slot number, that is, the data in the cellization table corresponding to the time slot number of the STM, and uses rule 1 as a shared slot for multiple calls. If it is confirmed that it can be used, it goes unconditionally to refer to the multiple table.
[0144]
From the multi-element table, cellized buffer address information in the waiting order at the head of the queue in which cell assembly preparation is completed is obtained at the time of the shared cell slot for multi-call.
[0145]
Next, the ATM cell assembling unit, from this cellization buffer address number, that is, a cellization table address corresponding to the time slot number of the STM frame, pointer information indicating the read start position of the cellization buffer, ATM header information, multiple number Get information necessary for cell assembly.
[0146]
The ATM assembling unit obtains the payload data for 47 bytes from the cellized buffer according to the pointer information indicating the read start position of the cellized buffer and the multiplex so that a fixed number corresponding to the multiplex call is obtained. Read by rule, add ATM header, assemble into ATM cell, and send to ATM switch on ATM side.
[0147]
The ATM cell assembling process may be performed with a cell slot time width, that is, 51 ns × 54 = 2754 ns, so that there is no particular problem in terms of processing speed.
[0148]
As described above, the problems (1) to (4) are solved by the solution provided by the ATM cell assembling apparatus of the present invention.
[0149]
Next, means for solving the conventional problems by the ATM cell disassembling apparatus of the present invention will be described.
[0150]
In the ATM cell disassembling apparatus, it is desired to realize means for solving the problems (1) and (2) among the conventional problems.
[0151]
As illustrated in the correspondence relationship between the STM time slot, the cell buffer, and the cell slot of the present invention in FIG. 3, in the present invention, in the case of a multiple call, the STM frame is used by using a plurality of continuous time slots of the STM frame. The connection interface with the network is used.
[0152]
In the configuration of the ATM cell disassembling apparatus of the present invention shown in FIG. 5, when an ATM cell arrives, the ATM cell write control unit refers to the write control table and writes control corresponding to the ATM address information in the header part of the ATM cell. From the table, the time slot number and the multiplex number at the head of the STM frame for the STM data of the multiplex call sent as the payload of the ATM cell are known.
[0153]
If the leading time slot number of the STM frame is known, the ATM cell payload is written to the cell decomposition buffer having the time slot address number that is continuous from the address of the leading time slot number by a multiple, and the remaining ATM payload The data is sequentially decomposed by multiples, written to the cell decomposition buffer corresponding to the time slot of the subsequent STM frame, and this operation is performed until there is no read data in the payload portion of the ATM cell.
[0154]
The STM read control unit sequentially takes the timing delay with an allowance so that the start time of the read cycle does not reverse the time of the write cycle with respect to the delay fluctuation that the ATM cell arrives, and sequentially starts from the cell decomposition buffer. The payload data for the STM frame is periodically read out in the order of the STM frame and the time slot, the overhead information is added, and the STM frame is assembled and sent out.
[0155]
The basic procedure for ATM cell disassembly of the present invention in FIG. 6 shows the procedure for performing ATM cell disassembly in accordance with the configuration of FIG.
[0156]
As described with reference to FIG. 5, it is necessary to take a timing margin from the read start time to the write start time so that the write and read timings are not reversed due to delay fluctuations in arrival of ATM cells.
[0157]
In addition, when the ATM cell is decomposed by multiple elements, it is necessary to maintain the continuity of the address at the write start point every time the ATM cell arrives.
[0158]
Meanwhile, in the cell disassembly apparatus of the present invention, unlike the prior art, it is not necessary to go to the address conversion memory every time slot for the address to be written to the cell decomposition buffer. The 1) high-speed memory is not required and the problem (2) is to reduce the memory scale.
[0159]
Next, the present invention will be described in more detail with reference to examples.
[0160]
DETAILED DESCRIPTION OF THE INVENTION
The ATM cell assembly device and the ATM cell disassembly device will be described in this order.
1． First, the ATM cell assembling apparatus will be described.
[0161]
FIG. 7 shows the configuration of the cellized buffer, FIG. 8 shows the configuration of the cellized table, FIG. 9 shows the configuration of the multi-component table, FIG. 10 shows an example of updating the multi-chain information, and FIG. Image of writing and reading to cellized buffer for 64 kbps call of FIG. 12, image of writing and reading of multiple call to cellized buffer of FIG. 13, example of STM frame number sequence at the time of completion of preparation of multiple number N and cell of FIG. 15, the multiple number N and cellized buffer address queue example in FIG. 15, a procedure diagram immediately after the start of communication in FIG. 16, an assembly procedure diagram after the second cell in FIG. 17, a procedure at the end of communication in FIG. Description will be made based on the detailed flowchart of the procedure for writing to and reading from the cellized buffer and the detailed functional information related diagram of the ATM cell assembling apparatus of the present invention shown in FIG.
[0162]
The description is a characteristic component of the present invention.
1) Cellized buffer in FIG. 7, 2) Cellized table in FIG. 8 and 3) Multiple table in FIG. 9 in order, with reference to other related drawings. 4) Finally, FIG. 19 and FIG. 20 were used. Follow the procedure in the summary.
[0163]
The realization point of the embodiment is to correctly perform writing and reading to the cellized buffer according to a predetermined rule according to the multinary number.
[0164]
The following description will be made in order with reference to the drawings.
1) Cellized buffer
As shown in the configuration of the cellized buffer in FIG. 7, the cellized buffer is generated by the column-direction address number FR # corresponding to the cycle number of the STM frame generated by the STM frame counter and the time slot counter in the STM frame. The time slot data from the STM frame is sequentially written in units of bytes for each address specified by the combination of the row direction addresses corresponding to the time slot number TS #.
[0165]
The number of cycles of the STM frame address of the cellized buffer may be any number that is 47 or more of the number of payloads and that has a timing margin between writing and reading of data. A value of 0 to 63 is selected as the counter value.
[0166]
Similarly, the time slot number TS # has a value of 0-2047 as a counter value in 2048. Of these, as described above, in the Japanese and US hierarchy, addresses 0 to 2015 corresponding to the multiplexing number 2016 of the STM1 frame configuration are actually used.
[0167]
As shown in FIG. 7, parity bits may be added to the stored data in order to increase the reliability of internal processing.
[0168]
The writing of STM data into the cell buffer is performed sequentially in the order of the time slot numbers in the row direction while fixing the column direction address of the cell buffer corresponding to the incoming STM frame number FR #. In the next STM frame, the frame number is incremented by 1, and the writing process is similarly performed in the order of the time slot numbers in the row direction with respect to the cellized buffer in the next column. Thereafter, this cycle is repeated. In the 64th STM frame, the next new data is written from the top of the previously written data. Therefore, it is necessary to read data for cell assembly before the STM frame number is completed.
[0169]
Conversely, it is necessary to prevent the timing of reading data from the cellized buffer from overtaking the timing of writing data.
[0170]
In addition, in the cellized buffer, the STM write control unit in the principle configuration diagram of the ATM cell assembling apparatus of the present invention in FIG. 1 removes extra information such as section overhead from the STM frame, and stores only the data corresponding to the payload. A writing process is in progress.
[0171]
The image of writing and reading to the 64 kbps call compatible cellized buffer in FIG. 12 and the image of writing and reading the multiple call to the cellized buffer in FIG. 13 show the image of writing the STM data to the cellized buffer and reading the ATM payload. .
[0172]
For 64 kbps calls, writing and reading are performed while keeping the time slot number, that is, the row constant, and for multiple calls, a plurality of multiple time slots corresponding to the multiple multiple time slots used are used. It can be seen that writing and reading are performed across the lines, and in particular, in the case of reading, the reading pointer position appears as an offset shift.
2) Cellization table
The cell conversion table of FIG. 8 plays a central role in the ATM cell assembly process together with the multi-element table in the present invention, and will be described in detail with reference to other related drawings.
[0173]
In the configuration of the cell conversion table in FIG. 8, the table is configured in the order of the addresses of the time slot numbers for each channel of the communication call. In the case of a multi-call channel, since it is obvious that multiple multi-time slots are used from the first time slot, necessary information is written in the cell table table address of the first time slot number as a representative. ing. In the figure, the numerical value in parentheses represents the number of bits.
[0174]
In FIG. 8, the channel data EN is information indicating whether the time slot TS # is used for communication or not used, and is 1 when communication is in progress, 0 when not in use, 1 bit, multiple The number N indicates a multiple number including a 64 kbps call of a multiple number 1 and is 11 bits, and the ATM data represents VPI, VCI, PTI, and CLP necessary as header information in the case of ATM cell assembly, and is 32 bits. .
[0175]
The SN of AAL data is 4 bits in total, 1 bit for CSI and 3 bits for SC, as described in the configuration of ATM cell for AAL1 for ATM network communication in FIG. And when reassembling into an STM frame, it plays the role of control information for instructing transmission of STM frame position information.
[0176]
One bit of FCA (First Cell Arrival) of the control information is a flag bit, and always takes a value of 0, and is initially set to 1 in the STM frame immediately after the start of communication according to the communication start information from the exchange.
[0177]
Similarly, one bit of LCA (Last Cell Arrival) always takes a value of 0, and is set to 1 by the communication end notification information from the exchange in the STM frame at the end of communication.
[0178]
FCA and LCA are used together with EN and N to instruct communication start, steady state, and communication end, and perform processing corresponding to the next time series according to the combination of the values.
(1). Processing for first cell: FCA = 1, LCA = 0
(A). Preparation process for starting cell assembly,
(B). First cell assembly process,
(2). Subsequent cell assembly processing after the second cell: FCA = 0, LCA = 0
(3). Processing for the last cell: FCA = 0, LCA = 1
(A). Preparation for cell assembly completion
(B). Final cell assembly process
These three state processes need to be performed in chronological order. Hereinafter, description will be made sequentially.
[0179]
The above processing is performed for a 64 kbps call and a multi-party call, as shown in the write and read images of the 64-kbps call-compatible cell buffer in FIG. 12 and the multi-call write and read images in the cell buffer shown in FIG. Since the writing and reading rules are different and the cell slot usage rules are different, it is necessary to perform different processes. Therefore, a description will be given separately for each procedure for each 64 kbps call and multiple call.
[0180]
The detailed ATM cell assembly flow diagram of the present invention in FIG. 11 shows the procedure for assembling the ATM cell in the steady state from the preparation of the ATM cell assembly in chronological order along with changes in FCA and LCA, and the final ATM cell assembly procedure. Show.
(1). Processing for the first cell: FCA = 1, LCA = 0, EN = 1
As the flag bit FCA is set to 1 by receiving the control signal from the exchange, the cell table processing program operated by the μP INF unit starts communication with the current STM frame for the target time slot. Knowing that it is the first STM frame, as shown in the procedure diagram immediately after the start of communication in FIG. 16, the following processing is performed separately for 64 kbps calls and multi-way calls.
(A). For 64 kbps calls: N = 1 o'clock
(A). Preparation process for starting cell assembly FCA = 1, LCA = 0
As shown in the detailed flow diagram of the ATM cell assembly of the present invention in FIG. 11, the cellization table processing program is started, and from which address of the cellization buffer is read by the cell slot for the first ATM cell assembly for a 64 kbps call. Read pointer information indicating whether it should be output is written in the cell conversion table. After this processing is completed, the value of FCA used as a flag is returned to zero.
(B). First cell assembly process FCA = 0, LCA = 0
When the first cell slot for the 64 kbps call arrives, 47 bytes of data of the required number of bytes are written into the cellized buffer for the time slot of the 64 kbps call to be assembled by the ATM cell assembling unit. It hasn't been done yet.
[0181]
Therefore, in the first cell slot, first, the position information of the STM frame in which communication of the first 64 kbps call is started using the corresponding time slot is known from the read pointer information set in (a).
[0182]
Next, as shown in the write / read image of the 64 kbps call corresponding cellized buffer in FIG. 12, the current STM frame number indicated by the STM frame counter at the time of the first cell slot from the address of the cellized buffer indicated by the read pointer is 1 Data corresponding to the number of bytes up to the previous cell buffer address is read as the first 64 kbps payload data.
[0183]
Further, in order to make a payload of less than 47 bytes into a complete payload data form, first, the number of bytes obtained by subtracting the number of bytes from the read pointer to the previous one of the current STM frame from 47 bytes is obtained. Next, 0 continuous data for the number of bytes is created as padding data.
[0184]
Data read after the zero-continuous padding data is combined as payload data to form a complete payload, an ATM header is added, and an ATM cell is assembled and transmitted.
[0185]
At the same time, in order to correctly perform the fraction processing when the payload of less than 47 bytes is generated in the final cell assembly after the second cell, the next frame of the STM frame that has been read for the payload, that is, the current frame Set the value of the STM frame counter for the cell slot.
[0186]
In the above description, the cellized buffer up to the previous STM frame counter number at the time of the cell slot is read out so that the timing of reading data from the cellized buffer does not overtake the timing of writing data. It is to make it.
[0187]
That is, as shown in the relationship between the STM frame and the cellized basic frame of the present invention in FIG. 2, one STM frame includes 45 cell slots.
[0188]
Therefore, when the position of the cell slot exists at the earlier time position in the STM frame, there is a high probability that the writing of the STM frame data to the cellized buffer has not yet been completed.
[0189]
In the worst case, the timing of writing and reading may collide. By shifting the write and read timings in this way, the parallel operation of writing and reading data to different addresses can be performed independently and stably using the dual port memory function of the cellized buffer.
[0190]
There is also an idea that when the first cell assembly for a 64 kbps call is made, for simplification, the cellization buffer up to the previous STM frame number at the time of the cell slot is mechanically read sequentially 47 bytes backward. . That is, it is a concept that a part of an error due to past residual data may be included in the payload of the first cell. This is because in the case of a 64 kbps call, the voice is the center of data, and in the case of voice, the noise immediately after the start of communication for the first cell, ie, about 6 milliseconds, has an effect on the human ear. Based on the idea of few.
[0191]
However, as described above, 64 kbps calls are increasingly used for data communication such as dial-up connection in the Internet and mobile computing in mobile communication.
[0192]
In data communication, when a large number of errors occur in a lower layer, an error correction process is generally performed by a retransmission process using an upper layer protocol. As a result, the delay time due to the retransmission process always appears as a delay in starting the application at the start of communication every time communication connection is established.
[0193]
Even when payload data for cell conversion is not yet stored in the case of a 64 kbps call, in order to start cell conversion in the first cell slot, the communication start flag information FCA and read start pointer information are used in combination. As a result, the above problem can be avoided and correct data communication can be performed.
(B). For multiple calls: N> 1 o'clock
(A). Cell assembly start preparation process, FCA = 1
When the multiplex N is 2 or more, that is, in the case of a multiplex call, the STM frame in which the flag bit FCA is set to 1 and which STM frame is ready for cellization are determined according to the multiplex. Calculate and predict using a formula determined by
[0194]
Note that after this processing is completed, the value of the FCA used as a flag is returned to zero.
[0195]
FIG. 13 shows an image of writing and reading multi-call data to the cellized buffer. As shown in FIG. 13, the writing can be performed periodically while shifting the STM frame number in the row direction, that is, in the order of the time slot by the multiple number, but each time an ATM cell is assembled, the reading start position is the reference position. A deviation from the position, that is, an offset ofs occurs.
[0196]
When the first time slot number position of the time slot number for the multi-call is defined as a reference position, that is, ofs = 0, the next cellized preparation is completed in the cellized buffer in which the ATM cell is assembled. The next STM frame position, that is, FRR can be obtained by the following calculation formula.
(FRR −FR # −1) modulo 64 × N −ofs> 47− (1)
If the minimum FRR value that satisfies the equation (1) is obtained, the FRR becomes the STM frame number at which the next cell assembly preparation is completed. That is,
FRR = [FR # + 1 + (47 + ofs) / N]] Modulo 64-(2)
Is required.
[0197]
Here, [] means that an integer value obtained by rounding down the decimal point is adopted.
[0198]
The modulo 64 calculation takes into account that the STM frame period repeats with a numerical value of 0-63. The term +1 in the arithmetic expression means that the timing when reading the cellized buffer is read in the frame next to the STM frame in which writing has been completed, and reading of the cellized buffer in the case of a 64 kbps call is performed. However, this is the same reason as reading the cell buffer of the STM frame address up to the previous one of the current STM frame.
[0199]
The example of the STM frame number sequence calculation at the time of completion of the multinary number and cell assembly preparation in FIG. 14 is an example of calculation of the multinary number N and the STM frame number at the time of cell assembly preparation completion. However, the case where any multinary number call starts data accumulation in the cell buffer with the frame of STM frame number 0 is illustrated.
[0200]
In FIG. 14, the horizontal axis of the frame is the STM frame number, the vertical axis is the multiple number of communication calls, and the numbers in the frame are the data for 47 bytes of payload stored in the cellized buffer for the multiple calls on the left horizontal axis. The STM frame number FR # for which cell assembly preparation is completed.
[0201]
In addition, the STM frames at the start of cell conversion are all the same, starting from FR # = 0.
[0202]
In this case, the first cell assembly preparation is completed in the frame of the STM frame number 46 in the multi-factor = 1, that is, 64 kbps call, and the first cell assembly preparation is completed in the STM frame number 23 in the multi-factor = 2, that is, 128 kbps call. . Similarly, when the multiple number = 3, it means that the cell assembly preparation is completed in the STM frames of STM frame numbers 15, 31, and 46.
[0203]
In the example of the multiple number and cellized buffer address queue in FIG. 15, a queue for each multiple number at each STM frame time point is formed in the STM frame order based on FIG. The numbers in the queue indicate the number of communication calls. The subscript number represents the identification number of the communication call. In this case, the communication call of each multinary number is one.
[0204]
In FIG. 15, for example, in any column of the STM frame, the multinary number 94 ₁ There are 2 matrix elements, multinary number 47 ₁ It can be seen that one is lined up.
[0205]
In this case, since the number of each multi-way call is only one, the identification subscripts are all one. In this example, since cell assembly preparation is started from 0 having the same STM frame number, the cell assembly preparation is completed for the STM frame of the 47th STM frame number 46 at the same time.
[0206]
As is clear from FIG. 14 and FIG. 15, the timing of the first cell conversion after the start of communication and the multi-call with a large multi-element arrives earlier.
[0207]
Therefore, even if a multi-factor call with a small multi-factor arrives at the beginning of the queue of STM frames ready for cell assembly and arrives at the beginning, It can happen that the STM frame at which the subsequent multi-call is ready for cell assembly comes before the STM frame that is ready for cell assembly for the first incoming multi-call.
[0208]
In this way, using the multi-element table formed in the queue order of the modified STM frames, the cellization buffer of each cell slot is sequentially updated in the order of the address queue of the STM frame number at the time of the cell slot. When reading and ATM cell assembly are performed, even if a multi-source call with a large number of elements arrives later and a reverse of the time when cell assembly preparation is completed, the queue order is maintained correctly, and ATM cell assembly for multi-source calls is performed. Can be done.
[0209]
When all the cell assemblies for the queue of cellized buffer addresses in STM frame units corresponding to the current STM frame counter in the multiple table are completed and the queue is empty, the cell assembly is stopped.
[0210]
When the queue of the STM frame number unit of the multi-element table corresponding to the STM frame counter at the time of the cell slot is 0 from the beginning, it means that there is no multi-call payload to be sent. No ATM cell assembly is performed.
[0211]
Conversely, in the multi-element table, the ATM cell assembly / transmission for the cellized buffer address queue in STM frame units corresponding to the STM frame counter for the cell slot does not end within the period indicated by the STM frame counter, and the queue remains. Cases are also conceivable.
[0212]
This is because when 64 kbps communication calls are concentrated near a specific time slot, all the cell slots are occupied by 64 kbps calls except for empty cell slots, and cell assembly preparation is completed at the same STM frame. This occurs when ATM cell assembly / transmission for a large number of multiple calls is awaited.
[0213]
In this case, using the cell slot for the multi-call at a later time, the head of the queue is returned to the head of the previous STM frame number queue that has not yet been assembled.
[0214]
At the end of this section, the ATM cell assembly preparation procedure for multi-way calls is summarized again.
[0215]
As shown in the processing procedure of FIG. 16, the STM frame position at which reception of the first data immediately after the start of communication is started for a multi-call that has started communication using a continuous time slot corresponding to the multi-element number from a specific time slot. From (2), the STM frame number in which data for cell assembly preparation, that is, 47 bytes of data is stored in the cell buffer is calculated.
[0216]
The STM frame immediately after the start of communication is added as a new queue element at the end of the matrix of the same STM frame number column of the multiple table predicted by calculation, and at the same time as the read pointer value of the cellization table. A number and an offset corresponding to the top number of the time slot for the multi-call, that is, 0 are set.
[0217]
Also, as multi-chain information, the cellized buffer address is the same cellized buffer as itself to indicate that the cellized buffer address is arranged at the end of the queue of the STM frame sequence predicted by the multi-table calculation. An address, that is, the first value of the time slot number of the multi-call is set. The above processing is performed as a preparation for cell assembly for multi-way calls.
[0218]
A read pointer indicating the read start address position of the cell buffer for the first ATM cell is also set, and the offset value of the first read pointer always takes a value of 0 even in the case of multiple calls.
[0219]
Similarly, in response to the addition of a new multi-call cellularization buffer address as a queuing element, the multi-chain information indicating the connection between the queuing is initialized.
(B). First cell assembly process,
The ATM assembling apparatus knows the time slot number corresponding one-to-one from the cell slot counter number, and the attribute of the communication channel using this time slot from the table value of the address of the corresponding time slot number in the cellized table of FIG. Data is obtained and it is determined according to rule 1 that the cell slot is assigned for multi-call.
[0220]
In this case, the multi-element table is unconditionally referred to, the queue sequence corresponding to the STM frame at the time of the current cell slot is viewed, and the multi-table of the multi-table forming the FIFO in the order of completion of ATM cell assembly preparation. Know the cellized buffer address number or time slot number of the first element in the queue.
[0221]
Next, the cellized table of the address of this time slot number is looked at, and the cellized buffer is used as the example of the multiple call write and read image to the cellized buffer of FIG. 13 using the value of the read pointer. Then, 47 bytes are read according to the read rule corresponding to the multinary number. The ATM cell assembling apparatus adds the ATM header obtained from the cell conversion table to the read payload data and assembles and sends it out to the ATM cell.
[0222]
At the same time, the timing at which the next ATM data is stored in the cell buffer of the multi-source call is calculated using the equation (2), and the new STM frame number of the multi-unit table is used to assemble the subsequent ATM cell. At the end, the cellized buffer addresses of the multi-call are rearranged.
[0223]
That is, based on the calculation prediction result, the matrix position corresponding to the next STM frame number in the multi-element table is obtained, and as a result of the prediction process for the other past time slot data, the already arranged ATM cell assembly waiting buffer addresses The cellized buffer address for the multi-call corresponding to the newly started time slot number is added at the end of the queue.
[0224]
Also, the value of the read pointer for the time slot number corresponding to the cellized buffer address in the cellized table is set to the address value next to the address of the read point when the cellized buffer is read, and the multi-chain information Set the value of to your own timeslot number value.
[0225]
Further, the multi-element table is changed so that the queue element which is the subsequent rank of the cellized buffer address of the multi-call that has been the head until now is used as the head element to prepare for the next ATM cell assembly.
(2). Subsequent cell assembly processing after the second cell: FCA = 0, LCA = 0
This is a steady state process and will be described separately for a 64 kbps call and a multi-way call.
(A). For a 64 kbps call, N = 1
Processing for reading 47 bytes from the read pointer to the address of the STM frame number one previous to the current STM frame, and a new read in preparation for the next ATM cell in the same processing procedure as the first cell assembly A pointer value setting process may be performed.
(B). For multi-way calls N> 1
In the same processing procedure as the first cell assembly, reading is performed by 47 bytes from the read pointer in accordance with the read rule corresponding to the multiple, and a new read pointer is set and the multiple table is updated.
(3). Processing for the last cell: FCA = 0, LCA = 1
This means that the end of the communication call, that is, this STM frame is the final frame for STM data communication, and the final ATM cell assembling process is performed separately for the 64 kbps call and the multi-party call.
(A). N = 1 at 64 kbps
(A). Preparation process for cell assembly completion, LCA = 1
The end processing module of the cellization table processing program is started, flag bit LCA = 1 is sent from the exchange, the set STM frame number, that is, the frame counter value is set as the end pointer value, and the final ATM Prepare for cell assembly. At this time, the value of LCA remains at 1.
(B). Last cell assembly process, LCA = 1
In the final cell slot for the 64 kbps call, referring to the cell conversion table for this cell slot and confirming that LCA = 1 is set, the next final ATM cell assembly process is performed.
[0226]
That is, the value from the read start pointer to the read end pointer is read as a payload, and is assembled and sent to an ATM cell.
[0227]
In the case of this last cell assembly, the payload data is less than 47 bytes. Therefore, the number of bytes from the read pointer to the final STM frame number is subtracted from the 47 bytes, and the number of bytes corresponding to the number of bytes corresponding to the remaining numerical value is consecutive. Let the data be padding data. After the payload data read out earlier, this zero-continuous padding data is combined to add an ATM header as complete payload data, and it is assembled and sent out as an ATM cell.
[0228]
Simultaneously with this processing, the value of the flag bit LCA that has been used is returned to zero.
[0229]
Finally, EN is set to 0 by the signal software processing program in order to clear the cellization table value of the address of the 64 kbps time slot number and indicate that the corresponding time slot has returned to the unused state. The
(B). Multi-call N> 1
(A). Cell assembly completion preparation LCA = 1
Similarly to the 64 kbps processing, the termination processing module of the cellization table processing program is activated, and the STM frame number, that is, the value of the frame counter for the timing of the last ATM cell to which LCA = 1 is sent, the value of the read end pointer To prepare for the final ATM cell assembly. At this time, the value of LCA remains at 1.
[0230]
In the case of a multi-source call, the value of the read end pointer may be the same as that for a 64 kbps call. This is because, in the case of a multi-factor call, data is sent using time slots corresponding to the number of adjacent multi-elements for each STM frame, so the final time slot position for communication in the final STM frame is the same as that for the multi-call. This is because the time slot including the first time slot is counted to determine the position of multiple time slots.
(B). Final cell assembly process, LCA = 1
The time slot information of the cellization table corresponding to the cellization buffer address at the head of the queue brought from the multiple table is the cell slot to which the target cell slot is assigned for the multiple call, and the flag bit LCA = 1. This is a case where it is found that it is the last frame of STM.
[0231]
In this case, in the final cell slot for the multi-call, referring to the cellization table for this cell slot, that is, the time slot, and confirming that LCA = 1 is set, the next final ATM cell assembly process is performed. .
[0232]
That is, a value from the read start pointer to the end pointer is read as a payload, and is assembled and sent to an ATM cell. The read rule may be exactly the same rule as in the steady state.
[0233]
At this time, as in the case of the 64 kbps call, 0 consecutive data of the number of bytes obtained by subtracting the number of bytes counted from the read start pointer to the end pointer from 47 bytes is created as padding data, and after the previously read data Combined, ATM header information is added as a complete 47-byte payload, and assembled and sent out to an ATM cell.
[0234]
Simultaneously with this processing, the value of the flag bit LCA that has been used is returned to zero.
[0235]
Further, the queue elements in the multi-element table for the multi-call are left deleted.
[0236]
Finally, as in the 64 kbps call, the time slot number table for the multiple call in the cellization table is cleared and EN = 0 is set.
[0237]
Next, the read pointer and the end pointer have been briefly described in the above description of the functions of the FCA and LCA, but will be described in more detail.
[0238]
The read pointer is represented by a shift of the read start position of the STM frame number FR # 6 bit and the time slot TS # generated every time an ATM cell is assembled, that is, a total of 17 bits of the offset number ofs11 bits.
[0239]
The read pointer indicates the read start position of the cellized buffer when the ATM cell is assembled, as shown in the write and read images of the cellized buffer for the 64 kbps call in FIG. 12 and the write and read images of the cellized buffer for the multiple call in FIG. Refers to information. The read pointer is written with a new value every time the cell buffer is read in preparation for the next cell assembly.
[0240]
By using the FRTM indicated by the read pointer, the value specified from the time slot TS # and the offset ofs as initial values, the STM frame counter for generating the read address and the time slot counter periodically perform a count-up operation. Data is read from the cellized buffer.
[0241]
In the case of a 64 kbps call, it plays an important role when the first cell is assembled immediately after the start of communication. In addition, in the case of 64 kbps calls and multi-source calls, each time an ATM cell is assembled in a steady state, the cell buffer is read using this read pointer as a read start point. The read pointer plays an important role in combination with the end pointer when the payload is correctly processed at the end of the communication call, that is, when the payload assembly process of less than 47 bytes is performed.
[0242]
Hereinafter, the case of a 64 kbps call and the case of a multiple call will be described separately.
(A). First, in the case of a 64 kbps call, the necessary payload data is obtained by reading the cellized buffers having the same STM frame time slot numbers in the order of the STM frame FR # numbers in the configuration of the cellized buffer of FIG. Therefore, the offset ofs is always set to 0 in the read pointer in cell assembly. This is also apparent from the image of writing to and reading from the 64 kbps call compatible cellized buffer in FIG.
(B). Next, in the case of multiple calls, data of multiple multiple time slots per STM frame comes periodically adjacently.
[0243]
Therefore, immediately after the start of the call, if the assigned time slot number and the multiple number in the first STM frame at the start of the call are known, the arrival time of the subsequent STM frame in which 47 bytes of information are accumulated is Because it is repeated repeatedly, it is easy to calculate and predict.
[0244]
However, in this case, unlike the case of the 64 kbps call, the read of the next payload is performed each time 47 bytes of data are read for the payload as shown in the image of writing and reading the multiple call to the cellized buffer in FIG. The start position takes a value different from the offset position ofs of the previous read start position.
[0245]
The first reading start position of the multi-call, that is, the first time slot position is defined as a reference position (ofs = 0) of the reading position shift in the column direction in the STM frame, that is, the offset ofs.
[0246]
At this time, for example, if N = 5, the offset position when the first ATM cell assembly is completed and the next second ATM cell assembly is started is obtained as 47 modulo 5 = 2. Further, when the next ATM cell is assembled, (47-3) modulo 5 = 4 is obtained.
[0247]
In order to obtain the offset value shifted every time by actual circuit processing, information on the deviation from the reference position of the STM frame number address and time slot number of the cellized buffer at the end of cell assembly is read from the value of the address counter. obtain.
[0248]
When 1 is added to the value of deviation from the reference position obtained from this address counter and the result of modulo 5 arithmetic processing, that is, remainder operation is 0, the end position of the payload read is the read STM for the multi-call. This means that it was the final position of the reading position in the column direction of the address corresponding to the frame number.
[0249]
Accordingly, in this case, the STM frame position at the next reading start position is set to a value obtained by adding 1 to the STM frame number FR # from which the payload data has been read, as the STM frame number in the new read pointer. A value of offset ofs = 0 is set.
[0250]
When the remainder calculation is a value other than 0, the STM frame number of the reading counter at the reading end position is used as the STM frame information of the next reading pointer, and 1 is added to the deviation value from the reference position at the reading end position. The value is set as offset information for the next read pointer.
[0251]
Thereafter, each time ATM cell assembly is performed, the above process is repeated to update the value of the read pointer.
[0252]
The end pointer is 6 bits, and is described in the case of FCA. However, when the end frame of the STM communication call is detected, the final ATM cell assembly for the specific communication call is 47 bytes generated in the ATM payload. Rounding off less than
[0253]
The offset is unnecessary as information, and if the value of the final STM frame is known, the final cell can be assembled for both 64 kbps calls and multi-way calls.
[0254]
With regard to the cell table shown in FIG.
[0255]
The multi-chain information includes the cell buffer of the column in which the cell buffer address of the cell assembly preparation completion for the multi-call forms a queue in the multi-table where the cell buffer address and thus the time slot number forms a queue. Points to the next cellized buffer address of the address.
[0256]
At this time, when the cell assembly buffer address waiting for cell assembly is arranged at the end of the queue, the multi-chain information is associated with the own cellization buffer address, that is, the STM frame, to indicate the end of the queue. Set the time slot number value. Such a case occurs immediately after the start of communication and immediately after ATM cell assembly.
[0257]
That is, immediately after the communication for the multi-call is started, the STM frame position at the time when the cell assembly preparation is completed is predicted and arranged as a new queue element at the tail of the queue corresponding to the STM frame number. Sometimes there is no subsequent queue element, so it sets its own address, that is, the address value of the cellized buffer that has entered cell assembly waiting.
[0258]
Similarly, when the ATM cell assembly steady mode is entered and the ATM cell is assembled for the multi-call, the end of the queue corresponding to the next STM frame in which the preparation for the next ATM cell assembly for the multi-call is completed. Rearrange to. At this time, since there is no subsequent queue element, the multi-chain information sets its own address.
[0259]
On the other hand, this new multi-chain information at the address of the time slot number of the cellization table for the queue element that was the last queue element immediately before the new queue element was added to the tail of the queue is newly added. The cellized buffer address of the multi-call added at the end, that is, the time slot number is written.
3) Multiple table
Next, the configuration of the multi-element table in FIG. 9 will be described.
[0260]
As shown in FIG. 9, for each STM frame number arranged in the sequence order, a cell buffer address waiting for cell assembly, that is, a queue of time slot numbers of the corresponding STM frame is formed. The numbers in parentheses in FIG. 9 indicate the required number of bits.
[0261]
Further, multi-chain information indicating the connection of multi-calls is held in the cell conversion table.
[0262]
In FIG. 9, for each queue of each STM frame, the first address value, the last address value of the cellization buffer to be cellized, the number of queue elements arranged in the STM frame, that is, the number of channels to be transmitted Is stored.
[0263]
The cellized buffer address value, that is, the time slot value arranged in the first queue as a multi-call immediately after the start of communication as the system automatically becomes the head of the queue, and thereafter, the STM frames are arranged in the STM frame order. The queue is formed so that the first queue element is always taken out as the first element of the queue of the multi-element table by the FIFO logic in the sequence order of the STM frame.
[0264]
The update example of the multi-chain information in FIG. 10 shows an update example of the multi-chain table and the multi-chain of the cellized table.
[0265]
FIG. 10 shows an excerpt of a table of the multi-chain information section showing the connection of the multi-call queue in the cell conversion table.
[0266]
In FIG. 10, it is assumed that the top cellized buffer address of the cell assembly target, that is, the time slot value at the head of the queue, that is, the time slot value is TS # = 3 in the second column of frame number FR #.
[0267]
In this state, when cell assembly is performed for a multiple call for the cellized buffer address of TS # = 3, TS # = 6 of the next queue element of the STM frame of FR # = 2 becomes the next cell assembly queue. As the first element, the first TS value of the STM frame FR # = 2 in the multi-element table is rewritten. Here, the TS value of this subsequent queuing element is obtained from the multi-chain information in the cellization table as described in the right of FIG. 10 with the multi-chain information extracted from the cell conversion table. In addition, the number of queue elements in the array of FR # = 2 is reduced from 3 to 2.
[0268]
At the same time, the predicted STM frame point at which the next cell assembly preparation for the TS = 3 cellized buffer address is completed is calculated by a predetermined calculation formula to obtain FR # = 8.
[0269]
The tail of this FR # = 8 queue was the cell buffer address of TS = 27, but this value is rewritten to TS = 3.
[0270]
At the same time, the multi-chain information for the last queue element of the queue of FR # = 8, TS = 27, is rewritten from TS = 27 to a new value, TS = 3.
[0271]
Finally, the multi-chain information in the cellization table corresponding to TS = 3 is set to TS = 3 in order to indicate that the multi-chain information is aligned at the end of the queue from the value of TS = 6 of the previous multi-chain information. .
[0272]
The same processing may be performed every time a new multi-way call is generated and when ATM cell assembly is completed.
3) General explanation
The above description is summarized and shown in an overall detailed flowchart of the ATM cell assembling procedure of the present invention in FIG. 19 and a function information related diagram of the ATM cell assembling apparatus of the present invention in FIG.
[0273]
A brief summary will be described below.
[0274]
In the operation flow of FIG. 19, the basic realization elements that characterize the present invention are the cellized buffer, the cellized table, and the multiple table in the principle configuration diagram of the ATM cell assembling apparatus of the present invention of FIG.
[0275]
The μP INF unit that has detected that a new communication call has occurred sets the initial value of the cellization table. As described above, the initial value is set by setting the value of the control information FCA from 0 to 1, setting the read pointer value corresponding to each of 64 kbps call and multiple call, and the first multiple chain. In the case of information, that is, setting of own TS value, setting of header value of ATM cell, multiple call, calculation of STM frame position to be prepared for assembly of ATM cell determined according to multiple number from this communication start STM frame position, and This includes updating the multi-element table by adding queue elements to the multi-element table.
[0276]
As shown in FIG. 9, the STM data is written into the cell buffer section at the time position where the frame counter in the order of the frame number FR # virtually added to the STM frame and the channel data in the STM frame are sent. On the other hand, it is periodically performed in the order of TS counters assigned numbers in order. The cellized buffer address has a one-to-one correspondence with the address value indicated by the write counter. At this time, unnecessary information such as the section overhead of the STM frame is removed.
[0277]
On the other hand, the reading of the payload data from the cellization buffer performed by the cell assembling unit is periodically performed at the timing of the cell slot which is a quantized time slot in the cellized basic frame shown in FIG.
[0278]
At this time, as described above, in the case of a 64 kbps call and a multi-party call, the STM data writing to the cellized buffer and the data reading timing for the ATM payload are read while being controlled so as not to be reversed. Dashi processing is performed.
[0279]
In the case of a 64 kbps call and in the case of a multi-way call, the usage of cell slots, the rules for reading a cell buffer, and the rules for updating the cell-by table are different. Need extra.
[0280]
As described above, the attribute of the cell slot is determined by referring to the attribute data of the time slot number of the cellization table corresponding to the cell slot number on a one-to-one basis.
[0281]
In the case of a 64 kbps call, when the first cell is assembled, the value of the STM frame at the start of communication is obtained as read pointer information indicating the read start position of the cell buffer. Payload data is read from the cell buffer address for the STM frame from the read start position to the previous STM frame of the cell slot, and an ATM header is added to assemble it as an ATM cell and sent to the ATM network side.
[0282]
In the case of a multi-call, the cell slot is an empty cell slot, a cell slot in which communication is not performed in the time slot of the corresponding STM frame, or a multi-call using a time slot of the STM frame corresponding to the multi-call. In this case, the cell slot is a cell slot that may be used as a shared slot by a multi-way call.
[0283]
Therefore, in this case, go to the multiple table and refer to the cell buffer read in the order of waiting for cell assembly, that is, the read value of the cell buffer using the first value of the queue of time slot numbers. Read with.
[0284]
At the same time, the cellized table and the multiple table are updated by the procedure described in the update of the multiple chain information in FIG.
[0285]
FIG. 20 shows a functional information related diagram of the ATM cell assembling apparatus according to the present invention, in which the above description is integrated.
[0286]
Mutual exchange of necessary information between each functional element, clocks necessary for each operation, and the like are shown. The actual configuration of each functional unit is realized by a combination of software processing such as computation using a microprocessor and mutual transfer of data, and hardware processing units such as a clock generation unit.
[0287]
Briefly, the STM multiplexed data is temporarily stored in the STM write control unit, subjected to serial / parallel conversion processing, stored in the buffer in units of bytes, and then excludes the section overhead unit. Only the time slot data of the channel data part is extracted and written sequentially into the cell buffer, in the STM frame order and in the time slot order.
[0288]
In parallel with these, the information at the start of the call from the exchange is obtained, and various initial setting values are written in the address corresponding to the time slot in the cell table where the call is started. Is a multi-way call, a new queue element is added to the multi-way table.
[0289]
The ATM cell assembling unit performs the ATM cell assembling operation in parallel for each cell slot quantized with the period of the cellized basic frame, and for each cell slot, a cell slot is allocated for a 64 kbps call. Information on whether the call has been completed or used for multiple calls from the information stored in the address of the time slot number corresponding to the cell slot of the cellization table on a one-to-one basis, corresponding to each of 64 kbps call and multiple call Perform cell assembly operation.
[0290]
In the case of a 64 kbps call, in the case of cell assembly immediately after the start of communication, the flag information FCA is 1, so that the first cell assembly is known and communication is started using the read pointer information. The correct number of payload data starting from the frame is read from the cellized buffer.
[0291]
In the case of multiple calls, the cell table buffer address of the first queue element ready for ATM cell assembly is known from the multiple table, and based on the read start pointer information and multiple number of this cell buffer address, that is, the time slot number. Read the cell buffer.
[0292]
Further, in accordance with this reading process, the next queue position is calculated, the multi-element table is updated, and the cellization table is simultaneously updated. When reading data from the cellization table, control is performed so that data is read from a cell that has been prepared for cellization and the timing of writing and reading data to the cellization table is not reversed.
[0293]
In FIG. 20, the generation rules are different between the case where the counter clocks FR # and TS # for controlling cell read buffer read are 64 kbps and the case of a multi-source call, and particularly in the case of a multi-source call, this occurs every time an ATM cell is assembled. In order to absorb the difference in offset, the read operation is performed while obtaining the offset data from the cell conversion table by the read pointer and changing the value of the address clock corresponding to the read start position each time.
[0294]
Next, a description will be given of a procedure when CSI becomes 1 and pointer information indicating the frame synchronization position of the STM frame must be sent.
[0295]
In this case, since the payload portion of the ATM cell needs to receive the instruction information of CSI = 1 and send the frame synchronization position information of the STM frame, it normally uses 47 bytes as the payload. One byte is used as pointer information. For this reason, the number of payload data in the ATM cell is 46 bytes.
[0296]
In this case, the STM frame number for which the assembly preparation of the ATM cell is completed is earlier, but the calculation of the STM frame number can be easily corrected by replacing the value of the number of payloads 47 in Equation (2) with 46. Is possible.
[0297]
In addition, when reading the cellization table for the corresponding time slot in the cellized slot and confirming that the flag of CSI = 1 is set, when reading data from the cellized buffer, the read pointer is used. Data of only 46 bytes is read as payload data.
[0298]
In this way, even when the payload data becomes 46 bytes corresponding to CSI = 1, it is possible to easily cope with the change by simply changing the control parameter without changing the circuit and the processing algorithm.
[0299]
The ATM cell assembling apparatus of the present invention has been described in detail above.
2. Next, the ATM cell disassembling apparatus of the present invention will be described.
[0300]
In addition to the configuration of the ATM cell disassembly apparatus of the present invention of FIG. 5, the outline of the cell disassembly process of the present invention for the 64 kbps call of FIG. 21, the outline of the cell disassembly process of the present invention for the 128 kbps call of FIG. Description will be made based on the configuration of the cell decomposition buffer, the configuration of the write control table in FIG. 24, the write sequence example in FIG. 25, and the read sequence example in FIG.
[0301]
As outlined in the configuration of the cell disassembly device of the present invention in FIG. 5, in the cell disassembly device of the present invention, as shown in FIG. 21 and FIG. 22, the ATM payload is STM in the case of a 64 kbps call. In the case of a call of 128 kbps, one byte at a time in the frame number order, it is only necessary to allocate and disassemble to time slots that are continuous by 2 bytes every STM frame period. FIG. 21 shows an example in which an ATM cell having an address value specified by VPI and VCI is disassembled into the position of time slot 5 in the STM frame. Similarly, FIG. 22 shows an example in which a multiplex call with multiplex number = 2 is disassembled into the positions of time slots 5 and 6 in the STM frame.
[0302]
In the case of a multiple call, the payload data of the ATM cell is generally decomposed into N time lots for each STM frame in a cluster of N bytes.
[0303]
As shown in the configuration of the cell decomposition buffer in FIG. 23, the address number assigned to the STM frame has a period value of 0 to 127, and is twice as large as the ATM cell buffer.
[0304]
This is because delay fluctuation absorption is taken into consideration. Each data storage area stores data in which parity bits are added to 8 bits as necessary.
[0305]
The time slot number is assigned a value from 0 to 2047 for each STM frame number. Of these, addresses from 0 to 2015 are actually used.
[0306]
In the case of a 64 kbps call, 1-byte data is read from the ATM cell and written for each STM frame. The time slot number for writing is obtained from the write control table.
[0307]
In the case of a multi-way call, writing is performed to continuous addresses corresponding to the multi-way number continuously from the address of the first TS number. At this time, the writing control unit performs writing by specifying the buffer address to be written from the first TS number obtained from the control table and the multiple number.
[0308]
On the other hand, the reading process on the STM side is always performed at a constant cycle independently of the writing side. That is, for each 125 μs STM frame, one frame of data is read from the ATM cell disassembly buffer in the order of TS numbers.
[0309]
The processing in the STM frame only needs to read data while cyclically counting up the STM frame clock and the TS clock.
[0310]
On the other hand, ATM cells generally have delay fluctuations due to fluctuations in waiting time when a path is used even if information is transmitted on the same path due to the degree of traffic congestion in the network.
[0311]
As a result, on the STM frame side, data is always read out at a constant cycle, whereas writing to the ATM cell disassembly buffer is performed in the time that is shifted by the delay fluctuation of arrival of the ATM cell. It will be.
[0312]
Therefore, in order to secure a time margin so that the write and read timings are not reversed taking this fluctuation into consideration, as shown in FIG. 23, the read start time on the STM frame assembling side is set in the case where there is no delay fluctuation. Assume that the start time position of the read frame clock on the STM frame side used for reading is delayed by an allowance time τ with respect to the write start time of the frame clock FR # used for writing used for disassembling. In the example of FIG. 23, the case of τ = 125 μs × 3 = 375 μs is illustrated. Conversely, when the read side is used as a reference, this means that data is written using a frame clock that is earlier by τ time than the frame clock on the read side.
[0313]
FIG. 24 shows the configuration of the write control table.
[0314]
In FIG. 24, each control data is held as a table for each communication channel determined from the VPI / VCI pair. The numbers in parentheses indicate the required number of bits.
[0315]
The ATM input cell VPI / VCI has a one-to-one correspondence with the channel number of the STM frame, that is, the TS number, and stores the following parameters for each VPI / VCI of the input cell. Each parameter has the following meaning.
EN: Call setting information (EN = 1: Call set, EN = 0: No call set)
N: Multiple (N = 1: 64 kbps call, N = 2: 128 kbps)
TTS: First time slot
TAU: Delay fluctuation absorption value (Example: When TAU = 2, fluctuation absorption for 2 STM frames, that is, 250 μs is possible. Also defined as τ = TAU + 1)
FCA: first cell arrival information (0: first cell not arrived, 1: first cell arrived)
Using this flag information, the arrival of the first ATM cell is detected, and a margin is set for delay fluctuation of the ATM cell through the setting of the first address position at the start of ATM cell disassembly.
LCA: indicates that the ATM cell is the last cell. In this way, preparation and end processing for cell disassembly end processing is performed. Normally, it takes a value of 0, and is set to 1 according to the setting information from the exchange side when communication ends, and is returned to 0 simultaneously with the end processing.
FR: Pointer information indicating the frame number of the first write start position when the payload decomposition data of the ATM cell is written to the ATM cell decomposition buffer with the write pointer 1 and used in combination with the write pointer 2 in the case of a multi-call. .
TS: Pointer information indicating the time slot number of the first write start position when the payload decomposition data of the ATM cell is written to the ATM cell decomposition buffer with the write pointer 2, and is used only in the case of multi-way calls. Used as a set with 1.
FRL: Last STM frame number for the last cell. End pointer information for data writing
Here, TS of the write pointer 2 indicates that the reading start position information of the time slot is shifted every time the ATM cell is decomposed, and is displayed as an absolute number, but when reading from the cellized buffer Similarly, it is possible to define a relative value from the reference point, that is, the first time slot TS.
[0316]
The write pointer 2 is a write start position that occurs when the data of the ATM cell payload number 47 is decomposed into each STM frame for each reason in the same manner as the read pointer in the case of a multi-source call. Is shown for the next ATM cell decomposition start.
[0317]
At the time immediately after the communication is started and the call is set up, EN, N, TTS, and TAU are written into the write control table by a microprocessor or the like.
[0318]
FIG. 25 shows an example of a write sequence.
[0319]
In FIG. 25, WD is the number of written bytes, WFD is the number of written bytes in the STM frame, TTS is the first time slot number in the STM frame of the multi-call, WFR is the STM frame number at the time of writing, WTS indicates a time slot number at the time of writing.
[0320]
Processing rules differ between the first cell that arrives immediately after call setup and the second and subsequent cells.
[0321]
In the first cell, in order to absorb delay fluctuation, writing is performed from the frame position shifted forward with respect to the STM frame side for reading by τ = TAU + 1. At this time, the write start address is the start position of the time slot.
[0322]
Here, the meaning of +1 in the expression of τ means that even if the delay fluctuation of arrival of the worst ATM cell occurs up to the fluctuation absorption value TAU, a margin of one STM frame is still observed.
[0323]
At the time when the decomposition of the first cell is completed, the time corresponding to the address VPI / VCI of the ATM cell in the control table is used as the write start pointer information at the time of the next write. Write to the slot number address.
[0324]
In the second and subsequent cells, following the first cell decomposition process, the cells are decomposed in the same manner from the address next to the address at which the decomposition of the first cell is completed.
[0325]
In the sequence on the left side of FIG. 25, when a call is set up immediately after the start of communication, the first write start point when the first cell is decomposed is absorbed with respect to the read frame in order to absorb delay fluctuation. This means that writing to the buffer is started from a position preceding by TAU + 1 frame. The start position of the time slot corresponds to the start position of the multi-call STM frame.
[0326]
The sequence on the right side of FIG. 25 is a processing procedure for writing 47 bytes of data for each STM frame by multiples and repeating the process to write data for the necessary STM frames. Show. Similarly, the address next to the address immediately after the end of the second cell is updated, and the control table is updated as the decomposition start position address at the time of the next cell decomposition. Thereafter, the same cycle is performed to the end.
[0327]
FIG. 26 shows a read sequence on the STM side. This indicates that data read processing is performed in the order of the cycle clock RFR of the STM frame and the time slot counter clock RTS.
[0328]
Here, RFR takes a value from 0 to 127, and RTS cycles from 0 to 2429. Of the RTS, 0 to 2015 corresponding to the time slot of the STM frame are actually used as the STM data.
[0329]
Thereafter, it is combined with the STM section header data and sent to the STM network side as STM frame data.
[0330]
As described above, in the ATM cell disassembling apparatus of the present invention, memory access and high-speed memory for address conversion are not necessary on the writing side, and ATM suitable for downsizing, economy, and low power of the apparatus. A cell disassembly device can be realized.
[0331]
Finally, the extended invention of the present invention will be supplementarily described.
[0332]
That is, in the above description, in order to avoid complexity of the description, the description has been made assuming that the communication call that requires real-time performance is only a 64-kbps call centered on voice, that is, a multinary one.
[0333]
However, in recent years, with the development of multimedia applications on the Internet, there have been cases where real-time characteristics are required for multi-rate communication calls of 64 kbps or higher such as video broadcasts and moving image communications.
[0334]
Also in the field of mobile communication, a high-speed digital communication service of 64 kbps or higher including moving images using W-CDMA is planned.
[0335]
Therefore, the present invention has been expanded and applied to such multi-way calls that require real-time characteristics such as moving images in addition to voice in such multi-way calls having a multiplex number N of 1 or more. Explain what you can do.
[0336]
The present invention is particularly applicable to a case where the present invention is applied to a multi-call in which a multi-factor having a multi-element number of about 2 to 3 is not so large and a relative improvement effect is large compared to a multi-element 1 64-kbps call. Great effect.
[0337]
In the present invention, as mentioned briefly in the explanation of the means for solving the problem, when cell assembly is performed in an ATM cell assembling apparatus for N> 1 multi-distance calls requiring real-time performance, the multi-element 1 The idea of the case is extended and applied as it is.
[0338]
That is, for cell lots allocated for multi-calls that do not require other real-time characteristics, the cell slot is used by all multi-calls in a shared manner, and the head of the queue that is queued in the multi-table is used. ATM cells are assembled and transmitted in order from the multi-party call.
[0339]
However, for a multi-call that requires real-time performance, in the case of a multi-call with a real-time request flag set in the cellization table corresponding to the cell slot, the cell slot is the same as the case of a 64 kbps call. Similarly, it is assumed that the multi-way call is occupied and used.
[0340]
That is, the communication data of multiple adjacent time slots of the STM frame for the multiple call for which real-time communication is requested uses multiple continuous cell slots corresponding to the time slot in a one-to-one relationship. Assembling and sending out ATM cells.
[0341]
By doing so, it is possible to cope with a multi-way call requiring real-time performance without changing the basic configuration and concept of the present invention.
[0342]
However, this extended invention has application restrictions because the occurrence of bursts of cells becomes large when the multinary number is large.
[0343]
27 shows the configuration of the cellization table in which the real time request flag R described above is added to the expanded configuration of the cellization table of FIG.
[0344]
A flag bit R for requesting real time property is added to the channel data. This information is obtained as signal information from the exchange side, and is set as a cellization table value of an address having a number corresponding to the channel (time slot) of the corresponding multiple call. R = 0 for a normal multi-way call, and R = 1 is set for a multi-way call that requires real-time performance.
[0345]
As a result, when a multi-call, ie, N> 1, and a communication call with R = 1 arrives, the multi-call is considered to correspond to the time slot of the STM frame in the same manner as the 64 kbps call. Assemble and send ATM cells by associating the relationship of cell slots on the cellized basic frame to one-to-one.
[0346]
The cell slot is not used in common with other multi-calls, but is used exclusively by specific multi-calls that require real-time performance, but the rules for writing and reading data to the cellized buffer are as follows: The same as in the case of a normal multi-way call.
[0347]
Accordingly, the setting and updating of the reading pointer are performed according to the same rules as in the case of multiple calls.
[0348]
As shown in the detailed flow chart of the writing and reading procedure to the cellized buffer in consideration of the extension to the real-time call in FIG. 28, the multi-call (N> 1) in the time slot corresponding to the cellized slot is real-time. For a call with a request (R = 1), as in the case of a 64 kbps call, the cell slot is occupied exclusively by a multi-way call requesting real-time property transmitted using the corresponding time slot, and the ATM cell. Assembling and sending out.
[0349]
Note that the ATM cell disassembly device is always restored to the STM frame period data, so there is no need to maintain real-time characteristics as in the case of ATM cell assembly, and other N> 1 multi-calls. Similarly, the ATM cell may be disassembled. In particular, the present invention may be applied as it is without changing the expansion.
[0350]
In particular, the present invention is applied in the range of N = 2 to 3 where the multinary number is not so large, and the influence of burst generation on the ATM network side is suppressed to a small extent. Can be effective.
[0351]
【The invention's effect】
The ATM cell assembling / disassembling apparatus of the present invention eliminates the need for high-speed memory, reduces the memory scale, eliminates the need for complicated processing for avoiding mutual collision during ATM cell assembly, and provides the same multi-factor for multiple calls. It is possible to realize a device suitable for LSI implementation that suppresses burst generation of ATM cells for calls and achieves effective load distribution to the ATM network, and its application effect is great.
[Brief description of the drawings]
FIG. 1 is a principle configuration diagram of an ATM cell assembling apparatus according to the present invention.
FIG. 2 shows the relationship between the STM frame and the cellized basic frame of the present invention.
FIG. 3 is a correspondence relationship between a time slot, a cell buffer, and a cell slot of an STM frame according to the present invention.
FIG. 4 is a basic procedure for assembling an ATM cell according to the present invention.
FIG. 5 is a configuration of an ATM cell disassembling apparatus according to the present invention.
FIG. 6 is a basic procedure of ATM cell decomposition of the present invention.
FIG. 7 shows a configuration of a cell buffer.
FIG. 8 is a configuration of a cellization table.
FIG. 9 is a configuration of a multi-component table.
FIG. 10 is an example of updating multi-chain information.
FIG. 11 is a detailed flow diagram of ATM cell assembly of the present invention.
FIG. 12 is an image of writing and reading in a cell buffer for 64 kbps call.
FIG. 13 is an image of writing and reading a multi-source call to a cell buffer.
FIG. 14 is a calculation example of an STM frame number sequence at the time of completion of multiple number N and cell assembly preparation.
FIG. 15 is an example of a multinary and cellized buffer address queue.
FIG. 16 is a procedure diagram immediately after the start of communication;
FIG. 17 is an assembly procedure diagram after the second cell.
FIG. 18 is a procedure diagram at the end of communication.
FIG. 19 is a detailed flowchart of a procedure for writing to and reading from a cellized buffer.
FIG. 20 is a functional information related diagram of the ATM cell assembling apparatus of the present invention.
FIG. 21 is an overview of the cell disassembly process of the present invention for a 64 kbps call.
FIG. 22 is an overview of the cell disassembly process of the present invention for a 128 kbps call.
FIG. 23 is a configuration of a cell decomposition buffer according to the present invention.
FIG. 24 is a configuration of a write control table.
FIG. 25 is an example of a write sequence.
FIG. 26 is a read sequence example.
FIG. 27 shows an expanded configuration of a cellization table.
FIG. 28 is a detailed flow diagram of a procedure for writing to and reading from a cellized buffer in consideration of expansion to a multiple real-time call.
FIG. 29 is an ATM cell assembling / disassembling apparatus for interconnecting an STM network and an ATM network.
FIG. 30 shows the correspondence between the ATM cell assembling / disassembling apparatus of the present invention and the application field.
FIG. 31 is a multiplexing hierarchy of SDH.
FIG. 32 shows the frame structure of STM1.
FIG. 33 shows the configuration of an AAL1-compatible ATM cell in the ATM network.
FIG. 34 shows an AAL1 ATM cell assembly / disassembly mechanism for a 64 kbps call.
FIG. 35 is a configuration of a conventional ATM cell assembling apparatus.
FIG. 36 is an explanatory diagram of cell assembly in a conventional ATM cell assembly apparatus.
FIG. 37 shows conventional ATM cell assembly for multi-call data.
FIG. 38 is a flowchart of a procedure for writing STM multi-call data to a cellized buffer according to the prior art.
FIG. 39 shows a mechanism for writing into a cellized buffer according to a conventional configuration.
FIG. 40 is a configuration example of a conventional ATM cell disassembling apparatus.

Claims (9)

In an ATM cell assembling apparatus for converting STM (Synchronous Transfer Mode) data into ATM (Asynchronous Transfer Mode) cells,
When transmitting / receiving multi-rate communication call data to / from the STM network, use the continuous multi-factor time slots in the STM frame,
When an ATM cell is assembled and sent to the ATM network, a cell slot obtained by time-quantizing the basic cell frame of time length obtained by multiplying the STM frame period by the number of payloads with the time width of the ATM cell is used.
ATM cell assembly / transmission for a communication call that requires real-time performance is performed in a specific cell slot that repeats periodically in the cellized basic frame corresponding to the communication call on a one-to-one basis,
In the ATM cell assembly / transmission for a multi-call that does not require real-time performance, the cell slot that is not allocated to a communication call that requires real-time performance is used as a shared cell slot for multi-call, and the ATM cell assembly preparation is completed. An ATM cell assembling apparatus characterized by performing in the order of calls . The ATM cell assembling apparatus according to claim 1,
A first data buffer for storing the STM data for each STM frame;
A write control unit for storing the STM data in the first data buffer byte by byte for each STM frame and each time slot;
An ATM cell assembly control unit which reads out desired data for ATM cell assembly from the first data buffer for payload and performs ATM cell assembly,
The write control unit performs a write process on the first data buffer for each STM frame and each time slot in the arrival order of the STM data independently of the ATM cell assembly control unit,
The ATM cell assembly control unit reads the data from the first data buffer, assembles the ATM cell into an ATM cell, and the STM data necessary for the ATM cell assembly unit to perform data reading and ATM cell assembly. The cellization table for storing attribute data for each time slot, and the address of the first data buffer is FIFO (in order of completion of storing data necessary for ATM cell assembly in the first data buffer for the multiple call. First In First Out) with multiple tables forming a logical queue,
The ATM cell assembling unit assembles an ATM cell based on data of the cell conversion table and the multi-component table . The ATM cell assembling apparatus according to claim 2 ,
The ATM cell assembly control unit
When an ATM cell is assembled, it is detected from the attribute data of the address of the corresponding time slot in the cellization table that the cell slot into which the ATM cell is assembled is a cell slot allocated for multi-call. The multi-call data buffer address value at the head of the queue is obtained from the multi-table, and the multi-call call is obtained from the cellized table at the time slot address corresponding to the data buffer address value on a one-to-one basis. An ATM cell assembling apparatus characterized in that a read control parameter necessary for the data acquisition is acquired and data is read from the first data buffer . The ATM cell assembling apparatus according to claim 2 ,
The data for each time slot making up the cellization table is:
A flag bit indicating the start of a communication call;
Instructing the starting point of data reading from the first data buffer, set at the start of communication, and updated when the payload data is read from the first data buffer,
A flag bit that indicates the end of communication;
ATM cell assembling apparatus characterized by being composed of a completion pointer to the end point of the data read from the first data buffer. The ATM cell assembling apparatus according to claim 4 ,
The multiple table is
The data buffer address for each multi-call is configured by concatenating a queue formed as a FIFO logic queue in units of STM frames in the order of completion of accumulation of data of the number of payloads, in the order of STM frame numbers,
For each ATM cell assembly for the multiple call, based on the number of payloads, the multiple number, and the payload data read end address position data of the first data buffer,
Prediction of the queue time position in units of a new STM frame in which data for the next payload number has been accumulated in the first data buffer area allocated for the multiple call,
An ATM cell assembling apparatus, wherein the arrangement position of the queue is updated . The ATM cell assembling apparatus according to claim 5 ,
The data table that displays the queue for each STM frame of the multi-element table is:
A data buffer address value of the first matrix element of the queue of the STM frame, a data buffer address value of the last matrix element, and a length of the queue;
The address of the subsequent queue element of the first matrix element is
In the table for each time slot in the cellization table corresponding one-to-one to the data buffer address of the head matrix element, it is held as multi-chain information,
In the table for each time slot in the cellization table corresponding one-to-one to the data buffer address of the last matrix element, the time slot value of the cellization table is held as multi-chain information. ATM cell assembly equipment. In an ATM cell disassembly device that converts ATM cells into STM data,
When transmitting / receiving multi-rate communication call data to / from the STM network, use the continuous multi-factor time slots in the STM frame,
When an ATM cell is assembled and sent to the ATM network, a cell slot obtained by time-quantizing the basic cell frame of time length obtained by multiplying the STM frame period by the number of payloads with the time width of the ATM cell is used.
A second data buffer for storing the payload data of the ATM cell;
An ATM cell write processor for writing to the second data buffer when the ATM cell arrives;
An ATM cell data write control unit having a write control table in which write control information necessary for writing the payload data of the ATM cell to the second data buffer is stored;
An STM data reading unit for reading the STM data,
The second data buffer reads data in the order of addresses of the cycle counter for each STM frame and each time slot,
When the ATM cell data write control unit stores the data of the multi-call in the second data buffer, the ATM cell data write control unit indicates the number value and multi-number indicating the head of the assigned time slot for the multi-call read from the write control table. The ATM cell disassembly apparatus is characterized in that, using the, a write control is performed for a plurality of consecutive addresses corresponding to consecutive time slots of STM frame data in a second data buffer. The ATM cell disassembling apparatus according to claim 7,
The ATM cell write control unit
Immediately after the call is set up, the STM frame number storing the payload data of the ATM cell that has arrived first is obtained by adding the number of frames corresponding to the delay fluctuation absorption time of arrival of the ATM cell to the currently read STM frame number. An ATM cell disassembling apparatus that controls to start storing ATM cell disassembled data in the second data buffer from the address of the STM frame number as a frame number . The ATM cell disassembling apparatus according to claim 7 ,
The write control table data is:
A flag bit that indicates the start of communication;
A write pointer that indicates a start point for decomposing an ATM cell and writing data to the second data buffer, and is set at the start of communication and updated each time an ATM cell is decomposed;
A flag bit that indicates the end of communication;
An ATM cell disassembling apparatus comprising: an end pointer that indicates an end point of data writing to the second data buffer .

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