JP4158564B2 - Synchronous transmission system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a synchronous transmission system for performing signal transmission between a plurality of nodes via a transmission path such as a CPU memory bus that requires high speed and low latency.
[0002]
[Prior art]
Although the operating frequency of the CPU has been improved by the advancement of semiconductor technology, the signal transmission frequency between the CPU memories is an order of magnitude lower than the operating frequency of the CPU, which is a performance bottleneck of the entire CPU memory system. In general, serial transmission is known as a method for improving the bandwidth of a transmission path. This is a method of transmitting a plurality of signals after performing speed conversion by parallel / serial conversion, and performing serial / parallel conversion on the receiving side to obtain the plurality of original signals.
[0003]
However, in the data transfer between the CPU memories, it is necessary not only to improve the bandwidth but also to reduce the data transfer delay time between them, so-called latency. The serial transmission described above has a problem in that in addition to the conventional method, parallel-serial conversion and latency for the time required for serial-parallel conversion increase.
[0004]
FIG. 3 is a diagram illustrating an example of a conventional synchronous transmission system. In this system, one CPU and one memory are connected by transmission lines 30 to 35. As shown in the figure, a clock signal S101, a chip select (CS) signal S102, a write / read (R / W) signal S103, an address signal S104, and a write data signal S105 are transmitted from the CPU side via transmission lines 30 to 34. Transmitted and received as corresponding signals S111, S112, S113, S114, S115 on the memory side. On the other hand, the read data signal S116 is transmitted from the memory side via the transmission path 35, and is received as the signal S106 on the CPU side.
[0005]
FIG. 4 is a diagram showing a timing chart in the system of FIG. As shown in the figure, the signals S102 to S105 output from the CPU are output in synchronization with the rising edge of the clock signal S101 having a duty of 50%. In the R / W signal S103, a value “1” indicates a read and a value “0” indicates a write instruction. The value “0” is valid for the CS signal S102. A symbol d in FIG. 4 represents a signal transmission time between the CPU and the memory. In the following, the signal transmission time d represents the time required for signal transmission from one node to another node, the propagation delay time of the transmission path and circuit parts existing between the nodes, and the synchronization signal generated when passing through the latch circuit Includes all waiting time. However, d in FIG. 4 corresponds to the propagation delay time of the transmission lines 30 to 35. The first period in FIG. 4 represents a read operation, and data RD is read from the memory address A1. Here, it is assumed that the read data signal S116 is determined after elapse of time r from the falling edge of the clock signal S111 received on the memory side. The symbol s in the figure indicates the setup time of the data signal on the CPU side. In the case of this system, the lower limit L0 of the latency and the upper limit F0 of the operating frequency are as follows.
L0 = max (d, 2d + r + s) × 2 = 4d + 2r + 2s, F0 = 1 / L0
[0006]
Note that Patent Document 1 discloses a clock generation circuit that generates a clock signal having a desired duty based on an input clock signal and a semiconductor memory device that controls operation timing using the clock signal generated by the clock generation circuit. This technique is for avoiding a collision between different operations in the memory, and does not solve the latency problem in the CPU memory bus or the like.
[Patent Document 1]
Japanese Patent Laid-Open No. 2000-99194
[Problems to be solved by the invention]
Accordingly, an object of the present invention is to provide a synchronous transmission system capable of reducing latency in data transfer and improving a transmission band.
[0008]
[Means for Solving the Problems]
The object is to provide a first node comprising first clock signal output means, data signal input means and / or output means, second clock signal input means, data signal input means and / or output means. A synchronous transmission system for transmitting a signal to and from a second node via a transmission path, wherein the first node and / or the second node is the first clock signal and / or Alternatively, this can be achieved by a synchronous transmission system including a duty adjustment circuit that changes the duty ratio of the second clock signal according to the adjustment signal.
[0009]
Here, the adjustment signal is transmitted from the first node to the second node, from the second node to the first node, and from the second node. It can be generated based on the processing time from the input to the output of the data signal. In addition, the synchronous transmission system can include a plurality of the first nodes and / or a plurality of the second nodes. In this case, the adjustment signal includes the maximum value of the signal transmission time from each first node to each second node and the signal transmission time from each second node to each first node. It can be generated based on the maximum value and the maximum value of the processing time from the input to the output of the data signal in each second node.
[0010]
The first node transmits a test signal to the second node, the second node returns the test signal to the first node, the test signal and the returned test signal, The signal transmission time can be calculated from the time difference. The test signal can be transmitted immediately after the system is turned on and / or during the unused time of the transmission line.
[0011]
Further, the output means includes electro-optical conversion means for converting an electric signal into an optical signal, and the input means includes photoelectric conversion means for converting the optical signal into an electric signal, the electro-optical conversion means and the photoelectric conversion The means can be optically connected by an optical transmission line. The signal transmission time can include an electro-optical conversion time in the electro-optical conversion means and a photoelectric conversion time in the photoelectric conversion means.
With this configuration, it is possible to reduce latency in data transfer and improve the transmission band.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a diagram showing an embodiment of a synchronous transmission system according to the present invention. This embodiment shows an example in which one CPU and one memory are connected by transmission lines 30 to 35, and a duty adjustment circuit 20 capable of changing the duty ratio of a clock signal by an adjustment signal S200 is provided on the CPU side. . The adjustment signal S200 may be generated based on, for example, a signal transmission time from the CPU to the memory, a signal transmission time from the memory to the CPU, and a processing time from the input to the output of the data signal in the memory. it can. A method of generating the adjustment signal will be described later.
[0013]
In FIG. 1, the CPU-side clock signal S101 is changed in duty ratio by the duty adjustment circuit 20 to become a signal S107, transmitted via the transmission path 30, and received as a signal S111 on the memory side. Further, the chip select (CS) signal S102, the write / read (R / W) signal S103, the address signal S104, and the write data signal S105 are transmitted via the transmission paths 31 to 34, and corresponding signals on the memory side. Received as S112, S113, S114, and S115. On the other hand, the read data signal S116 is transmitted from the memory side via the transmission path 35, and is received as the signal S106 on the CPU side.
[0014]
FIG. 2 is a block diagram showing an example of a CPU memory bus configured using the synchronous transmission system according to the present invention of FIG. The CPU memory bus includes one CPU 40 and a plurality of memories 41 to 43. The CPU 40 transmits the signals S107 and S102 to S105 via the transmission paths 30 to 34, and receives the signal S106 via the transmission path 35. On the other hand, the memories 41 to 43 receive the signals S111a to c, S112a to c, S113a to c, S114a to c, and S115a to c, respectively, via the transmission lines 30 to 34, and respectively transmit the signals S116a to c to the transmission lines. 35 for transmission.
[0015]
The CPU memory bus in FIG. 2 is composed of one CPU and a plurality of memories, but may be composed of a plurality of CPUs and one memory, or a plurality of CPUs and a plurality of memories. In this case, the adjustment signal for adjusting the duty ratio includes the maximum value of the signal transmission time from each CPU to each memory, the maximum value of the signal transmission time from each memory to each CPU, and the data signal in each memory. It can be generated based on the maximum value of processing time from input to output. That is, it is adjusted to the slowest one. A method of generating the adjustment signal will be described later. Further, although not shown, a duty adjustment circuit is provided on the CPU side. The duty adjustment circuit can be provided not on the CPU side but on the memory side, or on both the CPU side and the memory side.
[0016]
FIG. 5 shows a timing chart in the system of FIG. The system shown in FIG. 1 includes a clock signal duty adjustment circuit 20. The duty adjustment circuit 20 operates in accordance with the adjustment signal S200, and outputs a signal with the duty ratio adjusted to be d / (3d + r + s) as the clock signal S107. Here, the symbol d represents the signal transmission time between the nodes as in FIG. The first cycle in FIG. 5 represents a read operation, and data RD is read from the memory address A1. Here, it is assumed that the read data signal S116 is determined after elapse of time r from the falling edge of the clock signal S111 received on the memory side. That is, the time r is a processing time from the input to the output of the data signal in the memory. Symbol s indicates the setup time of the data signal on the CPU side. As a result, the timing chart is as illustrated, and the lower limit L1 of the latency and the upper limit F1 of the operating frequency are as follows.
L1 = 3d + r + s, F1 = 1 / L1
For example, in the case of d = 10 ns, r = 10 ns, and s = 5 ns, F0 = 14.3 MHz in the conventional technique described in FIG. 4, whereas F1 = 22.2 MHz in this embodiment.
[0017]
FIG. 6 is a block diagram showing an embodiment of the duty adjustment circuit used in the present invention. The duty adjustment circuit 20 of this example includes a duty setting delay circuit 60, a logical product circuit 61, and a phase adjustment delay circuit 62. FIG. 7 is a timing chart in the duty adjustment circuit of FIG. Hereinafter, the operation of the duty adjustment circuit 20 will be described using this timing chart. First, the duty setting delay circuit 60 outputs a delayed signal S601 so that the duty ratio of the clock signal S600 becomes d / (3d + r + s) in accordance with the adjustment signal S200. The logical product circuit 61 outputs a logical product of the signal S600 and the signal S601 as a signal S602. Here, since the signal S602 and the signal S600 are out of phase, the phase adjusting delay circuit 62 sets a delay so that the rising edges of both signals are synchronized, and outputs the signal S603 as a clock output.
[0018]
FIG. 8 is a block diagram illustrating an example of a method for generating an adjustment signal input to the duty adjustment circuit. As shown in the figure, on the CPU side which is the first node, a duty adjustment circuit 20 provided for the transmission line 30, a first control unit 80 which inputs an adjustment start signal and outputs an adjustment signal, A multiplexer (MUX) 81 and a demultiplexer (DMUX) 82 provided for the transmission paths 34 and 35, a phase difference detection circuit 83 for detecting a phase difference, and a ROM 84 as a storage device are provided. In addition, on the memory side, which is the second node, a first control unit 90 that inputs a signal via the transmission path 34, and a multiplexer (MUX) 91 and a demultiplexer provided for the transmission paths 35 and 34, respectively. A multiplexer (DMUX) 92 is provided.
[0019]
Hereinafter, a method of generating the duty adjustment signal S200 will be described with reference to FIG. First, among the signal transmission time d, the memory read time r, and the CPU setup time s required for calculating the duty adjustment signal S200, the memory read time r and the CPU setup time s are values inherent to the system. , Calculated in advance and stored in the ROM 84 by the signal S807. Since the signal transmission time d varies depending on the length of the transmission line and the like, it is calculated as follows. The first control unit 80 is activated by the adjustment activation signal S800, instructs the multiplexer 81 and the demultiplexer 82 to select by the signal S804, and selects the signal S801 and the signal S802, respectively. Then, the signal S801 is transmitted through the transmission line 34, and the adjustment start is instructed to the second control unit 90 provided on the memory side. Upon receiving the adjustment start, the second control unit 90 instructs the multiplexer 91 and the demultiplexer 92 to select by the signal S810, and both select the signal S811. In the figure, signals S805 and S815 are write data signals, and signals S806 and S816 are read data signals.
[0020]
Next, the first control unit 80 outputs a test signal as the signal S801. The test signal is transmitted to the memory side via the multiplexer 81 and the transmission path 34, and returns to the CPU side via the demultiplexer 92, the multiplexer 91, and the transmission path 35. The phase difference detection circuit 83 detects the phase difference (time difference) between the signal S801 that is the original test signal and the returned signal S802, and outputs the detection result to the first controller 80 as a signal S803. The signal S803 corresponds to the transmission time required for the reciprocation between the CPU side and the memory side, and half of this value is the signal transmission time d. The first control unit 80 generates the adjustment signal S200 based on the calculated signal transmission time d, the pre-calculated memory read time r, and the CPU setup time s, and sends the adjustment signal S200 to the duty adjustment circuit 20. Output.
[0021]
In this example, the CPU and the memory are provided on a one-to-one basis. However, in the case of a system having a plurality of CPUs and a plurality of memories, this adjustment signal is a signal transmission time from each CPU to each memory. It can be generated based on the maximum value, the maximum value of the signal transmission time from each memory to each CPU, and the maximum value of the processing time from the input to the output of the data signal in each memory. Further, the test signal output from the first control unit 80 can be transmitted immediately after the system is turned on and / or during the unused time of the transmission path. Especially when the environment surrounding the system, such as temperature, humidity, or power supply voltage fluctuation, is detected by a sensor, etc., and a test signal is output as necessary to change the duty ratio of the clock signal. Is preferred.
[0022]
Here, the CPU memory bus can be composed of an optical transmission path. In this case, each output means provided in the CPU and the memory includes an electro-optical conversion means having a light emitting element such as a semiconductor laser for converting an electric signal into an optical signal. On the other hand, the input means includes photoelectric conversion means having a light receiving element such as a light emitting diode for converting an optical signal into an electric signal. The electro-optical conversion means and the photoelectric conversion means are optically connected by an optical transmission path. The signal transmission time in this case includes the electro-optical conversion time in the electro-optical conversion means and the photoelectric conversion time in the photoelectric conversion means.
[0023]
The following is one implementation example in the present embodiment and does not limit the present invention.
(1) Each signal may be positive logic or negative logic. (2) In FIGS. 1, 2, 3, and 8, the read data signal, the write data signal, the address signal, the R / W signal, the CS signal, and the clock signal are all transmitted through different transmission paths. A method may be used in which all signals or some of these signals are transmitted through the same transmission path. (3) In FIGS. 4 and 5, the memory read-out starts from the falling edge of the memory reception clock signal S111. For example, after the CS signal, the R / W signal and the address signal are determined, Alternatively, the signal S116 may be latched and output at the falling edge of the signal S111 after the reading is started and the read data is internally determined. In this case, when the memory read time is r ′ and the latch output time is r ″, the duty ratio is adjusted to be (d + r ′) / (3d + r ′ + r ″ + s). At this time, the latency in the conventional method is L0 ′ = max (d + r ′, 2d + r ″ + s) × 2, and the latency in the present invention is L1 ′ = 3d + r ′ + r ″ + s, which is improved.
[0024]
As described above, in the present invention, by determining the duty ratio of the synchronous transmission clock from the time required for data transmission, data reception, and memory access in the CPU, the waiting time between the CPU and the memory is reduced, and latency in the CPU memory access is reduced. Improvement of the transmission band can be realized at the same time. Therefore, the performance of the entire system can be improved.
[0025]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, the synchronous transmission system which can reduce the latency in data transfer and can improve a transmission band can be provided.
[Brief description of the drawings]
FIG. 1 is a diagram showing an embodiment of a synchronous transmission system according to the present invention.
FIG. 2 is a block diagram showing an example of a CPU memory bus configured using the synchronous transmission system according to the present invention.
FIG. 3 is a diagram illustrating an example of a conventional synchronous transmission system.
FIG. 4 is a diagram showing a timing chart in the system of FIG. 3;
FIG. 5 is a diagram showing a timing chart in the system of FIG. 1;
FIG. 6 is a block diagram showing an embodiment of a duty adjustment circuit used in the present invention.
7 is a timing chart in the duty adjustment circuit of FIG. 6;
FIG. 8 is a block diagram illustrating an example of a method for generating an adjustment signal input to a duty adjustment circuit.
[Explanation of symbols]
20 Duty adjustment circuit 30 to 35 Transmission path S101, S107, S111 Clock signal S102, S112 CS signal S103, S113 R / W signal S104, S114 Address signal S105, S115 Write data signal S106, S116 Read data S200 Adjustment signal

Claims (8)

A first node comprising first clock signal output means and data signal input means and / or output means; a second node comprising second clock signal input means and data signal input means and / or output means; A synchronous transmission system for transmitting signals to and from a node via a transmission line, wherein the first node and / or the second node are the first clock signal and / or the second node. A synchronous transmission system comprising a duty adjustment circuit for changing a duty ratio of the clock signal according to an adjustment signal. The adjustment signal includes a signal transmission time from the first node to the second node, a signal transmission time from the second node to the first node, and a data signal in the second node. The synchronous transmission system according to claim 1, wherein the synchronous transmission system is generated based on a processing time from input to output. The synchronous transmission system according to claim 1, further comprising a plurality of the first nodes and / or a plurality of the second nodes. The adjustment signal includes a maximum value of signal transmission time from each first node to each second node, and a maximum value of signal transmission time from each second node to each first node; 4. The synchronous transmission system according to claim 3, wherein the synchronous transmission system is generated based on a maximum value of processing time from input to output of a data signal in each of the second nodes. The first node transmits a test signal to the second node, the second node returns the test signal to the first node, and a time difference between the test signal and the returned test signal The synchronous transmission system according to claim 2, wherein the signal transmission time is calculated from the above. 6. The synchronous transmission system according to claim 5, wherein the test signal is transmitted immediately after power-on of the system and / or in an unused time of the transmission line. The output means includes electro-optical conversion means for converting an electrical signal into an optical signal, and the input means includes photoelectric conversion means for converting an optical signal into an electrical signal, the electro-optical conversion means, the photoelectric conversion means, The synchronous transmission system according to claim 1, wherein the two are optically connected by an optical transmission line. The synchronous transmission system according to claim 7, wherein the signal transmission time includes an electro-optical conversion time in the electro-optical conversion unit and a photoelectric conversion time in the photoelectric conversion unit.

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