JP4157209B2 - Image processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to an image processing apparatus that stores image data input from an image data input unit in a storage unit.
[0002]
[Prior art]
  Conventionally, image data input from image input means such as an image scanner is registered in a storage means such as a magnetic disk, an optical disk, or a magneto-optical disk (registration processing), and the image data is retrieved from the storage means as necessary. There has been proposed an image processing apparatus that outputs (extracts) from an image output means such as a printer.
[0003]
  In such an image processing apparatus, in addition to the above “registration process” and “removal process”, it is usually possible to execute a “copy process” for simply copying a document set in the image input means. These processes can be operated using an operation panel having a plurality of keys such as an LCD panel with a touch panel and a numeric keypad.
[0004]
  Hereinafter, an example of the “registration process”, “extraction process”, and “copy process” in the conventional image processing apparatus will be described with reference to FIGS. 8, 9, and 10. FIG.
[0005]
  First, when the user instructs “registration processing” using the operation panel 572 shown in FIG. 8, this instruction information is held in the panel control means 571. Subsequently, when the user presses a start button (not shown) on the operation panel 572, the panel control unit 571 instructs the image input unit 500 to read a document and registers image data in the document management unit 590. Give instructions.
[0006]
  The image input unit 500 that has received a document reading instruction converts the document into digital data and inputs, for example, 8-bit multi-value image data (256 gradations) to the multi-value image processing unit 510. The multi-value image processing means 510 performs image processing (described later) such as zoom processing and edge enhancement processing on the multi-value image data.
[0007]
  By the way, when registering image data in the storage means 580, binary image data (two gradations) with a small data size or this binary image data is compressed, converted into encoded image data, and registered. Is customary. That is, the multi-value image data is first subjected to binarization processing by the binarization means 520 and converted to binary image data. In this binarization process, a simple binarization process for determining whether it is “1” or “0” depending on whether the value is larger or smaller than a predetermined threshold, an error diffusion method, a dither method, etc. It is effective to use such pseudo halftone binarization processing by switching at appropriate times. These binarization processing and switching method are described in detail in JP-A-8-223409.
[0008]
  The image data binarized as described above is converted into encoded image data by the encoding means 150 such as an encoding circuit. As the encoding method at this time, MH, MR, MMR, JBIG or the like used in the facsimile may be selected as appropriate.
[0009]
  As described above, the multi-valued image data generated by the image input unit 500 is binarized and encoded, so that the original data size of about 1/160 (2 bits of 8-bit multi-valued image data is converted to 2). The value is simply 1/8 by encoding, and further, by encoding, the average is about 1/20 for a normal manuscript. After that, the document management unit 590 described below stores the storage unit 580. Will be registered.
[0010]
  That is, the document management unit 590 that has received an image data registration instruction from the panel control unit 571 generates a document ID consisting of, for example, an 8-digit number corresponding to the encoded image data. The encoded file data is registered as an image data file 181 in the storage unit 580 with a corresponding file name. Here, the document management unit 590 stores the attribute information including “document ID”, “registration date”, “pointer information”, “image size”, and the like of the image data file 181 together with the registration of the image data file 181. Is stored in the attribute table 182. The “pointer information” is a registered address of the image data file 181 in the storage unit 580, and the “image size” is a standard paper size corresponding to the image data file 181.
[0011]
  In parallel with the above processing, the multi-value image data input from the image input unit 500 is printed by the image output unit 540 in the same data format.
[0012]
  As described above, the document set in the image input unit 500 is registered in the storage unit 580 as image data. When the registered image data is to be extracted, the extraction process described below is performed. Execute.
[0013]
  Next, the “extraction process” for extracting the image data registered in the storage means 580 by the “registration process” will be described with reference to FIG.
[0014]
  First, when a document ID corresponding to image data to be extracted is input using the operation panel 572 and an extraction process is instructed, the document ID is held in the panel control unit 571. Subsequently, when the start button on the operation panel 572 is pressed, the panel control unit 571 notifies the document management unit 590 of this document ID. Upon receiving the notification, the document management unit 590 refers to the attribute table 582 based on the document ID, and obtains the registration location of the image data file 581 corresponding to the document ID based on the pointer information. As described above, when the registration location is known, the document management unit 590 reads the image data file 581 from the storage unit 580 and inputs it to the decoding unit 560.
[0015]
  The decoding unit 560 decodes the encoded image data input as described above into binary image data, and inputs the decoded image data to the multilevel reproduction unit 530. The multi-value reproduction means 530 converts the decoded binary image data into multi-value image data.TactTo do. Thereafter, the image output means 540 such as a printer forms an image on a recording sheet based on the multivalued image data converted as described above, and outputs the image.
[0016]
  As described above, the image data registered by binarization and encoding in the storage unit 580 can be reproduced and printed as multi-value image data.
[0017]
  When “copy processing” is input from the operation panel 572, the multi-value image data obtained from the image input unit 500 is output as an image via the multi-value image processing unit 510 as shown in FIG. It is made to input into the means 540.
[0018]
  As described above, by including the binarizing means 520 and the multi-value reproducing means 530, binary image data having a small data capacity is registered when registered in the storage means 580, and image quality is reduced when printing. High multi-value image data can be used. Further, the user can perform “registration processing”, “removal processing”, and “copy processing” by a simple operation using the operation panel 572.
[0019]
  Hereinafter, the image processing and multilevel reproduction processing will be described.
[0020]
  FIG. 11 shows an example of the configuration of the multi-value image processing circuit (multi-value image processing means) 510. Here, the multi-value image processing circuit 510 will be described as having an edge enhancement processing circuit 511 and a zoom processing circuit 512. To do.
[0021]
  The edge emphasis processing circuit 511 is a circuit for emphasizing an edge portion, that is, a contour portion, and can be configured by a window generation circuit 511a and a matrix circuit 511b as shown in FIG. 12, for example.
[0022]
  The window generation circuit 511a is a line delay 511a that delays input multi-value image data in units of lines.₁And a flip-flop (FF) 511a that delays the pixel unit.₂The 3 × 3 pixel window data (W0 to W8) centering on the target pixel (W4) to be processed as shown in FIG. 13 is output to the matrix circuit 511b.
[0023]
  The matrix circuit 511b multiplies the window data (W0 to W8) by the coefficient shown in FIG. 13, that is, “−1/8” or “2”, and adds the result to the pixel of interest (W4). The differential value in the region is added to the target pixel (W4).
[0024]
  As a result, the density change in the region where the density changes rapidly, that is, the contour area becomes steeper, and the edge portion is emphasized.
[0025]
  The zoom process is a process for enlarging and reducing an image, and this zoom process can be performed independently for each of the main scanning direction and the sub-scanning direction perpendicular to each other. Hereinafter, the zoom process in the sub-scanning direction will be described. The main scanning direction is a direction in which the image sensor of the image scanner (image input means) 500 is electrically operated, and the sub-scanning direction is a direction in which the image sensor is mechanically operated.
[0026]
  As shown in FIG. 14, the zoom processing circuit 512 has a line delay 512a for delaying input multi-value image data in units of lines, and a flip-flop (hereinafter referred to as “FF”) 512b for delaying in units of pixels.₁512b₂Multi-valued image data adder 512c and divider 512d, and FF 512b.₁, Divider 512d, FF512b₂A selector 512e for selecting one of the outputs, and a skip table that is a RAM having a bit number of 9882 pixels corresponding to, for example, the long side (420 mm) of A3 size which is the maximum line length that can be processed by the image processing apparatus. Based on 512g and the data set in this skip table 512g, it is determined whether or not the input multi-valued image data is valid, and is constituted by a thinning circuit 512f that outputs only valid multi-valued image data. Is done.
[0027]
  The operation of the zoom processing circuit 512 having the above configuration will be described below.
[0028]
  First, for example, when an instruction for reduction processing is input together with the reduction ratio from the operation panel 572, the CPU always indicates that the selector 512e is FF512b.₁And the setting data based on the reduction ratio is written to the skip table 512g as follows. That is, for example, if a bit of “1” indicates a valid line and a bit of “0” indicates an invalid line, the CPU sets “1” and “0” when performing 50% reduction in the skip table 512g. Are written alternately, and when performing reduction of 66.66%, the bit string “110110...” Of “510” pattern is written.
[0029]
  With the above settings, the input multi-valued image data is once converted to FF512b.₁The delayed multi-valued image data is selected by the selector 512e and input to the thinning circuit 512f. Here, if the thinning circuit 512f refers to the skip table 512g for each line and determines that the line is a valid line, the thinning circuit 512f outputs the input data as it is and the line is an invalid line. If it is determined, input data is not output. That is, when 50% reduction is performed, since “1010...” Is set in the skip table 512g, the thinning circuit 512f outputs multi-value image data input every other line.
[0030]
  As described above, the reduction is performed by 50%. Further, if the setting data of the skip table 512g is changed, zoom with an arbitrary reduction ratio can be performed.
[0031]
  Next, the operation for enlarging will be described.
[0032]
  First, in the CPU, the selector 512e outputs the output of the divider 512d and the output of the line delay 512a to the FF 512b.₂The multi-value image data delayed by one line and one clock is set so as to be alternately selected for each line. Also, if one line of multi-value image data to be input is input, no time is input for one line.
[0033]
  FIG. 15 is a time chart in the case of enlarging processing (“enable signal” in FIG. 15 indicates that image data is valid), and will be described below according to this time chart.
[0034]
  First, the selector 512e selects the output of the divider 512d when multi-valued image data is input. The output of the divider 512d is a half of the value obtained by adding the multi-value image data of the currently input line and the multi-value image data delayed by one line by the line delay 512a, that is, an average value.
[0035]
  On the other hand, when multi-value image data is not input, the selector 512e receives multi-value image data delayed by one line by the line delay 512a, that is, the multi-value image input when selecting the output data of the divider 512d. Select data.
[0036]
  As a result, the output of the selector 512e is multi-valued image data obtained by interpolating the multi-valued image data sequentially input twice, which corresponds to 200% enlargement. Here, if a predetermined bit pattern is set in the skip table 512g, reduction from 200% can be performed at an arbitrary magnification. For example, if the pattern “110110...” Is set, the enlargement process of 133.33 (200 × 66.66)% can be performed.
[0037]
  As described above, zoom processing (reduction processing and enlargement processing) at an arbitrary magnification in the sub-scanning direction can be performed, and zoom processing in the main scanning direction can be similarly performed.
[0038]
  In the above description, the configuration in which image data is enlarged by interpolating is exemplified. However, if the mechanical speed of the image sensor of the image scanner (image input means) 500 is decreased, the pixel density at the time of reading increases. It can be printed substantially enlarged. Also in this case, the enlargement process to an arbitrary magnification can be performed by performing the thinning process.
[0039]
  An example of the multilevel reproduction process will be described below.
[0040]
  For example, as shown in FIG. 16, the multi-value reproduction means 130 includes a window generation circuit 531 that converts sequentially input binary image data into 5 × 5 pixel window data centered on the pixel of interest, A smoothing circuit 532 that adds the binary image data therein and normalizes it to 8-bit multi-value image data is provided.
[0041]
  As shown in FIG. 17, the window generation circuit 531 includes a line delay circuit 531a that delays input binary image data in units of lines and a flip-flop 531b that delays in units of pixels (hereinafter referred to as “FF531b”). It is described.) By combining the line delay circuit 531a and the FF 531b, window data (W0 to W24) centered on the target pixel (W12) to be processed as shown in FIG. 19 can be generated. Note that “× 1”, “× 2”, and “× 4” shown in FIG. 19 indicate the weights of the respective pixels in the smoothing processing described below.
[0042]
  FIG. 18 is a schematic block diagram of the smoothing circuit 532. The adder 532a adds all the 16 binary image data (W0 to W5, W9, W10, W14, W15, and W19 to W24) belonging to the outer periphery of the window. Similarly, the adder 532b adds all eight binary image data (W6 to W8, W11, W13, and W16 to W18) belonging to the inner periphery excluding the target pixel of the window. The multiplier 532c doubles the result of addition by the adder 532b, and the multiplier 532d multiplies the binary image data of the pixel of interest (W12) by four. Here, multiplication of powers of 2 such as 2 times and 4 times is very simple in terms of circuit because it only shifts the binary bits to the left.
[0043]
  The adder 532e adds all the results processed by the adder 532a, the results processed by the multiplier 532c, and the results processed by the multiplier 532d, and outputs the result as smoothed data.
[0044]
  Here, the values that can be taken by the smoothed data range from 0 (when W0 to W24 are all “0”) to 36 (when W0 to W24 are all “1”). In order to achieve this, it is necessary to process the value from 0 to 255. Therefore, the smoothed data is normalized in the normalizing circuit 532f so that 36, which is the maximum value, becomes 255.
[0045]
  In this normalization process, if the smoothed data is multiplied by 7.125, the configuration of the normalization circuit 532f can be simplified. That is, “7.125 = 4 + 2 + 1 + 0.125 = 2.²+2¹+2⁰+2^-3Therefore, multiplying the smoothed data by 7.125 means that the smoothed data is 2²Doubled value, 2¹Doubled value, and 2^-3Since the multiplied value is added to the smoothed data, normalization can be performed by addition of a power of 2 that facilitates the circuit configuration. When the result of 7.125 magnification becomes 256 or more, clipping is performed at 255.
[0046]
[Problems to be solved by the invention]
  However, in the above-described conventional image processing apparatus, the image printed during the “registration process” is the image input means.FromObtained multi-value image dataThings inWhereasSince the multi-value image data is binarized and registered (stored) in “registration processing”,By "removal processing"(During “Removal process”)The printed image isThat at the "registration process"A part of image information was lost by binarization processing.Played a thingMulti-level playback image dataThings inEnd up. That is, "registration process"In memory meansRegistrationButImage dataAt the same time as the registrationprintingThePrint image whenTheAfter registrationTheStorage meansFrom"Removal process"AtreadingTheprintingTheHowever, there was a problem that the image quality of printing was different.
[0047]
  Also, when performing electronic sorting (when a plurality of pages of a document is copied in plural copies, the first copy is output in the order of 1 page, 2 pages,..., 2 pages, 1 page, 2 pages,...) The multi-value image data output from the multi-value image processing means is printed out as it is by the image output means, and binarized and stored in the storage means, and the second and subsequent copies are read out from the storage means and multi-value reproduction means In general, it is converted into multi-value image data and printed out. However, there is a drawback that the image quality of the first copy is different from the image quality of the second and subsequent print images.
[0048]
  Further, the conventional configuration has a problem that image processing such as zoom processing cannot be executed during the extraction processing. For example, in the above configuration, it is impossible to print on a recording paper having a size different from the registered size while being enlarged or reduced.
[0049]
  The above problem can be solved by adding an expansion circuit for zooming, but this configuration increases the cost.
[0050]
  The present invention has been proposed based on the above-described conventional circumstances, and provides an image processing apparatus in which the image quality of an image taken out from a storage unit and printed is the same as the image quality of an image printed at the time of image registration. It is for the purpose. It is another object of the present invention to provide an image processing apparatus capable of executing various types of image processing when taking out registered image data.
[0051]
[Means for Solving the Problems]
  The present invention employs the following means in order to achieve the above object. That is, the image processing apparatus of the present invention binarizes the multi-valued image data input from the image input unit 100 by the binarization unit 130 and registers the binarized image data in the storage unit 210. Binary image data is subjected to multi-value reproduction by the multi-value reproduction means 150 and output to the image output means 170. The binary image data from the binarization means 130 or the binary image data from the storage means 210 is output. Select one of the image data and send it to the multilevel reproduction means 150When binary image data from the binarization unit 130 is selected, the binary image data from the storage unit 210 is input to the binarization unit 130 while multilevel image data is input from the image input unit 100. When selected, the binary image data is retrieved from the storage means 210,Second selection means 140 for outputting, and third value data for selecting either multi-value image data from the image input means 100 or multi-value image data from the multi-value reproduction means 150 for output to the image output means 170 The selection means 160 is provided.When the multi-value image data input from the image input means 100 is output to the image output means 170, and simultaneously registered in the storage means 210, the multi-value image data is converted into the binarization means 130, The second selection unit 140, the multi-value reproduction unit 150, and the third selection unit 160 are output to the image output unit 170 in that order.
[0052]
  When registering the image data in the storage unit 210, the multivalued image data input from the image input unit 100 is converted into binary image data by the binarizing unit 130, and this binary image data is converted by the document management unit 220. It is registered in the storage unit 210 and is selected by the second selection unit 140. The binary image data is converted into a multi-value by the multi-value reproduction unit 150 and output to the image output unit 170 by the third selection unit 160. With the above configuration, the image data that is printed simultaneously with the image registration processing is once binarized and then reproduced as multi-valued image data. Accordingly, the image quality is the same as when the registered image data is printed.
[0053]
  OrIn order to achieve the above object, the present inventionIn, Image input means 100Frominputis doingMulti-valueofThe image data is subjected to predetermined image processing by the multi-value image processing means 120 and then binarized by the binarization means 130 and registered in the storage means 210.Shi,Also,Binary values registered in the storage means 210ofMulti-value reproduction of image data by multi-value reproduction means 150TheImage output means 170WhatIn the image processing device to output,Shown belowFirst selection means 110 and,MoreoverSecond selection means 140WhenThe structure with is adopted.
[0054]
  The first selection means 110 selects either multi-value image data from the image input means 100 or multi-value image data from the multi-value reproduction means 150 and outputs it to the multi-value image processing means 120. Further, the second selection unit 140 selects either binary image data from the binarization unit 130 or binary image data from the storage unit 210 and sends it to the multilevel reproduction unit 150.When binary image data binarized by the binarizing means 130 is selected, multi-valued image data is input from the image input means 100 to the binarizing means 130 and binary data from the storage means 210 is input. When the image data is selected, the binary image data is retrieved from the storage means 210,Output. AndWhen the multi-value image data input from the image input means 100 is output to the image output means 170, and simultaneously registered in the storage means 210, the multi-value image data is stored in the first selection means 110, multi-value data. The value image processing means 120, the binarization means 130, the second selection means 140, and the multi-value reproduction means 150 are output to the image output means 170 in that order.
[0055]
  A CPU (not shown) controls the operations of the first selection unit 110 and the second selection unit 140 so that the image data extracted from the storage unit 210 is input to the multi-value image processing unit 120. In this way, the image data registered in the storage unit 210 can be zoomed out and extracted without adding an expansion circuit for performing image processing such as zooming or edge enhancement.
[0056]
  AlsoIsThe synchronization signal generating means 240 and the fourth selecting means 230 are added to the above configuration.didIt is good also as a structure.here,This synchronization signal generating means 240 is connected to the image output means 170.ofcontrolImage data is processed inRuNecessary forPeriod longer than the first synchronization signalButA short second synchronization signal is generated.
[0057]
  Further, the fourth selection unit 230 is configured such that the first selection unit 110 is the image input unit 100.Multi-valued image data fromWhen is selectedIsThe first synchronization signal is received by the first selection unit 110 from the multilevel reproduction unit 150.Multi-valued image data fromWhen is selectedIsSynchronization signal generating means 240InThe second synchronization signal obtained fromConcernedThe synchronization signal of the entire device andSelectTo do.
[0058]
  With the above configuration, high-speed processing is possible when the multi-value image processing unit 120 performs image processing on the registered image data.
[0059]
  The image input unit 100 is at least one of an image reading unit, a facsimile receiving unit, and a print controller, and the image output unit 170 is at least one of a printing unit, a facsimile transmission unit, and a filing unit. It is.
[0060]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
  As shown in FIGS. 1 to 4, the present embodiment includes a first selection unit 110, a second selection unit 140, and a third selection unit 160 in addition to the conventional configuration described above. . These three control means are controlled by a CPU (not shown), and the CPU performs the above control based on an instruction input from an operation panel 202 having a plurality of keys such as a touch panel and a numeric keypad.
[0061]
  The “registration process”, “retrieve process”, and “copy process” in the first embodiment of the present invention will be described below.
[0062]
  FIG. 1 shows a process flow in the “registration process”. When the operation panel 202 instructs to register at the same time as copying, the first selection unit 110 selects the image input unit 100 and the second selection unit 1.40 is binarization means 130 is selected, and the third selection unit 160 selects the multi-level reproduction unit 150. Here, since the first selection means 110 needs to be switched during feedback processing to be described later and normally selects an input from the image input means 100, the second selection means 1 is mainly used here.4The state of 0 and the third selection means 160 becomes a problem.
[0063]
  Obtained by the image input means 100ThisThe multi-value image data is passed to the binarization means 130 through the first selection means 110 and the multi-value image processing means 120 as in the conventional case. The binary image data generated by the binarization unit 130 is registered in the storage unit 210 by the document management unit 220 and input to the second selection unit 140. The second selection means 140 inputs this binary image data to the subsequent multi-value reproduction means 150, where it is converted into multi-value reproduction image data.
[0064]
  Here, the third selection means 160 selects not the image data from the multi-value image processing means 120 but the image data from the multi-value reproduction means 150, and selects the third selection means 160. The multi-valued reproduced image data thus printed is printed by the image output means 170 and the “registration process” is completed. In other words, printing is executed simultaneously with the image registration process.
[0065]
  Next, the extraction process will be described.
[0066]
  The “removal process” is divided into two processes: “removal process without image processing” and “removal process with image processing”. This “extraction process without image processing” refers to image data stored in the storage means 210.,This is a process of taking out the attributes (dice, direction, etc.) at the time of registration as they are. “Retrieving process with image processing” refers to image processing such as zoom processing for image data registered in the storage unit 210. It is a process to apply and take out.
[0067]
  That is, when the user sets the zoom rate via the operation panel 202 when performing the “extraction processing”, the operation automatically operates as “extraction processing with image processing”.
[0068]
  FIG. 2 shows a processing flow of extraction processing without image processing.
[0069]
  When an instruction “input processing” is input from the operation panel 202 (here, no image processing is input as described below), the second selection unit 140 selects binary image data from the decoding unit 190. The third selection unit 160 selects the multi-level reproduction unit 150 side. Here, the first selection means 110 is not involved in the processing.
[0070]
  Thus, when the encoded image data is read from the storage unit 210 by the document management unit 220, the read encoded image data is decoded into binary image data by the decoding unit 190, and further, multi-level reproduction is performed. After being reproduced as multi-valued image data by the means 150, it is printed by the image output means 170, and the extraction process is completed. Here, the first selection means 110 is not involved.
[0071]
  FIG. 3 shows a processing flow of the extraction processing accompanied with image processing.
[0072]
  When an instruction is input from the operation panel 202 to “take out processing” and an instruction is given to perform image processing such as zoom processing and edge enhancement processing, the first selection unit 110 causes the multi-value reproduction unit 150 to perform the processing. The reproduced multi-value image data is selected, and this multi-value image data is output to the multi-value image processing means 120. On the other hand, the second selection unit 140 selects the binary image data from the decoding unit 190 and outputs the binary image data to the multilevel reproduction unit 150. In addition, image data is not input to the third selection unit 160 or the image output unit 170. Alternatively, even if image data is input to the image output unit 170, printing is not performed.
[0073]
  In this state, when the encoded image data is read from the storage unit 210 by the document management unit 220, the read encoded image data is decoded into binary image data by the decoding unit 190. Next, the multi-level reproduction unit 150 reproduces the decoded binary image data into multi-level image data, and then inputs the multi-level image data to the multi-level image processing unit 120 via the first selection unit 110. Here, necessary image processing, that is, image processing such as edge enhancement processing and zoom processing is performed.
[0074]
  Here, when the image data path to the image output means 170 is used for performing multi-value reproduction processing, the multi-value image data subjected to the image processing is binarized by the binarization means 130. After being encoded by the encoding means 180, it is temporarily stored in the storage means 210, a buffer (not shown) or the like (hereinafter, this process is referred to as “feedback process”).
[0075]
  The encoded image data stored temporarily is extracted from the temporarily stored area as soon as the image data path to the image output means 170 becomes unused, and the above-mentioned “extraction processing without image processing” is performed. The image output means 170 prints in the same procedure as in the case of "." After that, the document management unit 220 deletes the temporarily stored image data, and the extraction process ends.
[0076]
  As described above, according to the present embodiment, various types of image processing can be executed when taking out registered image data.
[0077]
  Note that this image processing is not limited to edge enhancement processing and zoom processing, but masking processing, trimming processing, and the like (the description is omitted here because it is a widely known technique). A circuit to be added may be added, and a circuit unnecessary for the feedback processing may be set so as not to be processed.
[0078]
  In the above description, the multivalued image data subjected to the image processing is deleted. However, the present invention is not limited to this. That is, the document management unit 220 may register the image data that has been subjected to image processing as new image data.
[0079]
  Further, the multi-value image data subjected to image processing by the multi-value image processing means 120 is directly input to the image output means 170 when the path to the image output means 170 is unused. Not too long.
[0080]
  FIG. 4 shows a processing flow in copy processing.
[0081]
  When a copy processing instruction is issued from the operation panel 202, the first selection means 110 is the image input means 100, and the third selection means 160 is the multi-value image processing means 1.2The output of 0 is selected. Here, the second selection means 140 is not involved.NoIt will be.
[0082]
  That is, when multi-value image data is generated from the image input means 100, the generated multi-value image data is subjected to image processing such as zooming and edge enhancement by the multi-value image processing means 120, and the third selection is performed. Printing is performed by the image output unit 170 via the unit 160.
[0083]
  As described above, in the present embodiment, by providing the first selection unit 110, the second selection unit 140, and the third selection unit 160, the processing to be performed on the image data is selected as necessary. (FIG. 3). In this way, the image quality of the image obtained by printing at the same time as registration (FIG. 1) and the subsequent storage from the storage means are obtained.brothThe image quality (FIG. 2) of the image printed by the processing can be the same quality (both are multi-value images). Further, as in the prior art, it is possible to perform copy processing without using binarization means (FIG. 4).
[0084]
  The first, second, and third selection means are not particularly limited as long as the above-described process selection is possible.
[0085]
  In the above, when the extraction function with image processing is not provided, the multi-value image processing means 120 always receives the image data from the image input means 100, so the first selection means 110 is essentially unnecessary. It becomes. Further, when the feedback process is performed, since the data does not pass through the third selection means 160, the third selection means 160 is essentially unnecessary. However, it is necessary for the extraction after the feedback, but in this case, the processing is the same as the extraction without image processing.
[0086]
  [Second Embodiment]
  According to the first embodiment, when an image is formed by the image output unit 170, the line synchronization signal of the image output unit 170 (the cycle of the line synchronization signal is determined from the cycle of the operation clock and the mechanical configuration. In general, the image data corresponding to a width equal to or larger than the maximum size of the printable recording paper is fixed to a period necessary for processing with the operation clock. It is necessary to input to the image output means 170. For example, in a printer capable of printing up to A3 size recording paper, a line synchronization signal is output at a period necessary for processing image data corresponding to the A3 size width, that is, the short side of 297 mm, with the operation clock. All circuits handling image data of the image processing apparatus start processing for each line in synchronization with the line synchronization signal.
[0087]
  However, when the first selection unit 110 selects the multi-value reproduction unit 150 as an input, that is, during feedback processing, the image data is output from the storage unit 210 and subjected to a predetermined process and stored in the storage unit 210. It returns only, and the output process to the image output means 170 is not performed. Therefore, at this time, it is not necessary to synchronize the entire processing with the operation of the image output means 170, and it is preferable to enable processing at a higher speed.
[0088]
  Therefore, as shown in FIG. 5, the image processing apparatus according to the present embodiment has the same configuration as that of the first embodiment, for example, a synchronization signal generation unit 240 such as a synchronization signal generation circuit, and a fourth such as a selector. Thus, the feedback processing can be performed at a high speed.
[0089]
  Hereinafter, the synchronization signal generation means 240 will be described first.
[0090]
  The synchronization signal generation means 240 is a means for generating a second synchronization signal having a shorter cycle than the line synchronization signal (hereinafter referred to as “first synchronization signal”) for controlling the image output means 170. In the embodiment, the second synchronization signal is generated by the CPU controlling the synchronization signal generation circuit 240 as shown in FIG.
[0091]
  Hereinafter, the configuration of the synchronization signal generation circuit 240 will be described.
[0092]
  The counter 243 counts the operation clock and sequentially counts up, the pulse width setting register 241 holds a value set by the CPU (the pulse width of the second synchronization signal to be generated), and the cycle setting register 242 The value set by the CPU (the cycle of the second synchronization signal to be generated) is held. When the count value output from the counter 243 becomes “0”, the comparator 244 determines that the comparator 246 indicates that the count value is equal to the value of the pulse width setting register 241. When the count value becomes equal to the value of the period setting register 242, a high level signal is output. A set-reset flip-flop 247 (hereinafter referred to as “SRFF 247”) outputs a high-level signal when the set signal becomes high level, and a low-level signal when the reset signal becomes high level. Is output.
[0093]
  Hereinafter, an operation until the synchronization signal generation circuit 240 configured as described above generates the second synchronization signal will be described with reference to the time chart of FIG.
[0094]
  First, the CPU sets “3”, for example, in the pulse width setting register 241 and “100”, for example, in the period setting register 242. Here, the set value “100” is a value that determines the period of the second synchronization signal, which is slightly larger than the period necessary for processing the image data to be feedback-processed with the operation clock, and is the first value. The value is smaller than the period of the synchronization signal. Note that the value set in the pulse width setting register 241 may be fixed to the pulse width of a commonly used synchronization signal (not limited to “3”).
[0095]
  The counter 243 counts up the operation clock and sequentially counts up. When the counter value reaches “100” set in the cycle setting register 242, the comparator 246 becomes high level. Here, since the output of the comparator 246 is input to the clear terminal CLR of the counter 243, the counter 243 is cleared when the counter value reaches “100” and starts counting up again from the next operation clock. It will be.
[0096]
  On the other hand, when the counter value of the counter 243 becomes “0”, the output of the comparator 244 becomes high level, and since the output of the comparator 244 is input to the set terminal of the SRFF 247, At the next operation clock when the counter value becomes “0”, the output of the SRFF 247 becomes high level.
[0097]
  Here, when the counter value of the counter 243 becomes “3” set in the pulse width setting register 241, the output of the comparator 245 becomes high level, and the output of the comparator 245 becomes the reset terminal of the SRFF 247. As a result, the output of the SRFF 247 becomes low level.
[0098]
  By repeating the above operation, the SRFF 247 outputs a signal having a cycle of “100” and a pulse width of “3”, that is, a second synchronization signal based on the setting from the CPU.
[0099]
  The operation of the fourth selection unit 230 is controlled by the CPU, and the CPU performs different operations depending on whether or not it is during feedback processing, as described below.
[0100]
  When performing the feedback process, the CPU performs the operation described in the synchronization signal generation process and controls the fourth selection unit 230 to select the second synchronization signal. The fourth selection unit 230 receives the second synchronization signal generated by the synchronization signal generation process, and outputs the second synchronization signal as a synchronization signal for the entire apparatus.
[0101]
  During processing other than the feedback processing, the CPU controls the fourth selection unit 230 to select the first synchronization signal. The fourth selection unit 230 receives the first synchronization signal as an input and outputs the first synchronization signal as a synchronization signal for the entire apparatus.
[0102]
  As a result, during the feedback process, the entire process is synchronized with a synchronization signal having a shorter cycle than the synchronization signal for controlling the image output means 170, and the time during which image data is not processed (standby time) is reduced. Can do.
[0103]
  In the first and second embodiments, the image scanner (image reading unit) has been described as an example of the image input unit 100. However, the present invention is not limited to this. That is, the same effect can be obtained even when the image input means 100 is a fax modem (facsimile transmission means) for inputting image data via a public line or a printer controller for generating image data via a network or a dedicated line.
[0104]
  Similarly, a printer (printing unit) has been described as an example of the image output unit 170, but it goes without saying that a fax modem (facsimile receiving unit) or a storage device (filing unit) may be used as the image output unit 170. .
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a flow of image data in “registration processing” of the present invention.
FIG. 2 is an explanatory diagram of the flow of image data in “retrieve processing” of the present invention.
FIG. 3 is an explanatory diagram of a flow of image data in “copy processing” of the present invention.
FIG. 4 is an explanatory diagram showing a flow of image data in “feedback processing” of the present invention.
FIG. 5 is an explanatory diagram showing the flow of image data in “feedback processing” when a synchronization signal generation circuit is provided.
FIG. 6 is a schematic block diagram of a synchronization signal generation circuit.
FIG. 7 is a time chart of the synchronization signal generation circuit.
FIG. 8 shows image data in the conventional “registration process”.DataIt is explanatory drawing which shows the flow.
FIG. 9 shows image data in the conventional “retrieval process”.DataIt is explanatory drawing which shows the flow.
FIG. 10 shows image data in conventional “copy processing”.DataIt is explanatory drawing which shows the flow.
FIG. 11 is a block diagram of a multi-value image processing circuit.
FIG. 12 is a schematic block diagram of an edge enhancement processing circuit.
FIG. 13 is an explanatory diagram of coefficients (weighting) of pixels in a matrix circuit.
FIG. 14 is a schematic block diagram of a zoom processing circuit.
FIG. 15 is a time chart of the zoom processing circuit during enlargement processing;
FIG. 16 is an explanatory diagram of an example of a multi-value reproduction unit.
FIG. 17 is a circuit diagram of a window generation circuit.
FIG. 18 is a schematic block diagram of a smoothing circuit.
FIG. 19 is an explanatory diagram of weighting in the smoothing process.
[Explanation of symbols]
  100 Image input means
  110 First selection means
  120 Multi-value image processing means
  130 Binarization means
  140 Second selection means
  150 Multi-value reproduction means
  160 Third selection means
  170 Image output means
  210 Storage means
  220 Document management means
  230 Fourth selection means
  240 Synchronization signal generating means

Claims (10)

Multilevel image data input from at least one type of image input means is binarized by the binarization means and registered in the storage means, and the binary image data registered in the storage means is also reproduced in multiple values In an image processing apparatus for multi-value reproduction by means and outputting to at least one kind of image output means,
Either binary image data from the binarization means or binary image data from the storage means is selected and the binary image data from the binarization means is sent to the multi-value reproduction means. When selected, multi-value image data is input to the binarization means from the image input means, and when binary image data from the storage means is selected, the binary image data is taken out from the storage means. while, first selection means for outputting,
The multi-value image data from the image input unit, or image data of two values from said binarizing means is output to the multi-value reproduction means by the first selection means, the multi-level by the multivalue reproducing means Second selection means for selecting any of the reproduced image data and outputting the selected image data to the image output means;
An image processing apparatus comprising:   2. The first selection means selects binary image data from the binarization means, and the second selection means selects multi-value image data from the multi-value reproduction means. An image processing apparatus according to 1.   2. The image processing apparatus according to claim 1, wherein the first selection unit selects image data from the storage unit, and the second selection unit selects image data from the multilevel reproduction unit. The multi-value image data input from at least one kind of image input means is subjected to predetermined image processing by the multi-value image processing means, and then binarized by the binarization means and registered in the storage means. In the image processing apparatus which outputs the binary image data registered in the storage means to at least one kind of image output means by multi-value reproduction by the multi-value reproduction means,
First selection means for selecting either multi-value image data from the image input means or multi-value image data from the multi-value reproduction means and outputting to the multi-value image processing means;
The predetermined image processing in the image input is input from the unit above multivalued image processing means is performed, the image data of the binarized binary by the binarizing means, or the 2 value from the storage means When the binary image data binarized by the binarization unit is selected by selecting any one of the image data, the multilevel image data is input to the binarization unit. A second selection means for outputting binary image data from the storage means when the binary image data from the storage means is selected while being input from the image input means ;
An image processing apparatus comprising:   The first selection means selects multi-value image data from the multi-value reproduction means, and the second selection means selects binary image data from the storage means, and the storage means 5. The image processing apparatus according to claim 4, wherein the multi-valued image processing unit performs predetermined image processing on the image data registered in step S1, and then registers the image data in the storage unit again. Synchronization signal generating means for generating a second synchronization signal having a shorter cycle than the first synchronization signal necessary for processing image data in the control of the image output means;
When the first selection means is selecting multi-valued image data from the image input means, the first synchronization signal is displayed, and the first selection means is a multi-valued image from the multi-value reproduction means. Third selection means for selecting the second synchronization signal obtained by the synchronization signal generation means as a synchronization signal for the entire apparatus when data is selected;
The image processing apparatus according to claim 4, further comprising:   The image processing apparatus according to any one of claims 4 to 6, wherein the multi-value image processing means enlarges or reduces an image represented by multi-value image data.   The image processing apparatus according to claim 7, wherein the multi-value image processing means emphasizes an edge portion in an image represented by multi-value image data.   9. The image processing apparatus according to claim 4, wherein the image input unit is at least one of an image reading unit, a facsimile receiving unit, and a printer controller.   The image processing apparatus according to claim 4, wherein the image output unit is at least one of a printing unit, a facsimile transmission unit, and a filing unit.

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