JP4153811B2 - High breakdown voltage semiconductor device and manufacturing method thereof - Google Patents

High breakdown voltage semiconductor device and manufacturing method thereof Download PDF

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JP4153811B2
JP4153811B2 JP2003076252A JP2003076252A JP4153811B2 JP 4153811 B2 JP4153811 B2 JP 4153811B2 JP 2003076252 A JP2003076252 A JP 2003076252A JP 2003076252 A JP2003076252 A JP 2003076252A JP 4153811 B2 JP4153811 B2 JP 4153811B2
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layer
trench
high
trenches
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JP2004006723A (en
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孝 四戸
哲夫 畠山
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株式会社東芝
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Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a high voltage semiconductor device, and more particularly, to a high voltage semiconductor device such as an electrostatic induction transistor, an electrostatic induction thyristor, and a diode for power control, and a method for manufacturing the same.
[0002]
[Prior art]
Semiconductor devices for power control using silicon carbide (hereinafter abbreviated as SiC), which is a wide gap semiconductor material, have excellent characteristics such as high speed and low loss compared to conventional silicon elements, and are practical. It is awaited. In recent years, many semiconductor devices using SiC, such as Schottky barrier diodes, MOSFETs, and electrostatic induction transistors (hereinafter abbreviated as SIT), have been announced and have extremely superior characteristics compared to devices using silicon. Has been confirmed.
[0003]
Hereinafter, a conventional typical SIT structure and a manufacturing method thereof will be described. n - N on the surface of one of the drift layers + A layer (source) is formed around the p + A layer (gate) is formed, and n - N on the other surface of the drift layer + A layer (drain) is formed. n + Layer (source), p + Layer (gate), and n + A source electrode, a gate electrode, and a drain electrode are provided for each layer (drain).
[0004]
In this SIT, a current is passed between a source and a drain, and this current is controlled by a gate bias. When a negative bias is applied to the gate, the depletion layer expands, and the current value is changed by controlling the channel width through which the current passes. That is, when a positive bias with respect to the source is applied to the gate, the depletion layer spreads in the channel between the adjacent gates and the channel width is widened to be turned on. On the other hand, when a negative bias with respect to the source is applied to the gate, the depletion layer spreads over the entire width of the channel between the adjacent gates, and is turned off.
[0005]
[Problems to be solved by the invention]
In order to control the current path by expanding the depletion layer and increase the breakdown voltage when a reverse voltage is applied, it is necessary to deepen the gate region and narrow the channel width. On the other hand, in order to reduce the on-resistance per SIT area, it is necessary to increase the ratio of the source region to the element region, and fine processing is required for both the gate and the source. Further, since the diffusion coefficient of impurities is small in SiC, it is very difficult to deepen the gate region.
[0006]
In order to solve these problems, an element structure in which a trench is formed in a substrate and a gate is formed inside the trench has been proposed (for example, see Non-Patent Document 1). In this case, in order to form the gate inside the trench, the following advanced process technology or the like is used. That is, after a metal film is formed along the trench shape on the entire surface of the substrate including the inside of the trench, a resist is applied, and the resist is reflowed to be accumulated only in the trench. Thereafter, the metal film is etched using the resist accumulated only in the trench as a mask, and a gate electrode is formed by selectively leaving the metal film in contact with the bottom and lower side surfaces of the trench.
[0007]
However, the above method has a problem that when the resist is reflowed, the resist is likely to remain outside the trench. In this case, if etching is performed using a resist pattern generated by reflow as a mask, a metal film remains outside the trench, resulting in an electrical short circuit or deterioration in flatness of the element surface, resulting in deterioration in manufacturing yield and element characteristics. There was a problem of deterioration.
[0008]
On the other hand, regarding the switch-off characteristics of the SIT, in the element in which the gate electrode is formed by selectively leaving the metal film in contact with the bottom and lower side surfaces of the trench as described above, the depletion layer in the channel width direction is formed. However, there is a problem that the switch-off characteristic is not sufficient. Such a problem also exists in the switch-off characteristic of a junction barrier Schottky diode (hereinafter abbreviated as JBS). JBS selectively provides a p-type semiconductor layer around a Schottky junction and switches a depletion layer from the pn junction between the p-type semiconductor layer and the n-type high-resistance semiconductor layer into the n-type high-resistance semiconductor layer. Although this improves the off-characteristics, the device in which the control electrode is formed on the p-type semiconductor layer by the above-described method has a problem that the depletion layer does not spread sufficiently and the switch-off characteristics are not sufficient. It was.
[0009]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a high voltage semiconductor device capable of obtaining excellent element characteristics and improving the manufacturing yield, and a manufacturing method thereof.
[0010]
[Non-Patent Document 1]
Henning, JP; Przadka, A .; Melloch, MR; Cooper, JA, Jr .: IEEE Electron Device Letters, Volume: 21 Issue; 12, Dec. 2000, Page (s): 578-580.
[0011]
[Means for Solving the Problems]
In order to solve the above-described problem, a first high-voltage semiconductor device according to the present invention includes a first conductivity type or second conductivity type SiC substrate having first and second main surfaces, and the SiC substrate. A plurality of elongated planar first trenches formed on the first main surface and provided in parallel with each other; the plurality of first trenches communicated at both longitudinal ends thereof; and the plurality of first trenches A high-conductivity SiC layer of the first conductivity type that surrounds one trench from the outside, has a second trench wider than the first trench in its surface region, and has a higher resistance than the SiC substrate; A plurality of first conductivity type provided on the high-resistance SiC layer at a concentration higher than the impurity concentration of the SiC layer and sandwiched between adjacent trenches among the plurality of first trenches and second trenches. The first SiC region of the A plurality of first trenches, each of which is continuously provided on a side wall and a bottom portion of the first trench, and on a side wall and a bottom portion of the second trench on the first SiC region side, and a bottom corner portion of the first trench; A second SiC region of a second conductivity type formed so as to swell toward the high-resistance SiC layer at a corner of the bottom surface of the second trench on the first trench side; A sidewall insulating film provided on the second SiC region of the sidewall of each of the trenches and a sidewall of the second trench on the first SiC region side; and the bottoms of the plurality of first trenches; And a second trench having a higher impurity concentration than the impurity concentration of the second SiC region, provided in a surface region of the second SiC region at a part of the bottom of the second trench on the first SiC region side. Conductive third SiC region If, which is formed on the upper surface of each of the plurality of first of the plurality of first SiC region sandwiched between the trenches Made of metal silicide A first electrode and each of the plurality of first and second trenches are embedded and contacted with the third SiC region Made of metal silicide A second electrode and a third electrode formed on the second main surface of the SiC substrate are provided.
[0012]
Above SiC substrate Having the first conductivity type and the high resistance SiC The high breakdown voltage when having an impurity concentration higher than the impurity concentration of the layer SiC The device is an electrostatic induction transistor in which the first electrode is a source electrode, the second electrode is a gate electrode, and the third electrode is a drain electrode.
[0013]
Above SiC substrate When the semiconductor device has the second conductivity type, the high withstand voltage semiconductor device is an electrostatic induction thyristor in which the first electrode is an emitter electrode, the second electrode is a gate electrode, and the third electrode is a collector electrode. is there.
[0014]
A third trench may be provided in a termination region of the high voltage semiconductor device surrounding the plurality of first electrodes, and an electric field relaxation structure may be provided at the bottom of the third trench.
[0015]
A second high voltage semiconductor device of the present invention is formed on a first conductivity type SiC substrate having first and second main surfaces, and on the first main surface of the SiC substrate, and in parallel with each other. A plurality of elongated planar-shaped first trenches provided, the plurality of first trenches communicate with each other at both longitudinal ends thereof, and the plurality of first trenches are surrounded from the outside, A first conductivity type high-resistance SiC layer having a second trench wider than the trench and having a higher resistance than the SiC substrate; and adjacent to the plurality of first trenches and the second trenches Formed on a surface region of the high-resistance SiC layer sandwiched between trenches to form a Schottky junction with the surface region of the high-resistance SiC layer Made of metal silicide A first electrode, a plurality of first trenches, and a plurality of first trenches, and a side wall and a part of the bottom of the second trench on the first trench side. A first SiC region of a second conductivity type formed so as to swell toward the high-resistance SiC layer at a corner of the bottom surface of the second trench on the first trench side; A sidewall insulating film provided on the first SiC region of the sidewall of each trench and the first trench side sidewall of the second trench; and the bottom of each of the plurality of first trenches And a second SiC region of a second conductivity type provided in a surface region of the first SiC region at the bottom of the second trench and having an impurity concentration higher than the impurity concentration of the first SiC region; The plurality of first trenches Each and embed the second trench in contact with the second SiC region and connected to said first electrode Made of metal silicide A control electrode and a second electrode formed on the second main surface of the SiC substrate are provided.
[0016]
A third trench may be provided in a termination region of the high voltage semiconductor device surrounding the plurality of first electrodes, and an electric field relaxation structure may be provided at the bottom of the third trench.
[0017]
A third high voltage semiconductor device of the present invention is formed on a first or second conductivity type SiC substrate having first and second main surfaces, and on the first main surface of the SiC substrate. A plurality of elongated planar first trenches provided in parallel to each other, and the plurality of first trenches communicated at both longitudinal ends thereof, and the plurality of first trenches are surrounded from the outside, A first conductive type high-resistance SiC layer having a second trench wider than the first trench and having a higher resistance than the SiC substrate; and an impurity concentration greater than an impurity concentration of the high-resistance SiC layer And a plurality of first conductivity type first electrodes formed on the surface of the high resistance SiC layer, each being sandwiched between adjacent trenches among the plurality of first trenches and the second trenches. The SiC region and the high-resistance SiC layer. An impurity concentration higher than a pure concentration, and a first conductivity type first provided at least at the bottom of each of the plurality of first trenches and at the bottom of the second trench on the first trench side. 2 SiC regions, the side walls of each of the plurality of first trenches, and the side wall insulating film provided on the side wall of the second trench on the first trench side, and in the high resistance SiC layer A part of the upper surface thereof is in contact with the lower surface of the second SiC region, extends horizontally below the adjacent first SiC region, and terminates at a lower portion of the first SiC region. In addition, a portion extending to the second trench includes a third SiC region of a second conductivity type that terminates in the second trench outside the second SiC region, and the plurality of the first trenches. Formed on each of the SiC regions Made of metal silicide Formed on the first SiC and the second SiC region at the bottom of the first and second trenches Made of metal silicide A second electrode, a third electrode connected to the third SiC region through a contact hole formed in the second SiC region, and a second main surface of the SiC substrate are formed. And a fourth electrode.
[0018]
Above SiC substrate When the semiconductor device has the first conductivity type, the high breakdown voltage semiconductor device is an electrostatic induction transistor in which the first electrode is a gate electrode, the second electrode is a source electrode, and the fourth electrode is a drain electrode. .
[0019]
When the SiC substrate has the second conductivity type, the high breakdown voltage semiconductor device uses the first electrode as a gate electrode, the second electrode as an emitter electrode, and the fourth electrode as a collector electrode. It is a thyristor.
[0021]
According to the first method of manufacturing a high voltage device of the present invention, a first conductive type high resistance SiC layer having a higher resistance than the substrate is formed on one surface of the first conductive type SiC substrate. First Process,
Following the first step, A first conductivity type first SiC layer having a lower resistance than the high resistance SiC layer is formed on the surface of the high resistance SiC layer. Second Process, Following the second step, A plurality of first trenches extending from the surface of the first SiC layer to the high resistance SiC layer and a second trench wider than the first trench surrounding the first trench are formed. Third Process, Following the third step, The second conductivity type of the first trench has a side surface and a bottom surface, and part of the side surface and the bottom surface of the second trench on the first trench side so as to bulge toward the high-resistance SiC layer at the corner of the bottom surface. A second SiC layer is formed by multistage ion implantation. 4th Process,
Following the fourth step, An insulating layer pattern is formed on the second SiC layer on the side surfaces of the first and second trenches. 5th Process, Following the fifth step, A second conductivity type third SiC layer having a lower resistance than that of the second SiC layer is formed on the second SiC layer exposed from the insulating layer pattern. 6th Process, Following the sixth step, After forming the third SiC layer, a metal film is formed and heated on the entire surface of the substrate, and the first SiC layer and the third SiC layer sandwiched between the first and second trenches are formed on the surfaces of the first SiC layer and the third SiC layer. Form a metal silicide layer 7th Process, Following the seventh step, The metal film is selectively removed by etching, and a source electrode and a gate electrode made of the metal silicide layer are provided on the surfaces of the first SiC layer and the third SiC layer. 8th Process, Following the eighth step, Forming a drain electrode on the other surface of the SiC substrate; 9th And a process.
[0022]
In the second high breakdown voltage device manufacturing method of the present invention, a first conductive type high resistance SiC layer having a higher resistance than the substrate is formed on one surface of the first conductive type SiC substrate. First Process, Following the first step, A plurality of first trenches and a second trench wider than the first trench surrounding the first trenches are formed in the high resistance SiC layer. Second Process, Following the second step, The second conductivity type of the first trench has a side surface and a bottom surface, and part of the side surface and the bottom surface of the second trench on the first trench side so as to bulge toward the high-resistance SiC layer at the corner of the bottom surface. The first SiC layer is formed by multistage ion implantation. Third Process, Following the third step, An insulating layer pattern is formed on the first SiC layer on the side surfaces of the first and second trenches. 4th Process, Following the fourth step, A second conductivity type second SiC layer having a lower resistance than the first SiC layer is formed on the first SiC layer exposed from the insulating layer pattern. 5th Process, Following the fifth step, After forming the second SiC layer, a metal film is formed and heated on the entire surface of the substrate, and the surface of the high resistance SiC layer sandwiched between the first and second trenches and the second SiC layer are formed. Form a metal silicide layer on the surface 6th Process, Following the sixth step, The metal film is selectively etched away to form a first electrode that forms a Schottky junction with the surface of the high-resistance SiC layer, and the metal silicide layer is formed on the surface of the second SiC layer. A control electrode electrically connected to the 7th Process, Following the seventh step, Forming a second electrode on the other surface of the SiC substrate; 8th And a process.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0024]
(First embodiment)
The first embodiment relates to a high voltage semiconductor device (SIT).
[0025]
First, structural features and effects in the SIT of this embodiment will be described. As shown in FIG. 1, an n-type first semiconductor region having a lower resistance (higher impurity concentration) than that of the high-resistance semiconductor layer 2 is provided on one surface of the n-type high-resistance semiconductor layer (SiC layer) 2. (SiC layer) 3a is selectively provided as a source region. The impurity concentration and thickness of the high-resistance semiconductor layer 2 are determined by the design breakdown voltage. For example, the impurity concentration range is 1 × 10. 14 ~ 1x10 16 cm -3 The thickness range is 5 to 100 μm. The impurity concentration of the source region 3a is, for example, 1 × 10 20 cm -3 It is. As the n-type dopant, for example, nitrogen, phosphorus, or arsenic is used.
[0026]
As shown in FIGS. 1 to 3, the high resistance semiconductor layer 2 around the source region 3a is provided with trench portions 5 and 5 ', and the width of the trench portion 5 is narrower than the width of the trench portion 5'. It has become. The trench portion 5 is formed only in the element region, and the trench portion 5 ′ is formed from the element region to the termination region.
[0027]
As shown in FIG. 1, the trench portions 5 and 5 ′ are provided so as to dig a portion of the high resistance semiconductor layer 2 around the source region 3 a, and the source region 3 a is surrounded by the trench portions 5 and 5 ′. The structure is provided on the upper surface of the plurality of island-shaped convex portions. Diagram of trench portions 5 and 5 '. The width in the cross section of 1 is, for example, 1 μm and 100 μm, respectively, and the width of the island-shaped convex portion between the trench portions 5 and 5 ′ is, for example, 1 μm.
[0028]
A p-type second semiconductor layer (SiC layer) 9 is provided as a gate layer on the side surfaces 5 a and 5 b of the trench portion 5. Although the side surfaces 5a and 5b have been described as examples, the same applies to the other side surfaces of the trench portion 5. Typically, the impurity concentration of the gate layer 9 is, for example, 1 × 10. 18 cm -3 It is. As the p-type dopant, for example, aluminum or boron is used.
[0029]
A gate layer 9 is also provided on one side surface and a part of the bottom surface of the trench portion 5 ′. The gate layer 9 is formed such that the bottom corners of the gate layer 9 swell toward the high resistance semiconductor layer 2. The maximum thickness of the gate layer 9 on the bottom surfaces of the trench portions 5 and 5 ′ is, for example, 0.3 μm, and the maximum thickness of the gate layer 9 on the side surfaces 5a and 5b of the trench portions 5 and 5 ′ is, for example, 0.1 μm.
[0030]
Side wall insulating films 10a and 10b are selectively provided on the gate layer 9 on the side surfaces 5a and 5b of the trench portion 5, and these side wall insulating films 10a and 10b are shown in FIG. As shown to 2 and 3, it forms so that the outer periphery of the said several island-shaped convex part may be surrounded. A side wall insulating film 10c is also selectively provided on the other side surface 5c of the trench portion 5 '. As shown in FIGS. 2 and 3, the side wall insulating film 10c is formed along the inside of the outer peripheral portion 3b of the device. ing.
[0031]
Further, a p-type third semiconductor layer (SiC layer) 12 is selectively provided as a gate contact layer on the gate layer 9 portion on the bottom surface of the trench portion 5, and the side wall insulating films (spacer layers) 10a and 10b are formed. It is exposed in between.
[0032]
Although the gate contact layer 12 is also provided on the gate layer 9 on the bottom surface of the trench portion 5 ′, the gate contact layer 12 is in contact with the sidewall insulating film 10b only on one side. The impurity concentration of the gate contact layer 12 is, for example, 1 × 10 20 cm -3 It is. For example, aluminum is used as the p-type dopant.
[0033]
On the other hand, an n-type fourth semiconductor layer (SiC layer) 1 is provided as the drain layer on the other surface of the n-type high-resistance semiconductor layer 2. The impurity concentration of the drain layer 1 is, for example, 1 × 10 19 cm -3 It is. As the n-type dopant, for example, nitrogen, phosphorus, or arsenic is used.
[0034]
A source electrode 14, a gate electrode 15, and a drain electrode 16 are provided on the respective surfaces of the source layer 3 a, the gate contact layer 12, and the drain layer 1. Further, the source electrode 14, the gate electrode 15, and the drain electrode 16 are provided with a source electrode lead wiring 17, a gate electrode lead wiring 18, and a drain electrode lead wiring 19, respectively.
[0035]
As shown in FIG. 3, the source electrode lead-out wiring 17 is composed of an electrode pad portion having a large area and a plurality of striped connection electrode portions that electrically connect the electrode pad portion and each source electrode 14. It has a comb-like pattern.
[0036]
Similarly, the gate electrode lead-out wiring 18 is composed of an electrode pad portion having a large area and a plurality of striped connection electrode portions that electrically connect the electrode pad portion and the gate electrode 15, and has a comb-like shape. Has a pattern. The source electrode lead wiring 17 and the gate electrode lead wiring 18 are wired so as to mesh with each other.
[0037]
FIG. 4 shows a contact structure of each electrode schematically shown in FIG. Specifically, the insulating film 20 is formed on the entire surface including the trench structure, and contact holes that communicate with the source electrode 14 and the gate electrode 15 are provided in the insulating film. A source electrode lead-out wiring 17 and a gate electrode lead-out wiring 18 connected to the source electrode 14 and the gate electrode 15, respectively, are provided so as to fill these contact holes.
[0038]
In FIG. 4, for convenience of explanation, the source electrode lead wiring 17 and the gate electrode lead wiring 18 are shown in the same cross-sectional view, but these are provided so as to be shifted in a direction perpendicular to the drawing sheet. Only the gate electrode lead-out wiring 18 appears in this sectional view.
[0039]
Although not shown in FIG. 4, the gate electrode lead-out wiring 18 extends on the surface of the insulating film 20, and an interlayer insulating film is further formed to cover the insulating film 20 and the gate electrode lead-out wiring 18. The source electrode lead-out wiring 17 is led out to the surface of the interlayer insulating film, and the surface of the interlayer insulating film is extended.
[0040]
Next, the termination region will be described. As shown in FIGS. 1 to 3, a RESURF layer 7 is provided on the outer periphery of the gate layer 9 on the bottom surface of the trench portion 5 ′ in contact with the gate layer 9. The impurity concentration of the RESURF layer 7 is, for example, 3 × 10 17 cm -3 And the depth is 0.6 μm. However, the optimum value of the structure of the RESURF layer varies depending on the process conditions. As the p-type dopant, for example, aluminum or boron is used.
[0041]
A part of the surface of the high resistance semiconductor layer 2 appears on the bottom surface of the trench portion 5 ′ between the sidewall insulating film 10 c located on the side surface 5 c of the trench portion 5 ′ and the RESURF layer 7. An n-type semiconductor layer 3b is provided on the upper surface of the step on the outer periphery of the trench portion 5 ′. The impurity concentration of the n-type semiconductor layer 3b is, for example, 1 × 10 19 cm -3 As the n-type dopant, for example, nitrogen, phosphorus, and arsenic are used. The termination structure is constituted by the above components.
[0042]
One of the features of the element structure of the present embodiment is that the gate electrode lead-out wiring 18 is embedded in the trench portions 5 and 5 ′ on the side surfaces 5a and 5b with the side wall insulating films 10a and 10b interposed therebetween, The contact layer 12 and the gate electrode 15 are selectively provided on the portion of the gate layer 9 exposed from the sidewall insulating films 10a and 10b. That is, the gate electrode lead-out wiring 18 does not directly contact the gate layer 9 on the side surfaces 5a and 5b of the trench portions 5 and 5 ′, and the gate electrode 15 is connected to the gate contact layer 12 on the bottom surfaces of the trench portions 5 and 5 ′. Only contact through. Since the gate contact layer 12 and the gate electrode 15 are formed in a self-aligned manner with respect to the sidewall insulating films 10a and 10b, the gate contact layer 12 and the gate electrode 15 are accurately positioned in the center region of the bottom surfaces of the trench portions 5 and 5 ′.
[0043]
With this configuration, a gate potential can be selectively applied to the bottom surfaces of the trench portions 5 and 5 ′ through the gate electrode lead-out wiring 18, and the gate layers 9 on the side surfaces 5a and 5b of the trench portions 5 and 5 ′ can be applied. In this case, the gate potential is not directly applied. Accordingly, a gate voltage can be preferentially applied to the gate layer 9 portion located adjacent to the corners of the bottom surfaces of the trench portions 5 and 5 ′, and the high resistance semiconductor layer adjacent to the gate layer 9 portion. The extension of the depletion layer in 2 can be made dominant. Since the gate layer 9 is formed in a shape that swells toward the high-resistance semiconductor layer 2, the switch-off characteristics are improved by performing the switch-off mainly using the extension of the depletion layer in this part. Is possible.
[0044]
Another feature of the element structure of the present embodiment is that the source layer 3a at the upper end of the trench 5 and the gate contact layer 12 at the bottom of the trench 5 are formed in a self-aligned manner. Therefore, there is no influence of misalignment of the mask at the time of electrode formation, and it becomes possible to make the trench structure as fine as the limit of the exposure machine, and the miniaturization is easy.
[0045]
Further, as shown in FIG. 4, the source electrode lead wiring 17 and the gate electrode lead wiring 18 in the upper layer are connected to the source electrode 14 and the gate electrode 15 through the contact holes of the insulating film 20. Yes. That is, in the miniaturized structure, alignment accuracy is required between the source electrode or gate electrode and the contact hole. However, as shown in FIG. 4, the distance between the sidewall insulating films (spacer layers) 10a and 10b and the insulating film 20 is increased. By selecting the insulating material so that the etching selection ratio can be obtained, the margin of alignment between the contact hole and the source electrode and the gate electrode can be obtained by the side wall insulating films 10a and 10b. It becomes easy. For example, silicon nitride can be used as the material of the sidewall insulating films 10a and 10b, and silicon oxide can be used as the material of the insulating film 20.
[0046]
If the element structure can be miniaturized in this way, the channel width between each source layer 3a and the drain layer 1 can be narrowed, so that the depletion layer easily spreads over the entire channel width in the off-state. It is possible to improve the point that the pinch-off voltage, which is a peculiar difficulty, becomes high. Therefore, the element can be switched off more reliably, and the reliability of the element can be greatly improved.
[0047]
Further, since the source electrode 14 and the gate electrode 15 can be covered over the entire source layer 3a and the gate contact layer 12, the contact resistance can be lowered, and the resistance (on-resistance) when the device is energized can be lowered. it can. Further, since a large amount of current can be supplied to the gate electrode 15 at the time of switching, high-speed switching is possible.
[0048]
Furthermore, according to the apparatus of the present embodiment, as shown in FIGS. 1 to 3, the RESURF layer 7 is provided on the outer periphery of the gate layer 9 on the bottom surface of the trench portion 5 ′ in contact with the gate layer 9. Therefore, it is possible to increase the breakdown voltage of the element when the switch is turned off. In particular, since the RESURF layer 7 is provided together with the gate layer 9 on the bottom surface of the trench portion 5 ′, the surface of the gate layer 9 and the surface of the RESURF layer 7 can be located in the same plane. The layer can suppress the electric field concentration at the corner of the gate layer 9 to the maximum, and the effect of contributing to the high breakdown voltage is great.
[0049]
In addition, the sidewall insulating film 10c formed on the side surface 5c of the trench portion 5 ′ can provide an effect of increasing the margin of positional deviation of the electrode formed on the channel stopper (n-type semiconductor layer 3b). is there.
[0050]
Next, a method for manufacturing the SIT (FIG. 1) of this embodiment will be described with reference to FIGS. These drawings correspond to cross-sectional views taken along the line II of FIG.
[0051]
First, as shown in FIG. 5, an n-type high-resistance semiconductor layer (SiC layer) 2 is formed on an n-type high-concentration substrate (SiC substrate) 1 by an epitaxial growth method. The n-type high concentration substrate 1 corresponds to an n-type fourth semiconductor region (SiC layer) 1 as a drain region. Further, a low-resistance n-type first semiconductor layer (SiC layer) 3 is formed on the high-resistance semiconductor layer 2. The n-type first semiconductor layer 3 becomes the source region 3a. The first semiconductor layer 3 is formed by ion-implanting n-type impurities into the high resistance semiconductor layer 2 or performing epitaxial growth on the high resistance semiconductor layer 2.
[0052]
Next, as shown in FIG. 6, a mask pattern 4 is formed on the first semiconductor layer 3, and RIE (Reactive Ion Etching) is performed using the mask pattern 4, thereby forming the first semiconductor layer 3. Trench portions 5 and 5 'reaching the high resistance semiconductor layer 2 from the surface are formed. The width of the trench portion 5 is formed narrower than the width of the trench portion 5 ′.
[0053]
In this case, the mask pattern 4 can be made of a metal having high etching resistance, such as molybdenum, aluminum, tungsten, or a laminated film thereof, and the etching gas can be CF. Four , SF 6 Fluorine-based gas such as can be used. As a result of this etching step, the first semiconductor layer 3 is patterned to form a source region 3a and an n-type semiconductor region 3b.
[0054]
Next, as shown in FIG. 7, a resist pattern 6 that covers the trench portion 5 and exposes a part of the bottom surface of the trench portion 5 ′ is formed, and ion implantation of p-type impurities is performed using the resist pattern 6 as a mask. By this ion implantation, the RESURF layer 7 is selectively formed on a part of the bottom of the trench 5 ′.
[0055]
Next, as shown in FIG. 8, the resist pattern 6 is removed while leaving the mask pattern 4, and a new resist pattern 8 is formed so as to cover the n-type semiconductor layer 3 b and the RESURF layer 7. Using this resist pattern 8 as a mask, p-type impurity ions are implanted. By this ion implantation, the p-type gate layer 9 is selectively formed on the side surfaces 5a and 5b and the bottom surface of the trench portion 5, and the portion adjacent to the RESURF layer 7 on the bottom surface of the trench portion 5 ′ and the side surface portion 5b are selectively formed. A gate region 9 is formed.
[0056]
In this case, if the gate region 9 is as dense as possible, the gate performance is improved. However, if the dense gate region 9 is formed in the vicinity of the source region 3a, the source-gate breakdown voltage is lowered. It is desirable to adjust so that the doping amount in the vicinity of the source region 3a is reduced by performing multistage ion implantation while changing the acceleration voltage. Through the ion implantation process described above, the gate region 9 is formed such that the corner of the bottom surface swells toward the high resistance semiconductor layer 2.
[0057]
Next, as shown in FIG. 9, the resist pattern 8 is removed while leaving the mask pattern 4. Further, a continuous film made of silicon nitride or the like is formed on the entire surface including the trench portions 5 and 5 ′ by a CVD method or the like, and the entire surface of the continuous film is anisotropically etched (RIE or the like) to perform the trench portions 5 and 5 ′. Side wall insulating films 10a, 10b, and 10c are selectively left on the side surfaces 5a, 5b, and 5c, respectively.
[0058]
Thereafter, a new resist pattern 11 is formed so as to cover from the n-type semiconductor region 3 b to the gate region 9 adjacent to the RESURF layer 7. Using this resist pattern 11 as a mask, p-type impurity ions are implanted. By this ion implantation, a p-type gate contact region 12 is selectively formed on the bottom surfaces of the trench portions 5 and 5 ′.
[0059]
Next, as shown in FIG. 10, the mask pattern 4 and the resist pattern 11 are removed. In this step, the surfaces of the sidewall insulating films 10a, 10b, and 10c are receded so that the upper end portions of the sidewall insulating films 10a, 10b, and 10c substantially coincide with the upper surfaces of the source region 3a and the n-type semiconductor region 3b, respectively. Become. Furthermore, annealing for activating the source region 3a, the n-type semiconductor region 3b, the gate region 9, and the gate contact region 12 is performed under a high temperature condition of 1600 ° C., for example.
[0060]
Thereafter, a resist mask (not shown) is formed so as to cover from the n-type semiconductor region 3b to the periphery of the gate contact region 12, and a metal film made of Ni or the like is formed on the entire surface including the resist mask. Further, the metal mask 13 is formed by patterning the metal film by removing the resist mask and performing a lift-off method. (FIG. 10).
[0061]
Thereafter, as shown in FIG. 11, annealing of the metal pattern 13 is performed at 1000 ° C., for example, to cause silicidation reaction to proceed on the surfaces of the source region 3a and the gate contact region 12, respectively. For example, Ni 2 Si) layers 14 and 15 are formed. The silicidation reaction does not occur on the surfaces of the sidewall insulating films 10a and 10b, and a part of the metal pattern 13 remains in this portion.
[0062]
Further, as shown in FIG. 12, the remaining metal pattern 13 is selectively removed by etching using an etchant such as a mixture of hydrochloric acid and peroxide water (SC2), and the surfaces of the source region 3a and the gate contact region 12 are respectively removed. The nickel silicide layers 14 and 15 are left selectively. The nickel silicide layers 14 and 15 become the source electrode 14 and the gate electrode 15, respectively. It is possible to selectively form a nickel silicide layer also on the surface of the n-type semiconductor region 3b to reduce the contact resistance of this portion. In this case, the metal pattern 13 may be formed also on the n-type semiconductor region 3b in the above process.
[0063]
Next, the SIT of this embodiment shown in FIG. 1 is completed by performing a normal wiring process. That is, the drain electrode 16 is formed on the surface of the drain region 1, and the source electrode 14, the gate electrode 15, and the drain electrode 16 are respectively provided with the source electrode lead wiring 17, the gate electrode lead wiring 18, and the drain electrode lead wiring 19. The SIT of the first embodiment is completed.
[0064]
(Second Embodiment)
FIG. 13 is a cross-sectional view of a high voltage semiconductor device (SI thyristor) according to the second embodiment of the present invention. N on the back surface of the first embodiment (FIG. 1) + P layer + By changing to a layer, an SI (static induction) thyristor can be obtained. Since the configuration is similar to that of the first embodiment, the same parts are denoted by the same reference numerals, and redundant description is omitted. Also, the top view is the same as FIG.
[0065]
First, structural features and effects of the SI thyristor of the present embodiment will be described. As shown in FIG. 13, a low resistance p is formed on one surface (back surface) of the n-type high resistance semiconductor layer (SiC layer) 2. + A type semiconductor layer 1 ′ is provided as a collector layer. Reference numeral 16 'denotes a collector electrode, and 19' denotes a collector electrode lead line.
[0066]
The concentration and thickness of the high-resistance semiconductor layer 2 are determined by the design breakdown voltage. For example, the impurity concentration range is 1 × 10. 14 ~ 1x10 16 cm -3 The thickness range is 5 to 100 μm. The impurity concentration of the collector layer 1 ′ is, for example, 1 × 10 19 cm -3 It is. For example, nitrogen, phosphorus, or arsenic is used as the n-type dopant.
[0067]
Reference numeral 14 'is an emitter electrode, and 17' is an emitter electrode lead line. Other element structures are substantially the same as those in the first embodiment. For example, the termination structure (Resurf layer) 7 is a p-type low concentration layer, and its impurity concentration is, for example, 3 × 10. 17 cm -3 And the depth is 0.6 μm.
[0068]
A feature of the second embodiment is that the gate electrode and the emitter electrode are formed in a self-aligned manner. Therefore, an invalid area for allowing mask displacement is unnecessary, and an increase in resistance value per area caused by the invalid area can be suppressed. Further, since the gate electrode is above the buried p-type layer, the capacitance between the gate and collector is small, and high speed operation is possible.
[0069]
Further, if the above-described SI thyristor 20 and MOSFET 21 form a circuit called a cascode connection shown in FIG. 14, it can be operated from the outside as a normally-off switching element similar to a normal MOSFET. In this circuit, holes accumulated in the element are discharged from the gate electrode 18 during the off operation, but do not flow into the control gate of the MOSFET 21 because the gate electrode is connected to GND. Therefore, there is an advantage that the capacity of the gate power supply can be reduced.
[0070]
(Third embodiment)
The high breakdown voltage semiconductor device according to the third embodiment relates to a JBS (Junction Barrier Schottky Diode).
[0071]
First, the structural features and effects of the JBS of this embodiment will be described. As shown in FIG. 15, a Schottky electrode 114 that forms a Schottky junction with the high-resistance semiconductor layer 102 is provided on one surface of the n-type high-resistance semiconductor layer (SiC layer) 102. Reference numeral 103a denotes a Schottky junction region. The impurity concentration and thickness of the high-resistance semiconductor layer 102 are determined by the design breakdown voltage. For example, the impurity concentration range is 1 × 10. 14 ~ 1x10 16 cm -3 The thickness range is 5 to 50 μm. Further, when conductivity modulation is used, the thickness may reach 100 μm. As the n-type dopant, for example, nitrogen, phosphorus, or arsenic is used. As a material of the Schottky electrode 114, for example, Ti (titanium), Ni (nickel), or Mo (molybdenum) is used.
[0072]
As shown in FIGS. 15 and 16, the high resistance semiconductor layer 102 around the Schottky electrode 114 is provided with trench portions 105 and 105 ′, and the width of the trench portion 105 is larger than the width of the trench portion 105 ′. It is narrower. The trench portion 105 is formed only in the element region, and the trench portion 105 ′ is formed from the element region to the termination region. As shown in the top view of FIG. 16, the trench portions 105 and 105 ′ are provided by digging a portion of the high-resistance semiconductor layer 102 around the Schottky junction region 103a, and the Schottky junction region 103a is The structure is provided on the upper surfaces of a plurality of island-shaped convex portions surrounded by the trench portions 105 and 105 ′. The widths of the trench portions 105 and 105 ′ shown in FIG. 15 are, for example, 1 μm and 100 μm, respectively, and the width of the island-shaped protrusion between the trench portions 105 and 105 ′ is, for example, 2 μm.
[0073]
A p-type first semiconductor region (SiC layer) 109 is provided on the side surfaces 105a and 105b of the trench portion 105 as a control electrode layer. The impurity concentration of the first semiconductor region 109 is, for example, 1 × 10 18 cm -3 It is. As the p-type dopant, for example, aluminum or boron is used. A first semiconductor region 109 is also provided on one side surface and a part of the bottom surface of the trench portion 105 ′.
[0074]
These first semiconductor regions 109 are formed so that the bottom corners of the first semiconductor region 109 swell toward the high resistance semiconductor layer 102. The maximum thickness of the first semiconductor region 109 on the bottom surfaces of the trench portions 105 and 105 ′ is, for example, 0.3 μm, and the maximum thickness of the first semiconductor region 109 on the side surfaces 105a and 105b of the trench portion 105 is, for example, 0.1 μm.
[0075]
Side wall insulating films 110a and 110b are selectively provided in the first semiconductor regions 109 on the side surfaces 105a and 105b of the trench portion 105. These sidewall insulating films 110a and 110b are formed so as to surround the outer periphery of the plurality of island-shaped convex portions as shown in FIG. A sidewall insulating film 110c is selectively provided also on the other side surface 105c of the trench portion 105 ′, and as shown in FIG. 16, the sidewall insulating film 110c is formed along the inside of the outer peripheral portion 103b of the device. .
[0076]
Further, a p-type second semiconductor region (SiC layer) 112 is selectively contacted with a portion of the first semiconductor region 109 exposed from the sidewall insulating films (spacer layers) 110a and 110b on the bottom surface of the trench portion 105. It is provided as a region.
[0077]
The contact region 112 is also provided in the first semiconductor region 109 on the bottom surface of the trench portion 105 ′. The contact region 112 is in contact with the sidewall insulating film 110b only on one side. The impurity concentration of the contact region 112 is, for example, 1 × 10 20 cm -3 It is. As the p-type dopant, for example, aluminum or boron is used.
[0078]
On the other hand, an n-type third semiconductor region (SiC layer) 101 is provided as a cathode region on the other surface of the n-type high-resistance semiconductor layer 102. The impurity concentration of the cathode region 101 is, for example, 1 × 10 19 cm -3 It is. As the n-type dopant, for example, nitrogen, phosphorus, or arsenic is used.
[0079]
An anode electrode (Schottky electrode) 114, a control electrode 115, and a cathode electrode 116 are provided on the surfaces of the Schottky junction region 103a, the contact region 112, and the cathode region 101, respectively. Further, the anode electrode 114 and the control electrode 115 are provided with an anode electrode lead wire 117 so as to short-circuit both of them, and the cathode electrode 116 is provided with a cathode electrode lead wire 119. As shown in FIG. 16, the anode electrode lead-out wiring 117 is a connection electrode portion having a large area that electrically connects between the control electrode 115 having a relatively large area and each anode electrode 114 (a portion hatched around). It is configured as.
[0080]
Next, the termination region will be described. As shown in FIGS. 15 and 16, a RESURF layer 107 is provided on the outer periphery of the first semiconductor region 109 on the bottom surface of the trench portion 105 ′ in contact with the first semiconductor region 109. The impurity concentration of the RESURF layer 107 is, for example, 3 × 10 17 cm -3 And the depth is 0.6 μm. As the p-type dopant, for example, aluminum or boron is used.
[0081]
A part of the surface of the high-resistance semiconductor layer 102 appears on the bottom surface of the trench portion 105 ′ between the sidewall insulating film 110 c located on the side surface 105 c of the trench portion 105 ′ and the RESURF layer 107. An n-type semiconductor region 103b is provided on the upper surface of the step on the outer periphery of the trench portion 105 ′. The impurity concentration of the n-type semiconductor region 103b is, for example, 1 × 10 19 cm -3 As the n-type dopant, for example, nitrogen, phosphorus, and arsenic are used. The termination structure is constituted by the above components.
[0082]
One of the features of the element structure of the present embodiment is that the anode electrode lead-out wiring 117 is embedded in the trench portions 105 and 105 ′ with the side surfaces 105a and 105b interposed through the side wall insulating films 110a and 110b. The contact region 112 and the control electrode 115 are selectively provided in the portion of the first semiconductor region 109 exposed from the sidewall insulating films 110a and 110b.
[0083]
That is, the anode electrode lead-out wiring 117 does not directly contact the first semiconductor region 109 on the side surfaces 105a and 105b of the trench portions 105 and 105 ′, and the control electrode 115 is formed on the contact region 112 on the bottom surface of the trench portions 105 and 105 ′. Only contact through. Since the contact layer 112 and the control electrode 115 are formed in a self-aligned manner with respect to the side wall insulating films 110a and 110b, the contact layer 112 and the control electrode 115 are accurately positioned in the center region of the bottom surfaces of the trench portions 105 and 105 ′.
[0084]
With this configuration, an anode potential can be selectively applied to the bottom surfaces of the trench portions 105 and 105 ′ through the anode electrode lead-out wiring 117, and the first semiconductor regions on the side surfaces 105a and 105b of the trench portions 105 and 105 ′. No anode potential is directly applied to 109.
[0085]
Therefore, an anode voltage can be preferentially applied to the first semiconductor region 109 portion located adjacent to the corners of the bottom surfaces of the trench portions 105 and 105 ′, and the first semiconductor region 109 portion can be applied to the first semiconductor region 109 portion. The extension of the depletion layer in the adjacent high-resistance semiconductor layer 102 can be made dominant. Since the first semiconductor region 109 is formed in a shape that swells toward the high-resistance semiconductor layer 102, leakage current characteristics at the time of switching off are improved by dominantly using the extension of the depletion layer in this portion. Is possible.
[0086]
For example, in the JBS of the above embodiment, for example, when a 1500 V withstand voltage is designed, the leakage current when applying a reverse voltage can be greatly reduced as compared with a conventional Schottky diode, and the trade-off between leakage current and on-resistance is improved. Is done. On the other hand, in the conventional trench JBS of the type in which the anode electrode lead-out wiring is in direct contact with the first semiconductor region on the side surface of the trench, when operated under the same conditions as described above, the leakage current and the on-resistance are traded off. The effect is small.
[0087]
Further, since the control electrode 115 can be covered over the entire contact region 112, the contact resistance can be lowered, and a large amount of current can be supplied during switching, so that high-speed switching is possible.
[0088]
Furthermore, according to the semiconductor device of this embodiment, as shown in FIGS. 15 and 16, the RESURF is in contact with the outer periphery of the first semiconductor region 109 on the bottom surface of the trench portion 105 ′ in contact with the first semiconductor region 109. Since the layer 107 is provided, it is possible to increase the breakdown voltage of the element when the switch is turned off.
[0089]
In particular, since the RESURF layer 107 is provided together with the first semiconductor region 109 on the bottom surface of the trench portion 105 ′, the surface of the first semiconductor region 109 and the surface of the RESURF layer 107 can be located in the same plane. The depletion layer formed by the RESURF layer 107 can control the electric field concentration at the corners of the first semiconductor region 109 to the maximum, and the effect of contributing to high breakdown voltage is great.
[0090]
In addition, the sidewall insulating film 110c formed on the side surface 105c of the trench portion 105 ′ can provide an effect of increasing the margin of displacement of the electrode formed on the channel stopper (n-type semiconductor region 103b). is there.
[0091]
Next, a method for manufacturing the JBS of this embodiment will be described with reference to FIGS. These cross-sectional views correspond to cross-sectional views taken along the line XV-XV in FIG.
[0092]
First, as shown in FIG. 17, an n-type high-resistance semiconductor layer (SiC layer) 102 is formed on an n-type high-concentration substrate (SiC substrate) 101 by an epitaxial growth method. The n-type high concentration substrate 101 corresponds to the n-type third semiconductor region (SiC layer) 101 as a cathode layer.
[0093]
Next, as shown in FIG. 18, a mask pattern 104 is formed on the high-resistance semiconductor layer 102, and RIE is performed using the mask pattern 104 to form trench portions 105 and 105 ′. The width of the trench portion 105 is formed narrower than the width of the trench portion 105 ′. The mask pattern 104 can be made of a metal having high etching resistance, such as molybdenum, aluminum, or tungsten, and the etching gas can be CF. Four , SF 6 Fluorine-based gas such as can be used. As a result of this etching process, a Schottky junction region 103a is formed.
[0094]
Next, as shown in FIG. 19, a resist pattern 106 that covers the trench portion 105 and exposes a part of the bottom surface of the trench portion 105 ′ is formed, and ion implantation of p-type impurities is performed using the resist pattern 106 as a mask. By this ion implantation, the RESURF layer 107 is selectively formed on a part of the bottom of the trench portion 105 ′.
[0095]
Next, as shown in FIG. 20, the resist pattern 106 is removed while leaving the mask pattern 104, and a new resist pattern 108 is formed so as to cover the resurf layer 107 from the outermost peripheral portion of the substrate. Using this resist pattern 108 as a mask, ion implantation of p-type impurities is performed. By this ion implantation, the p-type first semiconductor region 109 is selectively formed on the side surfaces 105a and 105b and the bottom surface of the trench portion 105, and at the portion adjacent to the RESURF layer 107 on the bottom surface of the trench portion 105 ′ and the side surface portion 105b. A first semiconductor region 109 is selectively formed.
[0096]
In this case, the darker the first semiconductor region 109, the better the gate performance. However, when the dark first semiconductor region 109 is formed in the vicinity of the Schottky junction region 103a, the breakdown voltage is lowered. Therefore, it is desirable to adjust so that the doping amount in the vicinity of the Schottky junction region 103a is reduced by performing multi-stage ion implantation while changing the ion implantation angle, dose, and acceleration voltage. Through the ion implantation process described above, the first semiconductor region 109 is formed so that the bottom corner of the first semiconductor region 109 swells toward the high-resistance semiconductor layer 102.
[0097]
Next, as shown in FIG. 20, the resist pattern 108 is removed while leaving the mask pattern 104. Further, a continuous film made of silicon nitride or the like is formed on the entire surface including the trench portions 105 and 105 ′ by a CVD method or the like, and the entire surface of the continuous film is subjected to anisotropic etching (RIE) or the like to perform the trench portions 105 and 105 ′. Side wall insulating films 110a, 110b, and 110c are selectively left on the side surfaces 105a, 105b, and 105c, respectively.
[0098]
Thereafter, a resist pattern 111 is newly formed so as to cover from the outermost peripheral portion of the substrate to the first semiconductor region 109 adjacent to the RESURF layer 107. Using this resist pattern 111 as a mask, p-type impurity ions are implanted. By this ion implantation, a p-type contact layer 112 is selectively formed on the bottom surfaces of the trench portions 105 and 105 ′.
[0099]
Next, as shown in FIG. 22, the mask pattern 104 and the resist pattern 111 are removed. In this step, the surfaces of the side wall insulating films 110a, 110b, and 110c recede, and the upper end portions of the side wall insulating films 110a, 110b, and 110c substantially coincide with the upper surfaces of the Schottky junction regions 103a.
[0100]
If necessary, the n-type semiconductor region 103b may be provided on the outermost peripheral portion of the substrate by ion implantation using a mask. This ion implantation may be performed selectively in the termination region before forming the trench structure. In this way, it is not necessary to consider the mask alignment accuracy. Furthermore, annealing for activating the first semiconductor region 109, the contact region 112, and the n-type semiconductor region 103b is performed under a high temperature condition of 1600 ° C., for example.
[0101]
Thereafter, a resist mask (not shown) is formed so as to cover from the n-type semiconductor region 103b to the peripheral portion of the contact region 112, and a metal film made of Ni or the like is formed on the entire surface including the resist mask. Further, by removing the resist mask and performing a lift-off method, the metal film is patterned to form a metal pattern 113 (FIG. 22).
[0102]
Thereafter, as shown in FIG. 23, the metal pattern 113 is annealed at, for example, 1000 ° C. to cause silicidation reaction to proceed on the surfaces of the Schottky junction region 103a and the contact region 112, and nickel silicide is formed on each surface. (For example, Ni 2 Si) layers 114 and 115 are formed. In this silicidation process, a Schottky contact electrode (nickel silicide layer 114) and an ohmic contact electrode (nickel silicide layer 115) are formed in each of the Schottky junction region 103a and the contact region 112 by a single silicidation process. be able to.
[0103]
On the other hand, the silicidation reaction does not occur on the surfaces of the sidewall insulating films 110a and 110b, and a part of the metal pattern 113 remains in this portion. Further, as shown in FIG. 24, the remaining metal pattern 113 is selectively removed by etching using an etchant such as a mixed solution (SC2) of hydrochloric acid and hydrogen peroxide. Thus, nickel silicide layers 114 and 115 are selectively left on the surfaces of the Schottky junction region 103a and the contact region 112, respectively. The nickel silicide layers 114 and 115 become the anode electrode 114 and the control electrode 115, respectively.
[0104]
It is possible to selectively form a nickel silicide layer also on the surface of the n-type semiconductor region 103b to reduce the contact resistance of this portion. In this case, the metal pattern 113 may be formed also on the n-type semiconductor region 103b in the above process.
[0105]
Next, by performing a normal wiring process, the cathode electrode 116 is formed on the surface of the cathode region 101, the anode electrode lead wiring 117 is provided on the anode electrode 114 and the control electrode 115, and the cathode electrode lead wiring is provided on the cathode electrode 116. 119 is provided to complete the JBS of this embodiment shown in FIG.
[0106]
(Fourth embodiment)
FIG. 25 is a top view of a high voltage semiconductor device (SIT) according to the fourth embodiment of the present invention. FIG. 26 shows a partial cross-sectional view from the vicinity of the center of the element to the termination region in the cross-section along the line XXVI-XXVI in FIG. 25. The cross-sectional view is the same as FIG. 1 except for the termination region.
[0107]
As shown in FIG. 25, a plurality of stripe-shaped trench portions 205 are formed in parallel with each other on one surface of an n-type high-resistance semiconductor layer (SiC layer) 202. An n-type first semiconductor region (SiC layer) 203 a having a lower resistance than that of the high resistance semiconductor layer 202 is provided as a source region on the surface of the high resistance semiconductor layer 202 between the trench portions 205. The width of the trench portion 205 and the width of the source region 203a between the trench portions 205 shown in FIG. 26 are the same as those in the first embodiment.
[0108]
A p-type second semiconductor region (SiC layer) 209 is provided as a gate region on the side surface (205a, 205b, etc.) and the bottom surface of each trench portion 205, respectively. The gate region 209 is formed such that the bottom corner thereof swells toward the high resistance semiconductor layer 202. The maximum thickness on the side surface and the bottom surface of the gate region 209 is the same as that in the first embodiment.
[0109]
Side wall insulating films (spacer layers) 210a and 210b are selectively provided on the gate layer 209 on the side surfaces 205a and 205b of the trench portion 205. Further, a p-type third semiconductor region (SiC layer) 212 is selectively provided as a gate contact region on the bottom surface of the trench portion 205 in the portion of the gate region 209 exposed from the sidewall insulating films 210a and 210b.
[0110]
On the other hand, as shown in FIG. 26, an n-type fourth semiconductor region (SiC layer) 201 is provided as a drain region on the other surface of the n-type high-resistance semiconductor layer 202.
[0111]
A source electrode, a gate electrode, and a drain electrode are provided on the surfaces of the source region 203a, the gate contact region 212, and the drain region, respectively. Further, a source electrode lead wiring 217, a gate electrode lead wiring 218, and a drain electrode lead wiring (not shown) are provided on the source electrode, the gate electrode, and the drain electrode, respectively.
[0112]
As shown in FIG. 25, the source electrode lead-out wiring 217 is composed of an electrode pad portion having a large area and a plurality of striped connection electrode portions that electrically connect the electrode pad portion and each source electrode. And has a comb-like pattern. Similarly, the gate electrode lead-out wiring 218 is also composed of an electrode pad portion having a large area and a plurality of striped connection electrode portions that electrically connect the electrode pad portion and the gate electrode. Has a pattern. These source electrode lead-out wiring 217 and gate electrode lead-out wiring 218 are arranged so as to mesh with each other. Such a structure can be realized by the contact structure shown in FIG.
[0113]
As for the termination region, as shown in FIGS. 25 and 26, a RESURF layer 207 is provided on the surface region of the high-resistance semiconductor layer 202 including the trench structure, and the n-type semiconductor region 203b is provided on the outermost peripheral portion of the substrate. Is provided. A part of the surface of the high-resistance semiconductor layer 202 appears between the RESURF layer 207 and the n-type semiconductor region 203b, and the termination structure is configured by the above components.
[0114]
According to the SIT of the present embodiment described above, the same effect as that of the first embodiment can be obtained, and the effect that the termination region can be formed more easily can be obtained.
[0115]
Although the fourth embodiment has been described as a modification of the first embodiment, the termination structure of the fourth embodiment is also applied to the termination portions of the high voltage semiconductor devices of the second and third embodiments. can do.
[0116]
(Fifth embodiment)
FIG. 27 is a schematic partial cross-sectional view of a high voltage semiconductor device (SIT) according to the fifth embodiment of the present invention.
[0117]
The SIT of the fifth embodiment differs from the SIT of the first embodiment in that the gate layer (p + Layer) 309 is formed on the convex portion, and the source layer 303a is formed on the bottom of the groove. For this reason, since a top view becomes the same as FIG. 2 of 1st Embodiment, it abbreviate | omits and uses FIG.
[0118]
The gate layer 309 is p + The channel is narrowed by the mold buried layer 320. In this case, the channel is n + Type p source layer 303a, adjacent p + N between the mold buried layers 320 and n + A path reaching the type drain layer 301 is formed. When a reverse bias is applied between the gate layer 309 and the source layer 303a, the depletion layer extending from the gate layer 309 narrows the channel.
[0119]
The structural features and effects of the SIT of this embodiment will be described in more detail. As shown in FIG. 27, the n-type high-resistance semiconductor layer (SiC layer) 302 has a low resistance n on one surface (back surface). + A type semiconductor layer 301 is provided as a drain layer. Reference numeral 316 denotes a drain electrode (fourth electrode), and 319 denotes a drain lead wiring.
[0120]
The concentration and thickness of the high-resistance semiconductor layer 302 are determined by the design breakdown voltage. For example, the impurity concentration range is 1 × 10. 14 ~ 1x10 16 cm -3 The thickness range is 5 to 100 μm. The impurity concentration of the drain layer is, for example, 2 × 10 19 cm -3 It is. For example, nitrogen, phosphorus, or arsenic is used as the n-type dopant.
[0121]
Another surface (front surface) of the n-type high-resistance semiconductor layer 302 is a high-concentration p that is short-circuited with the source layer 303a (source electrode (second electrode) 314). + The mold embedding layer 320 is partially formed, and is connected to a termination structure (Resurf layer) 307 in the termination region. This p + The impurity concentration of the mold buried layer 320 is, for example, 2 × 10 18 cm -3 It is. (Third) electrode 315 and p + In order to form an ohmic contact at the contact portion of the mold buried layer 320, for example, 1 × 10 20 cm -3 High concentration p ++ A mold layer is formed. P in the middle region + Although not shown in the figure, the mold buried layer 320 is provided with an opening in the source layer 303a, and the source lead line 17 is connected through a contact or the like of the high concentration layer.
[0122]
p + The convex portion on the upper side of the mold buried layer 320 has a high concentration p in contact with the gate (first) electrode 321. + A mold gate layer 309 is formed. The impurity concentration of the gate layer 309 is, for example, 2 × 10 18 cm -3 It is. The concentration of the n-type layer under the gate layer 309 is, for example, 2 × 10 16 cm -3 It is. In order to form an ohmic contact in the portion of the gate layer 309 that is in direct contact with the gate electrode 321, 1 × 10 20 cm -3 The above high concentration layer (not shown) is formed. As the p-type dopant, for example, Al or boron (B) is used.
[0123]
The concentration of the source layer 301a is 2 × 10, for example. 19 cm -3 The contact portion with the source electrode 314 is 1 × 10 in order to form an ohmic contact 20 cm -3 The above high concentration layer (not shown) is formed.
[0124]
Termination structure (Resurf layer) 307 is p - The low concentration layer of the mold has an impurity concentration of, for example, 3 × 10 17 cm -3 And the depth is 0.6 μm.
[0125]
A feature of this embodiment is that the gate electrode 321 and the source electrode 314 are formed in a self-aligning manner. Therefore, an invalid area for allowing mask displacement is unnecessary, and an increase in resistance value per area caused by the invalid area can be suppressed. Also, the gate electrode 321 has a high concentration p. + Since it is above the mold buried layer 320, the capacitance between the gate and drain is small, and high-speed operation is possible. In addition, in the cascode-connected circuit shown in FIG. 14, if the device 300 of FIG. 27 is used instead of the device 20 with the drain electrode connected to the collector electrode side and the source electrode connected to the emitter electrode side, it is normal from the outside. It can be operated as a normally-off switching element similar to the MOSFET of FIG.
[0126]
(Sixth embodiment)
As shown in FIG. 28, the high voltage semiconductor device of the sixth embodiment is an SI thyristor by changing the semiconductor layer 301 on the back surface of the fifth embodiment (FIG. 27) from n-type to p-type. is there. The top view is the same as FIG.
[0127]
First, structural features and effects of the SI thyristor of the present embodiment will be described. As shown in FIG. 28, one surface (back surface) of the n-type high-resistance semiconductor layer (SiC layer) 302 has a low resistance p. + A type semiconductor layer 301 ′ is provided as a collector layer. Reference numeral 316 denotes a collector electrode (fourth electrode), and 19 'denotes a collector electrode lead line.
[0128]
The concentration and thickness of the high-resistance semiconductor layer 302 are determined by the design breakdown voltage. For example, the impurity concentration range is 1 × 10. 14 ~ 1x10 16 cm -3 The thickness range is 5 to 100 μm. The impurity concentration of the collector layer 301 ′ is, for example, 1 × 10 19 cm -3 It is. For example, nitrogen, phosphorus, or arsenic is used as the n-type dopant.
[0129]
Another surface (front surface) of the high-resistance semiconductor layer 302 is a high-concentration p that is short-circuited with the emitter layer 303a. + The mold embedding layer 320 is partially formed, and is connected to a termination structure (Resurf layer) 307 at the termination portion. This p + The impurity concentration of the mold buried layer 320 is, for example, 2 × 10 18 cm -3 It is. In order to form an ohmic contact at the contact portion between the p + type buried layer 320 and the (third) electrode 315, for example, 1 × 10 20 cm -3 High concentration of p ++ A mold layer is formed. P in the center + Although not shown in the figure, the mold buried layer 320 is provided with an opening in the source layer 303a, and an emitter lead line 17 'is connected through a contact or the like of the high concentration layer.
[0130]
A high concentration p in contact with the gate electrode (first electrode) 321 is formed on the convex portion above the p + type buried layer 320. + A mold gate layer 309 is formed. The impurity concentration of the gate layer 309 is, for example, 2 × 10 18 cm -3 It is. The concentration of the n-type layer under the gate layer 309 is 2 × 10, for example. 16 cm -3 It is. In order to form an ohmic contact in the portion of the gate layer 309 that is in direct contact with the gate electrode 321, 1 × 10 20 cm -3 The above high concentration layer (not shown) is formed. As the p-type dopant, for example, Al or boron (B) is used.
[0131]
The concentration of the emitter layer 301a is, for example, 2 × 10 19 cm -3 The contact portion with the emitter electrode (second electrode) 314 is 1 × 10 in order to form an ohmic contact. 20 cm -3 The above high concentration layer (not shown) is formed.
[0132]
Termination structure (Resurf layer) 307 is p - The low concentration layer of the mold has an impurity concentration of, for example, 3 × 10 17 cm -3 And the depth is 0.6 μm.
[0133]
The feature of this embodiment is that the gate electrode and the emitter electrode are formed in a self-aligning manner. Therefore, an invalid area for allowing mask displacement is unnecessary, and an increase in resistance value per area caused by the invalid area can be suppressed. The gate layer 309 is p + Since it is above the mold buried layer 320, the capacitance between the gate and collector is small, and high-speed operation is possible. In the cascode-connected circuit shown in FIG. 14, if the element of FIG. 28 is used instead of the element 20, it can be externally operated as a normally-off switching element similar to a normal MOSFET.
[0134]
(Seventh embodiment)
FIG. 29 is a partial cross-sectional view of a high voltage semiconductor device (MOSFET) according to the seventh embodiment. The MOSFET of this embodiment has a buried layer structure similar to that of the SIT of the fifth embodiment, and can be easily formed on the same substrate as this SIT.
[0135]
First, structural features and effects of the high breakdown voltage semiconductor switching element of this embodiment will be described. As shown in FIG. 29, the n-type high resistance semiconductor layer (SiC layer) 402 has a low resistance n on one surface (back surface). + A type semiconductor layer 401 is provided as a drain layer. Reference numeral 416 is a drain electrode, and 19 is a drain electrode lead line.
[0136]
The concentration and thickness of the high-resistance semiconductor layer 402 are determined by the design withstand voltage. For example, the impurity concentration range is 1 × 10. 14 ~ 1x10 16 cm -3 The thickness range is 5 to 100 μm. The impurity concentration of the drain layer 401 is, for example, 1 × 10 19 cm -3 It is. As the n-type dopant, for example, nitrogen, phosphorus, or arsenic is used.
[0137]
Another surface (front surface) of the n-type high-resistance semiconductor layer 402 is a high-concentration p that is short-circuited with the source layer 403 (source electrode 414). + A mold embedding layer 420 is partially formed, and is connected to a termination structure (Resurf layer) 407 at a termination portion. This p + The impurity concentration of the mold buried layer 420 is, for example, 2 × 10 18 cm -3 It is. p + In order to form an ohmic contact at the contact portion between the mold embedding layer 420 and the electrode 415, for example, 1 × 10 20 cm -3 High concentration of p ++ A mold layer is formed. P in the center + Although not shown, the mold buried layer 420 is provided with an opening in the source layer 403, and the source lead line 17 is connected through a contact or the like of the high concentration layer.
[0138]
p + The upper portion of the buried type layer 420 is adjacent to the n-type source layer 403 and has a low concentration p. - A mold layer is formed. Low concentration p - A gate electrode 409 made of polysilicon, for example, is formed insulatively on the mold layer. An n-type layer 430 is formed on the opposite side of the gate electrode 409 from the source layer 403, and adjacent p + The n-type region 431 between the mold buried layers 420 is connected.
[0139]
A high concentration p is formed above the n-type region 431. + A mold layer 423 is formed, and adjacent to n by a short-circuit electrode 425 + Shorted to the mold layer 422. The upper electrode 421, the source electrode 414, and the short-circuit electrode 425 of the gate electrode 409 are formed in a self-aligned manner using the sidewall insulating film 410.
[0140]
P under the gate electrode 409 - The concentration of the mold layer is, for example, 1 × 10 17 cm -3 It is. High concentration p + The impurity concentration of the mold layer 423 is, for example, 2 × 10 18 cm -3 However, in order to form an ohmic contact in the portion in direct contact with the short-circuit electrode 425, 1 × 10 20 cm -3 The above high concentration layer is formed. As the p-type dopant, for example, Al or boron (B) is used.
[0141]
The concentration of the n-type source layer 403 is, for example, 2 × 10 19 cm -3 The contact portion between the source layer 403 and the source electrode 414 is 1 × 10 in order to form an ohmic contact. 20 cm -3 The above high concentration layer is formed.
[0142]
The concentration of the n-type layer 430 on the drain side of the gate electrode 409 is 2 × 10, for example. 16 cm -3 N of the portion where the short-circuit electrode 425 contacts + The concentration of the mold layer 422 is 1 × 10 20 cm -3 The above high concentration layer is formed. Termination structure 407 is p - The low concentration layer of the mold has an impurity concentration of, for example, 3 × 10 17 cm -3 And the depth is 0.6 μm.
[0143]
The feature of this embodiment is that the gate electrode 421 and the source electrode 414 are formed in a self-aligned manner, and switching is controlled by a MOS gate. The self-alignment process eliminates the need for an invalid region for allowing mask displacement, and can suppress an increase in resistance value per area caused by the invalid region. Since it is controlled by the MOS gate, it can be operated as a normally-off switching element similar to a normal MOSFET without forming an external circuit.
[0144]
Also, when reverse voltage is applied, the voltage is not the MOSFET part, but p + Mold buried layer 420 and n - Since it is applied to the pn junction formed by the type high-resistance semiconductor layer 402, the breakdown voltage of the MOSFET portion can be lowered and the resistance of the MOSFET can be lowered. A single SiC-MOSFET has a high resistance in the MOSFET portion. By adopting this structure, a low-resistance and high-breakdown-voltage element can be realized.
[0145]
More specifically, when the MOSFET is off (for example, the gate voltage, the source voltage is 0 V, and the drain voltage is 1000 V), the leakage current flows from the drain electrode to the source via the n-type layer or region 401, 402, 431, 430. Flows to the electrode side. At this time, a voltage drop occurs in the n-type regions 431 and 430, and p is 0V. + A reverse bias is applied between the mold embedding layer 420. This allows p + The depletion layer extends from the mold buried layer 420, reaches the depletion layer on the p + layer 423 side, and pinches off the leakage current path. For this reason, the high voltage applied between the drain and the source is applied to the pn junction, and the MOSFET portion is protected from the high voltage.
[0146]
(Eighth embodiment)
As shown in FIG. 30, the high withstand voltage semiconductor device of the eighth embodiment changes the semiconductor layer 401 on the back surface of the seventh embodiment (FIG. 29) from an n-type to a p-type, thereby providing an IGBT (Insulated Gate Bipolar Transistor). ).
[0147]
First, structural features and effects of the high breakdown voltage semiconductor switching element of this embodiment will be described. As shown in FIG. 29, one surface (back surface) of the n-type high resistance semiconductor layer (SiC layer) 402 has a low resistance p. - A type semiconductor layer 401 ′ is provided as a collector layer. Reference numeral 416 is a collector electrode, and 19 'is a collector electrode lead line.
[0148]
The concentration and thickness of the high-resistance semiconductor layer 402 are determined by the design withstand voltage. For example, the impurity concentration range is 1 × 10. 14 ~ 1x10 16 cm -3 The thickness range is 5 to 100 μm. The impurity concentration of the collector layer 401 ′ is 1 × 10, for example. 19 cm -3 It is. For example, nitrogen, phosphorus, or arsenic is used as the n-type dopant.
[0149]
Another surface (front surface) of the n-type high-resistance semiconductor layer 402 is a high-concentration p that is short-circuited with the emitter layer 403 (emitter electrode 414). + A mold embedding layer 420 is partially formed, and is connected to a termination structure (Resurf layer) 407 at a termination portion. This p + The impurity concentration of the mold buried layer 420 is, for example, 2 × 10 18 cm -3 It is. p + In order to form an ohmic contact at the contact portion between the mold embedding layer 420 and the electrode 415, for example, 1 × 10 20 cm -3 High concentration of p ++ A mold layer is formed. P in the center + Although not shown in the figure, the mold buried layer 420 is provided with an opening in the emitter layer 403 and connected to the emitter lead-out line 17 ′ through a contact or the like of the high concentration layer.
[0150]
p + The upper portion of the buried type layer 420 is adjacent to the n-type source layer 403 and has a low concentration p. - A mold layer is formed. Low concentration p - A gate electrode 409 made of polysilicon, for example, is formed insulatively on the mold layer. An n-type layer 430 is formed on the opposite side of the gate electrode 409 from the source layer 403, and adjacent p + The n-type region 431 between the mold buried layers 420 is connected.
[0151]
A high concentration p is formed above the n-type region 431. + A mold layer 423 is formed, and adjacent to n by a short-circuit electrode 425 + Shorted to the mold layer 422. The upper electrode 421, the emitter electrode 414, and the short-circuit electrode 425 of the gate electrode 409 are formed in a self-aligned manner using the sidewall insulating film 410.
[0152]
P under the gate electrode 409 - The concentration of the mold layer is, for example, 1 × 10 17 cm -3 It is. High concentration p + The impurity concentration of the mold layer 423 is, for example, 2 × 10 18 cm -3 However, in order to form an ohmic contact in the portion in direct contact with the short-circuit electrode 425, 1 × 10 20 cm -3 The above high concentration layer is formed. As the p-type dopant, for example, Al or boron (B) is used.
[0153]
The concentration of the n-type emitter layer 403 is, for example, 2 × 10 19 cm -3 The contact portion between the emitter layer 403 and the emitter electrode 414 is 1 × 10 in order to form an ohmic contact. 20 cm -3 The above high concentration layer is formed.
[0154]
The concentration of the n-type layer 430 on the collector side of the gate electrode 409 is 2 × 10, for example. 16 cm -3 N of the portion where the short-circuit electrode 425 contacts + The concentration of the mold layer 422 is 1 × 10 20 cm -3 The above high concentration layer is formed. Termination structure 407 is p - The low concentration layer of the mold has an impurity concentration of, for example, 3 × 10 17 cm -3 And the depth is 0.6 μm.
[0155]
The feature of this embodiment is that the gate electrode and the emitter electrode are formed in a self-aligned manner, and switching is controlled by the MOS gate. The self-alignment process eliminates the need for an invalid region for allowing mask displacement, and can suppress an increase in resistance value per area caused by the invalid region. Since it is controlled by the MOS gate, it can be operated as a normally-off switching element similar to a normal IGBT without forming an external circuit.
[0156]
When applying reverse voltage, the voltage is not the MOSFET part, but p + Mold buried layer 420 and n - Since it is applied to the pn junction formed by the type high-resistance semiconductor layer 402, the breakdown voltage of the MOSFET portion can be lowered and the resistance of the MOSFET can be lowered. A single SiC-IGBT has a high resistance in the MOSFET portion. By adopting this structure, a low-resistance and high-breakdown-voltage element can be realized.
[0157]
More specifically, when the MOSFET is off (for example, the gate voltage, the source voltage is 0 V, and the drain voltage is 1000 V), the leakage current is emitted from the collector electrode through the n-type layer or region 401, 402, 431, 430 to the emitter. Flows to the electrode side. At this time, a voltage drop occurs in the n-type regions 431 and 430, and p is 0V. + A reverse bias is applied between the mold embedding layer 420. This allows p + The depletion layer extends from the mold buried layer 420, reaches the depletion layer on the p + layer 423 side, and pinches off the leakage current path. For this reason, the high voltage applied between the collector and the emitter is applied to the pn junction, and the MOSFET portion is protected from the high voltage.
[0158]
In each of the embodiments described above, the SiC layer is described as an example of the semiconductor layer. However, there are many polymorphs of the SiC crystal form, and it is desirable to use a crystal form called 4H—SiC. In addition, a crystal form called 3C—SiC may be used, and a crystal form called 2H—SiC or 6H—SiC may be used. In addition, although a plane called a (0001) plane is usually used for element formation, other crystal orientation planes such as (112-0) can also be used. Further, the present invention has a great effect particularly when a SiC layer is used as a semiconductor layer, but other semiconductors such as other group IV semiconductors (Si, SiGe, etc.) and group III-V semiconductors (GaAs, GaN, etc.). It can also be applied to. The conductivity type pn may be reversed.
[0159]
In the above embodiment, the RESURF layer is used as the termination structure, but other termination structures such as a guard ring structure may be used. In addition, in the case of SiC, the metal layer for making ohmic contact includes cobalt and aluminum in addition to the above embodiment, and the metal layer for taking Schottky contact is nickel, molybdenum, nickel other than the above embodiment. Examples include silicide, cobalt, cobalt silicide, and gold.
[0160]
Furthermore, in the above embodiment, the high resistance semiconductor layer is provided on the substrate containing one conductivity type impurity at a high concentration. However, the present invention is not limited to this, and one surface conductivity impurity is contained at a high concentration on one surface of the high resistance semiconductor substrate. It is also possible to form the semiconductor layer by ion implantation or epitaxial growth.
[0161]
In addition, various modifications can be made without departing from the spirit of the present invention.
[0162]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, the high voltage | pressure-resistant semiconductor element of the low on-resistance excellent in the switch-off characteristic can be provided with a high yield.
[Brief description of the drawings]
FIG. 1 is a schematic and partial cross-sectional view of a high voltage semiconductor device (SIT) according to a first embodiment of the present invention.
FIG. 2 is a top view of the high voltage semiconductor device according to the first embodiment of the present invention excluding electrodes.
3 is a top view including an electrode of the high voltage semiconductor device according to the first embodiment of the present invention, and FIG. 1 is a cross section taken along line II in FIG. It corresponds to a partial cross-sectional view.
4 is a schematic cross-sectional view showing a contact structure of the semiconductor device according to the first embodiment, and corresponds to a cross section taken along line II in FIG. 3;
FIG. 5 is a cross-sectional view of a stage in the manufacturing process of the high voltage semiconductor device (SIT) according to the first embodiment.
6 is a cross-sectional view showing a stage following FIG. 5. FIG.
7 is a cross-sectional view showing a stage following FIG. 6. FIG.
FIG. 8 is a cross-sectional view showing a stage following FIG.
9 is a cross-sectional view showing a stage following FIG. 8. FIG.
10 is a cross-sectional view showing a stage following FIG. 9. FIG.
FIG. 11 is a cross-sectional view showing a stage following FIG. 10;
12 is a cross-sectional view showing a stage following FIG. 11. FIG.
FIG. 13 is a schematic partial cross-sectional view of a high voltage semiconductor device (SI thyristor) according to a second embodiment.
FIG. 14 is a circuit diagram of a cascode-connected switch circuit using a high voltage semiconductor device according to a second embodiment.
FIG. 15 is a schematic partial cross-sectional view of a high voltage semiconductor device (JBS) according to a third embodiment.
16 is a top view of the high voltage semiconductor device according to the third embodiment, and FIG. 15 corresponds to a partial cross-sectional view from the vicinity of the center of the element to the termination region in the cross section taken along line XV-XV in FIG. 16; To do.
FIG. 17 is a cross-sectional view showing a step in the method for manufacturing a high voltage semiconductor device according to the third embodiment.
FIG. 18 is a cross-sectional view showing the next stage of FIG. 17;
FIG. 19 is a cross-sectional view showing the next stage of FIG. 18;
20 is a cross-sectional view showing the next stage of FIG. 19. FIG.
FIG. 21 is a cross-sectional view showing the next stage of FIG. 20;
22 is a cross-sectional view showing the next stage of FIG. 21. FIG.
FIG. 23 is a cross-sectional view showing the next stage of FIG. 22;
24 is a cross-sectional view showing the next stage of FIG. 23. FIG.
FIG. 25 is a top view showing a configuration of a high voltage semiconductor device (SIT) according to a fourth embodiment.
26 is a partial cross-sectional view from the vicinity of the center of the element to the terminal end in the cross section taken along line XXVI-XXVI in FIG.
FIG. 27 is a schematic partial cross-sectional view showing a configuration of a high voltage semiconductor device (SIT) according to a fifth embodiment.
FIG. 28 is a schematic partial cross-sectional view showing a configuration of a high voltage semiconductor device (SI thyristor) according to a sixth embodiment.
FIG. 29 is a schematic partial cross-sectional view showing a configuration of a high voltage semiconductor device (MOSFET) according to a seventh embodiment.
FIG. 30 is a schematic partial cross-sectional view showing a configuration of a high voltage semiconductor device (IGBT) according to an eighth embodiment.
[Explanation of symbols]
1 ... Drain layer
2 ... n-type high resistance semiconductor layer
3a: n-type first semiconductor layer
3b ... n-type semiconductor layer
4 ... Mask pattern
5, 5 '... trench
5a, 5b, 5c ... Side surfaces of the trench portion
6 ... resist pattern
7 ... RESURF layer
8 ... resist pattern
9: p-type second semiconductor layer (gate layer)
10a, 10b, 10c ... sidewall insulating film
11 ... resist pattern
12 ... Gate contact layer
13 ... Metal pattern
14 ... Source electrode
15 ... Gate electrode
16 ... Drain electrode
17 ... Source extraction electrode wiring
18 ... Gate extraction electrode wiring
19 ... Drain lead electrode wiring
20 ... Insulating film
21 ... MOSFET
22 ... Control gate
23 ... SI Thyristor

Claims (10)

  1. A first conductivity type or second conductivity type SiC substrate having first and second main surfaces;
    A plurality of elongated planar first trenches formed on the first main surface of the SiC substrate and provided in parallel with each other, and the plurality of first trenches communicated at both longitudinal ends thereof; The first conductive type high-resistance SiC having a resistance higher than that of the SiC substrate, surrounding the plurality of first trenches from the outside, having a second trench wider than the first trench in a surface region thereof. Layers,
    First conductivity provided on the high-resistance SiC layer at a concentration higher than the impurity concentration of the high-resistance SiC layer and sandwiched between adjacent trenches among the plurality of first trenches and second trenches. A plurality of first SiC regions of the mold;
    The side walls and bottom of each of the plurality of first trenches and the bottom corners of the first trench provided continuously on a part of the side walls and bottom of the second trench on the first SiC region side. And a second SiC region of the second conductivity type formed so as to bulge toward the high-resistance SiC layer at the bottom corner of the second trench on the first trench side,
    A sidewall insulating film provided on the second SiC region of the sidewall of each of the plurality of first trenches and the sidewall of the second trench on the first SiC region side;
    Provided in a surface region of the second SiC region at the bottom of the plurality of first trenches and a part of the bottom of the second trench on the first SiC region side; A third SiC region of the second conductivity type having an impurity concentration higher than the impurity concentration;
    A first electrode comprising a metal silicide layer formed on the upper surface of each of the plurality of first SiC regions sandwiched between the plurality of first trenches;
    A second electrode made of a metal silicide layer filling each of the plurality of first and second trenches and in contact with the third SiC region;
    A third electrode formed on the second main surface of the SiC substrate;
    A high breakdown voltage semiconductor device comprising:
  2.   The third SiC region is exposed from the sidewall insulating film formed on the sidewall of each of the plurality of first trenches, and the bottom portion of each of the plurality of first trenches and the second The high breakdown voltage semiconductor device according to claim 1, wherein the high breakdown voltage semiconductor device is formed on the second SiC region at a part of the bottom portion of the trench on the first SiC region side.
  3. A first conductivity type SiC substrate having first and second main surfaces;
    A plurality of elongated planar first trenches formed on the first main surface of the SiC substrate and provided in parallel with each other, and the plurality of first trenches communicated at both longitudinal ends thereof; And a high-resistance SiC layer of a first conductivity type that surrounds the plurality of first trenches from the outside, has a second trench wider than the first trench, and has a higher resistance than the SiC substrate;
    Formed on a surface region of the high-resistance SiC layer sandwiched between adjacent ones of the plurality of first trenches and the second trench, and a Schottky junction with the surface region of the high-resistance SiC layer A first electrode comprising a metal silicide layer formed;
    The plurality of first trenches and the second trenches are continuously provided on a part of the side wall and the bottom part on the first trench side, and the bottom corners of the first trenches and the second trenches are provided. A first SiC region of a second conductivity type formed so as to swell toward the high-resistance SiC layer at a bottom corner on the first trench side;
    A sidewall insulating film provided on the first SiC region of the sidewall of each of the plurality of first trenches and the first trench side sidewall of the second trench;
    Provided in the surface region of the first SiC region at the bottom of each of the plurality of first trenches and the bottom of the second trench, and having an impurity concentration higher than the impurity concentration of the first SiC region. A second conductivity type second SiC region having;
    A control electrode comprising a metal silicide layer embedded in each of the plurality of first trenches and the second trench to contact the second SiC region and connected to the first electrode;
    A second electrode formed on the second main surface of the SiC substrate;
    A high breakdown voltage semiconductor device comprising:
  4. According to claim 3, wherein the portion of the Schottky junction of the first electrode is surrounded by said first trench side surface of said plurality of first trenches and said second trench High voltage semiconductor device.
  5. The second SiC region is formed at the bottom of each of the plurality of first trenches so as to be exposed from the sidewall insulating film formed on the sidewall of each of the plurality of first trenches. The high breakdown voltage semiconductor device according to claim 3 , wherein the high breakdown voltage semiconductor device is formed at a part of a bottom portion of the second trench.
  6. A first conductivity type or second conductivity type SiC substrate having first and second main surfaces;
    A plurality of elongated planar-shaped first trenches formed on the first main surface of the SiC substrate and provided in parallel with each other, and the plurality of first trenches communicated at both longitudinal ends thereof; and A first conductivity type high-resistance SiC layer that surrounds the plurality of first trenches from the outside, has a second trench wider than the first trench, and has a higher resistance than the SiC substrate;
    The high-resistance SiC layer has an impurity concentration higher than that of the high-resistance SiC layer, and is sandwiched between adjacent trenches among the plurality of first trenches and the second trench, and is formed on the surface of the high-resistance SiC layer. A plurality of first SiC regions of the second conductivity type formed;
    The high-resistance SiC layer has an impurity concentration higher than that of the high-resistance SiC layer, and is provided at least at the bottom of each of the plurality of first trenches and at the bottom of the second trench on the first trench side. A second SiC region of one conductivity type;
    A sidewall insulating film provided on the sidewall of each of the plurality of first trenches and the sidewall of the second trench on the first trench side;
    The first SiC region is embedded in the high-resistance SiC layer, a part of the upper surface thereof is in contact with the lower surface of the second SiC region, and extends horizontally under the adjacent first SiC region. And a portion extending to the second trench has a second conductivity type third SiC region terminating in the second trench outside the second SiC region;
    A first electrode comprising a metal silicide layer formed on each of the plurality of first SiC regions;
    A second electrode comprising a metal silicide layer formed on the second SiC region at the bottom of the first and second trenches;
    A third electrode connected to the third SiC region through a contact hole formed in the second SiC region;
    A fourth electrode formed on the second main surface of the SiC substrate;
    A high breakdown voltage semiconductor device comprising:
  7.   7. The high voltage semiconductor device according to claim 1, wherein when the SiC substrate is of a first conductivity type, an SIT is formed, and when the SiC substrate is of a second conductivity type, an SI thyristor is formed.
  8. High-voltage semiconductor device according to claim 1, 3, 6, characterized in that the electric field relaxation layer is provided in the end region of the high voltage apparatus which surrounds the first electrode.
  9. On one surface of the SiC substrate of a first conductivity type, a first step of forming a high-resistance SiC layer of the first conductivity type high-resistance than the substrate,
    Subsequent to the first step, a second step of forming a first conductivity type first SiC layer having a lower resistance than the high resistance SiC layer on the surface of the high resistance SiC layer;
    Subsequent to the second step, a plurality of first trenches extending from the surface of the first SiC layer to the high-resistance SiC layer and a second trench wider than the first trench surrounding the first trench are formed . And the process of
    Subsequent to the third step, the side surface and the bottom surface of the first trench, the side surface and the bottom surface of the second trench on the first trench side, toward the high resistance SiC layer at the bottom corner portion. A fourth step of forming the second conductivity type second SiC layer so as to swell by multi-stage ion implantation;
    Subsequent to the fourth step, a fifth step of forming an insulating layer pattern on the second SiC layer on the side surfaces of the first and second trenches;
    Subsequent to the fifth step, a sixth step of forming a third conductivity type third SiC layer having a lower resistance than that of the second SiC layer on the second SiC layer exposed from the insulating layer pattern. When,
    Subsequent to the sixth step, after forming the third SiC layer, a metal film is formed and heated on the entire surface of the substrate, and the first SiC layer sandwiched between the first and second trenches and the A seventh step of forming a metal silicide layer on the surface of the third SiC layer;
    Subsequent to the seventh step, the metal film is selectively removed by etching, and a source electrode and a gate electrode made of the metal silicide layer are provided on the surfaces of the first SiC layer and the third SiC layer . 8 processes,
    Subsequent to the eighth step, a ninth step of forming a drain electrode on the other surface of the SiC substrate;
    A method of manufacturing a high voltage semiconductor device, comprising:
  10. On one surface of the SiC substrate of a first conductivity type, a first step of forming a high-resistance SiC layer of the first conductivity type high-resistance than the substrate,
    Subsequent to the first step, a second step of forming a plurality of first trenches and a second trench wider than the first trench surrounding the first trench in the high-resistance SiC layer;
    Continuing on from the second step, the side surface and bottom surface of the first trench, the side surface and bottom surface of the second trench on the first trench side, toward the high resistance SiC layer at the corner of the bottom surface. A third step of forming the first conductivity type first SiC layer so as to swell by multi-stage ion implantation;
    Subsequent to the third step, a fourth step of forming an insulating layer pattern on the first SiC layer on the side surfaces of the first and second trenches;
    Subsequent to the fourth step, a fifth step of forming a second conductivity type second SiC layer having a lower resistance than the first SiC layer on the first SiC layer exposed from the insulating layer pattern. When,
    Following the fifth step, after forming the second SiC layer, a metal film is formed and heated on the entire surface of the substrate, and the surface of the high-resistance SiC layer sandwiched between the first and second trenches And a sixth step of forming a metal silicide layer on the surface of the second SiC layer;
    Subsequent to the sixth step, the metal film is selectively etched away, the first electrode forming a Schottky junction with the surface of the high-resistance SiC layer, and the metal silicide on the surface of the second SiC layer. A seventh step of forming a control electrode comprising a layer and electrically connected to the first electrode;
    Subsequent to the seventh step, an eighth step of forming a second electrode on the other surface of the SiC substrate;
    A method of manufacturing a high voltage semiconductor device , comprising:
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