JP4151710B2 - Code conversion method - Google Patents

Description

  The present invention relates to a fixed length conversion code used in a recording / reproducing apparatus such as a hard disk drive for a computer, a data cartridge drive for a computer, a magneto-optical recording / reproducing apparatus such as a magneto-optical disk drive, and various communication apparatuses. The present invention relates to the code conversion method.

  A DC-free code is conventionally used as one of fixed length conversion codes represented as m / n codes, where m is the data word length and n is the code word length. It is generally known that the DC-free code is a very effective code because it can reduce noise in the low frequency band of the system in coding and modulation of a digital transmission signal.

  Such a DC-free code is a code spectrum on the frequency axis by limiting DSV (Digital Sum Value), that is, the amplitude value of DC accumulated charge (Running Digital Sum, hereinafter referred to as RDS) of a code sequence in a finite manner. This is a code designed such that the DC component of is null. As DC-free codes, 8/9 conversion, 8/10 conversion, and the like have been put into practical use so far. Here, the maximum run length of these DC-free codes, that is, the maximum number of continuous data '0' before NRZI modulation is 12 for 8/9 conversion and 2 for 8/10 conversion in the minimum case. In the minimum case, the DSV value is 25 for 8/9 conversion and 5 for 8/10 conversion.

  For example, in a tape-based magnetic recording / reproducing system that performs azimuth recording, even if an equalization method for suppressing a DC component of a signal spectrum such as partial response class 4 equalization is used, without using a DC-free code, It is difficult to sufficiently suppress the crosstalk noise.

  For this reason, in many conventional tape storage systems such as a digital audio tape recorder (R-DAT) digital data storage system (DDS) and an 8 mm advanced intelligent tape system (AIT), the DSV is 6, and the maximum run length is. 8/10 conversion DC-free codes, each of which is limited to 3, are widely used.

  FIG. 36 shows an example of a block diagram for digital signal processing of a general recording / reproducing apparatus. The input data is a code converted by the m / n conversion encoder 101 into a ratio of m: n. Here, m is the data bit length before encoding, and n is the data bit length after encoding. The code output from the m / n conversion encoder 101 is converted into a recording rectangular wave by the D / A converter 102 and supplied to the recording / reproducing circuit 103. The recording / reproducing circuit 103 drives a magnetic head or an optical pickup (not shown) to perform recording on a recording medium (not shown) such as a magnetic disk or a magneto-optical disk.

  On the other hand, a reproduction wave reproduced from a recording medium by a magnetic head or an optical pickup is equalized to a predetermined target equalization characteristic by an analog equalizer 104 and then converted into a digital signal by an A / D converter 105. Is done. After the code is detected by the code detector 106, the output data is converted by the n / m conversion decoder 107 at a ratio of n: m. Here, when equalization by the analog equalizer 104 is not sufficient, a digital equalizer may be provided between the A / D converter 105 and the code detector 106. In recent years, in order to reduce the error rate, a partial response equalization method or a decision feedback equalization method is used for equalization, and a maximum likelihood detector is often used as the code detector 106.

  In code, if the code performance such as DSV and maximum / minimum run length is equivalent, the higher the coding efficiency m / n, the higher the signal-to-noise ratio (SNR) of the recording system, reproduction system, transmission system, etc. It is generally well known that it is effective for improvement. For example, the code conversion with the highest coding efficiency capable of code conversion in units of 1 byte (8 bits) is the 8/9 conversion, and the 8/9 conversion DC-free code has been studied by Yoshida et al. (H. Yoshida, T. Shimada, Y. Hashimoto, "8-9 Block Code: A DC-Free Channel Code for Digital Magnetic Recording," SMPTE Journal, pp. 918-922. Sep. 1983) .

  However, although the 8/9 conversion has higher encoding efficiency than the 8/10 conversion, the performance of DSV, maximum run length, and the like is significantly inferior to the 8/10 conversion. Further, when combining the maximum likelihood detection method based on partial response class 1 equalization and a DC-free code, it is desirable that the number of consecutive data '1' in the code is finite, but in the 8/9 code, 9 Since it is necessary to use a bit '1' continuous code (511 decimal), there is a problem that it is difficult to impose restrictions on the number of continuous data '1'.

Further, if it is possible to create an 8/9 converted DC-free code, it is expected that the performance of the DSV and the maximum run length can be improved by configuring the 16/18 converted DC-free code. However, there has been a problem that there has been no example in which the configuration of the 16/18 conversion DC-free code has been specifically studied so far. The problem is that 8/9 conversion requires 8 bits, that is, 2 ⁸ = 256 words of code conversion, whereas 16/18 conversion has 16 bits, that is, 256 times 2 ¹⁶ = 65536. Since encoding for words is necessary, the encoding circuit becomes complicated, which is considered to be difficult to put into practical use at low cost.

  As an example of actually performing 16-bit conversion, as disclosed in US Pat. No. 5,635,933, a 16/17 conversion code is obtained by performing two 8/8 conversions and adding one bit. There is an example in which code conversion is simplified. However, this code conversion method achieves such simplification because the 16/17 conversion is a code to which only a simple run length restriction is added. Therefore, even if a method similar to the code conversion method according to the 16/18 conversion DC-free code with limited DSV is applied, it is difficult to greatly simplify the code conversion. In addition, since the two 8/8 conversions in the code conversion method are not completely independent code conversions, the number of necessary code words is not smaller than 65536 words.

As an example in which the number of necessary conversion codewords is actually reduced, a code division method (A. Widmer and P. Franaszec, “A DC-Balanced, Partitioned-Block, 8B / 10B Transmission code,” IBMJ.Res .Develop., Vol.27, No.5, Sep.1983). The feature of this code division method is that the number of states at the start and end points of the code is 2, and the 8/10 conversion DC-free code is code-divided into two completely independent 3/4 conversion and 5/6 conversion, The required number of conversion codewords was reduced from 256 words to 2 ³ +2 ⁵ = 40 words (thus about 84%).

  However, according to a report by Widmer et al., A code configuration with a maximum run length of 2 and a coding efficiency of 0.8 can be made when DSV = 10 is allowed when the number of code start and end states is 3. The point is only mentioned. This is because according to such a code, the complexity of the code conversion is remarkably increased and is not practical. For this reason, the examination of the more concrete code | symbol and the simplification method of the code conversion apparatus which performs code conversion in case the number of states is 3 are not performed at all.

  Further, there is a problem that there is no example in which such a code division method is specifically studied for codes other than the 8/10 conversion DC-free code. Furthermore, only the above-described code division method has been proposed as a method for substantially reducing the number of necessary conversion codewords.

  Therefore, the object of the present invention is to provide the necessary number of conversion codewords for codes other than 8/10 conversion DC-free codes, particularly for code 8/9 conversion with higher encoding efficiency or conversion code having equivalent encoding efficiency. The object is to provide a code conversion method for reduction.

According to the first aspect of the present invention, there are three possible states of the code at the start and end points of the code, that is, three states of RDS = 0, plus / minus 2, and minus / plus 2 expressed in the state before NRZI modulation. In a code conversion method of a DC free code,
Without using “codeword that can start only from RDS = 0”,
“Codeword that can start from all states of RDS = 0, plus / minus 2, and minus / plus 2”, “Codeword that can start from two states of RDS = 0, plus / minus 2” ”,“ Codeword that can start from two states, RDS = 0, minus plus 2 ”,“ codeword that can only start from RDS = plus or minus 2 ”, and“ RDS = minus ” By using only the five types of codewords “codewords that can start only with plus 2”, the number of code selection states is 3 and the type of code selection required is the head of some codes. The code conversion method is characterized in that it is reduced to two types that can be configured only by bit inversion.

  According to the invention as described above, in the code conversion method of the three-state code, the number of code selection states is three, and the necessary code selection types are configured only by inversion of the leading bits of some codes. Can be reduced to two possible types.

  Also, the code conversion method according to the present invention makes it possible to substantially reduce the number of necessary conversion codewords to ½, and when the code conversion method is combined with the code division method, it is divided. In addition, in at least one type of code, it is possible to eliminate both the dedicated encoding circuit and the decoding circuit.

In the code conversion method of the three-state code according to the present invention, the number of necessary code selections is two types that can be configured only by reversing the first bit of the code while the number of code selection states is three. Can be reduced.

  Further, when the code division method according to the present invention and the duplicate code conversion method according to the present invention are combined, in at least one of the divided codes, both the dedicated encoding circuit and the decoding circuit are provided. It can be made unnecessary.

  As a result of the effects as described above according to the present invention, for example, in a magnetic recording system or the like, it is possible to record / reproduce a signal at a recording density higher than that at a low cost, and its industrial value is extremely high. Big.

  Hereinafter, a code division method and a code conversion method according to the present invention will be described with specific embodiments. The description will be made in the order of the code division method according to the present invention, then the code conversion method according to the present invention, and the combination of the code conversion method according to the present invention and the code conversion method according to the present invention.

First, a general theory about the code division method will be described below. This theory can be applied to any code, not just DC-free codes. When dividing an m / n conversion code into a plurality of independent conversion codes, it is impossible for the number of output bits of the divided code to be equal to or less than the number of input bits. The number is nm. Therefore, when the m / n conversion code is divided into W m _x / n _x conversions (W is equal to or smaller than (n−m)), all m _x / n _x conversions are independent code conversions. in order, when the total code word length of n _x bit length according to the state transition diagram for generating said code was P (n _x), for all x, the following equation (1) may be Naritate.

  However, n and m satisfy the following conditions.

  Further, the total number of code words N required at this time is calculated by the following equation.

Therefore, for example, in order to minimize N when W = ₂ , each value of n ₁ , n ₂ , m ₁ , and m ₂ may be selected so that (m ₂ −m ₁ ) is minimized.

In the case of a 16/18 conversion code, since nm = 2, all combinations of (m ₁ / n ₁ , m ₂ / n ₂ ) conversions that may satisfy the above-described code division condition are (1/2, 15/16), (2/3, 14/15), (4/5, 12/13), (5/6, 11/12), (6/7, 10/11), There are 8 types (7/8, 9/10) and (8/9, 8/9). These combinations are not limited to DC-free codes, but are common for 16/18 conversion codes.

  In the conventional code-divided 8/10 conversion DC-free code, DSV = 6 and the number of states at the start point and end point of the codeword is two. On the other hand, here, the applicability of the code division method to the 16/18 conversion DC-free code in the case where the DSV is 8 or more and the number of states of the start point / end point of the code word is 3 or more is examined. View.

  FIG. 1 shows an example of a 12-state state transition diagram for explaining the configuration of codes used in the present invention. This state transition diagram is based on NRZI modulation and DSV is 12. In FIG. 1, when it is desired to set the DSV of the code to 8, the states 9, 10, 11, and 12 may be deleted. If the DSV of the code is desired to be 10, the states 11 and 12 may be deleted. However, the state number assignment method is not limited to that shown in FIG. It is also clear that the code according to the present invention can be configured on the assumption of NRZ modulation. Further, in the following description, the RDS in the state 4 is expressed as plus / minus 2, and the RDS in the state 5 is expressed as minus / plus 2.

FIG. 2 shows the results of examining the feasibility of all combinations of two-divided 16/18 codes in which DSV = 8 and the number of states at the start and end points of the codeword is 3. However, when n ₁ and n ₂ are even numbers, the states of the start point and end point of the code word are states 1, 4, and 5, respectively. When n ₁ and n ₂ are odd numbers, for m ₁ / n ₁ conversion, the start point of the code word is set to states 1, 4, 5 and the end point is set to states 2, 3, 6 and m ₂ / For n ₂ conversion, the start point of the code word is set to states 2, 3, and 6, and the end point is set to states 1, 4, and 5. For each such combination, the number of codewords P (n ₁ ) and P (n ₂ ) that can be generated was examined. In this case, each start point / end point is selected so that the number of codewords that can be generated is maximized when the number of codepoint start / end points is three.

In FIG. 2, “◯” indicates that the code conversion is possible, and “X” indicates that the code conversion is impossible. However, in order for code division to be possible, the code conversion must be possible for both (m ₁ / n ₁ , m ₂ / n ₂ ) conversion. From FIG. 2, when DSV = 8 and the number of states at the start and end points of the codeword is 3, the configuration of 16/18 conversion that can be divided into two is only (7/8, 9/10) conversion. I know that there is.

Next, FIG. 3 shows the result of examining the feasibility of all combinations of two-divided 16/18 conversion DC-free codes in which DSV = 10 and the number of states at the start and end points of the codeword is 3. It is. Here, the calculation conditions of P (n ₁ ) and P (n ₂ ) are the same as the calculation when creating FIG. Also in FIG. 3, symbols “◯” and “x” are assigned to indicate whether each code conversion is possible or not. From FIG. 3, when DSV = 10 and the number of states at the start and end points of the codeword is 3, the configuration of 16/18 conversion that can be divided into two is (4/5, 12/13), (5 / 6, 11/12) and (7/8, 9/10) conversion. Among these, (7/8, 9/10) conversion requires the least number of conversion codes.

Next, FIG. 4 shows the result of examining the feasibility of all combinations of two-divided 16/18 conversion DC-free codes with DSV = 12, and the number of states of the codeword start and end points is 3. It is. Here, the calculation conditions of P (n ₁ ) and P (n ₂ ) are the same as the calculation when creating FIG. Also in FIG. 4, symbols “◯” and “x” are assigned to indicate whether each code conversion is possible or not. From FIG. 4, when DSV = 12 and the number of states at the start and end points of the codeword is 3, the configuration of 16/18 conversion that can be divided into two is (2/3, 14/15), (3 / 4, 13/14), (4/5, 12/13), (5/6, 11/12), and (7/8, 9/10) conversion. Among these, (7/8, 9/10) conversion requires the least number of conversion codes.

Further, in the case where the number of states of the start point / end point of the code word is 4, the following will be examined in the same manner. FIG. 5 shows the results of examining the feasibility of all combinations of two-divided 16/18 conversion DC-free codes in which DSV = 8 and the number of states at the start and end points of the codeword is four. However, when n ₁ and n ₂ are even numbers, the states of the start point and the end point of the code word are states 2, 3, 6, and 7, respectively. When n ₁ and n ₂ are odd numbers, for m ₁ / n ₁ conversion, the start point of the code word is set to states 1, 4, 5, 8 and the end point is set to states 2, 3, 6, 7 , M ₂ / n ₂ conversion, the start point of the code word is set to states 2, 3, 6, and 7, and the end point is set to states 1, 4, 5, and 8. For each such combination, the number of codewords P (n ₁ ) and P (n ₂ ) that can be generated was examined. In this case, each start point / end point is selected so that the number of codewords that can be generated is maximized when the number of codepoint start / end points is three.

  From FIG. 5, it is impossible to code-divide a 16/18 conversion DC-free code into two independent conversion codes with a DSV = 8 and a code having four states as start and end points. However, in this case, the configuration of the 16/18 conversion code itself can be DSV = 8, and the number of code words usable at this time is 76875. A direct 16/18 conversion DC-free code can be constructed by selecting an appropriate 65536 codewords.

Next, FIG. 6 shows the result of examining the feasibility of all combinations of two-divided 16/18 conversion DC-free codes in which DSV = 10 and the number of states at the start and end points of the codeword is 4. It is. Here, the calculation conditions of P (n ₁ ) and P (n ₂ ) are the same as the calculation when creating FIG. From FIG. 6, when DSV = 10 and the number of states at the start and end points of the codeword is 3, the configuration of 16/18 conversion that can be divided into two is (5/6, 11/12), (7 / 8, 9/10) It can be seen that there are two types of conversion. Among these, (7/8, 9/10) conversion requires the least number of conversion codes.

Next, FIG. 7 shows the result of examining the feasibility of all combinations of two-divided 16/18 conversion DC-free codes with DSV = 12, and the number of states of the start and end points of the codeword is 4. It is. Here, the calculation conditions of P (n ₁ ) and P (n ₂ ) are the same as the calculation when creating FIG. From FIG. 7, when DSV = 12 and the number of states of the start point / end point of the codeword is 4, the configuration of 16/18 conversion that can be divided into two is (1/2, 15/16), (2 / 3, 14/15) (3/4, 13/14), (4/5, 12/13), (5/6, 11/12), (7/8, 9/10) 6 types of conversion It can be seen that it is. Among these, (7/8, 9/10) conversion requires the least number of conversion codes.

  However, if the DSV is 14 or more, (6/7, 10/11) code division is also possible. From the above description with reference to FIG. 2 to FIG. 7, the configuration of the two-divided 16/18 conversion DC-free code that requires the least number of conversion codewords when the DSV is any value between 8 and 12, (7/8, 9/10) conversion.

  Even if the DSV value is set to 13 or more, when the RDS of the code is integrated in 1-bit cell units as shown in FIG. 1, the 16/18 conversion DC-free code can be divided into (8/9, 8/9) conversion. Impossible. However, if the RDS of the code is integrated in units of 1/2 bit cells and the DSV of the code is 25 or more, the above-described 8/9 conversion DC-free code with 16 codeword start / end state numbers Configuration is possible.

  That is, the code division method according to the present invention uses 16 independent transform codes that alternately use two DC-free codes having a DSV of 8 or more in FIG. It is characterized by being converted to 18. The code division method according to the present invention can be applied to a DC-free code having a DSV of 8 or more. Hereinafter, in the case where DSV = 8 and the 16/18 conversion DC-free code is composed of two independent 7/8 conversion DC-free codes and 9/10 conversion DC-free codes, the code division method according to the present invention will be described. An applied embodiment of the present invention will be described. FIG. 8 is a diagram illustrating the configuration of the 16/18 conversion DC-free code in such a case using a trellis diagram showing RDS transition. Here, the white and black squares indicate the sign polarity, respectively, and follow a very general display method of this type of trellis diagram.

  9 to 20, all codewords that satisfy the state transition diagram when DSV = 8 by deleting states 9, 10, 11, and 12 in FIG. 1 are shown in decimal numbers. These codewords can be used for the 16/18 conversion of one embodiment of the present invention. Here, FIG. 9 shows 162 10-bit codewords that can start from all states 1, 4, and 5. FIG. 10 shows 234 10-bit codewords that can start from the two states 1, 4. FIG. 11 shows 234 10-bit codewords that can start from two states 1 and 5. FIG. 12 shows 20 10-bit codewords that can start from state 1 only.

  FIG. 13 shows 129 10-bit codewords that can start from state 4 only. FIG. 14 shows 129 10-bit codewords that can start from state 5 only. FIG. 15 shows 54 8-bit codewords that can start from all states 1, 4, and 5. FIG. 16 shows 62 8-bit codewords that can start from two states 1 and 4. FIG. 17 shows 62 8-bit codewords that can start from two states 1 and 5. FIG. 18 shows two 8-bit codewords that can start from state 1 only. FIG. 19 shows 29 8-bit codewords that can start from state 4 only. FIG. 20 shows 29 8-bit codewords that can start from state 5 only.

  However, in the code used in the present invention, since the number of states is 3, there are three types of codewords to be selected at the time of code conversion, which have been put into practical use, for example, in the conventional DAT (Digital Audio Tape). There is a problem that it becomes larger than the two types (two states) in the / 10 conversion code. As a result of intensive investigations on this problem, the present inventor has found the following solution. That is, among the codewords shown in FIGS. 9 to 20, do not use the “codeword that can start only from state 1” shown in FIGS. 12 and 18 at the time of code conversion. By doing so, at the time of code conversion, the number of codewords to be actually selected can be reduced to two while the number of states to be selected is three.

  That is, the code conversion method according to the embodiment of the present invention does not use “a codeword that can start from only state 1 (RDS = 0)”, but “states 1, 4, 5 (RDS = 0). , Plus / minus 2, plus / minus 2) codewords that can start from all states ”,“ states 1 and 4 (RDS = 0, plus / minus 2) can start from two states ” "Codeword that can start from two states 1 and 5 (RDS = 0, minus plus 2)" and "State 4 only (RDS = plus or minus 2)" Only 5 types of codewords are used, “a codeword that can be started only from state 5 (RDS = minus plus 2)”.

  As can be seen from FIGS. 9 to 20, the number of code words that can start from state 1 is larger than the number of code words that can start from state 4 or 5. For this reason, even if a code word that can start only from state 1 is removed from the used code, only an excess of code words that can start from state 1 is removed. Therefore, the number of codewords that can be finally used is 145 for the 7/8 conversion and 525 for the 9/10 conversion, and the number does not decrease. It never happens.

  However, when most of the code conversion is simplified by such an encoding method, for example, a code word that can start from only state 1 is also used for some codes such as a synchronization signal code. However, the complexity of the entire code conversion is not greatly increased. Therefore, it is obvious that such an encoding method is included in the technical scope of the present invention.

  Further, by classifying in this way, “a code word that can start from two states of states 1, 4 (RDS = 0, plus / minus 2)” and “state 4 (RDS = plus / minus 2)”. “A codeword that can start only from two states” is “a codeword that can start from two states of states 1 and 5 (RDS = 0, minus plus 2)” and “state 5”, respectively. Since it is possible to construct the codeword only by reversing the leading bits of “0”-“1” of a “codeword that can start only from (RDS = minus plus 2)”, the code conversion is remarkably easy.

  Next, the configuration of a 16/18 conversion encoder that realizes encoding by the 16/18 conversion method according to an embodiment of the present invention will be described with reference to FIG. Input data is input as 16-bit parallel data. Of these, the first 7 bits abcdefg are input to the 7/8 encoding circuit 10 and encoded into an 8-bit code ABCDEFGH. Further, the latter 9 bits hijklmnop are input to the 9/10 encoding circuit 11 and encoded into a 10-bit code IJKLMNOPQR. Here, the first half 7 bits and the latter half 9 bits of the 16-bit parallel data are input to the 7/8 encoding circuit 10 and the 9/10 encoding circuit 11, respectively. It may be configured such that it is input to the 7/8 encoding circuit 10 and the other 9 bits are input to the 9/10 encoding circuit 11.

  The 8-bit code output from the 7/8 encoding circuit 10 is supplied to a subsequent signal processing system that performs processing such as generating a recording signal for recording on an information recording medium such as a magnetic tape, and is also 8-bit code. Is supplied to the use state determination circuit 12. The 8-bit state determination circuit 12 generates a 2-bit code X′Y ′ representing any of the three states at the code end point for the supplied 8-bit code, and supplies the 2-bit code X′Y ′ to the 9/10 encoding circuit 11.

  On the other hand, the 10-bit code output from the 9/10 encoding circuit 11 is also supplied to the subsequent signal processing system and also supplied to the 10-bit state determination circuit 13. The 10-bit state determination circuit 13 generates a 2-bit code XY representing any of the three states at the code end point for the supplied 10-bit code, and supplies the 2-bit code XY to the 8/9 encoding circuit 10. The 7/8 encoding circuit 10 and the 9/10 encoding circuit 11 perform appropriate encoding with reference to the 2-bit codes XY and X′Y ′. As described above, the 16/18 conversion encoding method is realized.

  Next, the configuration of a decoder that decodes the code generated by the above-described encoding method will be described with reference to FIG. Such a code is input as 18-bit parallel data. Of these, the first half 8-bit ABCDEFGH is input to the 8/7 decoding circuit 20 and decoded into 7-bit data abcdefg, and the second half 10-bit IJKLMNOPQR is input to the 10/9 decoding circuit 21 to generate 9-bit data. Decoded to hijklmnop. In this way, the 18-bit code is decoded into 16-bit data. However, the 8 bits and 10 bits input to the 8/7 decoding circuit 20 and the 10/9 decoding circuit 21 need only correspond to the configuration of the 16/18 encoding circuit, and are not necessarily included in the 18-bit parallel data. It does not have to be in order.

  Next, a code conversion method other than the code division method (a code conversion method expressed as a duplicate code conversion method as will be described later) will be described. As a result of intensive studies on a new encoding method that simplifies code conversion other than the above-described code division method, the present inventor has found that an integer α that takes a value of 2 or more for an m / n conversion code (m− It has been found that the number of necessary code words can be substantially reduced to a maximum of 50% by performing code conversion of (α) / (n−α) conversion code in advance. More specifically, after the code conversion of the (m−α) / (n−α) conversion code is performed in advance on α having a value of 2 or more, two or more types of α bit codes are converted into (n−α) bits. It is a method of generating an n-bit code by connecting to a code. The number of codes substantially reduced by using such an encoding method will be described below. However, the following description is applicable not only to a DC-free code but also to any code.

In the case of m <n, m / n> (m−α) / (n−α) always holds. That is, the coding rate of the m / n conversion code is always higher than the coding rate of the (m−α) / (n−α) conversion code. For this reason, in many cases, if the configuration of the m / n conversion code is possible, the configuration of the (m−α) / (n−α) conversion code is possible. In this case, if ε is the number of α-bit codes that can be connected to the end points of all (n−α) bit codes, that is, the start point state that the code can take even when connected to the code end points is ε, substantially. The required number of conversion codewords N _eff is as follows.

但し、Ｔは以下のようになる。

However, T is as follows.

That is, the required number of conversion codewords is T times as compared with the number of conversion codewords N = 2 ^m required when the m / n conversion code is directly performed. Therefore, if ε> 1, T <1, so that the number of necessary conversion codewords can be surely reduced.

Here, in the case of a code based on the NRZI modulation in accordance with the state transition diagram (DSV = 12) in FIG. 1, for example, when α = 2, the maximum value of ε is 3, so that N _eff / N (ie, The minimum value of T) described above can be calculated as 0.5 by substituting α = 2 and ε = 3 into Equation (6). Furthermore, since the maximum values of ε are 9, 30, and 105 for α = 4, 6, and 8, respectively, the minimum values of N _eff / N are 0.5, 0.5, 0.547, and 0, respectively. .598. Also, when DSV = 8 and the number of states at the start and end points of the code is 3, the possible values of ε when α = 2, 4, 6, and 8 are 3, 9, 27, and 81, respectively. . The minimum value of N _eff / N, ie, to obtain N _eff / N = 1/2 may be an alpha = 2 or alpha = 4.

  For example, in an n-bit DC-free code premised on NRZI modulation, when α = 2, the following condition satisfying ε = 3 is satisfied from the state transition diagram of FIG. 1 or the trellis diagram of FIG. Each law can be confirmed.

[2-bit code connection law 1 for n-2 bit code]
In all n-2 bit codes, even if a 2-bit code '11' is connected to the end point, the state of the code end point does not change, and the start point state that the code can take does not change. For example, when a 2-bit code '11' is connected to an end point of an n-2 bit code that can start from all states 1, 4, and 5, the n-bit code is still in state 1, All the states 4 and 5 can be set as the starting point.

[2-bit code connection law 2 for n-2 bit code]
In all n-2 bit codes, even if a 2-bit code “01” is connected to the end point, the state of the code end point changes, but the start point state that the code can take does not change. For example, when a 2-bit code '01' is connected to the end point of an n-2 bit code that can start from all the states 1, 4 and 5, the n-bit code is also the state 1, All the states 4 and 5 can be set as the starting point.

[3-bit code connection law 3 for n-2 bit code]
In all n-2 bit codes, even if the last bit is inverted '0'-'1' and the 2-bit code '10' is connected to the end point, the code end point state does not change and the code The starting point state that can be taken does not change. For example, the last bit of an n-2 bit code that can start from all the states 1, 4, and 5 is reversed by “0”-“1”, and the end point is a 2-bit code “10”. When connected, the n-bit code can also start from all states 1, 4 and 5.

  Accordingly, by performing (m−2) / (n−2) conversion in advance, a 2-bit code “11”, “01” or “10” is connected to the code end point (however, the code “10”). In the configuration using a very simple additional circuit (the last bit of the code is inverted from “0” to “1” when the ”is connected), the code conversion of 3/4 of the number of conversion code words necessary for m / n conversion is performed. It can be carried out. For the remaining 1/4, it is necessary to perform code conversion separately, but the number of conversion codewords necessary for (m-2) / (n-2) conversion is the number of conversion codewords necessary for m / n conversion. Since it is 1/4, the number of conversion codewords substantially required is reduced to 1/2.

  In the code conversion method described above, code conversion is performed for a certain conversion code by collectively collecting in advance a code in which the (n−α) bit portion overlaps. Therefore, the code conversion method described above is referred to as a duplicate code conversion method. By combining this duplicate code conversion method and the above-described code division method, the effect of reducing the circuit scale can be further enhanced.

  Another embodiment of the present invention in which such a duplicate code conversion method is applied to a 9/10 conversion DC-free code in which m = 9 will be described below. For example, if α = 2, the (m−α) / (n−α) conversion code is 7/8 conversion. FIG. 23 is an example of a code conversion table in which codes are specifically assigned for 7/8 conversion for 128 codewords. Here, the input column describes the input 7-bit data expressed in decimal, and the output column expresses 8-bit data as a code word corresponding to the input data in binary. The thing was described.

  The code words in FIG. 23 are selected so that the maximum number of consecutive data '0's is 4 (for example, when the input data is “24”, etc.) when counted from the code head. When counted from the rear end of the code, the number is 3 (for example, when the input data is “26”), and when counted in the middle of the code, the number is 5 (for example, when the input data is “48”). Is selected. However, all the code words in FIG. 23 are elements in FIG. 15, FIG. 17, and FIG. In the state transition diagram of FIG. 1, 64 words in the first half are code words that can start from at least state 5, and 64 words in the latter half are code words that can start from at least states 1 and 5. A codeword is assigned.

  Therefore, in order to perform appropriate code conversion, in FIG. 23, for the first 64 words, code words that can start from both states 1 and 4 are used, and for the latter 64 words, at least state 4 is used as the start point. The code conversion table for further assigning each of the codewords that can be performed is necessary, but as described above, the code conversion table for this is the head of each codeword in FIG. 23 according to the appropriate logic. It can consist only of '0'-'1' inversion of bits.

  An example of a logical expression for performing “0”-“1” inversion of the first bit for a part of the codeword of FIG. 23 will be described. For the 2-bit code 'XY' representing the code state, '00', '01', and '10' are assigned to states 1, 4, and 5, respectively. However, 2 bits are allocated to 'XY' as 4! = 24 types exist, and the above-described allocation method is an example, and is not limited to this.

  At this time, the 1-bit parity code q is output according to the truth table shown in FIG. 24 with reference to the leading bit a of the input data and the code end state “XY” of the previously encoded code. That is, according to the Boolean algebra display, q is output as follows.

  At this time, if q = 1, the leading bit a of the input data and the leading bit A of the encoded data are both inverted by “0”-“1”. That is, according to the Boolean algebra display, it is expressed as follows.

  FIG. 25 shows a 7/8 code conversion table for 128 code words output when q = 1 according to the above logic. The codewords in FIG. 25 are all elements in Tables 13, 14, and 17. The first 64 words are codewords that can start at least in states 1 and 4, and the last 64 words are at least states. Each codeword is assigned to be a codeword that can start from 4. As described above, when q = 1 is output by the equation (7), the input shown in FIG. 25 is obtained from the correspondence between the input data and the code word shown in FIG. 23 according to the equations (8) and (9). Correspondence between data and codewords can be derived.

Therefore, if the configuration for realizing the correspondence between the input data and the code word shown in FIG. 23 is provided in the encoding circuit, it is necessary to separately provide the configuration for realizing the correspondence between the input data and the code word shown in FIG. No. As a configuration for realizing the correspondence between the input data and the code word, for example, a logic circuit, PLA (Plogramable Logical Array), ROM (Read Only Memory), or the like can be used. Further, a configuration for performing correspondence between the input data and the code word shown in FIG. 25 is provided in the encoding circuit, and the input shown in FIG. 23 is performed according to the logical expression opposite to the expressions (7) to (9). The correspondence between data and codewords may be derived. Therefore, any one of the logic circuit or the like that realizes the correspondence shown in FIG. 23 and the logic circuit or the like that realizes the correspondence shown in FIG. 25 may be provided.

  Here, in performing the 9/10 conversion, the 1-bit code Z indicating whether or not to select the 7/8 conversion table shown in FIG. 23 (or FIG. 25) is represented by the last 2 bits of the 9-bit input data abcdefghi. Using hi, it outputs in accordance with the truth table of FIG. That is, according to the Boolean algebra display, Z is output as follows.

  Z = hi (10)

  When Z = 0 is output, the 8-bit code ABCDEFGH is output using the 7/8 conversion table shown in FIG. 23 (or FIG. 25), and the 10-bit output necessary for performing 9/10 conversion is output. The remaining 2-bit output IJ is output according to the truth table of FIG. That is, according to the Boolean algebra display, I and J are output as in the following equation.

  However, as described above, when IJ = '10 ', it is necessary to invert the last bit of the 8-bit code by' 0 '-' 1 '. That is, the final bit H of the 8-bit code is output as shown in the following equation.

  As described above, 128 × 3 = 384 code assignments among 512 codewords necessary for 9/10 conversion are completed. Further, the remaining 128 codewords may be newly assigned code as 7/10 conversion.

  FIG. 28 is an example of a code conversion table in which codes are specifically assigned for 7/10 conversion for 128 codewords. However, the code words in FIG. 28 are all the elements of FIG. 9, FIG. 11 and FIG. 14, and the first 64 words are code words that can start at least at state 5, and the second 64 words are at least Each codeword is assigned so that the codeword can start from both states 1 and 5.

  Since the input data 0 to 127 has already been assigned in FIG. 23, the input data in FIG. 28 is set to 128 to 255. Since these input data are formed by adding 1-bit data “1” to the head of the input data (7-bit data) in FIG. 23, they substantially correspond to 7/10 conversion. However, the number of code words in FIG. 28 is five when the maximum number of consecutive data '0's is counted from the top of the code (for example, when the input data is “138”). When counted from the rear end of the code, the number is 4 (for example, when the input data is “168”), and when counted in the middle of the code, the number is 5 (for example, when the input data is “154”). Further, the number of such code words is 8 when the maximum number of consecutive data '1' is counted from the top of the code (for example, when the input data is “198”). When counting from the end of the code, select 7 (for example, when input data is “197”), and when counted in the middle of the code, select 7 (for example, when input data is “137”). It has been done.

  FIG. 29 is another example of a code conversion table in which codes are specifically assigned for 7/10 conversion for 128 codewords. However, the code words in FIG. 29 are all the elements in FIG. 9, FIG. 10, and FIG. 13, and the first 64 words are code words that can start at least at state 4, and the last 64 words. Each codeword is assigned such that at least a codeword that can start from state 4 is a codeword. Here, the code conversion shown in FIG. 25 is derived from the code conversion shown in FIG. 23 (or conversely, the code conversion shown in FIG. 23 is derived from the code conversion shown in FIG. 25). 29 can be derived from 28 (or conversely, the code conversion of FIG. 28 can be derived from the code conversion of FIG. 29). Therefore, in this case as well, for example, a configuration of a logic circuit or the like that performs correspondence between input data and codewords according to one of FIGS. 28 and 29 may be provided.

  A 9/10 transform encoder configured according to the above logic will be described with reference to FIG. In FIG. 30, the state determination circuit is not shown. The 8/8 encoding circuit 30 performs the 7/8 conversion shown in FIG. 23 to generate the first 128 words, and further, 8 bits from the head of each code word in the 7/10 conversion shown in FIG. This is an 8/8 conversion circuit configured to generate the minute as the last 128 words. In addition, the 6/2 encoding circuit 31 generates 32 codewords from the beginning of the 7/2 conversion for generating 2 bits from the rear end of each codeword in the 7/10 conversion shown in FIG. This is a 6/2 conversion circuit configured to generate a total of 64 code words corresponding to 32 and 65 code words from the 65th.

  In FIG. 28, since the 33 bits from the 33rd codeword and the 96th codeword to the 32 codeword are assigned so that all 2 bits from the rear end of each codeword are “00”, It is not necessary to perform 7/2 conversion for 32 codewords and 96th to 32th codewords. Accordingly, the configuration of the 6/2 encoding circuit 31 can be simplified. In FIG. 30, the additional circuit excluding the 8/8 encoding circuit 30 and the 6/2 encoding circuit 31 assumes that the AND circuit and the OR circuit are 1 gate, and the exclusive OR circuit is 3 gates. If the scale is estimated, it will be only 22 gates. According to the above description, the 9/10 conversion circuit can be substantially constituted by 7/8 conversion circuits for 128 code words and 7/10 conversion circuits for 128 words. It has been shown that the number of conversion codewords required for / 10 conversion encoding can be halved.

  Next, still another embodiment of the present invention will be described in which a code conversion method combining the code division method according to the present invention and the duplicate code conversion method according to the present invention is applied to a 16/18 DC free code. The 7/8 conversion circuit for 128 words included in the 9/10 conversion encoder described above with reference to FIG. 30 and the like is the same as the 7/8 conversion circuit in the above description of the code division method (see FIG. 21). It is easily guessed that they are exactly the same. That is, in the 16/18 DC free code conversion, when the code division method according to the present invention and the duplicate code conversion method according to the present invention are combined, the configuration of the 7/8 conversion circuit is the configuration of the 9/10 conversion circuit. include.

  Therefore, it can be seen that it is not necessary to provide the 7/8 conversion circuit separately from the 9/10 conversion circuit. That is, in the 16/18 DC-free code conversion, the number of conversion codewords reduced from 65536 codewords to 512 + 128 = 640 codewords by the above-described code division method is a conversion method in which the code division method and the duplicate code conversion method are combined. Is further reduced to 128 + 128 = 256 codewords.

  A 16/18 conversion encoder that realizes such a conversion method will be described with reference to FIG. In FIG. 31, 7-bit and 9-bit parallel data are alternately supplied as input data. When 9-bit data abcdefghhi is input as input data, the 9-bit data is converted into 10-bit data ABCDEFGHIJ by the 9/10 encoding circuit 40. On the other hand, when 7-bit data abcdefg is input as input data, hi = '10 'is forcibly assigned and supplied to the 9/10 encoding circuit 40.

  With such an operation, IJ = '11 'is output as the last 2 bits of the 10-bit output code when 7-bit data is sent, but this can be ignored. Therefore, the 9/10 encoding circuit 40 substantially operates as a 7/8 encoding circuit. The 9/10 converted 10-bit code is supplied to a subsequent signal processing system that performs processing such as generating a recording signal for recording on an information recording medium such as a magnetic tape, and a 10-bit state determination circuit. 41. The 10-bit state determination circuit 41 outputs a 2-bit code XY representing any one of the three states of the code end point of the supplied 10-bit code.

  Here, when the input data is 7 bits, IJ = '11 'is output. According to the above-mentioned [2-bit code connection rule 1 for n-2 bit code], the state of the code end point of this 10-bit code. Is exactly the same as the code end state of the code of 8 bits from the beginning. Therefore, the 10-bit state determination circuit 41 can share the same data when 7-bit data is input and when 9-bit data is input.

  An 18/16 conversion decoder that decodes a 16/18 conversion code generated by such a code conversion method will be described with reference to FIG. In FIG. 32, 8-bit and 10-bit parallel data are alternately supplied as input data. When 10-bit data ABCDEFGHIJ is input as input data, the 10-bit data ABCDEFGHIJ is decoded into 9-bit data abcdefghhi by the 10/9 decoding circuit 50. On the other hand, when 8-bit data ABCDEFGH is input as input data, as described above, IJ = '01 'or' 11 'is forcibly assigned. For this reason, hi = '00 'or' 10 'is output as the trailing 2 bits of 9-bit output data when 8-bit data is input, but this can be ignored.

  In the case of configuring an encoder and a decoder for encoding and decoding a 16/18 conversion code formed by combining the code division method according to the present invention and the duplicate code conversion method according to the present invention as described above When the circuit scale of the logic circuit was estimated, it was about 950 gates.

[Comparative Example 1]
FIG. 33 shows the results of examining the feasibility of all combinations of the two-divided 16/18 conversion codes in which DSV = 12, and the number of states at the start and end points of the codeword is two. However, when n ₁ and n ₂ are even numbers, the state of the start point / end point of the code word is set to states 2 and 3. When n ₁ and n ₂ are odd numbers, the code word start points P (n ₁ ) and P (n ₂ ) can be generated for each of the m ₁ / n ₁ conversions with the start points of the code words as states 1 and 4. ). In this case, each start point / end point is selected so that the number of code words that can be generated is maximized when the number of code point start / end points is two.

  Also, in FIG. 33, as in FIG. 2 and the like, symbols ○ / × are assigned corresponding to the possibility / impossibility of each code conversion. From FIG. 33, it is impossible to code-divide 16/18 conversion into two independent conversion codes even with DSV = 12, using a code having two state numbers as the start point and end point. This situation is the same even if the DSV is larger than 12. However, in the code having the two-state number as the start point / end point, the configuration of the 16/18 conversion code itself can be DSV = 8, and the number of code words usable at this time is 76875. By selecting an appropriate 65536 code word from these, a direct 16/18 conversion code can be constructed.

  A configuration of a 16/18 conversion encoder that generates a direct 16/18 conversion code when code division cannot be performed in this way will be described with reference to FIG. In FIG. 34, 16-bit parallel data abcdefghijklmnop is supplied as input data. The 16-bit data is converted into 18-bit data ABCDEFGHIJKLMNOPQR by the 9/10 encoding circuit 60. The 16 / 18-converted 18-bit code is supplied to a subsequent configuration that performs processing such as generating a recording signal for recording on an information recording medium such as a magnetic tape, and is also supplied to the 18-bit state determination circuit 61. Supplied. The 18-bit state determination circuit 51 outputs a 1-bit code X representing one of the two states of the code end point of the supplied 18-bit code.

  Further, an 18/16 conversion decoder that decodes a 16/18 conversion code when code division as described above cannot be performed will be described with reference to FIG. In FIG. 35, 18-bit parallel data ABCDEFGHIJKLMNOPQR is supplied as input data. The 18-bit data is decoded into 16-bit data abcdefghijklmnop by the 18/16 decoding circuit 62.

  As described above, when the encoder and the decoder configured to directly encode and decode the 16/18 conversion code are estimated, the circuit scale of the logic circuit is estimated to be about 6500 gates. there were.

[Comparative Example 2]
In the state transition diagram of FIG. 1, the number of codes having RDS of +4 or −4, ie, limiting the DSV of the code to 7, and having states 1, 4, and 5 as the start and end points , There are only 61390 words, each with an 18-bit code. Therefore, it can be seen that it is impossible to configure a 16/18 conversion code with a code having a DSV of 7 or less.

  The specific examples of the configuration of the code division method and the code conversion method of the 16/18 conversion DC-free code according to the present invention have been described above, and the features thereof will be described below. The code-divided 16/18 conversion DC-free code according to the present invention also has an effect of reducing the burst error length at the time of signal detection. That is, in a 16/18 conversion DC-free code that does not perform code division, an error of 1 bit when detecting an encoded signal is detected as a burst error of 16 bits at the time of decoding. The 16/18 conversion DC-free code encoded by the code division method according to the invention has the advantage that it is reduced to a burst error of 7 bits or 9 bits.

  The order of using the 7/8 conversion and the 9/10 conversion may be changed in any way, but in any case, it is desirable to use them alternately or in units of two and the same number. For example, 9/10 conversion → 7/8 conversion → 9/10 conversion → 7/8 conversion →..., 9/10 conversion → 7/8 conversion → 7/8 conversion Even if it is used in units of 2 like 9/10 conversion →..., Encoding / decoding is possible in 16 bits, that is, in units of 2 bytes. For example, 9/10 conversion → 9/10 When used in the order of conversion → 7/8 conversion → 7/8 conversion → 7/8 conversion →..., Encoding / decoding in units of 2 bytes is difficult.

  Furthermore, the 9/10 conversion DC-free code used in one embodiment of the present invention can be used as a 72/80 conversion DC-free code by using it in units of eight. In this case, since 9 bytes is a unit of input data, the data processing circuit is more complicated than when 16/18 conversion is used, but the encoding efficiency is 16/18 = 0.899 to 9/10 =. It becomes possible to improve to 0.9.

  The code that satisfies the state transition diagram of FIG. 1 used in the present invention is automatically limited to a maximum run length of DSV−1. For example, in the case of DSV = 8, in FIG. 9 to FIG. It is possible to limit the maximum run length to 6 by removing a code with a length of 7, and further limit the maximum run length to 5 by removing a code with a run length of 6. However, it is impossible to make the maximum run length 4 or less in the code of DSV = 8. For example, even if DSV is allowed up to 12, it is impossible to make the maximum run length 4 or less. If the maximum run length of the code is reduced, it is considered that the low-frequency noise suppression effect of the code is further increased.

  Moreover, as one of effective means for limiting the run length at the code connection point without reducing the number of usable code words in the limitation of the maximum run length, for example, FIGS. Among the codewords shown in Fig. 11, the run length counted from the code start point in the "codewords that can start from the two states 1 and 5" shown in Figs. A method using 4 or 4 and 3 as a code word starting from only state 5 without connecting to the code terminated in state 1 is conceivable.

  That is, the code conversion method according to the present invention has a run length counted from the code start point among “a code word that can start from two states of states 1 and 5 (RDS = 0, minus plus 2)”. 4 or 4 and 3 are not connected to the code terminated in state 1 (RDS = 0), but are used as codewords starting from state 5 (RDS = minus plus 2). .

  This method is based on the fact that the maximum run length counted from the code end point when the code ends in state 5 is shorter than that when it ends in state 1 (RDS = 0). It is possible to make effective use of codes without reducing possible codewords. In addition, with regard to a code word that can start from the two states of states 1 and 5 as described above, even if the code word that can start from state 1 is not used as the starting point, Since the number is larger than the number of codewords that can start from state 4 or 5, and only a part of this excess code has been removed, the number of codewords that can finally be used is After all, there are 145 in 7/8 conversion and 525 in 9/10 conversion, and the number does not decrease, so no problem occurs.

  In this way, by limiting the maximum run length to a value shorter than the value automatically limited by the state transition diagram for DSV restriction, run length 6 or run length 6 continuation or run length 7 Can be used as, for example, a synchronization signal as a special code of one codeword length (18 bits) or less.

  In addition, the code that satisfies the state transition diagram of FIG. 1 is not limited in the number of consecutive data '1'. For example, when this code is equalized to partial response class 1 and maximum likelihood signal detection is performed, In order to make the memory finite, it is desirable that the continuity of data '1' is finite and the maximum number of continuations is as small as possible. For example, in the case of a 16/18 conversion DC-free code according to an embodiment of the present invention, in order to minimize the decrease in the number of codewords, only codes in which 10-bit sequences are all '1' are removed. A method may be used.

  According to this method, it is possible to limit the maximum number of consecutive data '1' to 26. Furthermore, the maximum number of consecutive data '1's can be limited to a minimum of 10 when DSV = 8 by deleting a code in which data' 1 'continues, and when DSV = 10 and 12 Can be limited to 7 at a minimum. Further, by limiting the number of continuous data '1' in this way, a code including data '1' having a continuous number of 8 or more and 18 or less is used as a special code having a codeword length (18 bits) or less as a synchronization signal. It can also be used.

  Incidentally, in the 16/18 conversion DC free code according to the embodiment of the present invention, the maximum run length is limited to 6, the maximum number of consecutive data '1' is limited to 12, and 15-bit data '100000010000001' Is prohibited. Therefore, a code including such 15-bit data can be used as a one-word synchronization signal.

  The DC-free code according to the present invention is applied to any of commonly used equalization methods such as integration equalization, partial response class 1 equalization, partial response class 4 equalization, and extended partial response class 4 equalization. It is possible. Therefore, the maximum likelihood signal detection can naturally be performed.

  The present invention is used in, for example, a magnetic recording / reproducing device such as a hard disk drive for a computer, a data cartridge drive for a computer, or a magneto-optical recording / reproducing device such as a magneto-optical disk drive, and various communication devices. It can be applied to long conversion codes.

  The present invention is not limited to the above-described embodiment of the present invention, and various modifications and applications are possible without departing from the spirit of the present invention.

It is a state transition diagram of 12 states on the premise of NRZI modulation, with a DSV of 8, for explaining the configuration of codes used in the present invention. It is a basic diagram for demonstrating feasibility with respect to all the combinations for 2 division | segmentation 16/18 conversion codes | symbols with DSV = 8 and the number of states of the start point of a codeword, and an end point are three. It is a basic diagram for demonstrating feasibility with respect to all the combinations for 2 division | segmentation 16/18 conversion codes | symbols with DSV = 10 and the number of states of the start point of a codeword, and an end point are three. It is a basic diagram for demonstrating feasibility with respect to all the combinations for 2 division | segmentation 16/18 conversion codes | symbols with DSV = 12, and the number of states of the start point of a codeword, and an end point are three. It is a basic diagram for demonstrating feasibility with respect to all the combinations for 2 division | segmentation 16/18 conversion codes | symbols with DSV = 8 and the number of states of the start point of a codeword, and an end point of four. It is a basic diagram for demonstrating feasibility with respect to all the combinations for 2 division | segmentation 16/18 conversion codes | symbols with DSV = 10 and the number of states of the start point of a codeword, and an end point of 4. It is a basic diagram for demonstrating feasibility with respect to all the combinations for the 2 division | segmentation 16/18 conversion code | symbols with DSV = 12, and the number of states of the start point of a codeword, and an end point are four. FIG. 6 is a trellis diagram showing RDS transition for explaining a 16/18 conversion DC-free code division method according to the present invention. It is a basic diagram for demonstrating the 162 10-bit code | cord | chords which can make all the states of states 1, 4, and 5 start. It is a basic diagram for demonstrating 234 10-bit codes | symbols which can make two states of the states 1 and 4 a starting point. It is a basic diagram for demonstrating 234 10-bit codes | symbols which can make two states of the states 1 and 5 a starting point. It is a basic diagram for demonstrating the 20 10-bit codes | symbols which can make only the state 1 a starting point. It is a basic diagram for demonstrating 129 10-bit codes | symbols which can make only the state 4 a starting point. It is a basic diagram for demonstrating 129 10-bit codes | symbols which can make only the state 5 a starting point. It is a basic diagram for demonstrating 54 8-bit code | cord | chords which can make all the states of state 1, 4, and 5 start. It is a basic diagram for demonstrating the 62 8-bit code | cord | chords which can make the two states of the states 1 and 4 a starting point. It is a basic diagram for demonstrating the 62 8-bit code | cord | chords which can make two states of the states 1 and 5 a starting point. It is a basic diagram for demonstrating two 8-bit codes which can make only the state 1 a starting point. It is a basic diagram for demonstrating the 29 8-bit codes | symbols which can make only the state 4 a starting point. It is a basic diagram for demonstrating the 29 8-bit codes | symbols which can make only the state 5 a starting point. It is a block diagram for demonstrating the structure of the 16/18 conversion encoder which implement | achieves 16/18 conversion encoding by the code division | segmentation method which is one Embodiment of this invention. It is a block diagram for demonstrating the structure of the 18/16 conversion decoder which implement | achieves the decoding corresponding to 16/18 conversion encoding which is one Embodiment of this invention. It is a basic diagram which shows an example of the code conversion table for performing 7/8 conversion for 128 code words in 9/10 conversion encoding by the duplicate code conversion method which is other embodiment of this invention. In other embodiment of this invention, it is a basic diagram which shows an example of the code allocation table | surface used in order to determine the presence or absence of inversion of a code | symbol head bit. In other embodiment of this invention, it is a basic diagram which shows another example of the code conversion table for performing 7/8 conversion for 128 codewords. In other embodiment of this invention, it is a basic diagram which shows an example of the code allocation table used in order to determine whether the code conversion table for performing 7/8 conversion is selected. In other embodiment of this invention, when the code conversion table for performing 7/8 conversion is selected, it is a basic diagram which shows an example of the truth table used in order to output the remaining 2 bits. It is a basic diagram which shows an example of the code conversion table to which the code | symbol was specifically allocated about 7/10 conversion for 128 codewords used in other embodiment of this invention. It is a basic diagram which shows another example of the code conversion table to which the code | symbol was specifically allocated about 7/10 conversion for 128 codewords used in other embodiment of this invention. It is a block diagram for demonstrating the 9/10 conversion encoder which implement | achieves 9/10 conversion encoding by the duplicate code conversion method which is other Embodiment of this invention. It is a block diagram for demonstrating the 16/18 conversion encoder which implement | achieves 16/18 conversion encoding which combines the code division | segmentation method and the duplication code conversion method which are further another embodiment of this invention. is there. An 18/16 conversion decoder that realizes decoding corresponding to 16/18 conversion encoding combining the code division method and the duplicate code conversion method, which is still another embodiment of the present invention, will be described. It is a block diagram for. It is a basic diagram for demonstrating feasibility with respect to all the combinations for producing | generating 2 division | segmentation 16/18 conversion code | symbols with DSV = 12 and the number of states of the codeword start point / end point is 2. . It is a basic diagram for demonstrating the 16/18 conversion encoder (comparative example) which performs 16/18 conversion encoding when code division cannot be performed. It is a block diagram for demonstrating the 18/16 conversion decoder which performs the decoding corresponding to 16/18 conversion encoding performed when code division cannot be performed. It is a block diagram for demonstrating the signal processing in a general recording / reproducing apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 7/8 encoding circuit 11 9/10 encoding circuit 12 8-bit state determination circuit 13 10-bit state determination circuit 30 8/8 encoding circuit 31 6/2 encoding circuit 40 9/10 encoding circuit

Claims (1)

Code conversion method for DC-free code in which the states that the code can take at the start and end points of the code are three states, that is, three states of RDS = 0, plus / minus 2, and minus / plus 2 expressed in the state before NRZI modulation In
Without using “codeword that can start only from RDS = 0”,
“Codeword that can start from all states of RDS = 0, plus / minus 2, and minus / plus 2”, “Codeword that can start from two states of RDS = 0, plus / minus 2” ”,“ Codeword that can start from two states, RDS = 0, minus plus 2 ”,“ codeword that can only start from RDS = plus or minus 2 ”, and“ RDS = minus ” By using only the five types of codewords “codewords that can start only with plus 2”, the number of code selection states is 3 and the type of code selection required is the head of some codes. A code conversion method characterized by reducing to two types that can be configured only by bit inversion.

Images