JP4131691B2 - Digital receiver circuit - Google Patents

Description

  The present invention is used in a digital wireless communication system. In particular, the multi-carrier modulation signal receiving circuit is used in an OFDM (Orthogonal Frequency Division Multiplex) modulation system receiving circuit.

The multicarrier modulation scheme is a scheme for transmitting information using a plurality of subcarriers. The input data signal is modulated to 16QAM (Quadrature Amplitude Modulation) or the like for each subcarrier. Among the multicarrier modulation schemes, the orthogonal multicarrier modulation scheme in which the frequencies of the subcarriers are orthogonal to each other is orthogonal frequency division multiplexing (OFDM).
It is also called “Frequency Division Multiplexing” and is widely applied in wireless communication systems in which multipath propagation is a problem.

  OFDM is a modulation scheme that is less susceptible to multipath and suitable for high-speed transmission, but in order to further improve transmission speed, the signal bandwidth was increased to increase the number of subcarriers used for transmission. There is a method of using a wideband OFDM signal for transmission (see, for example, Non-Patent Document 1).

  At present, wireless systems in the microwave band are attracting attention because of the property that non-line-of-sight communication is easily realized and radio waves are easily diffracted. However, in this microwave band, when there is no mixing with other systems and a new wireless system is used, the usable frequency band is very limited. In terms of cost, when building a new system, all existing systems are replaced, and the transition to the new system is a system replacement from the viewpoint of the user who used the existing system. Cost is a problem.

  In particular, it is a big problem in a wireless LAN (for example, see Non-Patent Document 2) in which cost is very important. In addition, in a wireless LAN with a small system bandwidth allocated to the system, there is little possibility that a new frequency is allocated when a new system is constructed.

  Under such circumstances, when a new wireless system is constructed, it is desired to construct a new system that shares the frequency band with the existing system. In particular, when a broadband OFDM signal suitable for high-speed transmission is used, frequency coexistence with an existing system is important.

  In this case, various cases can be considered from the arrangement of frequencies. In this case, when the new system suppresses the minimum impact on the existing system, and the new system considers the viewpoint of implementation with the existing system, for example, the position of the pilot signal and each subcarrier frequency allocation are It is desirable to be common. A packet format in this case is shown in FIG. 8 (see, for example, Non-Patent Document 3). Further, FIG. 9 shows the frequency arrangement in this case. In FIG. 9, the frequency arrangement of the existing system and the new system is shown together. Here, the channel of the lower IEEE 802.11a signal is Ach, and the channel of the upper IEEE 802.11a signal is Bch. With reference to the OFDM receiver of Non-Patent Document 4, the receiver configuration in this case is as shown in FIG.

  The received signal S1 is input to the Bch timing detection circuit 1, and when a Bch signal arrives, a peak signal is output and timing detection is performed. The guard interval (hereinafter referred to as GI) removal circuit 2 uses the detected timing signal S2 to obtain a GI removal signal S3. In the FFT circuit 3, multicarrier demodulation is performed on the GI removal signal S3 to obtain a subcarrier signal S4. In the channel estimation circuit 4, transmission path distortion estimation is performed on the subcarrier signal S4 using a preamble signal, and a transmission path distortion signal S5 is obtained. In the channel equalization circuit 5, the channel equalization signal S6 is obtained by using the transmission path distortion signal S5 with respect to the subcarrier signal S4. The received signal S1 is input to the Ach timing detection circuit 6 and when an Ach signal arrives, a peak signal is output and timing detection is performed.

  The GI removal circuit 7 obtains the GI removal signal S8 by using the detected timing signal S7. In the FFT circuit 8, multicarrier demodulation is performed on the GI removal signal S8 to obtain a subcarrier signal S9. In the channel estimation circuit 9, transmission path distortion estimation is performed on the subcarrier signal S9 using a preamble signal, and a transmission path distortion signal S10 is obtained.

  In the channel equalization circuit 10, the channel equalization signal S11 is obtained using the transmission path distortion signal S10 with respect to the subcarrier signal S9. Further, the received signal S1 is input to the broadband signal timing detection circuit 11, and when a broadband signal arrives, a peak signal is output and timing detection is performed.

Using the detected timing signal S12, the GI removal circuit 12 obtains a GI removal signal S13. In the FFT circuit 13, multicarrier demodulation is performed on the GI removal signal to obtain a subcarrier signal S14. The channel estimation circuit 14 performs transmission path distortion estimation on the subcarrier signal S14 using a preamble signal, and obtains a transmission path distortion signal S15. In the channel equalization circuit 15, a channel equalization signal S16 is obtained using the transmission path distortion signal S15 with respect to the subcarrier signal S14.
G. Fettweis, IEEE 802.11-02 / 320r0, May. 2002 IEEE. Std802.11a-1999 Onizawa et al., 2003 Shingaku Sodai, B-5-222 Richard van Nee, Ramjee Prasad, “OFDM for wireless multimedia communications, Artechhouse publishers, 2000

  In the microwave band in which the wireless LAN is used, the available frequency band is very limited. In addition, when a new system is built, after replacing all existing systems, the transition to the new system is problematic because it is a system replacement for users who used the existing system. It becomes.

  Therefore, when a new wireless system is constructed, it is desired to construct a new system that can be operated by sharing the frequency with the existing system. It is also important that the existing system and the new system can be demodulated with a single receiver. When demodulating the existing system and the new system with one receiver, it is excellent in terms of cost, circuit scale, and power consumption.

  However, in the conventional technology, since it is necessary to provide the Ach and Bch of the existing system sharing the frequency and the receiving circuit of the new system, there is a problem that an increase in circuit scale and an increase in power consumption become large. In particular, in a wireless LAN, since communication using independent packets is common, it is necessary to first detect the timing of a received signal at the beginning of a receiving operation. In this case, a matched filter is often used to realize highly accurate timing detection characteristics. However, since the matched filter requires a multiplier that multiplies the coefficient of the matched filter, a memory circuit that includes the coefficient, and the like, the circuit scale increases. Therefore, providing a plurality of timing detection portions is a big problem from the viewpoint of circuit scale and power consumption.

  Naturally, if the signal length of the received signal to be detected by the matched filter increases, the number of stages of the matched filter increases accordingly, and the circuit scale increases. For example, when a long symbol defined in the IEEE802.11a standard is used for timing detection, in the case of 40 MHz sample, it is necessary to configure a matched filter for as many as 128 points, and the circuit scale and power consumption are There are problems that increase significantly.

  The present invention solves these problems, and when the existing system and the new system coexist, it can suppress the increase in circuit scale and power consumption, and can perform reception to identify the existing system and the new system. An object of the present invention is to provide a digital receiving circuit.

  In order to solve the conventional problems, the present invention shares the MF coefficient multiplication means of the Ach and Bch timing detection means, and realizes the phase rotation by the phase rotation amount or sign inversion for the difference between each channel. The timing detection and identification of both channels are performed.

  In addition, even when coexisting with the new system, only the total two systems of the timing detection part of the new system and the timing detection part of the existing system are provided in parallel, and the FFT circuit, channel estimation circuit, channel, etc. after the timing detection part are provided. Circuit, etc. can coexist between the existing system and the new system, and the circuit scale and power consumption can be reduced.

  The present invention will be described with reference to FIG. The MF coefficient of each Ach and Bch is realized using the MF coefficient of the IEEE802.11a signal including a normal DC component. For example, when the sampling frequency of an AD (Analog Digital) converter is 40 MHz, the MF coefficients of each Ach and Bch give a phase rotation of exp (−j2 / π) and exp (j2 / π) for each sample. This can be achieved. Therefore, the multiplication result can be expressed by multiplying the MF coefficient and each received signal and then rotating the phase. When there is a fixed relationship between the channel frequency interval and the sampling frequency, the phase rotation amount can be expressed by sign inversion, and the number of multipliers can be greatly reduced.

  For example, when the signal of the frequency interval of FIG. 9 is converted into a digital signal by 40 MHz sampling, the phase rotation amount can be realized by sign inversion. The sign inversion circuit can be realized only by changing the polarity of the signal, and is effective in reducing the circuit scale.

That is, the present invention has a receiving signal holding means for holding the received signal over a plurality of samples, the signal waveform of the noiseless state that cotton multiple samples for a given signal to the coefficient, the output signal and samples of the received signal holding means A matched filter (hereinafter referred to as MF) coefficient multiplying means for performing multiplication every time, a first adding means for adding each sample signal output from the MF coefficient multiplying means, and a first adding means It is a digital reception circuit comprising timing detection means for detecting the reception timing of a reception signal from an output signal.

Here, a feature of the present invention is that a first phase rotation calculation unit that applies a phase rotation to each sample signal of the MF coefficient multiplication unit between the MF coefficient multiplication unit and the first addition unit. the provided, and a second phase rotation calculating means for performing a phase rotation operation of the first phase rotation calculating means the opposite direction to each sample signals output from the MF coefficient multiplying means, the second phase rotation calculating means And a second addition means for adding each sample signal output from the first addition means, in addition to the output signal of the first addition means, the output signal of the second addition means is input to the timing detection means In addition, when any of the input signals satisfies a predetermined condition, a means for identifying the corresponding received signal in addition to detecting the timing of the received signal is provided. This is the first example.

  According to this, after multiplying the received signal by the coefficient of MF for each sample, the phase rotation calculation is performed and added, thereby performing timing detection for each channel, and using the determination by peak detection, Identification is possible. Further, since each channel is identified by calculating the amount of phase rotation, it is not necessary to provide a plurality of MF coefficients, and the circuit scale can be greatly reduced.

  That is, “when the predetermined condition is satisfied, in addition to detecting the timing of the received signal, the corresponding received signal is identified”, for example, the timing information of the signal input to the timing detecting means The signal type (Ach or Bch) is determined by determining whether or not the signal satisfies the predetermined condition, or by determining whether or not the level of the input signal satisfies the predetermined condition. be able to.

  Specifically, the received signal that is Ach or Bch is multiplied by the MF coefficient by the MF coefficient multiplying means, but when the phase rotation is performed by the + direction phase rotation calculating means or the − direction phase rotation calculating means, Only when the phase direction is rotated in a direction that matches the received signal, proper MF coefficient multiplication is performed. Therefore, when the phase direction is rotated in a direction that is incompatible with the received signal, the timing information that the received signal has is destroyed and does not satisfy the predetermined condition (in this case, the condition related to timing information), or As a result, the level of the received signal becomes low and a phenomenon such as not satisfying the predetermined condition (in this case, the condition relating to the level) occurs. By observing these phenomena, the type (Ach or Bch) of the received signal can be determined.

Alternatively, the digital reception circuit of the present invention includes a first phase rotation calculation unit that applies a phase rotation to each sample signal of the MF coefficient multiplication unit between the MF coefficient multiplication unit and the first addition unit. , Second phase rotation calculation means for performing phase rotation calculation in the opposite direction to the first phase rotation calculation means on each sample signal output from the MF coefficient multiplication means, and output from the second phase rotation calculation means A second adding means for adding the respective sample signals to be performed, and a signal waveform of a plurality of samples in a noiseless state for a predetermined signal different from the MF coefficient multiplying means as a coefficient, and an output signal of the received signal holding means And second MF coefficient multiplying means for performing multiplication for each sample, and third addition means for adding each sample signal output from the second MF coefficient multiplying means, In addition to the output signal of the first addition means, the output signal of the second addition means and the output signal of the third addition means are input to the detection means, and any one of the input signals satisfies a predetermined condition. In addition to detecting the timing of the received signal when the condition is satisfied, a means for identifying the corresponding received signal is provided (claim 2). This is a second example.

  According to this, after multiplying the received signal by the MF coefficient for each sample and adding the phase rotation calculation, timing detection is performed for each channel, and both channels can be identified using determination by peak detection. I have to. Further, even when a wideband signal and a band, which is a new system that shares a band, coexist, the timing detection unit can identify each channel of the existing system and the new system. Further, since each existing channel is identified by calculating the phase rotation amount, it is not necessary to provide a plurality of MF coefficients, and the circuit scale can be greatly reduced. In addition, it is possible to suppress an increase in circuit scale of the timing unit by sharing the reception new holding circuit of the broadband system and the existing system.

  Furthermore, in the digital receiving circuit of the second example, using the timing signal output from the timing detecting means for the received signal, a GI removing means for cutting out a signal input to the FFT means from the received signal, and the GI removing means The FFT means for selecting the number of subcarriers to be demodulated in response to the identification signal output from the timing detection means for the signal output from the multi-carrier simultaneous demodulation, and the output signal output from the FFT means A channel estimation unit that uses a preamble signal and selects the number of subcarriers according to the identification signal output from the timing detection unit to estimate transmission path distortion, and a data signal of the output signal output from the FFT unit. On the other hand, using the output signal from the channel estimation means, the identification signal output from the timing detection means. It may comprise a channel equalization unit to perform channel equalization processing for removing the distortion of the transmission path to select the number of subcarriers according to (Claim 3). This is the third example.

  According to this, in addition to the characteristics of the digital receiver circuit of the second example, the received signal information that has been identified is used to select the number of subcarriers for signal processing after the FFT circuit. Therefore, there is a feature that the circuits after the FFT circuit are shared, and the effect of realizing reduction in circuit scale and reduction in power consumption is great. Further, since each existing channel is identified by calculating the phase rotation amount, it is not necessary to provide a plurality of MF coefficients, and the circuit scale can be greatly reduced.

  Among various conceivable configurations of the present invention, a technique for reducing the circuit scale by reducing the number of bits indicating the coefficients of the MF coefficient multiplier circuit shown in the first example, the second example, and the third example is applicable. is there. Further, in the timing detection means, a method of applying a filter (FIR (Finite Impulse Response) filter, IIR (Infinite Impulse Response) filter) to the output result of the addition means in order to increase the timing detection accuracy, or input to the MF For example, a method of suppressing the fluctuation of the peak value which is the addition circuit output value even when the transmission line fluctuates by normalizing the addition circuit output with the signal power to be considered.

  As the timing detection means, a method of determining detection by comparison with a threshold value set in advance or by learning, or a method of performing waveform comparison by pattern matching of peak waveforms is naturally applicable. .

  Also, when timing is detected, the earliest waveform among the peak waveforms output according to the state of the transmission path is output as timing information, or the timing information using the peak waveform with a predetermined delay is output. Furthermore, it is possible to apply a technique such as setting a timing shifted forward by several samples from the timing of the selected peak waveform as an actual detection timing.

  Further, an identification method using timing information can be considered for identifying each channel and identifying a wideband signal. Further, a method of identifying a signal with reference to the received signal level is naturally conceivable.

  In the present invention, by performing the above-described operation, each signal can be received using a receiver whose circuit scale is greatly reduced in an environment where the existing system and the new system are operated by sharing the frequency. . By using the present invention, the problem of increasing the circuit scale and power consumption, which has been a problem in the past, is solved.

Another aspect of the present invention, by installing the information processing apparatus, to the information processing apparatus, a receiving signal holding function of holding the received signal over a plurality of samples, noiseless that cotton multiple samples for a given signal A matched filter (MF) coefficient multiplying function for multiplying the output signal of the received signal holding function by the sample and a sample for each sample, and addition of each sample signal output from the MF coefficient multiplying function. A program for realizing a function corresponding to a digital reception circuit having a first addition function to be performed and a timing detection function for detecting a reception timing of a reception signal from an output signal of the first addition function.

Here, a feature of the present invention is that a first phase rotation calculation function that gives a phase rotation to each sample signal of the MF coefficient multiplication function between the MF coefficient multiplication function and the first addition function. And a second phase rotation calculation function that performs a phase rotation calculation in the opposite direction to the first phase rotation calculation function on each sample signal output from the MF coefficient multiplication function, and the second phase rotation calculation A second addition function for adding each sample signal output from the function, and the timing detection function includes an output signal of the second addition function in addition to the output signal of the first addition function. When any of the input signals satisfies a predetermined condition, a function of identifying the corresponding received signal in addition to detecting the timing of the received signal is realized (claim 4).

Alternatively, the program of the present invention realizes a first phase rotation calculation function that gives a phase rotation to each sample signal of the MF coefficient multiplication function between the MF coefficient multiplication function and the first addition function, Output from the second phase rotation calculation function and the second phase rotation calculation function for performing phase rotation calculation in the opposite direction to the first phase rotation calculation function for each sample signal output from the MF coefficient multiplication function. A second addition function for adding each sample signal, and a signal waveform of a plurality of samples in a noiseless state for a predetermined signal different from the MF coefficient multiplication function as a coefficient, and an output signal of the received signal holding function A second MF coefficient multiplication function for performing multiplication for each sample, and a third addition function for adding each sample signal output from the second MF coefficient multiplication function; In addition to the output signal of the first addition function, the output signal of the second addition function and the output signal of the third addition function are input to the detection function, and any one of the input signals satisfies a predetermined condition. When the condition is satisfied, in addition to detecting the timing of the received signal, a function of identifying the corresponding received signal is realized (claim 5).

  In addition to this, a guard interval removing function for cutting out a signal input to the FFT function from the received signal using the timing signal output from the timing detection function for the received signal, and an output from the guard interval removing function An FFT function for performing multicarrier collective demodulation by selecting the number of subcarriers to be demodulated according to an identification signal output from the timing detection function for the received signal, and a preamble signal of an output signal output from the FFT function For the channel estimation function for estimating the distortion of the transmission path by selecting the number of subcarriers according to the identification signal output from the timing detection function, and the data signal of the output signal output from the FFT function, Using the output signal from the channel estimation function, output from the timing detection function. It is also possible to realize the channel equalization function for channel equalization process to remove the distortion of the transmission path to select the number of sub-carriers in accordance with that identification signal (claim 6).

  Still another aspect of the present invention is a recording medium readable by the information processing apparatus on which the program of the present invention is recorded (claim 7). By recording the program of the present invention on the recording medium of the present invention, the information processing apparatus can install the program of the present invention using this recording medium. Alternatively, the program of the present invention can be directly installed in the information processing apparatus via a network from a server holding the program of the present invention.

  As a result, when the existing system and the new system are operated together using a general-purpose information processing device, the increase in circuit scale and power consumption is suppressed, the existing system and the new system are identified, and Thus, it is possible to realize a digital receiving circuit that enables reception of signals of both systems.

  By using the digital receiver circuit of the present invention, when the existing system and the new system are operated in coexistence, the increase in circuit size and power consumption is suppressed, the existing system and the new system are identified, and A digital receiver circuit can be provided that allows reception of the signals of both systems.

  An embodiment of the present invention will be described with reference to FIGS.

  A first embodiment will be described with reference to FIG. FIG. 1 is a block diagram of the digital receiver circuit of the first embodiment.

First embodiment, as shown in FIG. 1, a reception signal holding circuit 101 for holding the received signal over a plurality of samples, having a coefficient signal waveform noiseless state across multiple samples for a given signal, the received signal hold A matched filter (MF) coefficient multiplying circuit 102 that multiplies the output signal of the circuit 101 for each sample, a summing circuit 104 that adds each sample signal output from the MF coefficient multiplying circuit 102, and an output of the summing circuit 104 This is a digital reception circuit including a timing detection identification circuit 107 that detects a reception timing of a reception signal from a signal.

Here, the feature of the first embodiment is that a + direction phase rotation calculation circuit 103 that applies phase rotation to each sample signal of the MF coefficient multiplication circuit 102 is provided between the MF coefficient multiplication circuit 102 and the summing circuit 104. A −direction phase rotation calculation circuit 105 that performs a phase rotation calculation in the opposite direction to the + direction phase rotation calculation circuit 103 on each sample signal output from the MF coefficient multiplication circuit 102, and an output from the −direction phase rotation calculation circuit 105. And a summing circuit 106 for adding the respective sample signals. The timing detection identification circuit 107 receives the output signal of the summing circuit 106 in addition to the output signal of the summing circuit 104, and any one of the input signals is predetermined. When the above condition is satisfied, means for identifying the corresponding received signal in addition to detecting the timing of the received signal is provided (claim 1).

  Next, the operation of the digital receiver circuit of the first embodiment will be described. The received signal S101 is input to the received signal holding circuit 101, and the signal is held and stored for each sample. The output signal S102 of the reception signal holding circuit 101 is input to the MF coefficient multiplication circuit 102 for each sample, and is multiplied for each sample. The output signal S103 of the MF coefficient multiplication circuit 102 is input to the + direction phase rotation calculation circuit 103, and the phase rotation calculation in the + direction is performed. The output signal S103 of the + direction phase rotation calculation circuit 103 is added by the summing circuit 104 for each sample.

  On the other hand, the output signal S106 of the MF coefficient multiplication circuit 102 is input to the − direction phase rotation calculation circuit 105, and the phase rotation calculation in the − direction is performed. The output signal S107 of the -direction phase rotation calculation circuit 105 is added by the summing circuit 106 for each sample. In the timing detection identification circuit 107, the output signal S105 of the summation circuit 104 and the output signal S108 of the summation circuit 106 are input, and when any one of the output signals S105 or S108 satisfies a predetermined condition, the output signal S105 or A timing signal S109 and an identification signal S110 corresponding to S108 are output.

  A second embodiment will be described with reference to FIG. FIG. 2 is a block diagram of the digital receiver circuit of the second embodiment.

Second embodiment, as shown in FIG. 2, the received signal hold circuit 201 for holding the received signal over a plurality of samples has a signal waveform noiseless state that cotton multiple samples for a given signal to the coefficient, the received signal A matched filter (MF) coefficient multiplication circuit 202 that multiplies the output signal of the holding circuit 201 for each sample, a summation circuit 204 that adds each sample signal output from the MF coefficient multiplication circuit 202, and a summation circuit 204 This is a digital reception circuit including a timing detection identification circuit 207 that detects reception timing of a reception signal from an output signal.

Here, a feature of the second embodiment is that a + direction phase rotation calculation circuit 203 that applies phase rotation to each sample signal of the MF coefficient multiplication circuit 202 is provided between the MF coefficient multiplication circuit 202 and the summing circuit 204. A -direction phase rotation calculation circuit 205 that performs a phase rotation calculation in the opposite direction to the + direction phase rotation calculation circuit 203 on each sample signal output from the MF coefficient multiplication circuit 202, and an output from the -direction phase rotation calculation circuit 205. A summing circuit 206 for adding the respective sample signals and a signal waveform of a plurality of samples in a noise-free state with respect to a predetermined signal different from the MF coefficient multiplying circuit 202 as coefficients, and the output signal of the received signal holding circuit 201 and each sample And a wideband signal MF coefficient multiplication circuit 208 for multiplying each of the sample signals output from the wideband signal MF coefficient multiplication circuit 208 The timing detection identification circuit 207 receives the output signal of the summing circuit 206 and the output signal of the summing circuit 209 in addition to the output signal of the summing circuit 204, and any one of the input signals is a predetermined signal. In addition to detecting the timing of the received signal when the condition is satisfied, a means for identifying the corresponding received signal is provided (claim 2).

  Next, the operation of the digital receiver circuit of the second embodiment will be described. The received signal S201 is input to the received signal holding circuit 201, and the signal is held and stored for each sample. The output signal S202 of the reception signal holding circuit 201 is input to the MF coefficient multiplication circuit 202 for each sample, and is multiplied for each sample. The output signal S203 of the MF coefficient multiplication circuit 202 is input to the + direction phase rotation calculation circuit 203, and the phase rotation calculation in the + direction is performed. The output signal S204 of the + direction phase rotation calculation circuit 203 is added by the summing circuit 204 for each sample.

  On the other hand, the output signal S206 of the MF coefficient multiplication circuit 202 is also input to the -direction phase rotation calculation circuit 205 to perform a phase rotation calculation in the -direction. Similarly, the output signal S207 of the -direction phase rotation calculation circuit 205 is added by the summing circuit 206 for each sample.

  On the other hand, the output signal S217 of the reception signal holding circuit 201 is input to the wideband signal MF coefficient multiplication circuit 208, and the output signal S211 of the wideband signal MF coefficient multiplication circuit 208 is output. The summing circuit 209 performs processing for adding the output signal S211 of the wideband signal MF coefficient multiplying circuit 208 output for each sample. The addition result is output as S212. The timing detection identification circuit 207 receives the output signals S205, S208, and S212 of the summing circuits 204, 206, and 209, and outputs the timing signal S209 and the identification signal S210. At this time, with respect to the output signals S205 and S208, as in the first embodiment, when any one of the output signals S205 or S208 satisfies a predetermined condition, a timing signal S209 corresponding to the output signal S205 or S208 The identification signal S210 is output.

  A digital receiving circuit according to a third embodiment will be described with reference to FIG. FIG. 3 is a block diagram of the digital receiver circuit of the third embodiment.

  In addition to the same configuration as the digital receiver circuit of the second embodiment, the digital receiver circuit of the third embodiment uses the timing signal output from the timing detection identification circuit 307 for the received signal S301, and uses the received signal S301 to the FFT. A GI removal circuit 310 that cuts out a signal input to the circuit 311 and a signal S313 output from the GI removal circuit 310 are selected in accordance with the identification signal S310 output from the timing detection identification circuit 307 and the number of subcarriers to be demodulated is selected. The FFT circuit 311 that performs multi-carrier batch demodulation and the preamble signal of the output signal S314 output from the FFT circuit 311 are used to select the number of subcarriers according to the identification signal S310 output from the timing detection identification circuit 307. A channel estimation circuit 312 for estimating the distortion of the transmission path, and F For the data signal of the output signal S314 output from the T circuit 311, the output signal S315 from the channel estimation circuit 312 is used to select the number of subcarriers according to the identification signal S310 output from the timing detection identification circuit 307. And a channel equalization circuit 313 for performing channel equalization processing for removing distortion of the transmission line.

  Next, the operation of the digital receiver circuit of the third embodiment will be described. The received signal S301 is input to the received signal holding circuit 301, and the signal is held and stored for each sample. The output signal S302 of the reception signal holding circuit 301 is input to the MF coefficient multiplication circuit 302 for each sample, and is multiplied for each sample. The output signal S303 of the MF coefficient multiplication circuit 302 is input to the + direction phase rotation calculation circuit 303, and the phase rotation calculation in the + direction is performed. The output signal S304 of the + direction phase rotation calculation circuit 303 is added by the summing circuit 304 for each sample.

  On the other hand, the output signal S306 of the MF coefficient multiplication circuit 302 is also input to the -direction phase rotation calculation circuit 305 to perform the phase rotation calculation in the -direction. The output signal S307 of the -direction phase rotation calculation circuit 305 is added by the summation circuit 306 for each sample.

  On the other hand, the output signal S317 of the reception signal holding circuit 301 is input to the wideband signal MF coefficient multiplication circuit 308, and the output signal S311 of the wideband signal MF coefficient multiplication circuit 308 is output. The summing circuit 309 performs processing for adding the output signal S311 of the wideband signal MF coefficient multiplying circuit 308 output for each sample. The addition result is output as S312. The timing detection identification circuit 307 receives the output signals S305, S308, and S312 of the summing circuits 304, 306, and 309, and outputs the timing signal S309 and the identification signal S310. At this time, as with the first embodiment, regarding the output signals S305 and S308, when any one of the output signals S305 or S308 satisfies a predetermined condition, the timing signal S309 corresponding to the output signal S305 or S308 The identification signal S310 is output.

  On the other hand, the reception signal S301 is input to the GI removal circuit 310, and the GI is removed based on the timing signal S309. The output signal S313 of the GI removal circuit 310 is input to the FFT circuit 311 and multi-carrier collective demodulation with subcarriers selected according to the identification signal S310 is performed to output a subcarrier signal S314. The channel estimation circuit 312 estimates the channel distortion of the transmission path with the number of subcarriers selected for the subcarrier signal S314 in accordance with the identification signal S310. The channel equalization circuit 313 performs channel equalization processing on the subcarrier signal S314 by selecting the subcarrier signal according to the identification signal S310 using the channel estimation signal S315, and outputs the channel equalization signal S316.

The present invention can be implemented as a program that, when installed in a general-purpose information processing apparatus, causes the information processing apparatus to realize a function corresponding to the digital reception circuit of the present invention (claims 4 to 6). The program is recorded on a recording medium and installed in the information processing apparatus (Claim 7), or installed in the information processing apparatus via a communication line, so that the GI removal circuit 310 and the FFT circuit are installed in the information processing apparatus. 311, channel estimation circuit 312, channel equalization circuit 313, received signal holding circuits 101, 201, 301, MF coefficient multiplication circuits 102, 202, 302, + direction phase rotation calculation circuits 103, 203, 303, total circuits 104, 204 , 304, 106, 206, 209, 306, 309, -direction phase rotation calculation circuits 105, 205, 305, timing detection identification circuits 207, 307, and broadband signal MF coefficient multiplication circuits 208, 308, respectively, corresponding functions are realized. be able to.
(Confirmation of effect)
The confirmation result of the effect by experiment is shown. The experiment is based on FPGA (Field
Evaluation by Programmable Gate Array). The experimental system conditions are shown in FIG.

  FIG. 4 also shows values based on the 1/5 scale model. A broadband signal was assumed as the new system, and an IEEE 802.11a signal was assumed as the existing system. In the experiment, the case where the symbol timing detection unit discriminates was evaluated in an environment where the IEEE802.11a signal and the broadband signal coexist.

  The IEEE802.11a signal is Ach and Bch. For signal transmission, an experiment was performed under the condition of pseudo-random reception by transmitting an IEEE802.11a signal using a common band with a wideband signal as Ach and Bch, and then sequentially transmitting the wideband signal. FIGS. 5 and 6 show PER (Packet Error Rate) characteristics when an IEEE802.11a signal and a broadband signal are received in a multipath environment.

  In FIG. 5 in which the IEEE802.11a signal is received, a characteristic with almost no deterioration is realized as compared with the case where the symbol timing is ideally given from the transmission side. Further, in the case of FIG. 6 in which a broadband signal is received, degradation of about 1.5 dB occurs with respect to ideal symbol timing, but it can be confirmed that the broadband OFDM signal can be identified and demodulated. Therefore, the effect of identifying and demodulating the wideband signal and the IEEE802.11a signal appropriately by the timing detector in this receiver can be confirmed from experiments.

  By using the digital receiver circuit of the present invention, when the existing system and the new system are operated in coexistence, the increase in circuit size and power consumption is suppressed, the existing system and the new system are identified, and Allows reception of signals from both systems. Thereby, since the cost at the time of a user introducing a new system can be reduced, it contributes to the sales channel expansion of a new system.

The block diagram of the digital receiver circuit of a 1st Example. The block diagram of the digital receiver circuit of a 2nd Example. The block diagram of the digital receiver circuit of a 3rd Example. The figure which shows the conditions of the experimental system which shows the effect of this invention. The figure which shows the PER characteristic at the time of discriminating and demodulating the 11a signal using this invention. The figure which shows the PER characteristic at the time of discriminating and demodulating a wideband signal using this invention. Explanatory drawing regarding the MF coefficient of the timing detection part of this invention. Explanatory drawing of the packet format transmitted from a digital transmission circuit. Explanatory drawing of the spectrum arrangement | positioning of the packet format transmitted from a digital transmission circuit. The block diagram which comprised the conventional receiving circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Bch timing detection circuit 2, 7, 12, 310 GI removal circuit 3, 8, 13, 311 FFT circuit 4, 9, 14, 312 Channel estimation circuit 5, 10, 15, 313 Channel equalization circuit 6 Ach timing detection circuit 11 Wide-band signal timing detection circuit 101, 201, 301 Received signal holding circuit 102, 202, 302 MF coefficient multiplication circuit 103, 203, 303 + direction phase rotation calculation circuit 104, 204, 304, 106, 206, 209, 306, 309 Total circuit 105, 205, 305 -Directional phase rotation calculation circuit 107, 207, 307 Timing detection identification circuit 208, 308 Wideband signal MF coefficient multiplication circuit

Claims (7)

A received signal holding means for holding a received signal over a plurality of samples, and a matched filter for multiplying the output signal of the received signal holding means with each sample having a noise waveform of a plurality of samples with respect to a predetermined signal as a coefficient Coefficient multiplication means (hereinafter referred to as MF), first addition means for adding each sample signal output from the MF coefficient multiplication means, and reception timing of the reception signal from the output signal of the first addition means In a digital receiving circuit comprising timing detection means for detecting
Between the MF coefficient multiplication means and the first addition means, a first phase rotation calculation means for giving a phase rotation to each sample signal of the MF coefficient multiplication means,
Second phase rotation calculation means for performing phase rotation calculation in the opposite direction to the first phase rotation calculation means for each sample signal output from the MF coefficient multiplication means, and output from the second phase rotation calculation means. Second adding means for adding each sample signal
The timing detection means receives the output signal of the second addition means in addition to the output signal of the first addition means, and when any of the input signals satisfies a predetermined condition, A digital receiving circuit comprising means for identifying a corresponding received signal in addition to timing detection. A received signal holding means for holding a received signal over a plurality of samples, and a matched filter for multiplying the output signal of the received signal holding means with each sample having a noise waveform of a plurality of samples with respect to a predetermined signal as a coefficient (MF) coefficient multiplication means, first addition means for adding each sample signal output from the MF coefficient multiplication means, and timing for detecting the reception timing of the received signal from the output signal of the first addition means In a digital receiving circuit comprising detection means,
Between the MF coefficient multiplication means and the first addition means, a first phase rotation calculation means for giving a phase rotation to each sample signal of the MF coefficient multiplication means,
Second phase rotation calculation means for performing phase rotation calculation in the opposite direction to the first phase rotation calculation means for each sample signal output from the MF coefficient multiplication means, and output from the second phase rotation calculation means. Second addition means for adding each sample signal, and a signal waveform of a plurality of samples in a noiseless state with respect to a predetermined signal different from the MF coefficient multiplication means as a coefficient, and an output signal of the received signal holding means A second MF coefficient multiplication means for performing multiplication for each sample; and a third addition means for adding each sample signal output from the second MF coefficient multiplication means,
In addition to the output signal of the first addition unit, the timing detection unit receives the output signal of the second addition unit and the output signal of the third addition unit, and any one of the input signals is a predetermined signal. A digital receiving circuit comprising means for identifying the corresponding received signal in addition to detecting the timing of the received signal when the condition is satisfied. Using a timing signal output from the timing detection means for the received signal, a guard interval removing means for cutting out a signal input to the FFT means from the received signal;
FFT means for selecting the number of subcarriers to be demodulated and performing multi-carrier collective demodulation according to the identification signal output from the timing detection means for the signal output from the guard interval removing means,
Channel estimation means that uses the preamble signal of the output signal output from the FFT means, selects the number of subcarriers according to the identification signal output from the timing detection means, and estimates transmission path distortion;
With respect to the data signal of the output signal output from the FFT means, the output signal from the channel estimation means is used to select the number of subcarriers according to the identification signal output from the timing detection means and to distort the transmission path. 3. A digital receiving circuit according to claim 2, further comprising: channel equalizing means for performing channel equalization processing for removing. By installing on an information processing device,
A received signal holding function for holding a received signal over a plurality of samples, and a matched filter that has a signal waveform of a noiseless state over a plurality of samples with respect to a predetermined signal as a coefficient, and performs multiplication for each output signal of the received signal holding function (MF) coefficient multiplication function, first addition function for adding each sample signal output from the MF coefficient multiplication function, and timing for detecting the reception timing of the received signal from the output signal of the first addition function In a program for realizing a function corresponding to a digital receiving circuit having a detection function,
Implementing a first phase rotation calculation function that gives a phase rotation to each sample signal of the MF coefficient multiplication function between the MF coefficient multiplication function and the first addition function,
A second phase rotation operation function for performing phase rotation operation of the first phase rotation operation function the opposite direction to each sample signals output from the MF coefficient multiplication function, is output from the second phase rotation operation function A second addition function that adds each sample signal
The timing detection function receives the output signal of the second addition function in addition to the output signal of the first addition function, and when any of the input signals satisfies a predetermined condition, A program characterized by realizing a function of identifying a corresponding received signal in addition to timing detection. By installing on an information processing device,
A received signal holding function for holding a received signal over a plurality of samples, and a matched filter that has a signal waveform of a noiseless state over a plurality of samples with respect to a predetermined signal as a coefficient, and performs multiplication for each output signal of the received signal holding function (MF) coefficient multiplication function, first addition function for adding each sample signal output from the MF coefficient multiplication function, and timing for detecting the reception timing of the received signal from the output signal of the first addition function In a program for realizing a function corresponding to a digital receiving circuit having a detection function,
Implementing a first phase rotation calculation function that gives a phase rotation to each sample signal of the MF coefficient multiplication function between the MF coefficient multiplication function and the first addition function,
Output from the second phase rotation calculation function and the second phase rotation calculation function for performing phase rotation calculation in the opposite direction to the first phase rotation calculation function for each sample signal output from the MF coefficient multiplication function. A second addition function for adding each sample signal, and a signal waveform of a plurality of samples in a noiseless state for a predetermined signal different from the MF coefficient multiplication function as a coefficient, and an output signal of the received signal holding function Realizing a second MF coefficient multiplication function for performing multiplication for each sample and a third addition function for adding each sample signal output from the second MF coefficient multiplication function;
In addition to the output signal of the first addition function, the output signal of the second addition function and the output signal of the third addition function are input to the timing detection function. A program characterized by realizing the function of identifying the corresponding received signal in addition to detecting the timing of the received signal when the condition is satisfied. A guard interval removal function that cuts out a signal input to the FFT function from the received signal using the timing signal output from the timing detection function with respect to the received signal;
An FFT function for performing multi-carrier collective demodulation by selecting the number of subcarriers to be demodulated according to the identification signal output from the timing detection function for the signal output from the guard interval removal function,
A channel estimation function that uses the preamble signal of the output signal output from the FFT function and selects the number of subcarriers according to the identification signal output from the timing detection function to estimate the distortion of the transmission path;
For the data signal of the output signal output from the FFT function, the output signal from the channel estimation function is used to select the number of subcarriers according to the identification signal output from the timing detection function and to distort the transmission path. The program according to claim 5, which realizes a channel equalization function for performing channel equalization processing for removing a channel.   A recording medium readable by the information processing apparatus on which the program according to claim 4 is recorded.

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