JP4130784B2 - Multi-level memory circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilevel memory circuit including a circuit for generating a multivoltage for reading multilevel memory cells.
[0002]
[Prior art]
Operations of conventionally known binary flash memories and multi-value flash memories will be described. A flash memory is a nonvolatile memory element that has a control gate and a floating gate, and is an electrically erasable non-volatile memory element. The flash memory uses a tunnel current or hot electrons to inject charge into the floating gate. In “write”, electrons are injected into the floating gate and the threshold value is set to a high voltage value. In “erasing”, electrons are emitted from the floating gate and the threshold value is set to a low voltage value.
[0003]
FIG. 6A shows a threshold distribution set in a memory cell of a normal binary flash memory. When the voltage of a word line (not shown) is 0V, if the threshold is “1”, a current flows in the memory cell, and if it is “0”, no current flows. Thus, the threshold value of “1” and “0” of the memory cell is determined depending on whether or not current flows. Therefore, one memory cell stores 1-bit data.
[0004]
Next, FIG. 6B shows a multi-value threshold distribution in which 2-bit data is stored in one memory cell. This is an example of threshold distribution corresponding to four data (four values) “11”, “10”, “01”, “00”. Further, FIG. 6C shows a multi-value threshold distribution in which 3-bit data is stored in one memory cell. This is an example of threshold distribution corresponding to 8 data (8 values).
[0005]
Next, how to read data will be described. FIG. 7 is a distribution diagram of threshold values when one memory cell has four-value data. In this example, there is a threshold distribution corresponding to “11” below 0V, “10” in the 0-1V region, “01” in the 1-2V region, and “00” in the 2-3V region. Therefore, the state of “11” is set by setting the read voltage to 0V, the state of “10” is set by setting the read voltage to 1V, and the state of “01” is set by setting the read voltage to 2V. In the state of “00”, a current flows by setting the read voltage to 3V.
[0006]
FIG. 8 shows an example of the voltage waveform of the word line when the verification by the writing and the reading described above is executed. After writing is performed on a certain memory cell by 20 V, a voltage of 0 V is applied to the word line of the memory cell to detect the read voltage, and then writing is performed on the same memory cell by 20 V, and then 1 V Is applied to the word line of the memory cell, and the read voltage is detected. Next, the same memory cell is written with 20 V, and then the voltage of 2 V is applied to the word line of the memory cell. The read voltage is detected, and then the same memory cell is written with 20 V, and then the 3 V voltage is applied to the word line of the memory cell to detect the read voltage. It is verified whether or not the threshold voltage is reached. Needless to say, when it is not necessary to write data, the writing is prohibited. In the verification of FIG. 8, the word line voltage is applied as 0V → 1V → 2V → 3V. If this state is “0123”, in the actual verification, as “00112233” or “0000111112223333” There are also other patterns.
[0007]
When the reading voltage is changed in this way, it is necessary to generate voltages of 1V, 2V, and 3V. A charge pump circuit shown in FIG. 9 is generally known as a circuit for stepping down a voltage. The charge pump circuit 9 is composed of switches SW1 and SW2 and capacitors Cp and Cb. By switching the contacts in the order of a → b → a → b → a by interlocking the switches SW1 and SW2, this is repeated. When switched to the contact a side, the capacitors Cp and Cb are connected in series to the power supply, and a voltage of 1/2 of the power supply voltage V is applied. When switched to the contact b side, both capacitors Cp and Cb are separated from the power supply. In addition, since it is connected in parallel, a voltage that is 1/2 of the power supply voltage V can be extracted from both ends of the capacitor Cb. However, it is not easy to generate multiple voltages by dividing the power supply voltage into n equal parts by simply combining a plurality of charge pump circuits of FIG.
[0008]
Therefore, as a method of generating a multi-voltage of V / n, 2V / n,..., (N−1) V / n by dividing the power supply voltage V into n, as shown in FIG. A circuit configuration is known in which n resistors R having the same value are connected in series between a power supply terminal and the ground (Non-Patent Document 1).
[0009]
[Non-Patent Document 1]
Edited by Kotaro Kato, "Basics of LSI Technology", Telecommunications Association, Ohmsha, 1992, p. 222 [Problems to be solved by the invention]
However, this method has a drawback in that power consumption increases because current always flows from the power supply terminal to the ground.
[0010]
An object of the present invention is to provide a multi-value memory circuit that can easily generate a multi-voltage for reading and further reduce power consumption.
[0011]
[Means for Solving the Problems]
According to the first aspect of the present invention, in a multi-value memory circuit having a memory cell having a threshold value of n (≧ 3), n steps increase and n steps decrease in steps of 1 / n of the power supply voltage, and this is repeated. A charge reusable stepped voltage generation circuit for generating a voltage, and the voltage of 0 to n steps is increased each time the voltage generated by the stepped voltage generation circuit is increased by n steps and decreased by n steps . The multi-level memory circuit is characterized in that voltages at different steps are applied to the word lines of the memory cells.
[0012]
According to a second aspect of the present invention, in the multilevel memory circuit according to the first aspect, the stepped voltage generation circuit includes first to n-1th tank capacitors, one end of which is connected to the ground, and each of the tanks. First to (n-1) th switching elements whose one ends are individually connected to the other ends of the capacitors, one end is connected to a power supply terminal, and the other end is connected to the other ends of the first to (n-1) th switching elements. And the (n + 1) th switch element having one end connected to the other end of the first to nth switch elements and the other end grounded. By turning on each of the first, second,..., N-th normal order for a predetermined time, and then turning it on for a predetermined time in the reverse order, and repeating the turn from the normal order to the reverse order. Steady at 1 / n the voltage of the power supply terminal. Generating a stepped voltage which changes looped and a multi-level memory circuit, characterized in that.
[0013]
According to a third aspect of the present invention, in the multilevel memory circuit according to the second aspect, when the stepped voltage generation circuit turns on the switch elements in the forward order or turns on the reverse order, The on-time of a specific switch element among the first to (n + 1) th switch elements is set longer than the on-time of other switches, and a voltage generated when the specific switch element is on is applied to the word line. The multi-value memory circuit is characterized by this.
[0014]
According to a fourth aspect of the present invention, in the multilevel memory circuit according to the second aspect, the stepped voltage generation circuit is configured to specify a specific one of the first to n + 1th switching elements after the generation of the stepped voltage. A voltage generated when the switch element is turned back from the normal order to the reverse order, the on time of the specific switch element is set longer than the on time of the other switch elements, and the specific switch element is on. Is applied to the word line.
[0015]
According to a fifth aspect of the present invention, in the multilevel memory circuit according to the second aspect, the stepped voltage generation circuit is configured to identify one of the first to (n + 1) th switching elements after the generation of the stepped voltage. Only the switch element is turned on for a predetermined time, and a voltage generated at that time is applied to the word line.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
In the present embodiment, a charge-reuse type switched capacitor circuit is used to generate a stepped voltage that changes by stepping up and down in steps of 1 / n of the power supply voltage, and the voltage of a desired step among them is generated. The multi-value memory cell is read (verified) by being applied to the word line as a read voltage.
[0017]
FIG. 1 is a circuit diagram of a charge recycling type switched capacitor circuit. C1, C2, C3 are the same capacity of the tank capacitor, C _L is the output capacitor, T0, T1, T2, T3 , T4 are MOS transistors. In this circuit, as shown in the waveform diagram of FIG. 2, the MOS transistors are turned on for a predetermined time in the order of T0 → T1 → T2 → T3 → T4 (normal order), and then turned on for a predetermined time in the reverse order. By repeating the turn from the normal order to the reverse order, the power supply voltage V is changed by a quarter step (0, V / 4, V / 2, 3V / 4, V) and stepped up and down. The voltage Vout can be generated. In order to generate an n-step stepped voltage, generally, “n−1” tank capacitors and “n + 1” MOS transistors may be used.
[0018]
Fig. 3 (a) shows an example of a 4-step stepped voltage waveform generated using the above-described switched capacitor circuit. Figs. 3 (b) to 3 (d) are generated by deforming this stepped voltage. Read voltage.
[0019]
First, FIG. 3B is a diagram in which the on-time of the MOS transistor T1 in the normal order is set longer than the on-time of the other MOS transistors, and the period of the voltage V / 4 in the first step is lengthened. .
[0020]
FIG. 3C shows a case where the ON time of the MOS transistor T2 in the normal order is set longer than the ON times of the other MOS transistors, and the period of the voltage V / 2 in the second step is lengthened.
[0021]
FIG. 3D shows a case where the on-time of the MOS transistor T3 in the normal order is set longer than the on-time of the other MOS transistors, and the period of the voltage 3V / 4 at the third step is lengthened.
[0022]
The voltage of each step created as described above is inputted to the terminal PCK of the selector SEL of the quaternary memory circuit shown in FIG. 4A, whereby the word lines WL1 to WL4 and the selection signal lines SG1 and SG2 are input. It is possible to set it to a desired voltage and use it for reading or passing. In FIG. 4, BL1 and BL2 are bit lines. As shown in FIG. 4B, each selector SEL is composed of one inverter INV and two analog switches ASW. By the select signal S, 0V and the voltage of the first to third steps are input to the PCK terminal. Select one.
[0023]
In FIG. 4A, when the threshold voltage is any one of “11”, “10”, “01”, and “00” as shown in FIG. 3V is applied as a string selection voltage to the string selection signal lines SG1 and SG2, 3V is applied as a pass voltage to the word lines WL1, WL3, and WL4, and 0V is applied to the word line WL2. , 1V, 2V, or 3V is applied, the threshold value of the memory cell M1 is read, and verification can be performed. For example, if a current flows through the bit line BL1 at 0V, the threshold is "11". If a current flows through the bit line BL1 at 1V, the threshold is "10", and a current flows through the bit line BL1 at 2V. For example, if the threshold value is “01” and 3 V and a current flows through the bit line BL1, it can be verified that the threshold value is “00”.
[0024]
FIG. 5A shows the voltage waveform of the word line when verifying with the second step voltage and the third step voltage when the stepped voltage rises. This verify voltage waveform is generated by the switched capacitor circuit of FIG. In this case, the ON time of the MOS transistor T2 that generates the voltage of the second step is made longer than the ON times of the other MOS transistors. In the next verify, the ON time of the MOS transistor T3 that generates the voltage at the third step is made longer than the ON times of the other MOS transistors. It should be noted that although verification is actually performed with a voltage of 0 V or a voltage at the first step according to the written threshold value, it is omitted here.
[0025]
FIG. 5 (b) also shows the voltage waveform of the word line when verifying with the voltage of the second step and the voltage of the third step of the stepped voltage, as in FIG. 5 (a). In this case, however, the MOS transistor T1 for generating the first step is used as usual when the voltage of the second step is used after once generating the stepped voltage of four steps as shown in FIG. The MOS transistor T2 that generates the second step is set to a long ON time, and the MOS transistors T3 and T4 that generate the third and fourth steps are not turned on. When the voltage of the third step is used for the next verification, the MOS transistors T1 and T2 that generate the first step and the second step are normally turned on, and the MOS transistor T3 that generates the third step The MOS transistor T4 that generates the fourth step is not turned on with a long on-time.
[0026]
FIG. 5 (c) also shows the voltage waveform of the word line at the time of verifying with the voltage at the second step and the voltage at the third step, as in FIGS. 5 (a) and 5 (b). However, in this case, after a four-step stepped voltage as shown in FIG. 3A is once generated, only the MOS transistor T2 corresponding to the second step is turned on for a long time. In the next verify, only the MOS transistor T3 corresponding to the third step is turned on for a long time.
[0027]
As described above, the read voltage setting method can be freely changed. Needless to say, other methods may be used.
[0028]
【The invention's effect】
As described above, according to the present invention, an n-step multi-voltage obtained by dividing the power supply voltage into n equal parts can be easily generated as a read voltage for a memory cell having an n-value threshold. In particular, since a charge recycle type switched capacitor circuit is used, a multi-voltage memory circuit can be easily generated with low power consumption and a low power consumption multi-value memory circuit can be realized.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a switched capacitor circuit for generating a read voltage in a multilevel memory circuit of the present invention.
FIG. 2 is a waveform diagram of the operation of the switched capacitor circuit of FIG.
3A is a waveform diagram of a stepped voltage, and FIGS. 3B to 3D are waveform diagrams of a read voltage. FIG.
4A is a circuit diagram of a NAND flash memory, and FIG. 4B is a specific circuit diagram of a selector.
FIGS. 5A to 5C are voltage waveform diagrams of writing and verifying.
6A is an explanatory diagram of a threshold distribution of a memory cell having a binary threshold value, and FIG. 6B is an explanatory diagram of a threshold distribution of a memory cell having a quaternary threshold value; (c) is an explanatory diagram of the threshold distribution of a memory cell having eight threshold values.
FIG. 7 is an explanatory diagram of a specific threshold distribution of a memory cell having a quaternary threshold value.
FIG. 8 is a voltage waveform diagram for writing and verifying.
FIG. 9 is a circuit diagram of a voltage drop circuit that generates a voltage that is ½ of a power supply voltage.
FIG. 10 is a circuit diagram of a voltage dividing circuit that generates a 1 / n step voltage of a power supply voltage.

Claims (5)

In a multi-value memory circuit having memory cells having a threshold value of n (≧ 3) values,
A charge reusable stepped voltage generating circuit for generating a voltage that rises by n steps in steps of 1 / n of the power supply voltage, decreases by n steps, and repeats the steps; A multi-level memory circuit , wherein a voltage of a different step among the voltages of 0 to n steps is applied to a word line of the memory cell each time a voltage that rises and falls n steps is repeated . The multi-value memory circuit according to claim 1,
The stepped voltage generation circuit includes:
First to (n-1) th tank capacitors having one end connected to ground;
First to (n-1) -th switching elements each having one end connected to the other end of each tank capacitor;
An nth switch element having one end connected to a power supply terminal and the other end connected to the other end of the first to n-1st switch elements;
An (n + 1) th switch element having one end connected to the other end of the first to nth switch elements and the other end grounded;
Consists of
The switch elements are turned on for a predetermined time in the (n + 1) th, first, second,..., Nth normal order, and then turned on for a predetermined time in the reverse order. Generating a stepped voltage that changes stepwise at 1 / n of the voltage of the power supply terminal by repeating the turn back to the sequence;
A multi-value memory circuit characterized by that. The multi-value memory circuit according to claim 2,
The stepped voltage generation circuit sets an ON time of a specific switch element among the first to (n + 1) th switch elements when the switch elements are turned on in the normal order or turned on in the reverse order. A multi-value memory circuit, wherein the voltage is set longer than an ON time of a switch and a voltage generated when the specific switch element is ON is applied to the word line. The multi-value memory circuit according to claim 2,
The stepped voltage generation circuit performs folding from the normal order to the reverse order with a specific switch element among the first to (n + 1) th switch elements after the generation of the stepped voltage. A multi-value memory circuit, wherein an on-time is set longer than an on-time of another switch element, and a voltage generated when the specific switch element is on is applied to the word line. The multi-value memory circuit according to claim 2,
The stepped voltage generation circuit turns on only a specific switch element among the first to (n + 1) th switch elements for a predetermined time after the generation of the stepped voltage, and the voltage generated at that time is supplied to the word line A multi-value memory circuit, characterized by being applied to:

Images