JP4128758B2 - Image suppression filter circuit - Google Patents

Description

ここで、θ=2tan^-1(1/(ωCR))を表す。
【００５５】
イメージ信号は同相出力信号Ｉ_ＯＵＴと直交出力信号Ｑ_ＯＵＴにおいて、θがπ／２に近ければ近いほど除去でき、同相入力信号Ｉ_ＩＮと直交入力信号Ｑ_ＩＮの係数の振幅比が１に近ければ近いほど除去できる。
例えばωＣＲを１．２とした場合、数式（８）、（９）から移相器を第１の高位相精度移相器６及び第２の高位相精度移相器７の１段のみからなるイメージ抑圧フィルタ回路の出力結果である減算信号Ｘ１及び加算信号Ｘ２では同相入力信号と直交入力信号の振幅比（１／（１／ωＣＲ））が１．２となり変わらない。同相入力信号と直交入力信号の位相差は９０度である。
【００５６】
これに対して、図６に示すイメージ抑圧フィルタ回路のように、第１の高位相精度移相器６、第２の高位相精度移相器７及び第３の高振幅精度移相器１４、第４の高振幅精度移相器１５の２段の出力結果である同相出力信号Ｉ_ＯＵＴ及び直交出力信号Ｑ_ＯＵＴにおいて振幅比は１となる。
【００５７】
一方同相出力信号Ｉ_ＯＵＴ及び直交出力信号Ｑ_ＯＵＴにおける位相差△φは数式（１０）、（１１）から以下のように計算できる。ここでは同相出力信号Ｉ_ＯＵＴについてのみ数式（１０）を用いて計算するが、同様に数式（１１）から直交出力信号Ｑ_ＯＵＴについても計算できる。
【００５８】
先ず、同相入力信号Ｉ_ＩＮに乗算された{e^{j( θ - π /2)}+1/(ωCR)}は下記に式で表される。

これから、この位相φ１は下記で表される。
φ1=tan^-1(B/A) (13)
数式（１２）においてθ=2tan^-1(1/ωCR))なので、値を代入すると
φ１＝−５．６である。
【００５９】
一方、直交出力信号Ｑ_ＩＮに乗算された{e^{j( θ−π /2)}/(ωCR)+1}は下記に式で表される。
cos(θ-π/2)/(ωCR)+jsin(θ-π/2)/(ωCR)+1
={1+cos(θ-π/2)/ - (ωCR)} +jsin(θ-π/2)/(ωCR)=C+JD (14)
これから、この位相φ２は下記で表される。
【００６０】
φ2=tan^-1(D/C) (15)
数式（１５）においてθ=2tan^-1(1/ωCR))なので、値を代入すると
φ２＝−４．７°である。
【００６１】
これから、位相差△φ＝−０．９°と非常に０と近くなる。これは高振幅精度移相器を１段用いた場合の位相誤差Δφ=π/2-θ=π/2-2tan^-1(1/(ωCR))=-10.4°よりも大幅に改善されている。尚、ＣＲの積が移相器６，７と１４，１５との間で同じであれば、ＣとＲの値が移相器６，７と１４，１５との間で異なっても良い。
【００６２】
以上の結果より、本実施形態によるイメージ抑圧フィルタ回路のように高位相精度移相器と高振幅精度移相器を縦列配置することで、位相精度は−０．９°および振幅精度は１であり高精度化を広帯域に実現できる。縦列接続する段数を増やせば、位相精度および振幅精度の高精度化をさらに広い帯域に渡り実現することができる。
【００６３】
次に、図３および図４で示したブロック回路を用いた図７に本発明の第３の実施形態に係るイメージ抑圧フィルタ回路を説明する。この実施形態によるイメージ抑圧フィルタ回路は、第１の高振幅精度移相器１６、第２の高振幅精度移相器１７及び第３の高位相精度移相器８、第４の高位相精度移相器９を２段縦列接続したものである。
【００６４】
このイメージ抑圧フィルタ回路は、同相入力信号Ｉ_ＩＮが入力され、第１の出力信号Ｖ_Ｉを出力し、更に第１の出力信号Ｖ_Ｉに対して実質的に直交する位相成分に変換された第２の出力信号Ｖ_Ｑを出力する第１の高振幅精度移相器１６を具備している。
【００６５】
同相入力信号Ｉ_ＩＮに対して実質的に直交する位相成分を有する直交入力信号Ｑ_ＩＮが入力され、第３の出力信号Ｖ_Ｉが出力され、更に第３の出力信号Ｖ_Ｉに対して実質的に直交する位相成分に変換された第４の出力信号Ｖ_Ｑを出力する第２の高位相精度移相器１７を具備している。
【００６６】
図７中同相入力信号Ｉ_ＩＮ、直交入力信号Ｑ_ＩＮは、例えば図示しない前段の直交ミキサの同相出力、直交出力に相当し、それぞれ第１の高振幅精度移相器１６の入力Ｖ_ＩＮ、第２の高振幅精度移相器１７の入力信号Ｖ_ＩＮとなっている。
【００６７】
第１の高振幅精度移相器１６から出力された第１の出力信号Ｖ_Ｉから第２の高振幅精度移相器１７から出力された第４の出力信号Ｖ_Ｑは第１の減算器１０によって減算され、この減算結果を減算信号Ｘ１として出力している。
第１の高振幅精度移相器１６から出力された第２の出力信号Ｖ_Ｑ及び第２の高振幅精度移相器１７から出力された第３の出力信号Ｖ_Ｉは第１の加算器１１によって加算され、この加算結果を加算信号Ｘ２として出力している。
【００６８】
減算信号Ｘ１は第３の高位相精度移相器８に入力され、第５の出力信号Ｖ_Ｉが出力され、更に第５の出力信号Ｖ_Ｉに対して直交する位相成分に変換された第６の出力信号Ｖ_Ｑを出力している。
加算信号Ｘ２は第４の高位相精度移相器９に入力され、第７の出力信号Ｖ_Ｉ更に第７の出力信号Ｖ_Ｉに対して実質的に直交する位相成分に変換された第８の出力信号Ｖ_Ｑを出力している。
【００６９】
第３の高位相精度移相器８から出力された第５の出力信号Ｖ_Ｉから第４の高位相精度移相器９から出力された第８の出力信号Ｖ_Ｑは第２の減算回路１２によって減算され、この減算結果を同相出力信号Ｉ_ＯＵＴとする。
第３の高位相精度移相器８から出力された第６の出力信号Ｖ_Ｑ及び第４の高位相精度移相器９から出力された第７の出力信号Ｖ_Ｉは第２の加算回路１３によって加算され、この加算結果を直交出力信号Ｑ_ＯＵＴとする。
【００７０】
このようにして構成されたイメージ抑圧フィルタ回路の減算信号Ｘ１、加算信号Ｘ２、同相出力信号Ｉ_ＯＵＴ、直交出力信号Ｑ_ＯＵＴは以下の式で表される。
X1=I_INe^{j θ}-Q_IN (16)
X2=I_IN+Q_INe^{j θ} (17)
I_OUT=e^{j( π /2)}[X1e^{-j( π /2)}+(X2/ωCR)]
= e^{j( π /2)}[I_IN{e^{j( θ - π /2)}+1/(ωCR)}
-Q_INe^{-j( π /2)}{e^{j( θ - π /2)}/(ωCR)+1}] (18)
Q_OUT=(X1/ωCR)e^{-j( π /2)}+X2 = I_IN{e^{j( θ - π /2)}/(ωCR)+1}
-Q_INe^{-j( π /2)}{e^{j( θ - π /2)}+1/(ωCR)} (19)
ここで、θ=2tan^-1(1/(ωCR))を表す。
【００７１】
イメージ信号は同相出力信号と直交出力信号において位相θがπ／２に近ければ近いほど除去でき、同相入力信号と直交入力信号の係数の振幅比が１に近ければ近いほど除去できる。
例えばωＣＲを１．２とした場合、数式（１６）、（１７）から移相器を第１の高振幅精度移相器１６及び第２の高振幅精度移相器１７の１段のみからなるイメージ抑圧フィルタ回路の出力結果であるＸ１信号及びＸ２信号では同相出力信号と直交出力信号の位相誤差はΔφ=π/2-θ=π/2-2tan^-1(1/(ωCR))
= -10.4°である。同相入力信号と直交入力信号の係数の振幅差はない。
【００７２】
これに対して、図７に示すイメージ抑圧フィルタ回路のように、第６の高振幅精度移相器１６、第２の高振幅精度移相器１７及び第３の高位相精度移相器８、第４の高位相精度移相器９の２段の出力結果である同相出力信号Ｉ_ＯＵＴ及び直交出力信号Ｑ_ＯＵＴの振幅比は１となる。
【００７３】
一方同相出力信号Ｉ_ＯＵＴ及び直交出力信号Ｑ_ＯＵＴにおける位相差Δφは数式（１８）、（１９）から以下のように計算できる。ここでは同相出力信号Ｉ_ＯＵＴについてのみ数式（１８）を用いて計算するが、同様に数式（１９）から直交出力信号Ｑ_ＯＵＴについても計算できる。
【００７４】
先ず、同相入力信号Ｉ_ＩＮに乗算された{e^{j( θ - π /2)}+1/(ωCR)}は下記に式で表される。
cos(θ-π/2)+jsin(θ-π/2)+1/(ωCR) = {cos(θ-π/2)+1/(ωCR)}
+jsin(θ-π/2)=A+jB (20)
これから、この位相φ１は下記で表される。
φ1=tan^-1(B/A) (21)
数式（２１）において、θ=2tan^-1(1/(ωCR))なので、値を代入すると
φ1=-5.6°である。
【００７５】
一方、直交出力信号Ｑ_ＩＮに乗算された{e^{j( θ - π /2)}/(ωCR)+1}は下記に式で表される。
cos(θ-π/2)/(ωCR)+jsin(θ-π/2)/(ωCR)+1
={1+cos(θ-π/2)/ (ωCR)} +jsin(θ-π/2)/(ωCR)=C+jD (22)
これから、この位相φ２は下記で表される。
φ2= tan^-1 (D/C) (23)
数式（２２）において、θ=2 tan^-1(1/(ωCR))なので、値を代入すると、φ2=-4.7°である。
これから位相差Δφ=-0.9°になる。
【００７６】
一方、高振幅精度移相器を１段用いた場合の同相信号と直交信号の位相誤差はΔφ=2 tan^-1 (1/(ωCR))= -10.4°となり、本実施形態に示すイメージ抑圧フィルタの方が位相精度は大幅に改善されている。
このことから、高振幅精度移相器と高位相精度移相器を縦列接続したイメージ抑圧フィルタを用いれば、位相精度および振幅精度の高精度化を広帯域に実現できることがわかる。
この結果から、縦列接続する段数を増やせば、位相精度および振幅精度の高精度化をさらに広い帯域にわたり実現することは容易に推測できる。
【００７７】
次に、図３、図４で示したブロック図を用いて図８に本発明の第４の実施形態に係るイメージ抑圧フィルタ回路の回路構成図を示す。この実施形態によるイメージ抑圧フィルタ回路は、第１の高振幅精度移相器１６、第２の高振幅精度移相器１７及び第３の高振幅精度移相器１４、第４の高振幅精度移相器１５を２段縦列接続したものである。
【００７８】
このイメージ抑圧フィルタ回路は、同相入力信号Ｉ_ＩＮが入力され、第１の出力信号Ｖ_Ｉが出力され、更に第１の出力信号に対して実質的に直交する位相成分に変換された第２の出力信号Ｖ_Ｑを出力する第１の高振幅精度移相器１６を具備している。
【００７９】
また、同相入力信号Ｉ_ＩＮに対して実質的に直交する位相成分を有する直交入力信号Ｑ_ＩＮが入力され、第３の出力信号Ｖ_Ｉが出力され、更に第３の出力信号Ｖ_Ｉに対して実質的に直交する位相成分に変換された第４の出力信号Ｖ_Ｑを出力する第２の高振幅精度移相器１７が設けられる。
【００８０】
図８の同相入力信号Ｉ_ＩＮ、直交入力信号Ｑ_ＩＮは、例えば図示しない前段の直交ミキサの同相出力、直交出力に相当し、それぞれ第１の高振幅精度移相器１６の入力Ｖ_ＩＮ、第２の高振幅精度移相器１７の入力信号Ｖ_ＩＮとなっている。
【００８１】
第１の高振幅精度移相器１６から出力された第１の出力信号ＶＩから第２の高振幅精度移相器１７から出力された第４の出力信号Ｖ_Ｑは第１の減算器１０によって減算され、この減算結果を減算信号Ｘ１として出力している。
第１の高振幅精度移相器１６から出力された第２の出力信号Ｖ_Ｑ及び第２の高振幅精度移相器１７から出力された第３の出力信号Ｖ_Ｉは第１の加算器１１によって加算され、この加算結果を加算信号Ｘ２として出力している。
【００８２】
減算信号Ｘ１は第３の高振幅精度移相器１４に入力され、第５の出力信号Ｖ_Ｉが出力され、第５の出力信号Ｖ_Ｉに対して実質的に直交する位相成分に変換された第６の出力信号Ｖ_Ｑを出力している。
加算信号Ｘ２は第４の高振幅精度移相器１５に入力され、第７の出力信号Ｖ_Ｉが出力され、第７の出力信号Ｖ_Ｉに対して実質的に直交する位相成分に変換された第８の出力信号Ｖ_Ｑを出力している。
【００８３】
第３の高振幅精度移相器１４から出力された第５の出力信号Ｖ_Ｉから第４の高振幅精度移相器１５から出力された第８の出力信号Ｖ_Ｑは第２の減算回路１２によって減算され、この減算結果を同相出力信号Ｉ_ＯＵＴとする。
第３の高振幅精度移相器１４から出力された第６の出力信号Ｖ_Ｑ及び第４の高振幅精度移相器１５から出力された第７の出力信号Ｖ_Ｉは第２の加算回路１３によって加算され、この加算結果を直交出力信号Ｑ_ＯＵＴとする。
【００８４】
このようにして構成されたイメージ抑圧フィルタ回路の減算信号Ｘ１、加算信号Ｘ２、同相出力信号Ｉ_ＯＵＴ、直交出力信号Ｑ_ＯＵＴは以下の式で表される。
【００８５】
X1=I_INe^{j θ}-Q_IN (24)
X2=I_IN+Q_INe^{j θ} (25)
I_OUT=X1e^{j θ}-X2=2e^{j( θ + π /2)}[I_INsinθ+Q_INe^{j( π /2)}] (26)
Q_OUT=X1+X2e^{j θ}=2e^{j θ}[I_IN+Q_INsinθe^{j( π /2)}] (27)
ここで、θ=2 tan^-1(1/(ωCR))を表す。
【００８６】
イメージ信号はθが９０に近ければ近いほど除去でき、同相入力信号Ｉ_ＩＮと直交入力信号Ｑ_ＩＮの係数の振幅比が１に近ければ近いほど除去できる。
例えばωＣＲを１．２とした場合、数式（８）、（９）から前述したように、高位相精度移相器１段を用いた場合の振幅比は１．２であり、位相差は０°である。これでは振幅比が大きくずれるため、広帯域特性が得られない。
【００８７】
これに対して、図８に示すイメージ抑圧フィルタ回路のように、第１の高振幅精度移相器１６、第２の高振幅精度移相器１７及び第３の高振幅精度移相器１４、第４の高振幅精度移相器１５の２段の出力結果である同相出力信号Ｉ_ＯＵＴ及び直交出力信号Ｑ_ＯＵＴにおいて、振幅比は数式（２６）、（２７）からわかるようにｓｉｎθ＝０．９８３となる。これは高位相精度移相器を２段縦列接続した第１の実施形態に示したイメージ抑圧フィルタの振幅比１．０１７の逆数とほぼ等しくなる。
【００８８】
一方、同相入力信号Ｉ_ＩＮの位相はejo(=1)であるのに対して、直交入力信号Q_INはe^{j( π /2)}であり、正確に９０°位相が行われている。これから、明らかに高振幅精度移相器を縦列接続する場合も位相精度および振幅精度の高精度化を広帯域に実現できることがわかる。
【００８９】
図９は本発明の第５の実施形態に係るイメージ抑圧フィルタ回路の回路図である。
本実施形態は第１の実施形態で説明した広帯域高精度イメージ抑圧フィルタ回路における第１の高位相精度移相器６から出力された第１の出力信号Ｖ_Ｉが、バッファ回路１８を介して、第１の減算回路１０に入力され、第２の高位相精度移相器７から出力された第４の出力信号Ｖ_Ｑが、バッファ回路１８を介して、第１の減算器１０に入力されて減算されている。
【００９０】
第１の高位相精度移相器６から出力された第２の出力信号Ｖ_Ｑが、バッファ回路１８を介して、第１の加算回路１１に入力され、第２の高位相精度移相器７から出力された第３の出力信号Ｖ_Ｉが、バッファ回路１８を介して、第１の加算回路１１に入力されて加算されている。
【００９１】
第３の高位相精度移相器８から出力された第５の出力信号Ｖ_Ｉが、バッファ回路１８を介して、第２の減算回路１２に入力され、第４の高位相精度移相器９から出力された第８の出力信号Ｖ_Ｑが、バッファ回路１８を介して、第２の減算器１２に入力されて減算されている。
【００９２】
第３の高位相精度移相器８から出力された第６の出力信号Ｖ_Ｑが、バッファ回路１８を介して、第２の加算回路１３に入力され、第４の高位相精度移相器９から出力された第７の出力信号Ｖ_Ｉが、バッファ回路１８を介して、第２の加算回路１３に入力されて加算されている。バッファ回路１８は、電圧電流変換器を含み、加算及び減算はバッファ回路１８の出力電流を用いた電流加算及び電流減算で行なっている。
【００９３】
図９には記していないが、第１の減算回路１０及び第１の加算回路１１で電流減算及び電流加算した後、その減算信号Ｘ１及び加算信号Ｘ２は例えば抵抗を用いて電圧に変換され第３の高位相精度移相器８及び第４の高位相精度移相器９に入力される。
【００９４】
このような広帯域高精度イメージ抑圧フィルタ回路は、接続段数を増やせば、さらに精度が高くなる。
ここでバッファ回路１８を用いた理由は、図１（ａ）に示すように高位相精度移相器の特性は、Ｖ_Ｉ，Ｖ_Ｑ出力端子からみた出力側が高インピーダンスであることが条件とされ、バッファ回路により高インピーダンスを実現するためである。さらに、このバッファ回路１８が高位相精度移相器での損失を補うことで、雑音特性劣化を低減できる。
【００９５】
このバッファ回路１８は、例えば図１０に示すような一般に用いられる線形化を施した差動回路で簡単に実現できる。図１０のトランジスタＱ１、トランジスタＱ２のエミッタ電極が抵抗ＲＥにより接続されている。それぞれコレクタ側から電流−Ｉ_ＯＵＴ、＋Ｉ_ＯＵＴが入力され、ベースにはベース電圧＋Ｖ_ＩＮ、−Ｖ_ＩＮが出力されている。
【００９６】
図１１は、図９に示したイメージ抑圧フィルタ回路の具体的な例を示す回路図である。
この回路図に示すイメージ抑圧フィルタ回路の構成は、基本的に図９に示したものと同様であるが、ＩＣ化に適した差動回路構成を用いている。
図１１中、Ｃ_ＡＣはＡＣカップリングキャパシタを表し、直流成分を除去するために一用いたものである。Ｒ_Ｌ１，Ｒ_Ｌ２は電圧電流変換された電流を電圧に変換するために用いた負荷抵抗を表す。各段に用いられる移相器は、図９に示した高位相精度移相器を用いている。
【００９７】
図１１に示すように、上段左側は同相入力信号＋Ｉ_ＩＮ、−Ｉ_ＩＮが入力され、上段右側は直交入力信号＋Ｑ_ＩＮ、−Ｑ_ＩＮが入力されている。第１の出力信号Ｉ_Ｉは、第４の出力信号Ｑ_Ｑと接続され減算されている。第２の出力信号Ｉ_Ｑは、第３の出力信号Ｑ_Ｉと接続され加算されている。このようにして、それぞれ減算信号Ｘ１及び加算信号Ｘ２が形成される。
【００９８】
第５の出力信号Ｉ_Ｉは、第８の出力信号Ｑ_Ｑと接続され減算されている。第６の出力信号Ｉ_Ｑは、第７の出力信号＋Ｑ_Ｉと接続され加算されている。このようにして、同相出力信号Ｉ_ＯＵＴ、Ｑ_ＯＵＴとして出力される。
【００９９】
図１１には示さないが、この広帯域高精度イメージ抑圧フィルタ回路は、接続段数を増やせば、さらに精度が高くなる。
【０１００】
図１２は本発明の第６の実施形態に係るイメージ抑圧フィルタ回路の回路図である。
本実施形態は第２の実施形態で説明した広帯域高精度イメージ抑圧フィルタ回路における第１の高位相精度移相器６から出力された第１の出力信号Ｖ_Ｉが、バッファ回路１８を介して、第１の減算回路１０に入力され、第２の高位相精度移相器７から出力された第４の出力信号Ｖ_Ｑが、バッファ回路１８を介して、第１の減算器１０に入力されて減算されている。
【０１０１】
第１の高位相精度移相器６から出力された第２の出力信号Ｖ_Ｑが、バッファ回路１８を介して、第１の加算回路１１に入力され、第２の高位相精度移相器７から出力された第３の出力信号Ｖ_Ｉが、バッファ回路１８を介して、第１の加算回路１１に入力されて加算されている。
【０１０２】
第３の高振幅精度移相器１４から出力された第５の出力信号Ｖ_Ｉが、バッファ回路１８を介して、第２の減算回路１２に入力され、第４の高振幅精度移相器１５から出力された第８の出力信号Ｖ_Ｑが、バッファ回路１８を介して、第２の減算器１２に入力されて減算されている。
【０１０３】
また、第３の高振幅精度移相器１４から出力された第６の出力信号Ｖ_Ｑが、バッファ回路１８を介して、第２の加算回路１３に入力され、第４の高振幅精度移相器１５から出力された第７の出力信号Ｖ_Ｉが、バッファ回路１８を介して、第２の加算回路１３に入力されて加算されている。バッファ回路１８は、電圧電流変換器を含み、加算及び減算はバッファ回路１８の出力電流を用いた電流加算及び電流減算で行なっている。
【０１０４】
図１２には記していないが、第１の減算回路１０及び第１の加算回路１１で電流減算及び電流加算した後、その減算信号Ｘ１及び加算信号Ｘ２は例えば抵抗を用いて電圧に変換され第３の高振幅精度移相器１４及び第４の高振幅精度移相器１５に入力される。
【０１０５】
このような広帯域高精度イメージ抑圧フィルタ回路は、接続段数を増やせば、さらに精度が高くなる。
【０１０６】
本実施形態のイメージ抑圧フィルタ回路において、バッファ回路を用いた主な理由は、以下の二つによる。一つは、図１（ｃ）で説明した高位相精度移相器の特性がＶ_Ｉ，Ｖ_Ｑ出力端子からみた出力側が高インピーダンスであることが条件とされることであり、もう一つは、図２（ｂ）で説明した高振幅精度移相器の特性がＶ_Ｉ出力端子からみた出力側が高インピーダンスであることが条件とされるためである。
【０１０７】
さらに、このバッファ回路１８が高位相精度移相器および高振幅精度移相器での損失を補うことで、つまりバッファ回路１８に利得を持たせることで、雑音特性劣化を低減することできるためである。バッファ回路は、図１０に示すような一般に用いられる線形化を施した差動回路で簡単に実現できる。
【０１０８】
高振幅精度移相器を初段、高位相精度移相器を次段とした第３の実施形態に示す構成にしても、同様な効果が得られる。
【０１０９】
図１３は、図１２に示した広帯域高精度イメージ抑圧フィルタ回路の具体的な一例を示すものである。基本的には図１１の構成と同様であるが、ＩＣ化に適した差動回路構成を用いている。図１３中、Ｃ_ＡＣはＡＣカップリングキャパシタを表し、直流成分を除去するために用いたものである。Ｒ_Ｌ１，Ｒ_Ｌ２は電圧電流変換された電流を電圧に変換するために用いた負荷抵抗を表す。
【０１１０】
初段に用いられる移相器は、図１（ａ）に示した高位相精度移相器を用いており、次段に用いた移相器は、図２（ａ）に示した高振幅精度移相器を用いている。
【０１１１】
図１３に示すように、上段左側は同相入力信号＋Ｉ_ＩＮ、−Ｉ_ＩＮが入力され、上段右側は直交入力信号＋Ｑ_ＩＮ、−Ｑ_ＩＮが入力されている。第１の出力信号Ｉ_Ｉは、第４の出力信号Ｑ_Ｑと接続され減算されている。第２の出力信号Ｉ_Ｑは、第３の出力信号Ｑ_Ｉと接続され加算されている。このようにして、それぞれ減算信号Ｘ１＝Ｉ_Ｉ−Ｑ_Ｑ及び加算信号Ｘ２＝Ｉ_Ｑ＋Ｑ_Ｉが形成される。
【０１１２】
第５の出力信号Ｉ_Ｉは、第８の出力信号Ｑ_Ｑと接続され減算されている。第６の出力信号Ｉ_Ｑは、第７の出力信号Ｑ_Ｉと接続され加算されている。こうして同相出力信号Ｉ_ＯＵＴおよびＱ_ＯＵＴが得られる。
【０１１３】
図１３には示さないが、この広帯域高精度イメージ抑圧フィルタ回路は、接続段数を増やせば、さらに精度が高くなる。
【０１１４】
高振幅精度移相器を初段、高位相精度移相器を次段とした第３の実施形態のイメージ抑圧フィルタ回路構成にしても、同様な効果が得られる。
【０１１５】
図１４は本発明の第７の実施形態に係るイメージ抑圧フィルタ回路の回路図である。本実施形態は第４の実施形態で説明した広帯域高精度イメージ抑圧フィルタ回路における第１の高振幅精度移相器１６から出力された第１の出力信号Ｖ_Ｉが、バッファ回路１８を介して、第１の減算回路１０に入力され、第２の高振幅精度移相器１７から出力された第４の出力信号Ｖ_Ｑが、バッファ回路１８を介して、第１の減算器１０に入力されて減算されている。
【０１１６】
第１の高振幅精度移相器１６から出力された第２の出力信号Ｖ_Ｑが、バッファ回路１８を介して、第１の加算回路１１に入力され、第２の高振幅精度移相器１７から出力された第３の出力信号Ｖ_Ｉが、バッファ回路１８を介して、第１の加算回路１１に入力されて加算されている。
【０１１７】
第３の高振幅精度移相器１４から出力された第５の出力信号Ｖ_Ｉが、バッファ回路１８を介して、第２の減算回路１２に入力され、第４の高振幅精度移相器１５から出力された第８の出力信号Ｖ_Ｑが、バッファ回路１８を介して、第２の減算器１２に入力されて減算されている。
【０１１８】
第３の高振幅精度移相器１４から出力された第６の出力信号Ｖ_Ｑが、バッファ回路１８を介して、第２の加算回路１３に入力され、第４の高振幅精度移相器１５から出力された第７の出力信号Ｖ_Ｉが、バッファ回路１８を介して、第２の加算回路１３に入力されて加算されている。バッファ回路１８は、電圧電流変換器を含み、加算及び減算はバッファ回路１８の出力電流を用いた電流加算及び電流減算で行なっている。
【０１１９】
図１４には記していないが、第１の減算回路１０及び第１の加算回路１１で電流減算及び電流加算した後、その減算信号Ｘ１及び加算信号Ｘ２は例えば抵抗を用いて電圧に変換され第３の高振幅精度移相器１４及び第４の高振幅精度移相器１５に入力される。
【０１２０】
このような広帯域高精度イメージ抑圧フィルタ回路は、接続段数を増やせば、さらに精度が高くなる。
【０１２１】
本実施形態においてバッファ回路１８を用いた主な理由は、図２（ｂ）で説明した高振幅精度移相器の特性が、Ｖ_Ｉ出力端子からみた出力側が高インピーダンスであることが条件とされるためである。さらに、このバッファ回路１８が高振幅精度移相器での損失を補うことで、つまりバッファ回路１８に利得を持たせることで、雑音特性劣化を低減することできるためである。バッファ回路１８は、図１０に示すような一般に用いられる線形化を施した差動回路で簡単に実現できる。
【０１２２】
図１５は、図１４に示した広帯域高精度イメージ抑圧フィルタ回路の具体的な一例を示すものである。基本的に図１４の構成と同様であるが、ＩＣ化に適した差動回路構成を用いている。図１５中、Ｒ_Ｌ１，Ｒ_Ｌ２は電圧電流変換された電流を電圧に変換するために用いた負荷抵抗を表す。本構成で用いられる移相器は、図２（ａ）に示した高振幅精度移相器を用いている。
【０１２３】
図１５に示すように、上段左側は同相入力信号＋Ｉ_ＩＮ、−Ｉ_ＩＮが入力され、上段右側は直交入力信号＋Ｑ_ＩＮ、−Ｑ_ＩＮが入力されている。第１の出力信号Ｉ_Ｉは、第４の出力信号Ｑ_Ｑと接続され減算されている。第２の出力信号Ｉ_Ｑは、第４の出力信号＋Ｑ_Ｉと接続され加算されている。このようにして、それぞれ減算信号Ｘ１＝Ｉ_Ｉ−Ｑ_Ｑ及び加算信号Ｘ２＝Ｉ_Ｑ＋Ｑ_Ｉが形成される。
【０１２４】
第５の出力信号Ｉ_Ｉは、第８の出力信号Ｑ_Ｑと接続され減算されている。第６の出力信号Ｉ_Ｑは、第７の出力信号Ｑ_Ｉと接続され加算されている。こうしてこの減算結果が同相出力信号Ｉ_ＯＵＴ，Ｑ_ＯＵＴを出力する。
【０１２５】
図１５では示していないが、本図による広帯域高精度イメージ抑圧フィルタ回路は、接続段数を増やせば、さらに精度が高くなる。
【０１２６】
図１６（ａ）は、図１（ａ）で説明した高位相精度移相器のＶ_ＩＮにキャパシタＣＡＣ、抵抗ＲＬ、電流源Ｉ_ＩＮを接続したものである。図１６（ｂ）は、図１（ａ）で説明した高位相精度移相器のＶ_ＩＮに抵抗Ｒ_Ｌ、電流源Ｉ_ＩＮを接続し電流駆動したものである。
【０１２７】
高位相精度移相器を電流駆動することで、移相器の利得を高める効果がある。この高利得、高位相精度移相器を前述した各実施形態に示したイメージ抑圧フィルタ回路に用いることで、雑音に関する特性が改善されることになる。
【０１２８】
図１７は、送受信システムの構成図である。これによると、受信（ＲＸ）側において、アンテナ２０で受けた受信信号はデュプレクサ（ＤＵＰ）２１、バンドパスフィルタ（ＢＰＦ）２３、低雑音増幅器（ＬＮＡ）２４を介して直交ミキサ（ＭＩＸ１）２５に入力される。ここで、バンドパスフィルタ（ＢＰＦ）２３は、所望の帯域近辺の信号を取り込むことを目的としており、イメージ信号をある程度低減できるものであればよい。
【０１２９】
次に、直交ミキサ（ＭＩＸ１）２５の出力は各実施形態で説明した広帯域イメージ抑圧フィルタ回路（ＩＲＳＣ）２６に入力される。直交ミキサ（ＭＩＸ１）２５の同相Ｉ／直交Ｑチャネル信号に含まれていたイメージ信号は広帯域イメージ抑圧フィルタ回路（ＩＲＳＣ）２６により低減され、次段の直交ミキサ（ＭＩＸ２）２７に入力される。
【０１３０】
図１８では、広帯域イメージ抑圧フィルタ（ＩＲＳＣ）２６の一方の出力（ここでは同相出力信号Ｉ_ＯＵＴのみ次段の直交ミキサ（ＭＩＸ２）２７に入力されており、他方の出力（ここでは直交出力信号Ｑ_ＯＵＴ）は廃棄している。しかしながら、場合によっては、両方の出力を用いることも可能である。直交ミキサ（ＭＩＸ２）２７は、ベースバンド信号となった同相Ｉ／直交Ｑ信号をＡ／Ｄ変換器に出力する。
【０１３１】
次に、送信（ＴＸ）側を説明する。先ずべースバンド信号の同相ＩＣＨ、直交ＱＣＨ信号が９０度移相器、ミキサー、加算器からなる直交変調器（ＱＭＯＤ１）２８により所望のＩＦ信号に変換される。このＩＦ信号は各実施形態で説明した広帯域イメージ抑圧フィルタ回路（ＩＲＳＣ）２９に入力される。
【０１３２】
この広帯域イメージ抑圧フィルタ回路（ＩＲＳＣ）２９は、イメージ信号を除去するために用いられているものではなく、ＩＦ信号を広帯域にわたり９０度位相の異なる同相Ｉ／直交Ｑ信号を生成するために用いている。
【０１３３】
これは、数式（６）、（７）、（１０）、（１１）、（１８）、（１９）、（２６）、（２７）に示す同相出力信号Ｉ_ＯＵＴ及び直交出力信号Ｑ_ＯＵＴを求める式からわかるように、各実施形態の広帯域イメージ抑圧フィルタ回路の同相入力信号Ｉ_ＩＮ及び直交入力信号Ｑ_ＩＮの一方を入力し、他方は入力しない場合、互いに９０度位相の異なる信号が出力されることを利用したものである。
【０１３４】
次に、この広帯域イメージ抑圧フィルタ回路（ＩＲＳＣ）２９の出力は、直交変調器（ＱＭＯＤ２）３０に入力され、イメージのないＲＦ信号が生成される。この出力されたＲＦ信号は、電力増幅器（ＰＡ）３１、バンドパスフィルタ（ＢＰＦ）３２、デュプレクサ（ＤＵＰ）２１、アンテナ２０を介して空間に出力される。
【０１３５】
ＲＦ用局部発振信号ＬＯ_ＲＦ、ＩＦ用局部発振信号ＬＯ_ＩＦは、受信用同相Ｉ／直交Ｑミキサまたは送信用直交変調器に９０度移相器（π／２）を介して入力される。この９０度移相器にも、各実施形態で説明した広帯域イメージ抑圧フィルタ回路を用いることができる。また、図中、点線で囲んだ部分は１つのＩＣチップに組み込むことが可能である。
【０１３６】
【発明の効果】
以上説明したように本発明は、減算回路及び加算回路を介して移相器を縦列接続することで、広帯域にわたって高精度のイメージ抑圧フィルタ回路を実現できる。またこれをＩＣ化することで無線部に必要なイメージ抑圧等の外部フィルタを削除できるので、無線部の小型化、低価格化できる。
【図面の簡単な説明】
【図１】高位相精度移相器の回路図、入力周波数出力振幅特性図、入力周波数出力位相特性図を示す。
【図２】高位相精度移相器の回路図、入力周波数出力振幅特性図、入力周波数出力位相特性図を示す。
【図３】高位相精度移相器のブロック図。
【図４】高振幅精度移相器のブロック図。
【図５】本発明の第１の実施形態に係る広帯域高精度イメージ抑圧フィルタ回路の回路図。
【図６】本発明の第２の実施形態に係る広帯域高精度イメージ抑圧フィルタ回路の回路図。
【図７】本発明の第３の実施形態に係る広帯域高精度イメージ抑圧フィルタ回路の回路図。
【図８】本発明の第４の実施形態に係る広帯域高精度イメージ抑圧フィルタ回路の回路図。
【図９】本発明の第５の実施形態に係る広帯域高精度イメージ抑圧フィルタ回路の回路図。
【図１０】線形化を施した作動回路で構成されるバッファ回路図。
【図１１】本発明の第５の実施形態に係る広帯域高精度イメージ抑圧フィルタ回路のＩＣ化に適した回路図。
【図１２】本発明の第６の実施形態に係る広帯域高精度イメージ抑圧フィルタ回路の回路図。
【図１３】本発明の第６の実施形態に係る広帯域高精度イメージ抑圧フィルタ回路のＩＣ化に適した回路図。
【図１４】本発明の第７の実施形態に係る広帯域高精度イメージ抑圧フィルタ回路の回路図。
【図１５】本発明の第７の実施形態に係る広帯域高精度イメージ抑圧フィルタ回路のＩＣ化に適した回路図。
【図１６】利得を高めた高位相精度移相器の回路図。
【図１７】本発明によるイメージ抑圧フィルタ回路を用いた送受信機のブロック図。
【符号の説明】
６…第１の高位相精度移相器
７…第２の高位相精度移相器
８…第３の高位相精度移相器
９…第４の高位相精度移相器
１０…第１の減算器
１１…第１の加算器
１２…第２の減算器
１３…第２の加算器
１４…第３の高振幅精度移相器
１５…第４の高振幅精度移相器
１６…第１の高振幅精度移相器
１７…第２の高振幅精度移相器
１８…バッファ回路
１０１…第１端子
１０２…第２端子
１０３…第３端子
１０４…第４端子
１０５…第１の抵抗
１０６…第１のキャパシタ
１０７…第２の抵抗
１０８…第２のキャパシタ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image suppression filter circuit.
[0002]
[Prior art]
In recent years, many wireless system terminals such as mobile phones and PHS have become widespread. As one of the wireless systems, there is a system in which a wireless terminal and a base station communicate with each other wirelessly and the base stations communicate with each other by wire.
[0003]
A wireless terminal for transmitting and receiving with a base station by radio waves includes an antenna, a low noise amplifier (LNA), a frequency converter (or mixer), an intermediate frequency bandpass filter (IF-BPF), an intermediate frequency mixer (IF-MIX), In general, the heterodyne system includes a low-pass filter (LPF) and an AD converter (ADC).
[0004]
With such a circuit configuration, the wireless terminal receives the high frequency radio wave RF flying from the base station as a high frequency signal by the antenna of the wireless terminal, and amplifies it by the low noise amplifier. The amplified high frequency signal is frequency converted from a high frequency RF to an intermediate frequency IF by a frequency converter, filtered by an intermediate frequency bandpass filter (IF-BPF), and digitally converted by an AD converter through an intermediate frequency mixer and a low pass filter. Converted to a signal.
As an integrated circuit necessary for a wireless terminal, there is an image suppression filter circuit for removing an image signal mixed in a desired frequency.
[0005]
The image signal does not require a frequency to be converted to the same frequency band as the intermediate frequency band to which the desired wave is converted when the received radio wave (desired wave) is converted from a high frequency to an intermediate frequency by the frequency converter. It is a wave.
[0006]
The frequency converter outputs an intermediate frequency obtained by subtracting the local frequency from the frequency of the desired wave. However, this frequency converter also converts the frequency component obtained by subtracting this intermediate frequency band from the local signal to the same intermediate frequency band. This frequency component is an image wave and becomes an unnecessary wave.
[0007]
In addition, signals of various frequencies are transmitted and received by various systems. For a desired wave of one system, a desired wave of another system becomes an interference wave, which becomes an image signal.
[0008]
In addition, broadband noise generated by the transistor itself becomes an image signal. Wideband noise includes thermal noise and shot noise.
[0009]
Such an image signal is overlapped with the same frequency band as the frequency-converted desired wave. All the signals other than the desired wave are unnecessary waves. However, since the image signal is converted to the same frequency as the desired wave, an image suppression filter circuit for removing the image signal is necessary.
[0010]
In the image suppression filter circuit used in the frequency converter section of the reception system of the wireless terminal described above, first, the high frequency RF signal is distributed into two. One RF signal is frequency-converted to an in-phase signal by a local signal of a cosine wave generated by a first 90-degree phase shifter connected to the local oscillation signal, and the other RF signal is shifted to the first 90-degree phase. The frequency is converted into a quadrature signal by a sine wave local signal generated by the phase shifter.
[0011]
Next, the quadrature signal frequency-converted with the sine wave is further delayed by 90 degrees by the second 90-degree phase shifter, and added by the adder with the in-phase signal frequency-converted by the cosine wave, whereby the image wave Repress.
[0012]
By the way, if the frequency conversion is simply performed using the local signal without removing the image signal, the signal is folded back, and the desired wave signal and the image signal are converted to the same frequency. That is, the desired wave signal is contaminated by the image signal. Therefore, if image suppression is performed, the image wave can be reduced while maintaining the desired wave signal.
[0013]
In other words, if the conversion gain of the desired wave signal is 1, the conversion gain of the image wave can be a small number of 1 or less (for example, about 0.01). Thereby, it is possible to prevent the desired wave signal from being contaminated by the image wave.
[0014]
In this image suppression filter, even if the quality factor of the inductor and the capacitor is reduced due to the integration of an IC, a satisfactory filter function can be achieved to some extent.
[0015]
For such an image suppression filter circuit, a high phase accuracy phase shifter whose phase accuracy is high and constant in a wide band or a high amplitude accuracy phase shifter whose output amplitude accuracy is high and constant in a wide band is used. The high phase accuracy phase shifter has good phase accuracy according to the applied frequency, but since the output amplitude is not constant, a sufficient filter characteristic cannot be obtained in a wireless system used in a wide band. The high amplitude accuracy phase shifter has good output amplitude accuracy according to the applied frequency, but since the output phase accuracy is not constant, sufficient filter characteristics cannot be obtained as a wireless system used in a wide band.
[0016]
[Problems to be solved by the invention]
As shown above, high phase accuracy phase shifter and high amplitude accuracy phase shifter cannot increase phase accuracy and amplitude accuracy simultaneously in a wide band, and an image suppression filter used in a broadband wireless system is manufactured on an IC. could not.
[0017]
In addition, since the desired wave band is narrow in conventional portable radio systems, it is only necessary that the phase accuracy and output amplitude accuracy of the 90-degree phase shifter be high only in a predetermined narrow band. However, in the future radio system, since the amount of information is expected to increase, the desired wave band becomes wide, and the 90-degree phase shifter is also required to maintain high accuracy in the wide band.
[0018]
However, in the high phase accuracy phase shifter and the high amplitude accuracy phase shifter, the output amplitude and the output phase fluctuate depending on the frequency, respectively, and there is a problem that the image suppression ratio cannot be increased in a broadband wireless system.
[0019]
An object of the present invention is to provide an image suppression filter circuit that is made into an IC that can also be used in a broadband wireless system.
[0020]
[Means for Solving the Problems]
According to a first aspect of the present invention, a first phase shifter that receives an in-phase input signal and outputs a first output signal and a second output signal having a phase component substantially orthogonal to the first output signal; A second phase shifter for receiving a quadrature input signal having a phase component substantially orthogonal to the in-phase input signal and outputting a third output signal and a fourth output signal having a phase component orthogonal to the third output signal; A first subtractor for subtracting the fourth output signal from the first output signal and outputting a subtracted signal; a first subtractor for adding the second output signal and the third output signal; And a third output signal that receives the subtraction signal and outputs a fifth output signal having a second phase component to the subtraction signal and a sixth output signal having a phase component orthogonal to the fifth output signal. A phase shifter and the addition signal are received and the addition signal is A fourth phase shifter that outputs a seventh output signal having the second phase component and an eighth output signal having a phase component orthogonal to the seventh output signal, and the eighth output from the fifth output signal. A second subtractor for subtracting the signal and outputting the subtraction result as an in-phase output signal; a second addition for adding the sixth output signal and the seventh output signal and outputting the addition result as a quadrature output signal; An image suppression filter circuit is provided.
[0021]
According to a second aspect of the present invention, a first phase shifter that receives an in-phase input signal and outputs a first output signal and a second output signal having a phase component substantially orthogonal to the first output signal; A second phase shifter for receiving a quadrature input signal having a phase component substantially orthogonal to the in-phase input signal and outputting a third output signal and a fourth output signal having a phase component orthogonal to the third output signal; A first subtracter that subtracts the fourth output signal from the first output signal and outputs a subtracted signal; a second subtractor that adds the second output signal and the third output signal; and outputs an added signal. A pre-stage phase shifter having a first adder, a fifth output signal that receives the subtraction signal, has a second phase component with respect to the subtraction signal, and has a phase component orthogonal to the fifth output signal A third phase shifter that outputs six output signals, and the addition signal A fourth phase shifter for outputting a seventh output signal having the second phase component and an eighth output signal having a phase component orthogonal to the seventh output signal to the sum signal; A second subtracter that subtracts the eighth output signal from the output signal and outputs the subtraction result as an in-phase output signal; adds the sixth output signal and the seventh output signal; And an image suppression filter circuit including a plurality of second-stage phase shifters each including a second adder that outputs the second adder.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. First, a high phase accuracy phase shifter and a high amplitude accuracy phase shifter used in the image suppression filter circuit according to the embodiment of the present invention will be described with reference to FIGS. 1 and 2.
[0023]
FIG. 1A shows a high phase accuracy phase shifter. According to this high phase accuracy phase shifter, one end of the first resistor R105 is connected to the first end 101, and one end of the first capacitor C106 is connected to the first end 101. The other end of the first capacitor C106 is connected to the second end 102. The second end 102 is connected to one end of the second resistor R107. The third end 103 is connected to the other end of the second resistor R107. One end of the second capacitor C108 is connected to the third end 103. The fourth end 104 is connected to the other end of the second capacitor C108. The fourth end 104 is connected to the other end of the first resistor R105. That is, the high phase accuracy phase shifter is constituted by a CR bridge circuit.
[0024]
Input signal V of this CR bridge circuit_INIs input as a potential difference between the fourth end 104 and the second end 102, and the output signal V_IAnd V_Q(For example, V within a range of ± 10%._I) Are output as potentials at the third end and the first end, respectively. Where R of the first and second resistors, C of the first and second capacitors, the input signal V_INAnd output signal V_I, V_QIndicates each symbol and is also used as a value of a mathematical expression described later. In this case, the resistance values of the first resistor and the second resistor are the same. In this case, the first capacitor and the second capacitor have the same value.
[0025]
As shown in the input frequency-output amplitude characteristic of FIG. 1B, this high phase accuracy phase shifter has a V_I, V_QAs shown in the input frequency-output phase characteristic of FIG._I, V_QThe output phase difference is a constant π / 2 (90 degrees) regardless of the input frequency, and is characterized in that phase conversion is performed with high accuracy. This characteristic is clear from the transfer function of the high phase accuracy phase shifter shown below.
[0026]
V_I/ V_IN = R / (R + (1 / jωC)) (1)
V_Q/ V_IN = (1 / jωC) / (R + (1 / jωC)) (2)
In this case V_IAnd V_QThe amplitude ratio (amplitude accuracy) is R: 1 / jωC, and the phase error is 0 degrees (accurately shifted by 90 degrees).
This phase shifter with high phase accuracy has high and constant phase accuracy over a wide band. However, since the output amplitude is not constant, a radio system used in a wide band cannot sufficiently remove an image signal as will be described later.
[0027]
FIG. 2A shows a high amplitude accuracy phase shifter. According to this high amplitude precision phase shifter, the first end 101 is connected to one end of the first resistor R105, and one end of the first capacitor C106 is connected to the first end 101. The second end 102 is connected to the other end of the first capacitor C106. One end of a second resistor R107 is connected to the second end 102. The third end 103 is connected to the other end of the second resistor R107, and one end of the second capacitor C108 is connected to the third end 103. The fourth end 104 is connected to the other end of the second capacitor C108. The fourth end 104 is connected to the other end of the first resistor R105.
[0028]
As described above, the high amplitude accuracy phase shifter is constituted by a CR bridge circuit. Input signal V of this CR bridge circuit_INIs input as a potential difference between the fourth end 104 and the second end 102, and the output signal V_IIs output as a potential difference between the third end 103 and the front end 106, and V_Q(For example, V within a range of ± 10%._I(A signal substantially orthogonal to) is output as a potential difference between the fourth end and the second end. Where R of the first and second resistors, C of the first and second capacitors, the input signal V_INAnd output signal V_I, V_QIndicates each symbol and is also used as a value of a mathematical expression described later. In this case, the resistance values of the first resistor and the second resistor are the same. In this case, the first capacitor and the second capacitor have the same value.
[0029]
As shown in the input frequency-output amplitude characteristic of FIG. 2B, this high amplitude accuracy phase shifter has an output amplitude ratio V_I, V_QHowever, as shown in the input frequency-output phase characteristic of FIG. 2C, the output phase difference varies depending on the input frequency. This characteristic is also evident from the transfer function of the phase shifter shown below.
V_I/ V_IN = V_I/ V_Q = (R- (1 / jωC)) / (R + (1 / jω) C)) (3)
In this case V_IAnd V_QHas an amplitude ratio (amplitude accuracy) of 1 and a phase error of 2 tan-1 (1 / (ωCR)).
[0030]
This high amplitude accuracy phase shifter has a constant output amplitude accuracy in a wide frequency range, but has a low output phase accuracy, so that sufficient filter characteristics can be obtained for a radio system used in a wide band as described later. Absent.
[0031]
In order to simplify the following description, the high phase accuracy phase shifter and the high amplitude accuracy phase shifter shown in FIGS. 1 (a) and 2 (a), respectively, are shown as block circuits in FIGS. V of the block circuit of FIGS._INIs the input signal, V_IIs the first output signal, V_QIs the first output signal V_IRepresents a second output signal converted into a phase component orthogonal to. A value enclosed by a square in the block circuit represents a phase, and a value written below the square represents an amplitude.
[0032]
Output signal V of the high phase accuracy phase shifter shown in FIG._IPhase of the output signal 0_IThe output amplitude was set to 1. At this time, the output signal V_QOutput phase is independent of frequency and output signal V_IIs set to -π / 2 and the output signal V_QIs set to 1 / ωCR which varies with the frequency ω.
[0033]
Output signal V of the high amplitude accuracy phase shifter shown in FIG._QThe output phase of the output signal V_QThe output amplitude was set to 1. Output signal V_IOutput phase is V_QΘ = 2tan for the output phase of^-1As shown in the graph of FIG. 2C, (1 / ωCR) varies depending on the frequency ω, but the output signal V_IThe output amplitude of was 1. Thus, the output amplitude ratio V_I/ V_Q= 1.
[0034]
Next, an image suppression filter circuit according to the first embodiment of the present invention using the block circuits of FIGS. 3 and 4 will be described with reference to FIG. The image removal filter circuit according to the first embodiment includes a first high phase accuracy phase shifter 6, a second high phase accuracy phase shifter 7, a third high phase accuracy phase shifter 8, and a fourth high phase. The precision phase shifter 9 is configured by connecting two stages in cascade.
[0035]
This image suppression filter circuit uses the common-mode input signal I_INAnd the first output signal V_IIn addition, for example, the first output signal V within a range of ± 10%._IThe second output signal V converted to a phase component substantially orthogonal to_QThe first high phase accuracy phase shifter 6 is provided.
[0036]
In-phase input signal I_INInput signal Q having a phase component substantially orthogonal to_INAnd the third output signal V_IAnd the third output signal V_IOutput signal V converted to a phase component substantially orthogonal to_QA second high phase accuracy phase shifter 7 is provided.
[0037]
In-phase input signal I shown in FIG._IN, Quadrature input signal Q_INCorresponds to the in-phase output and the quadrature output of the preceding quadrature mixer (not shown), for example, and the input V of the first high phase accuracy phase shifter 6 is_IN, The input signal V of the second high phase shift degree phase shifter 7_INIt has become.
[0038]
The first output signal V output from the first high phase accuracy phase shifter 6_ITo a fourth output signal V output from the second high phase accuracy phase shifter 7._QIs subtracted by the first subtracter 10, and the subtraction result is output as a subtraction signal X1.
The second output signal V output from the first high phase accuracy phase shifter 6_QAnd the third output signal V output from the second high phase accuracy phase shifter 7._IAre added by the first adder 11, and the addition result is output as an addition signal X2.
[0039]
The subtraction signal X1 is input to the third high phase accuracy phase shifter 8, and the third high phase accuracy phase shifter 8 receives the fifth output signal V._IAnd the fifth output signal V_IA sixth output signal having a phase orthogonal to_QIs output.
The addition signal X2 is input to the fourth high phase accuracy phase shifter 9, and the fourth high phase accuracy phase shifter 9 receives the seventh output signal V._IAnd the seventh output signal V_IOutput signal V having a phase substantially orthogonal to_QIs output.
[0040]
The fifth output signal V output from the third high phase accuracy phase shifter 8_ITo an eighth output signal V output from the fourth high phase accuracy phase shifter 9._QIs subtracted by the second subtracter 12 and the subtraction result is converted to the in-phase output signal I._OUTAnd
The sixth output signal V output from the third high phase accuracy phase shifter 8_QAnd a seventh output signal V output from the fourth high phase accuracy phase shifter 9._IAre added by the second adder circuit 13, and the result of the addition is added to the orthogonal output signal Q._OUTAnd
[0041]
The subtraction signal X1, addition signal X2, in-phase output signal IOUT, and quadrature output signal Q of the image suppression filter circuit configured as described above._OUTIs represented by the following equation.
[0042]
X1 = e^{j ( π / 2)}[I_INe^{-j ( π / 2)}+ (Q_IN/ ωCR)] (4)
X2 = (I_IN/ ωCR) e^{-j ( π / 2)}+ Q_IN                            (Five)
I_OUT = X1- (X2 / ωCR) e^{-j ( π / 2)} = e^{j ( π / 2)}[I_INe^{-j ( π / 2)}
{1 + 1 / (ωCR)²} + Q_IN{2 / (ωCR)}] (6)
Q_OUT = (X1 / ωCR) e^{-j ( ω / 2)}-X2 = I_INe^{-j ( π / 2)}{2 / (ωCR)}
+ Q_IN{1 + 1 / (ωCR)²} (7)
The image signal can be removed as the phase error is closer to 0 degree, and can be removed as the amplitude accuracy (the amplitude ratio between the in-phase output signal and the quadrature output signal is closer to 1).
[0043]
From the above formulas (4) and (5), for example, when ωCR is set to 1.2, the phase shifter is one stage of the first high phase accuracy phase shifter 6 and the second high phase accuracy phase shifter 7. In the one-stage image suppression filter circuit in which the subtraction signal X1 as the output result is the final in-phase output signal, the amplitude ratio (1 / (1 / ωCR)) of the in-phase output signal and the quadrature output signal is changed to 1.2. Absent. However, the phase difference between the in-phase output signal and the quadrature output signal is 90 degrees.
[0044]
On the other hand, like the image suppression filter circuit shown in FIG. 5, the first high phase accuracy phase shifter 6, the second high phase accuracy phase shifter 7, and the third high phase accuracy phase shifter 8, The in-phase output signal I which is the output result of the second stage of the fourth high phase accuracy phase shifter 9_OUTAnd quadrature output signal Q_OUTIn-phase input signal I_INAnd quadrature input signal Q_INAmplitude ratio ({1 + 1 / (ωCR)²} / {2 / (ωCR)}) is a two-stage first and second high phase accuracy phase shifters 6 and 7 and third and fourth high phase accuracy shifts as the image suppression filter shown in FIG. In-phase output signal I which is the output result of phase shifters 8 and 9_OUTAnd quadrature output signal Q_OUTThe amplitude ratio is closer to 1 (calculated from the equations (5) and (6)).
[0045]
On the other hand, the common-mode input signal I_INIs a phase of e-j (π / 2), whereas the quadrature input signal Q_INPhase is ejo (= 1) and in-phase output signal I_OUTAnd quadrature output signal Q_OUTThen, the phase is accurately 90 degrees. By cascading high phase accuracy phase shifters from these, the in-phase input signal I_INAnd quadrature input signal Q_INThe amplitude ratio is 1.017, which is sufficiently small compared to 1.2 in a single stage, and the phase accuracy is constant at 90 degrees. it can. The phase shifters 6 and 7 have the same circuit configuration so that the phase difference between the phase shifters 6 and 7 is 90 °. Similarly, in order to set the phase difference between the phase shifters 8 and 9 to 90 °, the phase shifters 8 and 9 have the same circuit configuration.
If the number of stages connected in cascade is increased, the phase accuracy and the amplitude accuracy can be improved over a wider band.
[0046]
Next, FIG. 6 shows a circuit configuration diagram of an image suppression filter circuit according to the second embodiment of the present invention using the block circuits shown in FIGS. The image suppression filter circuit according to this embodiment includes a first high phase accuracy phase shifter 6, a second high phase accuracy phase shifter 7, a third high amplitude accuracy phase shifter 14, and a fourth high amplitude accuracy phase shifter. Phaser 15 is connected in two stages in cascade.
[0047]
This image suppression filter circuit has an in-phase input signal I_INAnd the first output signal V_IAnd this first output signal V_IOutput signal V having a phase orthogonal to_QThe first high phase accuracy phase shifter 6 is provided.
[0048]
In-phase input signal I_INInput signal Q having a phase component substantially orthogonal to_INAnd the third output signal V_IAnd this third output signal V_IOutput signal V having a phase substantially orthogonal to_QThe second high phase accuracy phase shifter 7 is provided.
[0049]
In-phase input signal I of FIG._IN, Quadrature input signal Q_INCorresponds to the in-phase output and the quadrature output of the preceding quadrature mixer (not shown), for example, and the input V of the first high phase accuracy phase shifter 6 is_IN, The input signal V of the second high phase accuracy phase shifter 7_INIt has become.
[0050]
The first output signal V output from the first high phase accuracy phase shifter 6_ITo a fourth output signal V output from the second high phase accuracy phase shifter 7._QIs subtracted by the first subtracter 10, and the subtraction result is output as a subtraction signal X1.
The second output signal V output from the first high phase accuracy phase shifter 6_QAnd the third output signal V output from the second high phase accuracy phase shifter 7._IAre added by the first adder 11, and the addition result is output as an addition signal X2.
[0051]
The subtraction signal X1 is input to the third high amplitude accuracy phase shifter 14, and the third high amplitude accuracy phase shifter 14 has a fifth output signal V having the same component as the subtraction signal X1._IAnd the fifth output signal V_IA sixth output signal V including a phase component substantially orthogonal to_QIs output.
The addition signal X2 is input to the fourth high amplitude accuracy phase shifter 15, and the fourth high amplitude accuracy phase shifter 15 has a seventh output signal V having substantially the same phase component as the addition signal X2._IAnd the seventh output signal V_IOutput signal V having a phase component substantially orthogonal to_QIs output.
[0052]
Third_{High phase accuracy phase shifter 8}The fifth output signal V output from_ITo an eighth output signal V output from the fourth high amplitude accuracy phase shifter 15._QIs subtracted by the second subtraction circuit 12, and the subtraction result is converted to the common-mode output signal I._OUTAnd
Third_{High phase accuracy phase shifter 8}The sixth output signal V output from_QAnd a seventh output signal V output from the fourth high amplitude accuracy phase shifter 15._IAre added by the second adder circuit 13, and the result of the addition is added to the orthogonal output signal Q._OUTAnd
[0053]
The subtraction signal X1, the addition signal X2, and the in-phase output signal I of the image suppression filter circuit configured as described above._OUT, Quadrature output signal Q_OUTIs represented by the following equation.
[0054]

Where θ = 2tan^-1(1 / (ωCR)).
[0055]
The image signal is the in-phase output signal I_OUTAnd quadrature output signal Q_OUT, The closer θ is to π / 2, the more it can be removed, and the in-phase input signal I_INAnd quadrature input signal Q_INThe closer the amplitude ratio of the coefficients is to 1, the more it can be removed.
For example, when ωCR is 1.2, the phase shifter is composed of only one stage of the first high phase accuracy phase shifter 6 and the second high phase accuracy phase shifter 7 according to the equations (8) and (9). In the subtraction signal X1 and the addition signal X2, which are output results of the image suppression filter circuit, the amplitude ratio (1 / (1 / ωCR)) of the in-phase input signal and the quadrature input signal is 1.2, which is unchanged. The phase difference between the in-phase input signal and the quadrature input signal is 90 degrees.
[0056]
On the other hand, like the image suppression filter circuit shown in FIG. 6, the first high phase accuracy phase shifter 6, the second high phase accuracy phase shifter 7, and the third high amplitude accuracy phase shifter 14, The in-phase output signal I which is the output result of the second stage of the fourth high amplitude accuracy phase shifter 15_OUTAnd quadrature output signal Q_OUTThe amplitude ratio is 1.
[0057]
On the other hand, the common-mode output signal I_OUTAnd quadrature output signal Q_OUTThe phase difference Δφ in can be calculated from the equations (10) and (11) as follows. Here, the in-phase output signal I_OUTIs calculated using Equation (10) only, and similarly, the orthogonal output signal Q is obtained from Equation (11)._OUTCan also be calculated.
[0058]
First, the in-phase input signal I_INMultiplied by {e^{j ( θ - π / 2)}+ 1 / (ωCR)} is expressed by the following equation.

From this, this phase φ1 is expressed as follows.
φ1 = tan^-1(B / A) (13)
In Equation (12), θ = 2tan^-1(1 / ωCR))
φ1 = −5.6.
[0059]
On the other hand, the quadrature output signal Q_INMultiplied by {e^{j ( θ−π / 2)}/ (ωCR) +1} is expressed by the following equation.
cos (θ-π / 2) / (ωCR) + jsin (θ-π / 2) / (ωCR) +1
= {1 + cos (θ-π / 2) /-(ωCR)} + jsin (θ-π / 2) / (ωCR) = C + JD (14)
From this, this phase φ2 is expressed as follows.
[0060]
φ2 = tan^-1(D / C) (15)
In equation (15), θ = 2tan^-1(1 / ωCR))
φ2 = −4.7 °.
[0061]
From this, the phase difference Δφ = −0.9 °, which is very close to zero. This is a phase error Δφ = π / 2-θ = π / 2-2tan when using one stage of high amplitude precision phase shifter^-1This is a significant improvement over (1 / (ωCR)) =-10.4 °. If the product of CR is the same between the phase shifters 6, 7 and 14, 15, the values of C and R may be different between the phase shifters 6, 7, 14, 15.
[0062]
From the above results, the phase accuracy is −0.9 ° and the amplitude accuracy is 1 by arranging the high phase accuracy phase shifter and the high amplitude accuracy phase shifter in series as in the image suppression filter circuit according to the present embodiment. High accuracy can be achieved over a wide band. If the number of stages connected in cascade is increased, the phase accuracy and the amplitude accuracy can be increased over a wider band.
[0063]
Next, an image suppression filter circuit according to a third embodiment of the present invention will be described with reference to FIG. 7 using the block circuit shown in FIGS. The image suppression filter circuit according to this embodiment includes a first high amplitude accuracy phase shifter 16, a second high amplitude accuracy phase shifter 17, a third high phase accuracy phase shifter 8, and a fourth high phase accuracy phase shifter. The phase shifters 9 are connected in two stages in cascade.
[0064]
This image suppression filter circuit uses the common-mode input signal I_INAnd the first output signal V_IAnd the first output signal V_IThe second output signal V converted to a phase component substantially orthogonal to_QThe first high amplitude accuracy phase shifter 16 is provided.
[0065]
In-phase input signal I_INInput signal Q having a phase component substantially orthogonal to_INAnd the third output signal V_IAnd the third output signal V_IOutput signal V converted to a phase component substantially orthogonal to_QThe second high phase accuracy phase shifter 17 is provided.
[0066]
In-phase input signal I in FIG._IN, Quadrature input signal Q_INIs equivalent to the in-phase output and the quadrature output of the preceding quadrature mixer (not shown), for example, and the input V of the first high amplitude accuracy phase shifter 16 is_INThe input signal V of the second high amplitude accuracy phase shifter 17_INIt has become.
[0067]
The first output signal V output from the first high amplitude accuracy phase shifter 16_ITo a fourth output signal V output from the second high amplitude accuracy phase shifter 17._QIs subtracted by the first subtracter 10, and the subtraction result is output as a subtraction signal X1.
The second output signal V output from the first high amplitude accuracy phase shifter 16_QAnd the third output signal V output from the second high amplitude accuracy phase shifter 17._IAre added by the first adder 11, and the addition result is output as an addition signal X2.
[0068]
The subtraction signal X1 is input to the third high phase accuracy phase shifter 8 and the fifth output signal V_IAnd the fifth output signal V_IOutput signal V converted into a phase component orthogonal to_QIs output.
The addition signal X2 is input to the fourth high phase accuracy phase shifter 9 and the seventh output signal V_IFurthermore, the seventh output signal V_IOutput signal V converted to a phase component substantially orthogonal to_QIs output.
[0069]
The fifth output signal V output from the third high phase accuracy phase shifter 8_ITo an eighth output signal V output from the fourth high phase accuracy phase shifter 9._QIs subtracted by the second subtraction circuit 12, and the subtraction result is converted to the common-mode output signal I._OUTAnd
The sixth output signal V output from the third high phase accuracy phase shifter 8_QAnd a seventh output signal V output from the fourth high phase accuracy phase shifter 9._IAre added by the second adder circuit 13, and the result of the addition is added to the orthogonal output signal Q._OUTAnd
[0070]
The subtraction signal X1, the addition signal X2, and the in-phase output signal I of the image suppression filter circuit configured as described above._OUT, Quadrature output signal Q_OUTIs represented by the following equation.
X1 = I_INe^{j θ}-Q_IN                                          (16)
X2 = I_IN+ Q_INe^{j θ}                                          (17)
I_OUT= e^{j ( π / 2)}[X1e^{-j ( π / 2)}+ (X2 / ωCR)]
= e^{j ( π / 2)}[I_IN{e^{j ( θ - π / 2)}+ 1 / (ωCR)}
-Q_INe^{-j ( π / 2)}{e^{j ( θ - π / 2)}/ (ωCR) +1}] (18)
Q_OUT= (X1 / ωCR) e^{-j ( π / 2)}+ X2 = I_IN{e^{j ( θ - π / 2)}/ (ωCR) +1}
-Q_INe^{-j ( π / 2)}{e^{j ( θ - π / 2)}+ 1 / (ωCR)} (19)
Where θ = 2tan^-1(1 / (ωCR)).
[0071]
The image signal can be removed as the phase θ is closer to π / 2 in the in-phase output signal and the quadrature output signal, and can be removed as the amplitude ratio of the coefficients of the in-phase input signal and the quadrature input signal is closer to 1.
For example, when ωCR is 1.2, the phase shifter is composed of only one stage of the first high amplitude accuracy phase shifter 16 and the second high amplitude accuracy phase shifter 17 according to the equations (16) and (17). In the X1 signal and the X2 signal that are output results of the image suppression filter circuit, the phase error between the in-phase output signal and the quadrature output signal is Δφ = π / 2-θ = π / 2-2tan^-1(1 / (ωCR))
= -10.4 °. There is no amplitude difference between the coefficients of the in-phase input signal and the quadrature input signal.
[0072]
On the other hand, like the image suppression filter circuit shown in FIG. 7, the sixth high amplitude accuracy phase shifter 16, the second high amplitude accuracy phase shifter 17, and the third high phase accuracy phase shifter 8, The in-phase output signal I which is the output result of the second stage of the fourth high phase accuracy phase shifter 9_OUTAnd quadrature output signal Q_OUTThe amplitude ratio of is 1.
[0073]
On the other hand, the common-mode output signal I_OUTAnd quadrature output signal Q_OUTThe phase difference Δφ in can be calculated from the equations (18) and (19) as follows. Here, the in-phase output signal I_OUTIs calculated using the equation (18), but similarly, the orthogonal output signal Q is calculated from the equation (19)._OUTCan also be calculated.
[0074]
First, the in-phase input signal I_INMultiplied by {e^{j ( θ - π / 2)}+ 1 / (ωCR)} is expressed by the following equation.
cos (θ-π / 2) + jsin (θ-π / 2) + 1 / (ωCR) = {cos (θ-π / 2) + 1 / (ωCR)}
+ jsin (θ-π / 2) = A + jB (20)
From this, this phase φ1 is expressed as follows.
φ1 = tan^-1(B / A) (21)
In equation (21), θ = 2 tan^-1(1 / (ωCR))
φ1 = -5.6 °.
[0075]
On the other hand, the quadrature output signal Q_INMultiplied by {e^{j ( θ - π / 2)}/ (ωCR) +1} is expressed by the following equation.
cos (θ-π / 2) / (ωCR) + jsin (θ-π / 2) / (ωCR) +1
= {1 + cos (θ-π / 2) / (ωCR)} + jsin (θ-π / 2) / (ωCR) = C + jD (22)
From this, this phase φ2 is expressed as follows.
φ2 = tan^-1 (D / C) (23)
In Equation (22), θ = 2 tan^-1Since (1 / (ωCR)), when a value is substituted, φ2 = −4.7 °.
From this, the phase difference Δφ = −0.9 °.
[0076]
On the other hand, the phase error between the in-phase signal and quadrature signal when using one stage of high-amplitude precision phase shifter is^-1 (1 / (ωCR)) = − 10.4 °, and the phase accuracy of the image suppression filter shown in this embodiment is greatly improved.
From this, it can be seen that the use of an image suppression filter in which a high amplitude accuracy phase shifter and a high phase accuracy phase shifter are connected in cascade can achieve high accuracy in phase accuracy and amplitude accuracy in a wide band.
From this result, it can be easily estimated that the phase accuracy and the amplitude accuracy can be improved over a wider band by increasing the number of stages connected in cascade.
[0077]
Next, using the block diagrams shown in FIGS. 3 and 4, FIG. 8 shows a circuit configuration diagram of an image suppression filter circuit according to a fourth embodiment of the present invention. The image suppression filter circuit according to this embodiment includes a first high amplitude accuracy phase shifter 16, a second high amplitude accuracy phase shifter 17, a third high amplitude accuracy phase shifter 14, and a fourth high amplitude accuracy phase shifter. Phaser 15 is connected in two stages in cascade.
[0078]
This image suppression filter circuit uses the common-mode input signal I_INAnd the first output signal V_IAnd the second output signal V converted into a phase component substantially orthogonal to the first output signal._QThe first high amplitude accuracy phase shifter 16 is provided.
[0079]
In-phase input signal I_INInput signal Q having a phase component substantially orthogonal to_INAnd the third output signal V_IAnd the third output signal V_IOutput signal V converted to a phase component substantially orthogonal to_QThe second high amplitude accuracy phase shifter 17 is provided.
[0080]
In-phase input signal I in FIG._IN, Quadrature input signal Q_INIs equivalent to the in-phase output and the quadrature output of the preceding quadrature mixer (not shown), for example, and the input V of the first high amplitude accuracy phase shifter 16 is_INThe input signal V of the second high amplitude accuracy phase shifter 17_INIt has become.
[0081]
The fourth output signal V output from the second high amplitude accuracy phase shifter 17 from the first output signal VI output from the first high amplitude accuracy phase shifter 16._QIs subtracted by the first subtracter 10, and the subtraction result is output as a subtraction signal X1.
The second output signal V output from the first high amplitude accuracy phase shifter 16_QAnd the third output signal V output from the second high amplitude accuracy phase shifter 17._IAre added by the first adder 11, and the addition result is output as an addition signal X2.
[0082]
The subtraction signal X1 is input to the third high amplitude accuracy phase shifter 14 and the fifth output signal V1._IIs output, and the fifth output signal V_IOutput signal V converted to a phase component substantially orthogonal to_QIs output.
The addition signal X2 is input to the fourth high amplitude accuracy phase shifter 15 and the seventh output signal V_IIs output, and the seventh output signal V_IOutput signal V converted to a phase component substantially orthogonal to_QIs output.
[0083]
The fifth output signal V output from the third high amplitude accuracy phase shifter 14_ITo an eighth output signal V output from the fourth high amplitude accuracy phase shifter 15._QIs subtracted by the second subtraction circuit 12, and the subtraction result is converted to the common-mode output signal I._OUTAnd
The sixth output signal V output from the third high amplitude accuracy phase shifter 14_QAnd a seventh output signal V output from the fourth high amplitude accuracy phase shifter 15._IAre added by the second adder circuit 13, and the result of the addition is added to the orthogonal output signal Q._OUTAnd
[0084]
The subtraction signal X1, the addition signal X2, and the in-phase output signal I of the image suppression filter circuit configured as described above._OUT, Quadrature output signal Q_OUTIs represented by the following equation.
[0085]
X1 = I_INe^{j θ}-Q_IN                                          (twenty four)
X2 = I_IN+ Q_INe^{j θ}                                          (twenty five)
I_OUT= X1e^{j θ}-X2 = 2e^{j ( θ + π / 2)}[I_INsinθ + Q_INe^{j ( π / 2)}] (26)
Q_OUT= X1 + X2e^{j θ}= 2e^{j θ}[I_IN+ Q_INsinθe^{j ( π / 2)}] (27)
Where θ = 2 tan^-1(1 / (ωCR)).
[0086]
The image signal can be removed the closer θ is to 90, and the in-phase input signal I_INAnd quadrature input signal Q_INThe closer the amplitude ratio of the coefficients is to 1, the more it can be removed.
For example, when ωCR is set to 1.2, the amplitude ratio is 1.2 and the phase difference is 0 as described above using Equations (8) and (9) when one stage of the high phase accuracy phase shifter is used. °. In this case, since the amplitude ratio is largely deviated, broadband characteristics cannot be obtained.
[0087]
On the other hand, like the image suppression filter circuit shown in FIG. 8, the first high amplitude accuracy phase shifter 16, the second high amplitude accuracy phase shifter 17, and the third high amplitude accuracy phase shifter 14, The in-phase output signal I which is the output result of the second stage of the fourth high amplitude accuracy phase shifter 15_OUTAnd quadrature output signal Q_OUT, The amplitude ratio is sin θ = 0.983 as can be seen from the equations (26) and (27). This is approximately equal to the reciprocal of the amplitude ratio 1.017 of the image suppression filter shown in the first embodiment in which two phase shifters with high phase accuracy are connected in cascade.
[0088]
On the other hand, the common-mode input signal I_INIs the phase of ejo (= 1), while the quadrature input signal Q_INIs e^{j ( π / 2)}The phase is precisely 90 °. From this, it is apparent that the phase accuracy and the amplitude accuracy can be increased over a wide band even when high amplitude accuracy phase shifters are connected in cascade.
[0089]
FIG. 9 is a circuit diagram of an image suppression filter circuit according to the fifth embodiment of the present invention.
In the present embodiment, the first output signal V output from the first high phase accuracy phase shifter 6 in the broadband high accuracy image suppression filter circuit described in the first embodiment._IIs input to the first subtraction circuit 10 via the buffer circuit 18 and is output from the second high phase accuracy phase shifter 7._QIs input to the first subtractor 10 via the buffer circuit 18 and subtracted.
[0090]
The second output signal V output from the first high phase accuracy phase shifter 6_QIs input to the first adder circuit 11 via the buffer circuit 18 and is output from the second high phase accuracy phase shifter 7._IAre input to the first adder circuit 11 via the buffer circuit 18 and added.
[0091]
The fifth output signal V output from the third high phase accuracy phase shifter 8_IIs input to the second subtraction circuit 12 via the buffer circuit 18 and the eighth output signal V output from the fourth high phase accuracy phase shifter 9._QIs inputted to the second subtractor 12 via the buffer circuit 18 and subtracted.
[0092]
The sixth output signal V output from the third high phase accuracy phase shifter 8_QIs input to the second adder circuit 13 via the buffer circuit 18 and the seventh output signal V output from the fourth high phase accuracy phase shifter 9._IAre input to the second adder circuit 13 via the buffer circuit 18 and added. The buffer circuit 18 includes a voltage-current converter, and addition and subtraction are performed by current addition and current subtraction using the output current of the buffer circuit 18.
[0093]
Although not shown in FIG. 9, after the current subtraction and the current addition are performed by the first subtraction circuit 10 and the first addition circuit 11, the subtraction signal X1 and the addition signal X2 are converted into a voltage using, for example, a resistor and converted into a voltage. 3 to the high phase accuracy phase shifter 8 and the fourth high phase accuracy phase shifter 9.
[0094]
Such a broadband high-accuracy image suppression filter circuit has higher accuracy if the number of connection stages is increased.
Here, the reason why the buffer circuit 18 is used is that, as shown in FIG._I, V_QThis is because the output side viewed from the output terminal is required to have high impedance, and the buffer circuit realizes high impedance. Further, the buffer circuit 18 compensates for the loss in the high phase accuracy phase shifter, so that the noise characteristic deterioration can be reduced.
[0095]
The buffer circuit 18 can be easily realized by a generally used differential circuit as shown in FIG. 10, for example. The emitter electrodes of the transistors Q1 and Q2 in FIG. 10 are connected by a resistor RE. Current -I from the collector side_OUT, + I_OUTIs input and the base voltage is + V_IN, -V_INIs output.
[0096]
FIG. 11 is a circuit diagram showing a specific example of the image suppression filter circuit shown in FIG.
The configuration of the image suppression filter circuit shown in this circuit diagram is basically the same as that shown in FIG. 9, but uses a differential circuit configuration suitable for IC implementation.
In FIG. 11, C_ACRepresents an AC coupling capacitor and is used to remove a DC component. R_L1, R_L2Represents a load resistance used for converting the voltage-current converted current into a voltage. The phase shifter used in each stage uses the high phase accuracy phase shifter shown in FIG.
[0097]
As shown in FIG. 11, the upper left side is the in-phase input signal + I._IN, -I_INIs input, and the upper right is the quadrature input signal + Q_IN, -Q_INIs entered. First output signal I_IIs the fourth output signal Q_QConnected and subtracted. Second output signal I_QIs the third output signal Q_IConnected and added. In this way, the subtraction signal X1 and the addition signal X2 are formed.
[0098]
Fifth output signal I_IIs the eighth output signal Q_QConnected and subtracted. Sixth output signal I_QIs the seventh output signal + Q_IConnected and added. In this way, the in-phase output signal I_OUT, Q_OUTIs output as
[0099]
Although not shown in FIG. 11, the broadband high-accuracy image suppression filter circuit has higher accuracy if the number of connection stages is increased.
[0100]
FIG. 12 is a circuit diagram of an image suppression filter circuit according to the sixth embodiment of the present invention.
In the present embodiment, the first output signal V output from the first high phase accuracy phase shifter 6 in the broadband high accuracy image suppression filter circuit described in the second embodiment._IIs input to the first subtraction circuit 10 via the buffer circuit 18 and is output from the second high phase accuracy phase shifter 7._QIs input to the first subtractor 10 via the buffer circuit 18 and subtracted.
[0101]
The second output signal V output from the first high phase accuracy phase shifter 6_QIs input to the first adder circuit 11 via the buffer circuit 18 and is output from the second high phase accuracy phase shifter 7._IAre input to the first adder circuit 11 via the buffer circuit 18 and added.
[0102]
The fifth output signal V output from the third high amplitude accuracy phase shifter 14_IIs input to the second subtraction circuit 12 via the buffer circuit 18 and the eighth output signal V output from the fourth high amplitude accuracy phase shifter 15._QIs inputted to the second subtractor 12 through the buffer circuit 18 and subtracted.
[0103]
Further, the sixth output signal V outputted from the third high amplitude accuracy phase shifter 14 is used._QIs input to the second adder circuit 13 via the buffer circuit 18 and the seventh output signal V output from the fourth high amplitude accuracy phase shifter 15._IAre input to the second adder circuit 13 via the buffer circuit 18 and added. The buffer circuit 18 includes a voltage-current converter, and addition and subtraction are performed by current addition and current subtraction using the output current of the buffer circuit 18.
[0104]
Although not shown in FIG. 12, after the current subtraction and the current addition are performed by the first subtraction circuit 10 and the first addition circuit 11, the subtraction signal X1 and the addition signal X2 are converted into a voltage using, for example, a resistor and converted into a voltage. The third high amplitude accuracy phase shifter 14 and the fourth high amplitude accuracy phase shifter 15 are input.
[0105]
Such a broadband high-accuracy image suppression filter circuit has higher accuracy if the number of connection stages is increased.
[0106]
The main reason for using the buffer circuit in the image suppression filter circuit of the present embodiment is as follows. One is that the characteristics of the high phase accuracy phase shifter described in FIG._I, V_QThe condition is that the output side viewed from the output terminal has a high impedance, and the other is that the characteristics of the high amplitude accuracy phase shifter described in FIG._IThis is because the output side viewed from the output terminal is required to have high impedance.
[0107]
Furthermore, since the buffer circuit 18 compensates for the loss in the high phase accuracy phase shifter and the high amplitude accuracy phase shifter, that is, the buffer circuit 18 has a gain, noise characteristic deterioration can be reduced. is there. The buffer circuit can be easily realized by a commonly used differential circuit as shown in FIG.
[0108]
The same effect can be obtained even if the configuration shown in the third embodiment is such that the high amplitude accuracy phase shifter is the first stage and the high phase accuracy phase shifter is the next stage.
[0109]
FIG. 13 shows a specific example of the broadband high-precision image suppression filter circuit shown in FIG. The configuration is basically the same as that shown in FIG. 11, but uses a differential circuit configuration suitable for IC implementation. In FIG. 13, C_ACRepresents an AC coupling capacitor, which is used to remove a DC component. R_L1, R_L2Represents a load resistance used for converting the voltage-current converted current into a voltage.
[0110]
The phase shifter used in the first stage uses the high phase accuracy phase shifter shown in FIG. 1 (a), and the phase shifter used in the next stage uses the high amplitude accuracy shifter shown in FIG. 2 (a). A phaser is used.
[0111]
As shown in FIG. 13, the upper left side is the in-phase input signal + I._IN, -I_INIs input, and the upper right is the quadrature input signal + Q_IN, -Q_INIs entered. First output signal I_IIs the fourth output signal Q_QConnected and subtracted. Second output signal I_QIs the third output signal Q_IConnected and added. In this way, the subtraction signal X1 = I_I-Q_QAnd the addition signal X2 = I_Q+ Q_IIs formed.
[0112]
Fifth output signal I_IIs the eighth output signal Q_QConnected and subtracted. Sixth output signal I_QIs the seventh output signal Q_IConnected and added. In-phase output signal I_OUTAnd Q_OUTIs obtained.
[0113]
Although not shown in FIG. 13, the accuracy of the broadband high-accuracy image suppression filter circuit is further improved if the number of connection stages is increased.
[0114]
The same effect can be obtained even if the image suppression filter circuit configuration of the third embodiment is such that the high amplitude accuracy phase shifter is the first stage and the high phase accuracy phase shifter is the next stage.
[0115]
FIG. 14 is a circuit diagram of an image suppression filter circuit according to the seventh embodiment of the present invention. In the present embodiment, the first output signal V output from the first high amplitude accuracy phase shifter 16 in the broadband high accuracy image suppression filter circuit described in the fourth embodiment._IIs input to the first subtraction circuit 10 via the buffer circuit 18 and the fourth output signal V output from the second high amplitude accuracy phase shifter 17._QIs input to the first subtractor 10 via the buffer circuit 18 and subtracted.
[0116]
The second output signal V output from the first high amplitude accuracy phase shifter 16_QIs input to the first adder circuit 11 via the buffer circuit 18 and the third output signal V output from the second high amplitude accuracy phase shifter 17._IAre input to the first adder circuit 11 via the buffer circuit 18 and added.
[0117]
The fifth output signal V output from the third high amplitude accuracy phase shifter 14_IIs input to the second subtraction circuit 12 via the buffer circuit 18 and the eighth output signal V output from the fourth high amplitude accuracy phase shifter 15._QIs inputted to the second subtractor 12 through the buffer circuit 18 and subtracted.
[0118]
The sixth output signal V output from the third high amplitude accuracy phase shifter 14_QIs input to the second adder circuit 13 via the buffer circuit 18 and the seventh output signal V output from the fourth high amplitude accuracy phase shifter 15._IAre input to the second adder circuit 13 via the buffer circuit 18 and added. The buffer circuit 18 includes a voltage-current converter, and addition and subtraction are performed by current addition and current subtraction using the output current of the buffer circuit 18.
[0119]
Although not shown in FIG. 14, after the current subtraction and the current addition are performed by the first subtraction circuit 10 and the first addition circuit 11, the subtraction signal X1 and the addition signal X2 are converted into a voltage using, for example, a resistor and converted into a voltage. The third high amplitude accuracy phase shifter 14 and the fourth high amplitude accuracy phase shifter 15 are input.
[0120]
Such a broadband high-accuracy image suppression filter circuit has higher accuracy if the number of connection stages is increased.
[0121]
The main reason for using the buffer circuit 18 in the present embodiment is that the characteristics of the high amplitude accuracy phase shifter described in FIG._IThis is because the output side viewed from the output terminal is required to have high impedance. Furthermore, the buffer circuit 18 compensates for the loss in the high amplitude accuracy phase shifter, that is, the buffer circuit 18 has a gain, so that the noise characteristic deterioration can be reduced. The buffer circuit 18 can be easily realized by a commonly used differential circuit as shown in FIG.
[0122]
FIG. 15 shows a specific example of the broadband high-precision image suppression filter circuit shown in FIG. Although basically the same as the configuration of FIG. 14, a differential circuit configuration suitable for IC implementation is used. In FIG. 15, R_L1, R_L2Represents a load resistance used for converting the voltage-current converted current into a voltage. The phase shifter used in this configuration uses the high amplitude accuracy phase shifter shown in FIG.
[0123]
As shown in FIG. 15, the upper left side is the in-phase input signal + I._IN, -I_INIs input, and the upper right is the quadrature input signal + Q_IN, -Q_INIs entered. First output signal I_IIs the fourth output signal Q_QConnected and subtracted. Second output signal I_QIs the fourth output signal + Q_IConnected and added. In this way, the subtraction signal X1 = I_I-Q_QAnd the addition signal X2 = I_Q+ Q_IIs formed.
[0124]
Fifth output signal I_IIs the eighth output signal Q_QConnected and subtracted. Sixth output signal I_QIs the seventh output signal Q_IConnected and added. Thus, the subtraction result is the in-phase output signal I_OUT, Q_OUTIs output.
[0125]
Although not shown in FIG. 15, the accuracy of the broadband high-accuracy image suppression filter circuit according to this figure is further improved by increasing the number of connection stages.
[0126]
FIG. 16A shows V of the high phase accuracy phase shifter described in FIG._INCapacitor CAC, resistor RL, current source I_INAre connected. FIG. 16B shows the V of the high phase accuracy phase shifter described in FIG._INResistance R_L, Current source I_INAre connected and current driven.
[0127]
Driving the high phase accuracy phase shifter with current has the effect of increasing the gain of the phase shifter. By using this high gain, high phase accuracy phase shifter for the image suppression filter circuit shown in each of the above-described embodiments, the noise characteristics are improved.
[0128]
FIG. 17 is a configuration diagram of a transmission / reception system. According to this, on the reception (RX) side, the reception signal received by the antenna 20 is sent to the quadrature mixer (MIX1) 25 via the duplexer (DUP) 21, the bandpass filter (BPF) 23, and the low noise amplifier (LNA) 24. Entered. Here, the band-pass filter (BPF) 23 is intended to capture a signal in the vicinity of a desired band, and may be any filter that can reduce the image signal to some extent.
[0129]
Next, the output of the quadrature mixer (MIX1) 25 is input to the wideband image suppression filter circuit (IRSC) 26 described in each embodiment. The image signal included in the in-phase I / quadrature Q channel signal of the quadrature mixer (MIX1) 25 is reduced by the wideband image suppression filter circuit (IRSC) 26 and input to the next-stage quadrature mixer (MIX2) 27.
[0130]
In FIG. 18, one output of the broadband image suppression filter (IRSC) 26 (here, the in-phase output signal I_OUTOnly to the next-stage quadrature mixer (MIX2) 27, and the other output (here, quadrature output signal Q_OUT) Is discarded. However, in some cases, both outputs can be used. The quadrature mixer (MIX2) 27 outputs the in-phase I / quadrature Q signal that has become the baseband signal to the A / D converter.
[0131]
Next, the transmission (TX) side will be described. First, the in-phase ICH and quadrature QCH signal of the baseband signal are converted into a desired IF signal by a quadrature modulator (QMOD1) 28 including a 90-degree phase shifter, a mixer, and an adder. This IF signal is input to the broadband image suppression filter circuit (IRSC) 29 described in each embodiment.
[0132]
The wideband image suppression filter circuit (IRSC) 29 is not used to remove the image signal, but uses the IF signal to generate an in-phase I / quadrature Q signal having a phase difference of 90 degrees over a wide band. Yes.
[0133]
This is because the in-phase output signal I shown in equations (6), (7), (10), (11), (18), (19), (26), and (27)._OUTAnd quadrature output signal Q_OUTAs can be seen from the equation for obtaining the common-mode input signal I of the wideband image suppression filter circuit of each embodiment,_INAnd quadrature input signal Q_INWhen one of the signals is input and the other is not input, the fact that signals having phases different from each other by 90 degrees are output is utilized.
[0134]
Next, the output of the broadband image suppression filter circuit (IRSC) 29 is input to a quadrature modulator (QMOD2) 30 to generate an RF signal without an image. The output RF signal is output to space via a power amplifier (PA) 31, a band pass filter (BPF) 32, a duplexer (DUP) 21, and the antenna 20.
[0135]
RF local oscillation signal LO_RF, IF local oscillation signal LO_IFIs input to the reception in-phase I / quadrature Q mixer or the transmission quadrature modulator via a 90-degree phase shifter (π / 2). The wideband image suppression filter circuit described in each embodiment can also be used for this 90 degree phase shifter. In the drawing, the portion surrounded by a dotted line can be incorporated into one IC chip.
[0136]
【The invention's effect】
As described above, the present invention can realize a highly accurate image suppression filter circuit over a wide band by cascading phase shifters via a subtraction circuit and an addition circuit. Further, by making this an IC, an external filter such as image suppression necessary for the wireless unit can be deleted, so that the wireless unit can be reduced in size and price.
[Brief description of the drawings]
FIG. 1 shows a circuit diagram, an input frequency output amplitude characteristic diagram, and an input frequency output phase characteristic diagram of a high phase accuracy phase shifter.
FIG. 2 shows a circuit diagram, an input frequency output amplitude characteristic diagram, and an input frequency output phase characteristic diagram of a high phase accuracy phase shifter.
FIG. 3 is a block diagram of a high phase accuracy phase shifter.
FIG. 4 is a block diagram of a high amplitude accuracy phase shifter.
FIG. 5 is a circuit diagram of a wideband high-precision image suppression filter circuit according to the first embodiment of the present invention.
FIG. 6 is a circuit diagram of a wideband high-precision image suppression filter circuit according to a second embodiment of the present invention.
FIG. 7 is a circuit diagram of a wideband high-precision image suppression filter circuit according to a third embodiment of the present invention.
FIG. 8 is a circuit diagram of a wideband high-precision image suppression filter circuit according to a fourth embodiment of the present invention.
FIG. 9 is a circuit diagram of a broadband high-precision image suppression filter circuit according to a fifth embodiment of the present invention.
FIG. 10 is a buffer circuit diagram including a linearized operating circuit.
FIG. 11 is a circuit diagram suitable for integration of a wideband high-precision image suppression filter circuit according to a fifth embodiment of the present invention.
FIG. 12 is a circuit diagram of a broadband high-precision image suppression filter circuit according to a sixth embodiment of the present invention.
FIG. 13 is a circuit diagram suitable for integration of a wideband high-precision image suppression filter circuit according to a sixth embodiment of the present invention.
FIG. 14 is a circuit diagram of a broadband high-precision image suppression filter circuit according to a seventh embodiment of the present invention.
FIG. 15 is a circuit diagram suitable for integration of a wideband high-precision image suppression filter circuit according to a seventh embodiment of the present invention.
FIG. 16 is a circuit diagram of a high phase accuracy phase shifter with increased gain.
FIG. 17 is a block diagram of a transceiver using an image suppression filter circuit according to the present invention.
[Explanation of symbols]
6 ... 1st high phase accuracy phase shifter
7 ... Second high phase accuracy phase shifter
8 ... Third high phase accuracy phase shifter
9 ... Fourth high phase accuracy phase shifter
10: First subtractor
11: First adder
12 ... Second subtractor
13 ... second adder
14 ... Third high amplitude accuracy phase shifter
15 ... Fourth high amplitude accuracy phase shifter
16 ... 1st high amplitude precision phase shifter
17 ... Second high amplitude accuracy phase shifter
18 ... Buffer circuit
101 ... 1st terminal
102 ... 2nd terminal
103 ... Third terminal
104 ... 4th terminal
105 ... 1st resistance
106: First capacitor
107: Second resistance
108: Second capacitor

Claims (17)

Receiving the in-phase input signal, a first high phase accuracy phase shifter for outputting a second output signal having substantially quadrature phase component to the first output signal and the first output signal,
Second high phase accuracy for receiving a quadrature input signal having a phase component substantially orthogonal to the in-phase input signal and outputting a third output signal and a fourth output signal having a phase component orthogonal to the third output signal A phase shifter,
A first subtractor that subtracts the fourth output signal from the first output signal and outputs a subtracted signal;
A first adder that adds the second output signal and the third output signal and outputs an added signal;
A first buffer that outputs the first output signal and the fourth output signal to the first subtractor, respectively, to compensate for a loss in the first high amplitude accuracy phase shifter;
A second buffer circuit for outputting the second output symbol and the third output signal to the first adder, respectively, in order to compensate for the loss in the second high amplitude accuracy phase shifter;
A third high phase accuracy phase shifter that receives the subtraction signal and outputs a fifth output signal and a sixth output signal having a phase component orthogonal to the fifth output signal;
A fourth high phase accuracy phase shifter that receives the addition signal and outputs a seventh output signal and an eighth output signal having a phase component orthogonal to the seventh output signal;
A second subtractor that subtracts the eighth output signal from the fifth output signal and outputs a subtraction result as an in-phase output signal;
A second adder for adding the sixth output signal and the seventh output signal and outputting the addition result as an orthogonal output signal;
A third buffer circuit for outputting the fifth output signal and the eighth output signal to the second subtracter to compensate for the loss in the third high amplitude accuracy phase shifter;
A fourth buffer circuit for outputting the sixth output signal and the seventh output signal to the second adder in order to compensate for the loss in the fourth high amplitude accuracy phase shifter;
An image suppression filter circuit comprising: The image suppression filter circuit according to claim 1, wherein the buffer circuit has a gain. The image suppression filter circuit according to claim 1, wherein the buffer circuit has a gain of 1 or more. The image suppression filter circuit according to claim 1, wherein the buffer circuit is configured by an electrical current conversion circuit having a differential circuit configuration, and the adder or the subtracter performs addition or subtraction in a current mode. 2. The image suppression filter circuit according to claim 1, wherein the first high phase accuracy phase shifter and the second high phase accuracy phase shifter have the same circuit configuration. The image suppression filter circuit according to claim 1, wherein the third high phase accuracy phase shifter and the fourth high phase accuracy phase shifter have the same circuit configuration. Each of the first high phase accuracy phase shifter, the second high phase accuracy phase shifter, the third high phase accuracy phase shifter, and the fourth high phase accuracy phase shifter includes: A resistor and a first end connected to one end of the first resistor;
A first capacitor having one end connected to the first end;
A second end connected to the other end of the first capacitor;
A second resistor having one end connected to the second end;
A third end connected to the other end of the second resistor;
A second capacitor having one end connected to the third end;
A fourth end connected to the other end of the second capacitor;
A bridge circuit in which the fourth end and the other end of the first resistor are connected;
The first phase shifter receives the in-phase input signal as a potential difference between the fourth end and the second end of the bridge circuit, and uses the first output signal as a potential of the third end of the bridge circuit. Output the second output signal as the potential of the first end of the bridge circuit;
The second high phase accuracy phase shifter receives the quadrature input signal as a potential difference between the fourth end and the second end of the bridge circuit, and receives the third output signal at the third end of the bridge circuit. And output the fourth output signal as the potential of the first end of the bridge circuit,
Said third high phase accuracy phase shifter receives the subtraction signal as a potential difference between the fourth and second ends of said bridge circuit, said fifth output signal of said third end of said bridge circuit Output as a potential, and output the sixth output signal as the potential of the first end of the bridge circuit,
The fourth high phase accuracy phase shifter receives the addition signal as a potential difference between the fourth end and the second end of the bridge circuit, and receives the seventh output signal of the third end of the bridge circuit. 2. The image suppression filter circuit according to claim 1, wherein the image suppression filter circuit outputs the eighth output signal as a potential of the first terminal of the bridge circuit. Each of the first high phase accuracy phase shifter, the second high phase accuracy phase shifter, the third high phase accuracy phase shifter, and the fourth high phase accuracy phase shifter,
A first resistor;
A first end connected to one end of the first resistor;
A first capacitor having one end connected to the first end;
A second end connected to the other end of the first capacitor;
A second resistor having one end connected to the second end;
A third end connected to the other end of the second resistor;
A second capacitor having one end connected to the third end;
A fourth end connected to the other end of the second capacitor;
A bridge circuit in which the fourth end and the other end of the first resistor are connected;
The first high phase accuracy phase shifter receives the in-phase input signal as a potential difference between the fourth end and the second end of the bridge circuit, and receives the first output signal at the third end of the bridge circuit. Output the second output signal as the potential of the first end of the bridge circuit,
The second high phase accuracy phase shifter receives the quadrature input signal as a potential difference between the fourth end and the second end of the bridge circuit, and receives the third output signal at the third end of the bridge circuit. Output the fourth output signal as the potential of the first end of the bridge circuit,
The third high phase accuracy phase shifter receives the subtraction signal as a potential difference between the fourth end and the second end of the bridge circuit, and receives the fifth output signal from the third end of the bridge circuit and Output as a potential difference between the first ends, output the sixth output signal as a potential difference between the fourth end and the second end of the bridge circuit, the fourth high phase accuracy phase shifter, The addition signal is received as a potential difference between the fourth end and the second end of the bridge circuit, and the seventh output signal is output as a potential difference between the third end and the first end of the bridge circuit, The image suppression filter circuit according to claim 1, 5 or 6 that outputs eight output signals as a potential difference between the fourth end and the second end of the bridge circuit. Each of the first high phase accuracy phase shifter, the second high phase accuracy phase shifter, the third high phase accuracy phase shifter, and the fourth high phase accuracy phase shifter,
A first resistor;
A first end connected to one end of the first resistor;
A first capacitor having one end connected to the first end;
A second end connected to the other end of the first capacitor;
A second resistor having one end connected to the second end;
A third end connected to the other end of the second resistor;
A second capacitor having one end connected to the third end;
A fourth end connected to the other end of the second capacitor;
A bridge circuit in which the fourth end and the other end of the first resistor are connected;
The first high phase accuracy phase shifter receives the in-phase input signal as a potential difference between the fourth end and the second end of the bridge circuit, and receives the first output signal at the third end of the bridge circuit. And outputting the second output signal as a potential difference between the fourth end and the second end of the bridge circuit,
The second high phase accuracy phase shifter receives the quadrature input signal as a potential difference between the fourth end and the second end of the bridge circuit, and receives the third output signal at the third end of the bridge circuit. And the fourth output signal is output as a potential difference between the fourth end and the second end of the bridge circuit,
Said third high phase accuracy phase shifter receives the subtraction signal as a potential difference between the fourth and second ends of said bridge circuit, said fifth output signal of said third end of said bridge circuit Output as a potential, and output the sixth output signal as the potential of the first end of the bridge circuit,
The fourth high phase accuracy phase shifter receives the addition signal as a potential difference between the fourth end and the second end of the bridge circuit, and receives the seventh output signal of the third end of the bridge circuit. The image suppression filter circuit according to claim 1, wherein the image suppression filter circuit is output as a potential, and the eighth output signal is output as a potential of the first end of the bridge circuit. The first high phase accuracy phase shifter, the second high phase accuracy phase shifter, the third high phase accuracy phase shifter, and the fourth high phase accuracy phase shifter are:
A first resistor;
A first end connected to one end of the first resistor;
A first capacitor having one end connected to the first end;
A second resistor having a second end connected to the other end of the first capacitor and one end connected to the second end;
A third end connected to the other end of the second resistor;
A second capacitor having one end connected to the third end;
A fourth end connected to the other end of the second capacitor;
A bridge circuit having the fourth end and connected to the other end of the first resistor;
The first high phase accuracy phase shifter receives the in-phase input signal as a potential difference between the fourth end and the second end of the bridge circuit, and receives the first output signal at the third end of the bridge circuit. And outputting the second output signal as a potential difference between the fourth end and the second end of the bridge circuit,
The second high phase accuracy phase shifter receives the quadrature input signal as a potential difference between the fourth end and the second end of the bridge circuit, and receives the third output signal at the third end of the bridge circuit. And output the fourth output signal as a potential difference between the fourth end and the second end of the bridge circuit,
The third high phase accuracy phase shifter receives the subtraction signal as a potential difference between the fourth end and the second end of the bridge circuit, and receives the fifth output signal from the third end of the bridge circuit and Outputting as a potential difference between the first ends, outputting the sixth output signal as a potential difference between the fourth end and the second end of the bridge circuit;
The fourth high phase accuracy phase shifter inputs the addition signal as a potential difference between the fourth end and the second end of the bridge circuit, and inputs the seventh output signal to the third end of the bridge circuit. 7. The image suppression filter circuit according to claim 1, wherein the output signal is output as a potential difference between the first end and the eighth output signal is output as a potential difference between the fourth end and the second end of the bridge circuit. . Receiving the in-phase input signal, a first high phase accuracy phase shifter for outputting a second output signal having substantially quadrature phase component to the first output signal and the first output signal,
Second high phase accuracy for receiving a quadrature input signal having a phase component substantially orthogonal to the in-phase input signal and outputting a third output signal and a fourth output signal having a phase component orthogonal to the third output signal A phase shifter,
A first subtractor that subtracts the fourth output signal from the first output signal and outputs a subtracted signal;
A first adder that adds the second output signal and the third output signal and outputs an added signal;
A buffer for inputting each of the first output signal and the fourth output signal to the first subtractor;
A buffer circuit for inputting the second output symbol and the third output signal to the first adder;
A pre-stage phase shifter configured by:
A third high phase accuracy phase shifter that receives the subtraction signal and outputs a fifth output signal and a sixth output signal having a phase component orthogonal to the fifth output signal;
A fourth high phase accuracy phase shifter that receives the addition signal and outputs a seventh output signal and an eighth output signal having a phase component orthogonal to the seventh output signal;
A second subtractor that subtracts the eighth output signal from the fifth output signal and outputs a subtraction result as an in-phase output signal;
A second adder for adding the sixth output signal and the seventh output signal and outputting the addition result as an orthogonal output signal;
A buffer circuit for inputting each of the fifth output signal and the eighth output signal to the second subtractor;
A buffer circuit for inputting each of the sixth output signal and the seventh output signal to the second adder;
A plurality of subsequent phase shifters, each of which includes an image suppression filter circuit. The image suppression filter circuit according to claim 11, wherein the buffer circuit has a gain. The image suppression filter circuit according to claim 11, wherein the buffer circuit has a gain of 1 or more. 12. The image suppression filter circuit according to claim 11, wherein the first high phase accuracy phase shifter and the second high phase accuracy phase shifter have the same circuit configuration. 12. The image suppression filter circuit according to claim 11, wherein the third high phase accuracy phase shifter and the fourth high phase accuracy phase shifter have the same circuit configuration. An amplifier for amplifying the input signal;
An input mixer that receives the amplified signal of the amplifier and outputs an in-phase signal and a quadrature signal orthogonal to the in-phase signal;
The image suppression filter circuit according to claim 1, wherein an in-phase input signal corresponding to the in-phase signal and a quadrature input signal corresponding to the quadrature signal are input and an in-phase output signal is output.
An output-side mixer that converts the in-phase output signal of the image suppression filter circuit into an in-phase received signal and a quadrature received signal;
Receiver composed of. A first quadrature modulator that converts the in-phase signal for transmission and the quadrature signal for transmission into an intermediate frequency signal;
The image suppression filter circuit according to claim 1, which generates an in-phase output signal and a quadrature output signal orthogonal to the in-phase output signal based on the intermediate frequency signal;
A second quadrature modulator for converting the in-phase output signal and the quadrature output signal into a radio frequency signal;
Transmitter composed of.

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