JP4127719B2 - Concurrent development system and development method for ASIC and programmable logic device - Google Patents

Description

  The present invention relates to a ASIC and a programmable logic device concurrent development system and development method that a user uses from a computer connected to a network.

  More specifically, it relates to a programmable logic device configuration method in the development of an integrated circuit, and is a block that does not depend on device technology by using only connection information of a port specification of a block that is a result of a circuit architecture study and is a part of a logic design document. A net list called a core (logical core) consisting of the ports connecting the ports is generated, the target block is selected from the core (logical core), grouped, and the grouped core (logical core) data is used. , Integrated circuit development methods, and seamless concurrent development of ASICs and programmable logic devices, ensuring both design quality and shortening development time, and reducing development human resources and costs ASIC and Programmable that can be reduced Logic about concurrent development system and how to develop device.

  In the procedure of the integrated circuit, first, when determining the specification, after carefully examining whether there is a leak or the like, the design is performed according to the specification. FIG. 11 is a flowchart showing an integrated circuit design procedure. First, an ASIC (specific application IC) specification is acquired from the product specification (g1). Next, consider the circuit architecture (g2). Next, circuit design is performed based on the circuit architecture examination result (g3). This circuit design is performed while performing logic verification (g4).

  Next, when the circuit design is completed, logic synthesis of the circuit is performed (g5). When the logic synthesis is completed, the layout is developed based on the logic synthesis result (g6). At this stage, the circuit has been designed. When the circuit can be designed, the circuit is manufactured (g7), and the actual device is evaluated using the manufactured circuit (g8). Of the above sequence, the part according to the present invention is a part related to logic synthesis in step g5.

  In the development of integrated circuits, a study of a circuit architecture that examines a function to be realized with specifications as an input and a circuit configuration to realize the function is performed in the following flow. Usually, in the development of integrated circuits, the functions that realize the product are thoroughly identified from the product specifications, the circuit configuration that realizes the identified function, and the macro such as IP (Intellectual Property) are examined. Do. Here, the macro refers to a macro that can be used without changing RAM, ROM, etc. including IP.

  Estimate the realization scale of the circuit or IP whose configuration has been examined. If it is known in advance, the number of gates is calculated. If the number of gates is not known, the number of flip-flops is calculated from the number of necessary signals and the time required for processing. To calculate the realization scale. Here, a plurality of functions are grouped into one block based on the estimated scale and the number of input / output signals (hereinafter referred to as ports) of each function. This grouping is performed for all functions.

  In the logic design, circuit design is performed for a programmable logic device by means of HDL (hardware description language) or the like based on the above-described function and estimated scale, and on-board function evaluation is performed. After the evaluation was completed, redesign and revalidation were performed in the case of ASIC conversion.

  When cost reduction by ASIC implementation is performed after the function evaluation is completed, it is rare that the design considering the ASIC is performed from the time of designing the programmable logic device (for example, FPGA), and the I / O buffer, Due to the differences between programmable logic devices and ASICs, such as device test circuits and memory macros, redesign occurs based on the design data of programmable logic devices for ASICs. Longer development periods and increased development costs due to dual management, redesign, and functional revalidation are becoming apparent.

  Here, the ASIC has a feature that the development period is long but the cost is low. On the other hand, the programmable logic device (FPGA) has a feature that the development period is short but the cost is high.

  The present invention has been made in view of such problems. In the logic architecture in the development of a large-scale ASIC, the logic architecture, and the circuit architecture examination applied to the concurrent (parallel) development of the layout, Integrated circuit development method applying a method (described in Japanese Patent Laid-Open No. 2000-90142) for generating an inter-block netlist as port-to-port connection information from functionally divided block port information and chip port information And an apparatus for controlling a logic synthesis tool to generate an arbitrary size and number of blocks and inter-block nets constituting an integrated circuit developed by the integrated circuit development method from the inter-block net list, and to share the architecture Integrated circuit development method and integrated circuit capable of realizing and avoiding redesign and reverification as much as possible And its object is to provide a program storage medium storing the developed method.

  In recent years, it has become possible to develop ASICs with more than 10M gates due to semiconductor miniaturization. However, as electronic devices become more sophisticated and complex, specification design, logic design and floor plan, logic synthesis, layout design, The implementation design for timing verification has been prolonged and it has become difficult to ensure the design quality. In particular, the remake of ASIC development not only prolongs the development period of electronic devices, but also increases costs and loses opportunity to market.

  For this reason, programmable logic devices with short development TAT (Turn Around Time) and easy design changes are being used frequently. However, programmable logic devices are expensive and difficult to miniaturize, so In many cases, the function is realized by a logic device, and after debugging by prototyping, ASIC is used at the time of mass production.

  However, even if verification is performed by prototyping a programmable logic device on the premise of ASIC implementation, there is a problem that it is difficult to shorten the total development time in serial development from a programmable logic device to an ASIC. In particular, if a timing problem occurs in the implementation design during ASIC development, there is a possibility that the programmable logic device will be redesigned, and if it is entrusted outside the company such as a semiconductor vendor, the human resources of the entrusted party will be increased. This increases costs associated with securing and securing human resources.

  Furthermore, if a redesign occurs exclusively for an ASIC due to the difference in structure between a programmable logic device and an ASIC device, not only debugging with a programmable logic device becomes meaningless, but also the development period becomes longer and costs increase. Increase. Either way, there will be a loss of opportunity to market.

  As a measure for prolonging the development period accompanying the increase in the scale of ASIC, circuit architecture examination, logic design / verification, and implementation design are performed concurrently as described in JP-A-2000-90142. Due to the complexity of device functions and the rapid movement of the market, specification design, logic design, and verification have become longer, making it difficult to shorten development time. In addition, when developing concurrently, human resources with knowledge of ASIC development and development tools are required, and there is a problem that education of development tools that become complicated as semiconductor technology progresses is required. .

  Therefore, the present invention enables seamless concurrent development of an ASIC and a programmable logic device, ensures both design quality and shortens the development period, and reduces the development resources and costs. -Another object is to provide a logic device concurrent development system and method.

In order to solve the above-described problems and achieve the object, the present invention is an ASIC that is connected to a computer used by a user via a network and that develops an ASIC and a programmable logic device concurrently in response to the user's request. a concurrent development system programmable logic device, the ASIC logic synthesis means for performing a logic synthesis of the ASIC in response to a request of the user, said ASIC logic synthesis logic synthesis result of ASIC created by means of the user ASIC logic synthesis result judgment means for judging whether or not the requested speed performance is satisfied, and programmable logic device logic synthesis for executing logic synthesis of the programmable logic device based on the judgment result by the ASIC logic synthesis result judgment means Means and said A An ASIC logic synthesis execution result by the IC logic synthesis means and a logic synthesis result display means for displaying the execution result of the programmable logic device logic synthesis by the programmable logic device logic synthesis means on the computer, and an ASIC by the ASIC logic synthesis means Logic synthesis notification means for notifying the user of the execution start and execution result of logic synthesis and the execution start and execution result of the programmable logic device logic synthesis by the programmable logic device logic synthesis means, and to the user's request In response, a net list generating means for generating a net list composed of inter-port connection information of a plurality of functional blocks designated by the user from the functional blocks constituting the ASIC, and a net generated by the net list generating means ROM data generating means for generating ROM data in which the logic synthesized target functional block data is embedded in a list and recording the circuit of the programmable logic device, and the ROM data generation result generated by the ROM data generating means ROM data generation result display means for displaying on a computer, and ROM data generation result notification means for notifying the user of the ROM data generation result generated by the ROM data generation means by e-mail .

In addition, the present invention is a method for concurrent development of an ASIC and a programmable logic device that is connected to a computer used by a user via a network, and that meets the user's request, using a concurrent development system for the ASIC and the programmable logic device. Te, and the ASIC logic synthesis step of performing logic synthesis of ASIC in response to a request of the user, whether the logic synthesis result of ASIC created by the ASIC logic synthesis step satisfies a speed performance required of the user ASIC logic synthesis result determination step, programmable logic device logic synthesis step for performing logic synthesis of a programmable logic device based on the determination result of the ASIC logic synthesis result determination step, and ASI by the ASIC logic synthesis step A logic synthesis result display step for displaying a logic synthesis execution result and a programmable logic device logic synthesis execution result by the programmable logic device logic synthesis step on the computer; and an ASIC logic synthesis execution start by the ASIC logic synthesis step; A logic synthesis notifying step for notifying the user of the execution result and the execution of the programmable logic device logic synthesis by the programmable logic device logic synthesis step and the execution result by e-mail, and configuring the ASIC according to the user's request A netlist generating step for generating a netlist composed of inter-port connection information of a plurality of functional blocks designated by the user from the functional blocks to be processed, and a logically synthesized target functional block in the netlist generated by the netlist generating step. ROM data generating step for generating ROM data in which the circuit of the programmable logic device is recorded by inserting the data of the memory, and ROM data for displaying the generation result of the ROM data generated by the ROM data generating step on the computer The method includes a generation result display step and a ROM data generation result notification step of notifying the user of the generation result of the ROM data generated by the ROM data generation step by e-mail .

  According to this invention, the ASIC logic synthesis is executed in response to the user's request, it is determined whether or not the created ASIC logic synthesis result satisfies the speed performance requested by the user, and programmable based on the determination result Execute logic synthesis of logic device, display execution result of ASIC logic synthesis and execution result of programmable logic device logic on computer, start execution of ASIC logic synthesis and execution result, and execute programmable logic device logic synthesis Since the start and the execution result are notified to the user by e-mail, the user does not need to set up a logic synthesis specialist, and can perform the logic synthesis at any time. It can be kept uniform, and you can be notified of the start of synthesis and the result by e-mail Come, there is no need to check in regularly computer the progress of logic synthesis.

Further , according to the present invention, a netlist composed of inter-port connection information of a plurality of functional blocks designated by the user is generated from the functional blocks constituting the ASIC in response to a user request, and the synthesized netlist is logically synthesized. Since the ROM data in which the target functional block data is inserted and the programmable logic device circuit is recorded is generated, the generated ROM data generation result is displayed on the computer, and the user is notified by e-mail. The user does not need a development environment dedicated to the programmable logic device, and can reduce the load, time, and cost for creating ROM data recording the circuit of the programmable logic device.

  Further, the present invention uses a temporary flip-flop or the like for the input terminal and the output terminal of the functional block when the design of the functional block constituting the ASIC specified by the user is not completed and there is no circuit data. And provisional net list generation means for generating a net list in which the inserted circuit is inserted.

  According to the present invention, when design of a functional block constituting an ASIC designated by a user is not completed and no circuit data exists, a circuit using temporary flip-flops or the like for the input terminal and output terminal of the functional block The netlist is inserted, so the verification by prototyping of the programmable logic device can be performed even if the design of the functional block that is not the verification target is not completed. Can be made more efficient.

  The present invention also relates to monitoring means for monitoring the scale of change between the latest circuit data held by the user and the circuit data taken into the implementation design by the implement designer, and the monitoring results and layout design by the monitoring means. A change timing notification means for notifying the user and the ASIC implementation designer by e-mail that the change is in a timing of reflection in the implementation design of the ASIC when the planned date and time is reached based on time; and Reflection stop requesting means for requesting stop by the user changing the reflection date in response to the change timing notification means is further provided.

  According to the present invention, the scale of the change between the latest circuit data held by the user and the circuit data taken into the implementation design by the implement designer is monitored, and the date and time planned based on the monitoring result and the time taken for the layout design. When it reaches, the user and the ASIC implementation designer are notified by e-mail that it is time to apply the change to the ASIC implementation design, and the user requests a stop by changing the reflection date in response to this notification. Therefore, it is possible to efficiently reflect the changes that have occurred in the layout design of the ASIC, and by setting the timing to reflect the changes, the user can determine how long it can be changed. The schedule can be reviewed at an early stage.

  According to the present invention, ASIC logic synthesis is executed in response to a user request, and it is determined whether or not the created ASIC logic synthesis result satisfies the speed performance requested by the user, and programmable based on the determination result. Execute logic synthesis of logic device, display execution result of ASIC logic synthesis and execution result of programmable logic device logic on computer, start execution of ASIC logic synthesis and execution result, and execute programmable logic device logic synthesis Since the configuration is such that the start and execution results are notified to the user by e-mail, the user does not need to have a dedicated logic synthesis person, and can perform logic synthesis at any time. It can be kept uniform, and you can be notified of the start of synthesis and the result by e-mail An effect that it is not necessary to check regularly the computer progress of logic synthesis.

  Further, according to the present invention, a netlist composed of inter-port connection information of a plurality of functional blocks designated by the user is generated from the functional blocks constituting the ASIC in response to a user request, and logical synthesis has been performed on the generated netlist Since the ROM data in which the data of the programmable logic device is recorded by inserting the data of the target functional block is generated, the generation result of the generated ROM data is displayed on the computer and notified to the user by e-mail. This eliminates the need for a development environment dedicated to the programmable logic device, and can reduce the load, time, and cost of creating ROM data recording the circuit of the programmable logic device.

  In addition, according to the present invention, when design of a functional block constituting an ASIC specified by a user is not completed and circuit data does not exist, temporary flip-flops are used for the input terminal and output terminal of the functional block. Therefore, even if the design of the functional block that is not the verification target has not been completed, the verification by prototyping can proceed. Thus, it is possible to improve the efficiency of verification.

  Further, according to the present invention, the scale of change between the latest circuit data held by the user and the circuit data taken into the implementation design by the implement designer is monitored, and the plan is based on the monitoring result and the time taken for the layout design. When the date and time arrives, the user and the ASIC implementation designer are notified by e-mail that it is time to reflect the change in the ASIC implementation design, and in response to this notification, the user changes the reflection date and stops. Therefore, it is possible to efficiently reflect the change that has occurred in the layout design of the ASIC and to determine how long the user can make the change by setting the timing to reflect the change. It can be done and the schedule can be reviewed at an early stage.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a flowchart showing the principle of the method of the present invention. According to the present invention, the connection between ports and ports of an arbitrary scale and number is made by means of selecting and grouping arbitrary blocks having a connection relationship from ASIC cores (logical cores) which are block port-port connection information. Generate HDL format core (logic core) that can be read by logic synthesis tool consisting of information (step 1), create temporary chip design with logic synthesis tool from chip terminal information, and generate terminals in this design (Step 2), the same design as in Step 2 is generated as a cell in the created design (Step 3), the port of the same name between the design and the cell is connected (Step 4), and the network between the connected ports Insert the I / O buffer depending on the device technology (step 5), and the core created in step 1 Replacing the logic core) and cells, to expand the design hierarchy is the top hierarchy, to generate a net list (step 6), characterized in that.

  In the present invention, an entity that is a port specification of a block is created from a port name, a range, and an input / output definition, and is output to a file (written to a file). Check if the output port name of the output source instance specified for the input port of a block is correct by means of creating an output signal file for the ports defined for output in the input / output, and specify the device as the output source instance name If there is a keyword definition such as I / O to connect to the terminal of the package, the name in the output port name of the output source instance is used as the terminal name of the device package, and whether the terminal is one or more ( A vector) based on the definition of the range, a means for determining whether the terminal is an input or an output from the input / output definition, and a means for determining whether the terminal is bidirectional from the type definition Create an entity that is a port specification of the core (logical core) and output it to a file. Here, an instance is a circuit unit.

When the port of the block is input-defined in the input / output definition, means for checking whether a pair of the output source instance name of the port and the output port name of the output source instance exists in the output signal file, and the check result When it is determined that ports can be connected between instances, a signal for connecting the instances is generated and output to a file. When processing is completed, including checking all instances, the core (logical core) entity and the inter-instance net are read, a core (logical core) is generated and output to a file.
If the check result is satisfactory, the HDL (Hardware Description Language) is composed of block input / output port specifications, a connection net between instances, and a connection net between instances and external terminals that are terminals of the device package, and has no logical design part. ) File (hereinafter referred to as a core (logical core)).

  Therefore, according to the method of generating the core (logical core) of the present invention, there is an effect that the quality of the port specification of the block serving as the input of the RTL design can be secured in advance in the development of the integrated circuit, and there are many functional blocks However, even in the development of a large-scale integrated circuit with many design resources, the connection between the blocks can be confirmed in advance, thereby ensuring that the chip is assembled.

Embodiment 1 FIG.
FIG. 2 is an operation explanatory diagram of Embodiment 1 of the present invention. In this figure, the circuit architecture study result is input, design data is shared, and an integrated circuit is developed while sharing the circuit architecture.

  When designing a function to be realized using HDL as a means, a chip which is a product itself is configured by an instance having a certain function. This instance refers to a block composed of a plurality of functions designed in HDL. If a specific block is necessary for realizing the function of the chip, a plurality of such blocks are referred to. .

  The flow of the present invention will be described with reference to FIG. X, Y, and Z are tables in which port specifications of blocks created from circuit architecture examination results are defined according to a predefined format. These tables X, Y, and Z are always created when designing a block, and block name, instance name, port name, range, input / output, type, output source instance name, output source instance output port It consists of names. These data are input manually by the user. Thus, it is a point of the present invention to prepare each table in advance.

  S1 inputs the table data of all the above-mentioned instances, defines a means for checking whether the instances and the external terminals defined as terminals of the device package are connected without contradiction, and defines a net between the instances. This is a step of generating a core (logical core) consisting only of block ports and inter-block connection information. If there is an error in step S1, the error is returned to the user, and the user starts data input again (the circular arrow 1 shown in the figure indicates repetition).

  S2 refers to the FPGA table 2, reads the core (logic core) output in step S1 into the logic synthesis tool, selects a group of instances to be programmable logic devices by controlling the function of the logic synthesis tool, and selects hierarchical information. This is a step of generating a new core (logical core) in the maintained state and outputting a net list of cores (logical cores) similar to the output of step S1 that does not include an I / O buffer or the like depending on device technology. In this figure, X and Y are designated by the user.

  In S3, a temporary core (logical core) is generated from the terminal name of the terminal specification table data of the device package in a predefined format, and an I / O buffer depending on the device technology specified by the table data is generated as a temporary core ( This is a step of replacing the net list of step S2 after insertion into the port of the logical core), which is the point of the present invention. After the netlist of the target device chip is created by this processing, the function of the logic synthesis tool is controlled, and the circuit data that has been subjected to logic synthesis by the target device technology is read from the FPGA synthesis result library 3 and corresponding. It is inserted into a block to complete a netlist of a desired device. The net list generated as an FPGA is fitted with an FPGA layout tool and converted into ROM data.

  Further, from step S2, the ASIC is made into an ASIC by referring to the ASIC synthesis result library 4.

  According to the first embodiment, in integrated circuit development, there is an effect that the quality of the port specification of a block serving as an input for RTL design can be secured in advance, and there are many functional blocks and large-scale integration with many design resources. Even in the development of a circuit, the connection between the blocks can be confirmed in advance, so that it can be guaranteed that the chip is always assembled.

  FIG. 3 is a block diagram showing an embodiment of the logic synthesis tool control device of the present invention. In the figure, 22 is a control device for controlling the overall operation, 24 is a CRT for displaying various information, 21 is an input device for inputting various commands to the control device 22, 23 is connected to the control device 22, It is a storage device that stores information.

  The input device 21 inputs a start command for a core (logical core) generation program and a logic synthesis tool control command. The storage device 23 includes a logic synthesis tool, a core (logical core) generation program, and a logic synthesis control program. It is remembered.

  When the block (table file) is specified from the input device 21 and a core (logical core) generation program start command is input, the core (logical core) generation program reads the table file, generates a core (logical core), and the storage device 23. Output to file. If there is an error during this process, the error information is displayed on the CRT 24 which is a display device.

  If there is an error, the designer corrects the table file and executes the command again. In the control of the logic synthesis tool, first, necessary data for control is prepared as a file, and stored in a predetermined location in the storage device 23 together with the core (logical core) file generated by the core (logical core) generation program. . When a control command for the logic synthesis tool is input from the input device 21, the logic synthesis tool is activated and the processing result is displayed on the CRT 24. If the process fails midway, the state at the time of failure is displayed on the CRT 24.

  FIG. 4 is a block diagram showing an embodiment of the control device 22 of FIG. The same parts as those in FIG. 3 are denoted by the same reference numerals. In the figure, 31 is a CPU for controlling the overall operation, 32 is a memory for storing various information, 21 is a keyboard for inputting various commands, and 24 is a CRT as a display device. A storage device 23 includes a core (logical core) generation program 36, a logic synthesis tool control program 35, a logic synthesis tool 34, and an operating system (OS) 33. Reference numeral 37 denotes a bus for connecting the components. As the storage device 23, for example, a hard disk device is used.

  In the system configured as described above, when the CPU 31 inputs a command from the keyboard 21, the CPU 31 searches the storage device 23, calls the corresponding program, and executes the corresponding program.

  FIGS. 5 and 6 are flowcharts showing a core (logical core) generation program. Here, description will be made using the X, Y, and Z table data of FIG. The table data X, Y, Z (instances are also X, Y, Z) files are read and processed one by one. The data of X is read by F1, all the data of the port A table is extracted and stored in the memory by F2, and the next processing is performed while referring to the data of the memory. In F2 ′, it is checked whether or not the port is an output.

  Since port A is an input, step F3 of outputting the instance name and port name to file A is skipped and the process proceeds to F3 ′. In F3 ′, it is checked whether or not there is a connection keyword with the package terminal. Next, since there is no connection keyword of the package terminal, F4 for storing the package terminal information in the memory is skipped, and all data of the next port B is stored in the memory.

  Since the port B is an output, “XB” is output to the file A of the storage device 23 in the step F3. Here, X is a file name, and B is a port name. Next, since there is no connection keyword for the package terminal, F4 is skipped and all data of the next port Z is stored in the memory. Since the port Z is an output, "XZ [2: 0]" is output to the file A in the step F3. Here, [2: 0] indicates 2, 1, 0.

  Next, since there is no connection keyword for the package terminal, F4 is skipped and all data of the next port I is stored in the memory. Since port I is an input, F3 is skipped, and since there is a connection keyword “IO” of the package terminal, “INPUT, in, 2: 0” is stored in the memory as the port name of the core (logical core). Next, it is checked whether or not all ports are finished (F4 ′). If all the ports have not ended, the process returns to step F2.

This completes the processing of all ports of X, and if it is VHDL, an entity file having the following information is output to the storage device 23.
A: in std_logic;
B: out std_logic;
Z: out std_logic vector (2 downto 0);
I: in std_logic;

The above processing is also performed for the Y and Z data, and when all the files are completed (F5 ′), if it is VHDL by the step of F6, the entity file of the core (logical core) having the following information is stored. Output to the device 23.
INPUT: in std_logic;
OUT: out std_logic;
Further, the following data is recorded in the file A.
XB, XZ [2: 0], YC [1: 0], YO, ZF

  Next, the data of file A is read in step F7, stored in the memory in step F8, and processed one file at a time. In step F8 ′, it is checked whether the port is an input. Here, X table data will be described as an example. Since port A is an input, output source Y and port name C are extracted in step F9, and YC [1: 0] is searched with the data stored in F8 in the subsequent step F10. Then, it is checked whether or not they match at F10 ′.

Since it exists as a result of the search, the following connection information is output to the file B in step F12. If the results do not match, error information indicating that the port name or range is different is output to the log file of the storage device 23 and also displayed on the CRT 24.
A => YC
Next, similarly, since the port B is an output, the following connection information is output to the file B by the step F11.
B => XB
Next, similarly, since the port Z is an output, the following connection information is output to the file B by the step F11.
Z => XZ

Next, although port I is an input, “IOINPUT” cannot be found in the search of step F10, and is output to the log file as an error in step F13 and also displayed on the CRT 24. However, this is not a problem in the case of a port connected to a package terminal, and conversely, which port of which instance is connected to which terminal of the package can be confirmed from the error information output in the log. Next, the following connection information is output to the file B in step F12.
I => IOINPUT
In step F12 ′, it is checked whether all ports in all tables have been completed. If not, the process returns to step F8 ′.

  The above processing is also performed for the Y and Z table data. When the processing is completed, the port for which connection information could not be created is output to the log file in step F14, and the core (logic) output in step F6 by step F15. The core) entity list and the connection information output in the steps F11 and F12 are combined to generate a core (logical core) netlist, which is output to the storage device 23 and the program is terminated.

  Next, a detailed procedure of the first embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a flowchart showing the detailed procedure of the first embodiment of the present invention. This flowchart shows in detail the processing after S2 in which the core (logical core) output in S1 is input in the first embodiment described in FIG. In the figure, the solid line shows the flow of processing, and the broken line shows the data flow. Before executing the process, operate the input device and copy the core (logical core) output in step S2 and, if necessary, the control file output in the following description to the location in the storage device referenced by the control program Prepare by such means.

  First, the core (logical core) design is checked (a1). Then, it is checked whether or not the core (logical core) design is OK (a1 ′). If it is not OK, the table data described in FIG. 2 is checked and re-executed (a10). If it is OK, the files 12 and 13 are referred to, grouped (a2), and stored as a core (logical core) 10. Next, a dummy core (logical core) is generated with reference to the table 14 consisting of terminal names and buffer names (a3). As a result, a dummy core (logical core) 11 is generated.

  Next, an I / O buffer is inserted based on the dummy core (logical core) 11 and the table 14 (a4). Next, the core (logical core) 10 and the dummy core (logical core) 11 are compared and checked (a5). Then, it is checked whether or not it is OK (a5 ′). As a result of the comparison, if it is OK, termination processing is performed (a6). If it is not OK, the terminal specification of the device package is checked (a9), and the table data described in FIG. 2 is checked and then re-executed (a10).

  When the termination process of step a6 is completed, the circuit data is inserted with reference to the synthesis result file 15 (a7), and the DFT circuit is inserted with reference to the file 16 (a8).

  Next, each step described with reference to FIG. 7 will be described in more detail. FIG. 8 is a flowchart showing core (logic core) design check control. First, it is checked whether there is a core (logical core) file (a11), and if there is, it is read by a logic synthesis tool (a12). If not, do nothing. In step a1 (see FIG. 7), the core (logical core) output in step S2 is input, and the HDL description grammar of the core (logical core), the empty input port, etc. are checked. If the file exists, the core (logic core) is read by the logic synthesis tool in step a12. The logic synthesis tool has a function for checking the grammar and the like when it is read. If the result is an error, the contents are checked with the CRT, and the table data describing the port specification of the block is reviewed as shown in step a10. Execute the design check again.

  FIG. 9 is a flowchart showing the grouping control, and shows details of step a2 in FIG. First, it is checked whether there is a core (logical core) file (a13), and if there is, it is checked whether there is an instance file to be grouped (a14). If there is a problem, that is, if there is no problem in the result of step a1, if there is a file 13 in which the block name to be converted into a programmable logic device is described, one block per line, it is read (a21). Grouping is performed by controlling the grouping function of the logic synthesis tool as a new core (logical core) while maintaining the hierarchical information of the block (a22).

  When using the grouping function, the port name of the core (logical core) is the net name that connects the instances, so all the ports of the core (logical core) are connected to the core (logical core). Trace and create a new port in the core (logical core) with the port name of the first instance found, and generate a net connected to the core (logical core) port that is the net name Connect and delete the port with the net name (a23). This is to create a new port and erase the old port.

  Next, it is checked whether there is monitor port information (a23 '). If there is, a port is generated in the core (logical core) with the port name of the designated instance and connected to the terminal of the block (a24). If not, a netlist not including an I / O buffer or the like depending on the device technology is output to the storage device 10 (see FIG. 7) (a25). In this case, in the display device, it can be confirmed using the display function of the logic synthesis tool.

  In this step a2, if there is another need, the grouped block ports can be generated as core (logical core) ports (a24). This function is used when there is a port to be monitored during the function evaluation of the programmable logic device. As shown in the file 12, the designation method is performed by reading a file in which a port name is described in one port per line after grouping and port name change.

  Up to this point, the designer himself / herself generates the core (logical core) using the data that determines the port specifications of the block, so there should be no mistake in the port connection between the blocks in the core (logical core). However, in the case of an ASIC that uses the core (logical core) generated in step S1 (see FIG. 2) as it is, the terminal name of the device package defined in the table data of the block in the core (logical core) is the terminal specification of the device package. Therefore, there may be a difference due to a simple mistake or a change from the printed circuit board design. On the other hand, if the port of the core (logical core) generated in step a2 (see FIG. 7) becomes a terminal of the device package, the port becomes a specification, so there may be a difference as described above There is. This problem is solved in steps a3 to a5.

  FIG. 10 is a flowchart showing the I / O buffer insertion control and an image of processing. This flowchart shows the processing of step a4 in FIG. In the following description, a3 to a5 are different, but the process is a series of processes with one command.

  First, it is checked whether there are external terminal information and a core (logical core) file (a15). In some cases, the following processing is performed. In a3, unlike a2, table data of the terminal specifications of the device package in which the terminal name is defined in the first column and the I / O buffer name depending on the device technology used in the second column is defined as shown in 14 of FIG. If it exists, it is read to create a dummy chip design (first design describing the terminal information of the name in the first column) (a31), and the dummy chip design is stored in the cell (first A second design describing the same terminal information as the first design described as a lower layer of the design, connecting ports of the same name between the design and the cell, and connecting a dummy core (logic Core).

  In step a4, the dummy core (logical core) of the storage device 11 is read, and the I / O buffer in the second column of the device package terminal specification table data 14 is read from the dummy core (logical core) net. An I / O buffer depending on the device technology is inserted from the terminal information (a32).

  In step a5, among the ports of the dummy core (logical core), a device-specific port that is not related to the function and is not related to the logic is deleted and replaced with the core (logical core) of the storage device 10 as an internal cell. (A33), it is checked whether there is a mismatch of terminal names (a33 ′). If all the port names between the two cores (logical cores) match, the insertion is successful. By doing so, the terminal name of the device package terminal specification table data and the port name of the core (logical core) can be cross-checked, and the above problem can be solved. If there is, the process ends. If not, the net list is output.

  If unsuccessful, the terminal specification of the device package is checked as shown in step a9 and re-executed from step a3, or the table data defining the terminal specification of the block is checked as shown in step a10, and step S1 is executed. Re-execute from (see FIG. 2). If successful, the chip is formed by expanding the core (logical core) hierarchy.

  In step a6, flip-flops are connected to the input / output ports of all the blocks of the chip and terminated. This termination processing is for generating a net list without any problem even if there is a block for which circuit design has not been completed, and enabling layout work.

  In step a7, the logic-synthesized circuit data is read from the synthesis result library and inserted into the corresponding block. At this time, if there is no synthesis result for the block inside the chip, and the design name or cell name of the block conforms to the naming rule, the input port and output port of the block are determined according to the rule in advance. Connect internally.

  This processing does not exist in the case of a programmable logic device, and is performed when a specific block such as a DLL of the programmable logic device is used as an ASIC. The architecture can be maintained by the process of connecting the blocks without deleting them. If a macro such as a memory exists in the block, it is replaced with circuit data of the memory specific to the device.

  a8 is a process in the case of the ASIC, and the file 16 defining the order of the blocks connecting the SCAN test circuit or the automatic insertion of the SCAN test circuit for testing the device is input and connected in the definition order.

  As described above, according to the first embodiment, a core (logical core) is generated from data from a design document, and the hierarchical structure and connection information are retained from this core (logical core). By creating a new core (logical core) for a logic device, there is an effect that the circuit architecture can be shared, and the device technology within the instance that verified the function by filling the circuit data into this core (logical core) The circuit data that does not depend on the network and the net between instances can be avoided when the ASIC is used. Therefore, there is an effect that the concurrent development of the ASIC and the programmable logic device can be efficiently advanced.

Embodiment 2. FIG.
Next, the ASIC and FPGA concurrent development system according to the present invention will be described in detail. Note that logic design languages include C language and UML. In the second embodiment, HDL is described as a design language.

  First, the concept of concurrent development of ASIC and FPGA according to the second embodiment will be described. FIG. 12 is an explanatory diagram for explaining the concept of concurrent development of ASIC and FPGA according to the second embodiment. As shown in the figure, the feature of concurrent development of ASIC and FPGA is that ROM data that records the FPGA circuit necessary for prototyping verification in order to advance prototyping verification by FPGA to ASIC implementation design and concurrent. Provided from ASIC implementation design, FPGA and ASIC development can be seamless.

  In this concurrent development of ASIC and FPGA, prototyping verification by FPGA is considered in circuit architecture examination, division of realized functions in an implementation circuit of an appropriate expected scale, and hierarchization of functions related to structural differences between ASIC and FPGA The common functional block configuration between the ASIC and the FPGA design and the port specification of the functional block are created. The functional block configuration and the functional block port specification data are common data for the ASIC implementation design floorplan, logic synthesis, and layout design.

  In RTL design and verification, RTL design common to ASIC and FPGA is performed according to the structure of the circuit architecture examination result, and software verification is performed using a logic verification tool with emphasis on the corner case for each function. If the ASIC logic synthesis is performed concurrently with the RTL design / verification and the characteristics as the ASIC can be secured, then the FPGA logic synthesis is performed, and a circuit is sequentially formed on the FPGA on the prototyping board. Allows verification by prototyping.

  On the other hand, in the layout of ASIC, ASIC development from the completion of verification by prototyping of FPGA by reflecting the verification results by soft verification and prototyping on a concurrent basis based on the common functional block configuration between ASIC and FPGA design. Reduce the time to completion.

  Next, a system configuration of an ASIC and FPGA concurrent development system according to the second embodiment will be described. FIG. 13 is a functional block diagram showing a system configuration of an ASIC and FPGA concurrent development system according to the second embodiment. As shown in the figure, the ASIC and FPGA concurrent development system 200 includes a firewall 210, a Web server 220, a user authentication server 230, a user management server 240, a logic synthesis server 250, a mail server 260, A file server 270, an application server 280, and a monitoring server 290 are included. The ASIC and FPGA concurrent development system 200 can be used from the Web client 100 via the Internet.

  The firewall 210 is a computer that accepts only an access request in accordance with a set communication procedure in response to an access request from the Internet, and prevents unauthorized access from the outside to the concurrent development system 200 of the ASIC and FPGA.

  The Web server 220 is a computer that transmits information in response to a request from the Web client 100 made through the Internet, and the logical CORE is obtained only from the connection information between the function block ports and the function block ports constituting the ASIC or FPGA. A logical CORE generation interface program 221, a logical synthesis interface program 222, a fitting interface program 223, a status display interface program 224, a format file necessary for logical CORE generation and a format file necessary for logical synthesis. Executes these programs in response to a request from the Web client 100 and transmits the result to the Web client 100.

  The user authentication server 230 is a computer that performs user authentication, and a user name and a password to be used based on a contract are registered. The user management server 240 is a computer for registering and deleting a user, and a user name used based on a contract, a project name and an e-mail address to be described later are registered.

  The logic synthesis server 250 is a computer having an ASIC logic CORE generation program 251, an FPGA logic CORE generation program 252, an ASIC logic synthesis program 253, an FPGA logic synthesis program 254, and a fitting program 255 which is an FPGA layout. The logic synthesis and fitting program in the logic synthesis server 250 is started from the logic synthesis interface program 222, reads the RTL source stored in the file server 270, and performs logic synthesis of ASIC and FPGA and fitting of FPGA. To do.

  The mail server 260 is a computer having mail transmission / reception software, and distributes processing information executed from the Web server 220 and information from the Web client 100 to the user and the system.

  The file server 270 is a storage medium for storing a logic synthesis target RTL source, a logic synthesis result, FPGA ROM data, and the like. FIG. 14 is a diagram showing an example of a directory structure for storing data in the file server. A project 41 shown in FIG. 4 is a directory of a project name for developing an ASIC and FPGA or a nickname of the ASIC, and this name is set based on a contract.

  The IO 42 is a directory for storing data for generating a logical CORE, and stores a logical CORE generation table file describing the port specifications of the functional blocks shown in FIG. 15 for each functional block constituting the ASIC. The directory ASIC 48 and the logical CORE generation interface program 221 have a directory FPGA 49 for copying and storing the logical CORE generation table file in the directory ASIC 48 in accordance with the user's specification. Further, under the directory FPGA 49, there are as many directories as the number of FPGAs designated by the user. Details of the logical CORE generation table and the logical CORE generation interface program 221 will be described later.

  The CORE 43 is a directory for storing the logical CORE generated by the logical CORE generation program, the directory ASIC 50 for storing the ASIC logical CORE generated from the port specification of the functional block configuring the ASIC, and the port of the functional block configuring the FPGA. A directory FPGA 51 for storing the logic CORE of the FPGA from the specification is provided.

  The RTL 44 is a directory for storing circuit design data (hereinafter referred to as RTL) expressed in HDL (hardware description language) uploaded by a user from a logic synthesis interface, which will be described later, and is stored in units of functional blocks constituting an ASIC logic CORE. And a directory FPGA 53 for copying and storing the RTL in the ASIC directory according to the user's specification.

  The SYNTHESIS 45 is a directory for storing the result of logical synthesis of the RTL by the logical synthesis server 250. The directory ASIC 54 having a directory for storing the logical synthesis result of the ASIC in units of functional blocks constituting the logical core of the ASIC, and the respective FPGAs. A directory FPGA 55 having a directory for storing the logic synthesis results of

  The ROM 46 is a directory for storing ROM data for storing FPGA circuit data generated after fitting, which is a layout of the FPGA based on the logic synthesis result of the FPGA, and has a directory for storing for each FPGA. LAYOUT 47 is a working directory in which an ASIC layout designer is responsible for ASIC layout design.

  The application server 280 is a computer having a program for performing an ASIC floor plan, layout design, and timing verification. With this computer, the implement designer performs ASIC floorplanning, layout design, and timing verification.

  The monitoring server 290 acquires the user name and the project name registered in the user management server 240, and the data in the directory LAYOUT 47 managed by the implement designer and other directories in the data in the respective project name directories. The time required for the comparison, logic synthesis, and layout processing by the tool is collected twice a day, and the first time notifies the implementation designer of the changes. The computer updates the schedule reflecting the change based on the time collected for the second time.

  Next, a processing procedure of the ASIC and FPGA concurrent development system 200 according to the second embodiment will be described. FIG. 16 is a flowchart showing a processing procedure of the ASIC / FPGA concurrent development system 200 according to the second embodiment.

  As shown in the figure, when the ASIC and FPGA concurrent development system 200 is accessed using the Web client 100, the Web server 220 sends the login screen display control data shown in FIG. The client 100 displays a screen based on the received data. When the user inputs the user name and password registered based on the contract on this login screen and presses the Login button, the Web client 100 sends the user name and password to the Web server 220.

  The Web server 220 inquires of the user authentication server 230 about the received user name and password. The user authentication server 230 confirms whether or not the user name and password are registered (step S501), and returns the result to the web server 220. When rejected from the user authentication server 230, the Web server 220 sends display control data for the login rejection screen to the Web client 100, and the Web client 100 displays a login rejection on the screen based on the received data and ends. (Step S502).

  When the web server 220 receives a login from the user authentication server 230, it sends the display control data for the procedure screen shown in FIG. 18 to the web client 100, and the web client 100 displays the procedure screen based on the received data. (Step S503).

  The user selects a menu according to the procedure screen shown in FIG. 18, and performs concurrent development of the ASIC and the FPGA. When the user selects “Format 1” and “Format 2” (Yes in Step S504), a format file necessary for the design of the target in the Web server 220 is downloaded to the Web client 100 (Step S505).

  “Format 1” is the format data of the logical CORE generation table shown in FIG. “Format 2” is format data of a table in which terminal names and terminal numbers assigned to ASIC packages used in ASIC logic synthesis, which will be described later, and IO buffers that electrically interface the ASIC and external devices are defined.

  When the user selects logical CORE generation (Yes in step S506), the Web client 100 sends the selection of logical CORE generation to the Web server 220, and the Web server 220 activates the logical CORE generation interface program 221 (step S507). ).

  When the user selects logic synthesis (Yes in step S508), the web client 100 sends the fact that logic synthesis is selected to the web server 220, and the web server 220 activates the logic synthesis interface program 222 (step S509).

  When the user selects the fitting (Yes in step S510), the web client 100 sends the fact that the fitting is selected to the web server 220, and the web server 220 activates the fitting interface program 223 (step S511).

  When the user selects the status display (Yes in step S512), the web client 100 sends the status display selected to the web server 220, and the web server 220 activates the status display interface program 224 (step S513).

  Next, the processing procedure of the logical CORE generation interface program 221 will be described. FIG. 19 is a flowchart showing the processing procedure of the logical CORE generation interface program 221. As shown in the figure, the logical CORE generation interface program 221 sends display control data for the logical CORE generation interface screen shown in FIG. 20 to the Web server 220, and the Web server 220 displays the received logical CORE generation interface screen. The control data is sent to the Web client 100, and the Web client 100 displays the logical CORE generation interface screen based on the received logical CORE generation interface screen display control data (step S801).

  The user inputs the project name, selects the execute button, and defines the IO specifications of the functional blocks constituting the ASIC for generating the ASIC logical CORE according to the file selection screen displayed by the Web client 100. FIG. The file of the logical CORE generation table shown in Fig. 2 is specified.

  The Web client 100 sends the specified data of the project and the file of the IO logical CORE generation table to the Web server 220. The Web server 220 stores the IO 42, CORE 43, RTL 44, and SYNTHESIS 45 shown in FIG. , ROM 46, LAYOUT 47, and the like (step S802), the logical CORE generation table file is stored in the directory ASIC 48 under the IO 42, the project name is specified, the ASIC logical CORE generation program 251 is executed, and the execution process The ID is stored in the memory (step S803).

  Here, a processing procedure of the ASIC logic CORE generation program 251 will be described. 21 and 22 are flowcharts showing the processing procedure of the ASIC logic CORE generation program 251. As shown in FIG. 21, the ASIC logic CORE generation program 251 reads the logic CORE generation tables X, Y, and Z shown in FIG. 15 from the directory ASIC 48 shown in FIG. 14 and processes each file one by one. .

  The logic CORE generation tables X, Y, and Z are tables in which the port specifications of the functional blocks created from the circuit architecture examination result are defined according to the defined “format 1”. This table is always created when designing a functional block, and consists of the functional block name, instance name, port name, range, input / output, type, output source instance name, output port name of the output source instance, etc. . An instance refers to a function block that constitutes an ASIC. When a plurality of function blocks having the same function are used, the instance name is changed and incorporated.

  First, X data is read (step S1001), all data in the table of port A is extracted and stored in the memory (step S1002), and it is checked whether port A is output (step S1003). As a result, since port A is an input, the presence / absence of the connection keyword “IO” of the package terminal is checked (step S1005). As a result, since there is no connection keyword “IO”, all data of the next port B is stored in the memory.

  Since port B is an output, "XB" is output as a file with the name A to the directory ASIC 50 in FIG. 14 (step S1004). Next, since there is no connection keyword “IO” of the package terminal, all data of the next port Z is stored in the memory. Since port Z is an output, "XZ [2: 0]" is output to file A. Next, since there is no connection keyword “IO” for the package terminal, all data of the next port I is stored in the memory.

Port I is an input, and next there is a connection keyword “IO” of the package terminal, so “INPUT, in, 2: 0” is stored in the memory as the port name of the logical CORE (step S1006). This completes the processing of all the ports of X (Yes in step S1007), and outputs the entity file defining the port name, input / output, and range information according to the HDL syntax to the directory ASIC 50 of FIG. 14 with the name of X. (Step S1008). If the output content is VHDL, it is as follows.
A: in std_logic;
B: out std_logic;
Z: out std_logic vector (2 downto 0);
I: in std_logic;

The above processing is also performed for Y and Z data. At this stage, the following data is recorded in the file A.
XB, XZ [2: 0], YC [1: 0], YO, ZF

When the processing of all the files X, Y, and Z is completed (Yes in step S1009), the data of the file A (step S1010) is read and stored in the memory (step S1011), and the processing is performed for each file. Here, X table data will be described as an example. First, it is checked whether or not the port A is an input (step S1012). As a result, since the port A is an input, the output source Y and the port name C are extracted (step S1013). Then, the memory is searched with YC [1: 0] (step S1014), and the presence or absence of matching data is checked (step S1016). As a result, since matching data exists in the memory, the following connection information is output as a file with the name B to the directory ASIC 50 in FIG. 14 (step S1018). If the results do not match, error information indicating that the port name or range is different is output to the log file of the directory ASIC 50 (step S1017).
A => YC

Similarly, since the port B is an output, the following connection information is output to the file B of the directory ASIC 50 (step S1015).
B => XB

Similarly, since the port Z is an output, the following connection information is output to the file B of the directory ASIC 50.
Z => XZ

Similarly, since port I is an input and “IOINPUT” cannot be found by the search, it is output to the log file of the directory ASIC 50 as an error. However, in the case of a port connected to a package terminal, this is not a problem. Conversely, it is possible to check which port of which instance is connected to which terminal of the package from the error information output in the log. Next, the following connection information is output to the file B of the directory ASIC 50.
I => IOINPUT

When the above processing is also performed for the Y and Z table data (Yes in step S1019), the port for which connection information could not be created is output to the log file (step S1020). An ASIC logical CORE entity file having such information is output to the directory ASIC 50 (step S1021).
INPUT: in std_logic;
OUT: out std_logic;

  Also, the logical CORE entity file and the connection information are combined, the ASIC logical CORE is output to the directory ASIC 50 as a file with the project name specified in FIG. 17, the processing is terminated, and the logical CORE generation shown in FIG. 19 is completed. The process returns to the interface program 221 (step S1022).

  The logical CORE generation interface program 221 searches the log file in the directory ASIC 50 for an error. If an error is recorded (Yes in step S804), the error is read (step S805), and the project name, the user's mail address obtained by inquiring the user management server 240 with the project name, error information, and process The ID is sent to the mail server 260, and the mail is sent from the mail server 260 to the user (step S806). The user confirms the error content by this mail and repeats the process of generating the logical CORE until there is no error.

  On the other hand, if no error is recorded in the log file (No in step S804), the project name, the user's mail address obtained by inquiring the user management server 240 with the project name, the process ID, and the logical CORE generation end message Are sent to the mail server 260 (step S807), and mail is sent from the mail server 260 to the user.

  In addition, a directory is created in the directory ASIC 50 with the name “CORE + process ID + date”, the logical CORE generated with the project name and the log file are moved to the directory ASIC 50, and a directory is created in this directory with the name of IO. Then, the table data in the directory ASIC 48 used to generate the logical CORE is moved to this IO directory, and the logical name created in the logical CORE check program in the logical synthesis server 250 with the name of this project and “CORE + process ID + date / time” is created. The CORE directory name is designated, and the logical CORE check program is started (step S808).

  In this logic CORE check program, a logic synthesis tool command is described so as to check the syntax of the ASIC logic CORE, check whether the input / output ports of each instance constituting the logic CORE are unconnected, and output a report.

  Here, the processing procedure of the logical CORE check program will be described. FIG. 23 is a flowchart showing the processing procedure of the logical CORE check program. This logical CORE check program is under the directory of the received Project name, and checks whether there is a directory of the target ASIC logical CORE in the directory ASIC 50 of FIG. 14 (step S1201). A WORK directory is created in the ASIC directory in which the directory is located (step S1202), and the logic synthesis tool is checked (step S1203).

  When the execution is completed, the error information is extracted from the report file in the WORK directory, and the mail server together with the process ID extracted from the user mail address obtained by inquiring the user management server 240 with the project name and the directory name of the logical CORE. Then, the mail server 260 sends a mail to the user (step S1204). The user confirms whether the error information is intended by the contents of the sent mail.

  The logical CORE generated by this series of flows guarantees that the logical CORE is always assembled as an ASIC unless there is a connection error between instances constituting the ASIC in the logical design of the user. This effect appears in logic verification. When an operation different from the expectation is performed in the function verification of a plurality of instances constituting the ASIC, the connection between the instances can be guaranteed, so that the debugging can be limited to each function constituting the instance.

  Next, processing when the user selects status display on the procedure screen of FIG. 18 will be described. When the user selects status display on the procedure screen of FIG. 18, the status display interface program 224 is activated. The status display interface program 224 sends the display control data for the status display selection screen shown in FIG. 24 to the Web server 220, and the Web server 220 sends the received display control data for the status display selection screen to the Web client 100. The client 100 displays a screen based on the received display control data of the status display selection screen.

  When the user selects logical CORE creation on this screen, the status display interface program 224 generates display control data without the logical CORE name display on the logical CORE generation status screen shown in FIG. 25 and sends it to the Web server 220. The Web server 220 sends the received logical CORE generation status screen display control data to the Web client 100, and the Web client 100 displays a screen based on the received logical CORE generation status screen display control data.

  When the user inputs a project name and selects a display button on this screen, the Web client 100 sends the project name to the Web server 220 and receives the project name from the Web server 220. The status display interface program 224 receives the specified project name. The directory name of the logical CORE in the directory ASIC 50 in FIG. 14 is extracted from the directory, the display control data of the logical CORE generation status screen is updated and sent to the Web server 220, and the Web server 220 receives the received logical CORE generation status screen. The display control data is sent to the Web client 100, and the Web client 100 displays a screen based on the received logical CORE generation status screen display control data. On this screen, the directory name of the previously generated ASIC logical CORE is displayed.

  Here, a processing procedure on the ASIC logical CORE generation status display screen will be described. FIG. 26 is a flowchart showing a processing procedure on the ASIC logical CORE generation status display screen. As shown in the figure, when the user selects one of the displayed logical COREs and selects download (step S1501), the target logical CORE can be downloaded to the Web client 100 (step S1502). The downloaded logic CORE can be used for logic verification as an ASIC chip-level netlist, and debugging can be limited to the function of configuring an instance as described above.

  On the other hand, when the user designates the logical CORE name and selects the FPGA button (step S1503), the Web client 100 sends the Project name, the logical CORE name, and FPGA selection to the Web server 220, The server 220 sends the received data to the status display interface program 224. The status display interface program 224 extracts the file names of the table data in the IO directory under the target logical CORE name in the directory ASIC 50 in FIG. 14, and as a result, as shown in FIG. A display control data for a new FPGA logic CORE generation interface screen is created and sent to the Web server 220.

  The Web server 220 sends the received display control data of the FPGA logical CORE generation interface screen to the Web client 100, and the Web client 100 displays a screen based on the received display control data of the FPGA logical CORE generation interface screen (step S1504). . On this screen, a list of designated project names, logical CORE names, and instance names constituting the logical CORE are listed in the left list box. In this screen, the target logical CORE can be changed. When the user designates the project name and the logical CORE name, the screen is updated by the same processing designated in FIG.

  Further, this screen is an interface for generating the FPGA logical CORE from the table data of the instances constituting the target ASIC logical CORE. The user designates the instance from the left list box and selects the add button. To add an instance to the list box on the right. An instance listed in the list box on the right is one FPGA. When the user selects an instance, sets an FPGA name and an FPGA number that is a unique integer of 1 or more, which is a management number, and selects an execution button, the Web client 100 selects the target Project name, ASIC, The logical CORE name, FPGA name, instance name list of FPGA, and FPGA number are sent to the Web server 220, and the Web server 220 sends the received data to the status display interface program 224.

  Then, the status display interface program 224 creates a directory with the FPGA number designated in the directory FPGA 49 in FIG. 14 according to the received instance name list, and under the CORE name directory in the directory ASIC 50 in FIG. The table data having the same name is copied from the IO directory to the directory having the number, and the FPGA logic CORE generation program 252 is executed with the list of table data names as an argument.

  Here, a processing procedure of the FPGA logic CORE generation program 252 will be described. 28 and 29 are flowcharts showing the processing procedure of the FPGA logic CORE generation program 252. FIG. FIG. 28 is the same as the process shown in FIG. 21, and FIG. 29 is the same as the process shown in FIG. 22 except for steps S1717 and S1720, so these two steps will be described. .

  In step S1017 of FIG. 22, if the connection partner instance name defined in the port that is the input of the target instance and the output port name thereof are not in the information stored in the memory, an error is output to the log file. However, in step S1717 in FIG. 29, the connection between the ports of the instance is originally guaranteed as the logic core of the ASIC, and in this step S1717, it is additionally stored in the memory as input terminal information of the package rather than an error.

  In step S1020 of FIG. 22, the remaining unconnected port information is output to the log file. On the other hand, in step S1720, the log file in the logical CORE directory of the target ASIC created by “CORE + process ID + date” under the directory ASIC 50 in FIG. 14 is compared with the log file output in step S1720. The output port not included in the log file output in step S1020 is additionally stored in the memory as the output terminal information of the package. Thereafter, the logical CORE is output as a file with the specified FPGA name in the directory of the specified number under the directory FPGA 51 of FIG.

  Then, the status display interface program 224 reads the FPGA logical CORE file, counts the number of terminals to be input / output of the package, and shows the ratio of the number of IOs in the second column of the table of the compatible package shown in FIG. All are calculated, the package with the largest ratio and its compatible package data are extracted, the package name and the IO usage rate screen display control data of the FPGA logic CORE generation interface screen shown in FIG. send. The Web server 220 sends the received display control data of the FPGA logical CORE generation interface screen to the Web client 100, and the Web client 100 updates the input screen based on the received display control data of the FPGA logical CORE generation interface screen.

  If the user is not satisfied with the result, the FPGA logic CORE generation is performed again. When the user selects the decision, the web client 100 sends the decision that the decision was made, the FPGA number, the package name, and the IO usage rate data to the web server 220 and received the data from the web server 220. The interface program 224 creates a directory having the number designated in the directory FPGA 55 in FIG. 14, and outputs the data received under the name of plist, for example.

  Next, the processing procedure of the logic synthesis interface program 222 will be described. FIG. 31 is a flowchart showing the processing procedure of the logic synthesis interface program 222. As shown in the figure, the logic synthesis interface program 222 sends the logic synthesis interface screen display control data as shown in FIG. 32 to the web server 220, and the web server 220 receives the received logic synthesis interface screen display control. The data is sent to the Web client 100, and the Web client 100 displays a screen based on the received logic synthesis interface screen display control data (step S2001).

  The user designates the Project name, the logical CORE name displayed in FIG. 25, the functional block name to be logically synthesized, the FPGA number to be incorporated, and the area priority or speed priority, and Debug (FPGA If the logic is not executed) or Fix (if FPGA logic synthesis is executed) is specified (step S2002), and the execution button is selected (step S2003), the Web client 100 displays a data selection screen.

  When the user selects an RTL source for logic synthesis according to this screen, the Web client 100 sends these data to the Web server 220, and the logic synthesis interface program 222 that receives the data from the Web server 220 sets the RTL source as shown in FIG. A directory is created with a function block name designated in the directory ASIC 52, and the RTL is stored (step S2004). Then, the RTL source is read one file at a time, the operating frequency data defined by the user is extracted in the header portion describing the change history, version number, etc. in the RTL source, and the frequency increased by 20% with respect to the extracted value The ASIC logic synthesis program 253 of the ASIC logic synthesis tool is executed by designating the functional block name of the logic synthesis target using the value and the logic synthesis condition of speed priority or area priority specified by the user as the constraints of logic synthesis (step S2005). ).

  When the ASIC logic synthesis is completed, the logic synthesis interface program 222 sends a report file as a result output by the ASIC logic synthesis program 253 to the directory of the designated functional block under the directory ASIC 54 in FIG. The user's mail address and block name obtained by inquiring with the Project name are sent to the mail server 260, and mail is sent from the mail server 260 to the user (step S2006).

  Then, the logic synthesis interface program 222 executes this process for all RTL sources existing in the directory created with the specified function block name under the directory ASIC 52 in FIG. When logic synthesis of all RTL sources is completed (Yes in step S2007), the logic synthesis interface program 222 searches for a report of the logic synthesis results of all RTLs in the case of speed priority designation (Yes in step S2008), and the RTL source. It is determined whether or not the operating frequency defined in (1) is satisfied (steps S2009 to S2010). If the area is important, do nothing.

  Next, the Fix designation is checked (step S2011). If the Fix designation is made, the logic synthesis interface program 222 creates a directory under the directory FPGA 55 of FIG. 14 with the designated FPGA number, and the 14th is included in this directory. The RTL in the designated functional block directory under the directory ASIC 52 in the figure is copied and stored, and the FPGA logic synthesis interface program is executed with the designated Project name and FPGA number as arguments (step S2012).

  Then, the logic synthesis interface program 222 starts the logic synthesis tool, inputs a command to the logic synthesis tool from the specified logic CORE directory in the directory ASIC 50 in FIG. Read a file that defines the ASIC package terminal assignments uploaded and exists in the directory ASIC 54 of FIG. 14 and a buffer that electrically interfaces with an external device connected to the ASIC, and inputs a command to the logic synthesis tool according to the definition The test circuit such as the ASIC buffer and the scan is inserted and connected between the ASIC logic CORE terminal and the chip pad connected to the package terminal, and the logic synthesized directory ASIC 52 in FIG. The function block data in all the directories in FIG. 14 is input by inputting a command to the logic synthesis tool, loaded into the logic CORE, and an ASIC netlist is generated for layout design, and the directory ASIC 54 in FIG. A file is output (step S2013).

  Next, the processing procedure of the FPGA logic synthesis interface program will be described. FIG. 33 is a flowchart showing the processing procedure of the FPGA logic synthesis interface program. As shown in the figure, this FPGA logic synthesis interface program creates a directory in the directory FPGA 55 in FIG. 14 with the FPGA number specified from the ASIC logic synthesis interface program, and designates the directory under the directory FPGA 53 in FIG. The RTL source in the directory with the specified number is read one file at a time, and the operating frequency data defined by the user is extracted in the header portion describing the change history, version number, etc. in the RTL source, and for the extracted value The FPGA logic synthesis program 254 of the FPGA logic synthesis tool is executed by designating the function block name of the logic synthesis target with the frequency value increased by 20% as the constraint of logic synthesis (step S2201).

  When the FPGA logic synthesis is completed, the FPGA logic synthesis program 254 outputs the logic synthesis result to the directory of the target number in the directory FPGA 55 of FIG. By doing so, the user can proceed with the design work while confirming the gate usage rate in the logic synthesis status display of FIG. 34 described later. Then, the FPGA logic synthesis interface program sends the logic synthesis end message, the FPGA number, the block name, and the mail address of the user who has inquired the user management server 240 using the project name to the mail server 260, A mail is transmitted from 260 to the user (step S2202).

  Next, the FPGA logic synthesis interface program checks whether all logic synthesis of the functional blocks constituting the FPGA of the designated number has been completed (step S2203). This confirmation is performed by extracting the name of the function block in the directory of the number targeted by the directory FPGA 51 of FIG. 14 and comparing it with the name of the function block for which the logic synthesis has been completed. If there is no difference, the FPGA logic synthesis interface program next extracts the file name of the logical CORE that is the FPGA name in the directory of the target number in the directory FPGA 51 of FIG. In the directory FPGA 55 in the figure, a fitting control file that defines the correspondence between the terminal name and terminal number of the package that is the same as the port name of the logic CORE of the FPGA used for fitting, the operation frequency, etc., is the layout of the FPGA. It is checked whether it has been uploaded and exists (step S2206).

  If it exists, the FPGA logic synthesis interface program designates all the functional blocks constituting the FPGA and the logic CORE of the FPGA in the directory of the target number under the directory FPGA 51 in FIG. 254 is executed. When the FPGA logic synthesis is completed, the FPGA logic synthesis interface program starts the fitting program 255, inputs a net list of the logic synthesis result into the fitting program 255, performs layout, and displays the FPGA layout result as circuit information. The recorded ROM data is generated and output with the FPGA name to the directory of the target number under the directory ROM 46 in FIG. 14 (step S2207). Then, the ROM data generation end message, the FPGA number, the project name, and the mail address of the user obtained by making an inquiry to the user management server 240 are sent to the mail server 260, and the mail is transmitted (step S2208).

  If there is a difference, it is determined whether or not an execution button has been selected on the fitting data input and execution screen described below (step S2204). If not selected, the process ends. For all the blocks, flip-flops are connected to all the input / output ports in each functional block in the FPGA logic CORE in the directory of the target number under the directory FPGA 51 in FIG. Connect the output port of the flip-flop to an appropriate gate, for example, the input port of a 2-input NAND, connect the output of all NAND gates to the input port of a new 2-input NAND gate, and Multi-stage connection is repeated, and the output of the 2-input NAND in the final stage is used as the input port for all flip-flops on the output side Insert the HDL description to continue to synthesizable state (step S2205).

  The subsequent processing is the same as when there is no difference. Depending on the verification strategy at the start of development, if the functional block configuration is functionally divided into upstream and downstream in the circuit architecture study, insert a dummy circuit using the flip-flop described above. Therefore, if the design of the upstream function is completed, the verification can be performed even if the design of the downstream function is not completed, which greatly contributes to the efficiency of the verification.

  Next, the logic synthesis status display screen of FIG. 34 will be described. When the user selects logic synthesis on the status display screen of FIG. 24 on the Web client 100, this screen sends to the Web server 220 that the logic synthesis has been selected and receives data from the Web server 220. The status display interface program 224 calculates the gate scale from the logical synthesis results in the directory of all numbers under the directory FPGA 55 in FIG. 14 for all the project names obtained by inquiring the user management server 240 with the name of the logged-in user. To extract.

  Then, the package information is extracted from the plist in the same directory created by the above-described FPGA logic CORE generation, and the gate scale ratio is 75% or less in the table of FIG. 30 based on this package information. Is selected, and the display control data of the logic synthesis status display screen of FIG. 34 is generated and sent to the Web server 220. The Web server 220 sends display control data for the logic synthesis status display screen to the Web client 100, and the Web client 100 displays a screen based on the received display control data for the logic synthesis status display screen.

  Here, the gate scale ratio of 75% will be briefly described. Usually, the logic synthesis tool of FPGA suggests an appropriate package and gate usage rate from the database of the logic synthesis tool based on the gate scale as a result of the logic synthesis. However, in FPGA fitting, a unit block that realizes logic in the FPGA is used for wiring in order to increase wiring efficiency in the cell placement process. Therefore, considering that the gate scale becomes larger than the logical synthesis result, the gate usage rate after fitting is set to 75% so as not to exceed 100%, and may differ depending on the FPGA. For this reason, it is effective to execute the logic synthesis of the FPGA described above for each functional block.

  Next, the fitting data input and execution screen will be described. FIG. 35 is a diagram showing an example of a fitting data input and execution screen. When the user selects the fitting on the procedure screen shown in FIG. 18 on the Web client 100, the Web client 100 sends the fact that the fitting has been selected to the Web server 220 and receives the data from the Web server 220. Are all the project names obtained by inquiring the user management server 240 with the name of the logged-in user, the number names of all directories under the directory FPGA 55 in FIG. The file name of the list, that is, the FPGA name is extracted, and fitting data input and execution screen display control data shown in FIG. 35 are generated and sent to the Web server 220.

  The Web server 220 sends fitting data input and execution screen display control data to the Web client 100, and the Web client 100 displays a screen based on the received fitting data input and execution screen display control data. When selecting the input of condition data on this screen, the data selection screen is displayed by the Web client 100.

  When the user selects the above-described fitting control file according to this screen, the Web client 100 sends the selected FPGA number and the fitting control file to the Web server 220 and receives the data from the Web server 220. Stores the fitting control file in the directory of the target number under the directory FPGA 55 of FIG.

  When the user selects the execute button, the web client 100 sends the selected FPGA number, project name, and execution selected to the web server 220 and receives the data from the web server 220. In step S223, the FPGA logic synthesis interface program is executed with the project name and the FPGA number as arguments. The processing of the FPGA logic synthesis interface program is as described above.

  Next, the ROM data generation status screen will be described. FIG. 36 is a diagram showing an example of a ROM data generation status screen. When the user selects ROM data on the status display selection screen shown in FIG. 24 on the Web client 100, the Web client 100 sends to the Web server 220 that the ROM data has been selected.

  The status display interface program 224 that has received data from the Web server 220 uses the names of all the directories under the directory ROM 46 in FIG. 14 for all project names obtained by inquiring the user management server 240 with the name of the logged-in user. The ROM data name, that is, the FPGA name, which is the fitting result in each directory, is extracted, and the display control data of the ROM data generation status screen shown in FIG. 36 is generated and sent to the Web server 220.

  The Web server 220 sends ROM data generation status screen display control data to the Web client 100, and the Web client 100 displays a screen based on the received ROM data generation status screen display control data. When the user selects the date part of the target FPGA on this screen, the ROM data can be downloaded.

  Next, processing of the monitoring server 290 will be described. First, what is monitored by the monitoring server 290 is used for implementation design based on the presence / absence of RTL changes, the time required for logic synthesis, fitting, and layout design tool processing, and the scale of functional block changes defined by the designer. This is the manual time required to reflect the changes, other than the processing time of the tool to be used.

  The directory LAYOUT 47 in FIG. 14 managed by the implement designer has a project name directory for each project. Each project name directory has an LAY directory in which layout design data is stored and an RTL directory in which RTL sources are stored. The directory structure below the RTL directory is the same as the directory ASIC 52 and below in FIG.

  The monitoring server 290 monitors the LAY and RTL directories. The schedule reflecting the result of totaling the time is stored in the Project name directory under the name of Schedule, and in the initial state, the scheduled date of 1stRTL and the scheduled date of Sign Off are set based on the contract. The 1st RTL is defined as an RTL in which layout design can be started and no significant change is expected at that time, and the function verification has been completed about 80%. “Sign Off” is the date when the ASIC manufacturing data is delivered to the device vendor after the ASIC layout design is completed.

  FIG. 37 is a diagram showing an example of a schedule and results screen. In the figure, the Schedule file is converted into screen display control data and displayed by the Web client 100. That is, when the user selects a record and a schedule on the status display screen of FIG. 24, the Web client 100 sends the selection of the record and schedule to the status display interface program 224 via the Web server 220. The status display interface program 224 that has received the selection of the record and schedule converts the Schedule file into screen display control data and sends it to the Web client 100 via the Web server 220. The Web client 100 that has received the screen display control data displays the screen based on the screen display control data.

  FIG. 38 is a diagram showing an example of a work time setting file set by the layout designer. This file is stored under the name Manual in the same directory as the Schedule file.

  When the monitoring time comes, the monitoring server 290 acquires the user name, the project name to which the user belongs, and the mail address from the user management server 240. Then, the Schedule file is read and the scheduled date of 1st RTL is extracted. If this scheduled date is later than the monitoring execution date, the process ends without doing anything. If the scheduled date is earlier than the monitoring execution date, the subsequent processing is executed.

  First, if there is no RTL source in the RTL directory in the project name directory under the LAYOUT directory managed by the implement designer, the processing is interrupted. If there is an RTL source, the RTL sources in the directory of each block under the directory ASIC 52 in FIG. 14 are compared.

  If there is a difference, the block name with the difference, the project name, and the mail address of the implement designer are sent to the mail server 260, and the mail server 260 sends them to the implement designer. The implement designer estimates the time required to reflect the change by this mail. As a result of the estimation, the implementation designer updates, adds, or deletes the time data of the Schedule file as necessary.

  Next, the monitoring server 290 extracts the block names constituting the ASIC from the logic CORE of the ASIC with the newest creation time under the directory ASIC 50 in FIG. 14, and stores it in the memory. Then, the logic synthesis processing time is extracted from the report file of the logic synthesis result in the directory of each block under the directory ASIC 54 in FIG. If the report file for the block name previously stored in the memory does not exist, that is, has not yet been logically synthesized, the average time extracted from the existing report file is applied, and the total time is calculated and stored in the memory.

  Then, if there is a timing verification result file that is the final step of the layout design process among the layout design results in the project name directory under the directory LAYOUT 47 of FIG. 14 managed by the implement designer, The processing time is extracted from the processing result file output by the tool used in the entire layout design process, and the total time is calculated together with the time previously stored in the memory. When the timing verification result file does not exist, the time set by the layout designer at the time of the contract and preliminarily set in the monitoring server is applied.

  Next, the monitoring server 290 calculates the number of days by taking the total of the total time and the time set in the above-described Manual as 12 hours, and updates the Schedule file if necessary. That is, in the initial state, the Schedule file has only the 1st RTL scheduled date, and the total time is added to this scheduled date, and the change is scheduled to be incorporated into the implementation design as the reflection start date as shown in FIG. Add a day.

  In the next monitoring, if the reflection start date is later than the monitoring execution date, the number of days from the 1st RTL scheduled date, which is one before the reflection start date, to the scheduled date set as the reflection start date is used as a comparison. If it is longer than the calculated number of days for implementation design, the reflection start date is not updated. When the reflection start date is before the monitoring execution date, the monitoring server 290 sends the mail address of the user and the implement designer and a message indicating the opportunity to start the reflection to the mail server 260, and the mail server 260 implements the user and the implementation. Send an email to the designer. At this time, when the latest reflection start date is before the date of the monitoring execution, the monitoring server 290 does not update the Schedule file unless the date of the reflection start date is the actual date.

  When an approval / rejection email arrives at the monitoring server 290 from both the user and the implementation designer for the message email that is the opportunity to start the reflection, if both are approval, the Schedule file reflection start date is immediately Set the date when the e-mail was received, and in the next monitoring, if the most recent reflection date is before the monitoring date, and if there is a date on the actual reflection date, the actual date will be Based on this, calculate the number of days for implementation design and add a new reflection start date. As this process continues, the reflection start date approaches the Sign Off date.

  When the estimated start date of the reflection is calculated and the Sign Off date is exceeded, the monitoring server 290 displays a message indicating the date on which the expected start date of the reflection cannot be set, and the mail of the user and the implement designer. The address is sent to the mail server 260, and mail is sent from the mail server 260 to both sides.

  When the user rejects the mail of the message that is the opportunity to start reflection, a message to set the scheduled date from the Web client 100 and the mail address of the user and the implement designer are sent to the mail server 260. The mail server 260 transmits mail to both sides.

  Next, the schedule and results screen will be described. FIG. 37 is a diagram showing an example of a schedule and results screen. The logical Fix button and the change button in the same figure are before the monitoring execution date of the monitoring server 290 and are arranged at the most recent reflection start date. When the user designates the date in the date setting field below this button and selects the change button, the Web client 100 informs the Web server 220 that the set date and change have been selected. The status display interface program 224 that sent and received the data from the Web server 220 changes the scheduled date of the latest reflection start date in the Schedule file to the specified date, and the message indicating that the change has been made, the user, The mail address of the implement designer is sent to the mail server 260, and mail is sent from the mail server 260 to both sides.

  When the logical Fix button in FIG. 37 is selected together with the designation of the date, the status display interface program 224 performs the same processing as when the change button is selected, and then stops monitoring of the monitoring server 290. The process to do is performed. This will clarify the short-term goals for both the user and the implement designer, and the greater the number of implementation design trials, the more accurate the scheduled start date of the change will be. Both will be able to give the opportunity to think about how to proceed, and as a result will contribute greatly to the improvement of efficiency.

  As described above, in the second embodiment, the ASIC logic synthesis program 253 performs ASIC logic synthesis based on a user request from the Web client 100, and the FPGA logic synthesis program 254 performs FPGA logic synthesis. The logic synthesis interface program 222 displays the result of logic synthesis of ASIC and FPGA on the Web client 100, and the mail server 260 notifies the user of the start of the logic synthesis of ASIC and FPGA and the result by e-mail. It is not necessary to set up a dedicated logic synthesis person, logic synthesis can be performed at any time, and the logic synthesis quality can be kept uniform as the dedicated person did. You can receive notifications and regularly check the progress of logic synthesis. There is no need to be confirmed by Yuta.

  In the second embodiment, based on a user request from the Web client 100, the ASIC logic CORE generation program 251 uses only the inter-port connection information of a plurality of functional blocks designated by the user from the functional blocks constituting the ASIC. A logic list generation interface, generating ROM data in which a programmable logic device circuit is recorded by inserting data of functionally synthesized target function blocks into the netlist generated by the FPGA logic core generation program 252. Since the mail server 260 displays the generation result of the ROM data generated by the program 221 and notifies the user by e-mail, the user does not need a development environment dedicated to the programmable logic device, A load for creating ROM data recorded circuits Roguramaburu logic device, it is possible to reduce time and a costly.

  In the second embodiment, when the design of the functional block constituting the ASIC specified by the user is not completed and no circuit data exists, the FPGA logic CORE generation program 252 is connected to the input terminal and the output terminal of the functional block. Since we decided to generate a netlist with a circuit using a temporary flip-flop, etc., even if the design of the functional block that is not the verification target is not completed in the verification by prototyping of the programmable logic device, Verification by typing can be promoted, and verification efficiency can be improved.

  In the second embodiment, the monitoring server 290 monitors the scale of the change between the latest circuit data held by the user and the circuit data taken into the implementation design by the implementation designer, and the monitoring result and layout design are applied. When the planned date and time is reached, the user and the ASIC implementation designer are notified by email that the mail server 260 is ready to reflect the change in the ASIC implementation design, and in response to this notification Since the user has requested a stop by changing the reflection date, the change that has occurred can be efficiently reflected in the layout design of the ASIC, and by setting the timing to reflect the change, the user can It is possible to determine how long it can be changed, and at an early stage It is a review of Lumpur.

  As described above, according to the present invention, the following effects can be obtained. According to the program storage medium storing the program for causing the computer to execute the technique for generating the core (logical core) of the present invention, the quality of the port specification of the block serving as the input of the RTL design can be secured in advance in the development of the integrated circuit Even in the development of large-scale integrated circuits that are effective, have many functional blocks, and have many design resources, the connection between the blocks can be confirmed in advance to ensure that the chip is assembled. it can.

  Further, according to the present invention, a programmable logic device using this core (logical core) is used to cut out from the ASIC core (logical core) while maintaining the inter-block connection as the core of the programmable logic device (logical core). In the ASIC, at least duplication of verification with the same configuration can be avoided. Therefore, concurrent development of the ASIC and the programmable logic device can be efficiently advanced.

  In addition, when inserting an I / O buffer, a temporary core (logical core) is generated from the terminal information of the chip and replaced with a core (logical core) generated from the block. The information and the terminal information of the chip can be cross checked, and the quality of both the port specification of the block and the chip terminal specification can be ensured.

  Further, according to the present invention, it is possible to generate a netlist composed of ports and port connection information of an arbitrary scale and number.

  Further, according to the present invention, a chip net list can be generated from a net list composed of ports and port connection information of an arbitrary scale and number.

  In addition, according to the present invention, according to a storage medium storing a program for causing a logic synthesis tool to execute a technique for generating a core (logic core) of a programmable logic device, it is difficult to determine a port function. It is possible to prevent a decrease in debugging efficiency such as logic verification when is a port name.

  As described above, a core (logical core) is generated from the data of the design document, and a new core (logical core) is created for the programmable logic device while maintaining the hierarchical structure and connection information from the core (logical core). By creating the circuit architecture, the circuit data can be shared, and the circuit data that does not depend on the device technology in the instance in which the function verification is performed and the net between the instances are re-verified when the ASIC is created. It becomes possible to avoid this, and redesign due to the difference between the ASIC and the programmable logic device can also be avoided.

  As described above, according to the present invention, there is provided an integrated circuit development method capable of realizing architecture sharing and avoiding redesign and reverification as much as possible, and a programmable storage medium storing the integrated circuit development method. be able to.

  As described above, the ASIC and programmable logic device concurrent development system, development program, and development method according to the present invention are suitable for the development of integrated circuits, particularly the development of ASICs and programmable logic devices.

FIG. 1 is a flowchart showing the principle of the method of the present invention. FIG. 2 is an operation explanatory diagram of Embodiment 1 of the present invention. FIG. 3 is a block diagram showing an embodiment of the logic synthesis tool control device of the present invention. FIG. 4 is a block diagram showing an embodiment of the control device. FIG. 5 is a flowchart (1) showing a core (logical core) generation program. FIG. 6 is a flowchart (2) showing a core (logical core) generation program. FIG. 7 is a flowchart showing a detailed procedure of the first embodiment of the present invention. FIG. 8 is a flowchart showing core (logic core) design check control. FIG. 9 is a flowchart showing grouping control. FIG. 10 is a flowchart showing the I / O buffer insertion control and an image of processing. FIG. 11 is a flowchart showing an integrated circuit design procedure. FIG. 12 is an explanatory diagram for explaining the concept of concurrent development of ASIC and FPGA according to the second embodiment. FIG. 13 is a functional block diagram showing a system configuration of an ASIC and FPGA concurrent development system according to the second embodiment. FIG. 14 is a diagram showing an example of a directory structure for storing data in the file server. FIG. 15 is a diagram showing an example of a logical CORE generation table. FIG. 16 is a flowchart showing a processing procedure of the ASIC and FPGA concurrent development system of the second embodiment. FIG. 17 is a diagram showing an example of a login screen. FIG. 18 is a diagram showing an example of a procedure screen. FIG. 19 is a flowchart showing the processing procedure of the logical CORE generation interface program. FIG. 20 is a diagram showing an example of a logical CORE generation interface screen. FIG. 21 is a flowchart (1) showing the processing procedure of the ASIC logic CORE generation program. FIG. 22 is a flowchart (2) showing the processing procedure of the ASIC logic CORE generation program. FIG. 23 is a flowchart showing the processing procedure of the logical CORE check program. FIG. 24 is a diagram showing an example of a status display selection screen. FIG. 25 is a diagram showing an example of a logical CORE generation status screen. FIG. 26 is a flowchart showing a processing procedure on the ASIC logical CORE generation status display screen. FIG. 27 is a diagram showing an example of an FPGA logic CORE generation interface screen. FIG. 28 is a flowchart (1) showing the processing procedure of the FPGA logic CORE generation program. FIG. 29 is a flowchart (2) showing the processing procedure of the FPGA logic CORE generation program. FIG. 30 is a diagram showing an example of a compatible package table. FIG. 31 is a flowchart showing the processing procedure of the logic synthesis interface program. FIG. 32 is a diagram showing an example of a logic synthesis interface screen. FIG. 33 is a flowchart showing the FPGA logic synthesis interface processing procedure. FIG. 34 is a diagram showing an example of a logic synthesis status display screen. FIG. 35 is a diagram showing an example of a fitting data input and execution screen. FIG. 36 is a diagram showing an example of a ROM data generation status screen. FIG. 37 is a diagram showing an example of a schedule and results screen. FIG. 38 is a diagram showing an example of manual work time.

Claims (4)

A concurrent development system of an ASIC and a programmable logic device that is connected to a computer used by a user via a network and that develops an ASIC and a programmable logic device in response to the user's request ,
ASIC logic synthesis means for performing ASIC logic synthesis in response to the user's request;
ASIC logic synthesis result judging means for judging whether or not the ASIC logic synthesis result created by the ASIC logic synthesis means satisfies the speed performance requested by the user;
Programmable logic device logic synthesis means for executing logic synthesis of a programmable logic device based on a determination result by the ASIC logic synthesis result determination means;
Logic synthesis result display means for displaying the execution result of ASIC logic synthesis by the ASIC logic synthesis means and the execution result of programmable logic device logic synthesis by the programmable logic device logic synthesis means on the computer;
Logic synthesis notification means for notifying the user of the start and execution results of ASIC logic synthesis by the ASIC logic synthesis means and the execution start and execution results of programmable logic device logic synthesis by the programmable logic device logic synthesis means When,
A netlist generating means for generating a netlist composed of inter-port connection information of a plurality of functional blocks designated by the user from functional blocks constituting the ASIC in response to a request from the user;
ROM data generation means for generating ROM data in which the data of the logic synthesized target functional block is embedded in the net list generated by the net list generation means and the circuit of the programmable logic device is recorded;
ROM data generation result display means for displaying the generation result of the ROM data generated by the ROM data generation means on the computer;
A concurrent development system for an ASIC and a programmable logic device, comprising: ROM data generation result notification means for notifying the user of the generation result of the ROM data generated by the ROM data generation means by e-mail .   Temporary netlist generation for generating a netlist in which dummy circuits are inserted into the input terminal and output terminal of the functional block when the design of the functional block constituting the ASIC specified by the user is incomplete and circuit data does not exist The concurrent development system for an ASIC and a programmable logic device according to claim 1, further comprising means. The monitoring means for monitoring the scale of changes between the latest circuit data held by the user and the circuit data incorporated in the implementation design by the implement designer, and the monitoring result by the monitoring means and the time taken for the layout design are planned. A change timing notification means for notifying the user and the ASIC implementation designer by e-mail that the change is in a timing for reflection in the ASIC implementation design, and responding to the change timing notification means. concurrent development system ASIC and a programmable logic device according to claim 1 or 2, characterized in that it comprises reflecting stop request means and further that the user requests to stop by changing the date of the reflected and . A method for concurrent development of an ASIC and a programmable logic device that is connected to a computer used by a user via a network, and that meets the requirements of the user by a concurrent development system for the ASIC and the programmable logic device,
An ASIC logic synthesis step for performing ASIC logic synthesis in response to the user's request;
An ASIC logic synthesis result determination step for determining whether or not the ASIC logic synthesis result created by the ASIC logic synthesis step satisfies the speed performance requested by the user;
A programmable logic device logic synthesis step for performing logic synthesis of a programmable logic device based on the determination result of the ASIC logic synthesis result determination step;
A logic synthesis result display step of displaying on the computer the execution result of the ASIC logic synthesis by the ASIC logic synthesis step and the execution result of the programmable logic device logic synthesis by the programmable logic device logic synthesis step;
ASIC logic synthesis execution start and execution result by the ASIC logic synthesis step, and logic synthesis notification step of notifying the user of the execution start and execution result of the programmable logic device logic synthesis by the programmable logic device logic synthesis step to the user by e-mail When,
A netlist generating step for generating a netlist composed of inter-port connection information of a plurality of functional blocks designated by the user from functional blocks constituting the ASIC in response to a request from the user;
ROM data generation step of generating ROM data in which the data of the logic synthesis target functional block is embedded in the net list generated by the net list generation step and the circuit of the programmable logic device is recorded;
ROM data generation result display step for displaying the generation result of the ROM data generated by the ROM data generation step on the computer;
Features and to Turkey the concurrent development method that contains the ROM data generation result notification step of notifying email the result of generating the ROM data generated by the ROM data generating step to the user.

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