JP4127681B2 - RECORDING INFORMATION GENERATION METHOD, INFORMATION RECORDING MEDIUM, INFORMATION REPRODUCTION METHOD AND DEVICE, AND INFORMATION RECORDING METHOD - Google Patents

Description

  The present invention relates to a synchronization code, a recording method thereof, a reproducing method, an information reproducing apparatus, and an information storage medium. The present invention is useful as an information recording format (information recording format) for an information storage medium, and is useful as a method for recording information on an information storage medium of an information recording / reproducing apparatus and a method for reproducing information from an information recording medium. . The present invention is useful when applied to next-generation DVD-ROMs, next-generation DVD-Rs, and next-generation DVD-RAMs.

  In a DVD (Digital Versatile Disc), the content of a synchronization code (SYNC Code) in the current DVD format is defined. In this rule, there are 32 types of synchronization codes in total.

  The information reproducing apparatus or the information recording / reproducing apparatus employs the following method in order to detect the position of the synchronization code from the reproduced data. That is, the reproduction data reproduced from the information storage medium is brute-forced with respect to 32 types of patterns, and whether or not pattern matching is performed is detected.

  This synchronization code position detection process is very time-consuming. For this reason, the synchronization code detection circuit becomes complicated, and the price of the information reproducing apparatus or information recording / reproducing apparatus is increased. Further, as described above, the synchronization code detection algorithm is complicated (due to the presence of 32 types of synchronization codes). For this reason, not only is the detection reliability low, but the number of bits of the code to be compared with the reproduced signal (the number of bits of the entire synchronization code) is as long as 32 bits. There is a problem that the reliability of the position detection of the resulting synchronization code is further lowered.

Further, when examining the contents of the synchronization code, at least three “0” s continue immediately before and immediately after the place where “0” continues for a long time (13 consecutive), and PLL (Phase Lock Loop) before and after this place. There is a problem that the reliability of the synchronization code detection is likely to drop.
JP-A-9-162857 Japanese Patent Laid-Open No. 6-267075 Microfilm of Japanese Utility Model No. 54-046952 (Japanese Utility Model Application Publication No. 55-148255) Japanese Patent Application No. 2001-177408 (Japanese Patent Laid-Open No. 2002-304589)

  Accordingly, the present invention is to provide a synchronization code generation method having a structure capable of simplifying the detection of the position of the synchronization code and improving the detection reliability of the synchronization code, and is generated by this method. An object is to provide an information recording method, an information reproducing method, an information reproducing apparatus, and an information storage medium using a synchronization code.

  [A] A synchronization code structure and a detection method that can greatly simplify the synchronization code position detection algorithm are provided. That is, it is intended to facilitate the detection of the synchronization code of the information reproducing apparatus or the information recording / reproducing apparatus, to reduce the price of the information reproducing apparatus or the information recording / reproducing apparatus, and to increase the detection reliability of the synchronization code.

  [B] A synchronization code structure that greatly improves the reliability of synchronization code position detection is provided. As a result, a synchronization code pattern that facilitates discrimination between the synchronization code and other (modulated) user-recorded data and is difficult to cause a PLL (phase locked loop) failure is proposed. To improve.

In the present invention, one ECC block is divided into first and second small ECC blocks, and the first and second small ECC blocks are included in a group of a plurality of sectors. In the second small ECC block, first and second PO information for error correction is generated, and when the plurality of sectors are recorded in each sector of the recording track, Includes a synchronization code and user data, a part of the first PO information generated by the first small ECC block, and the second PO information generated by the second small ECC block. A part is set to be alternately arranged in the connection of the sectors,
The user data is modulated according to a (d, k; m, n) modulation rule, d = 1, and is reproduced by a PRML reproduction system, and each sector is composed of a plurality of sync frames, The sync code and user data are included in each of a plurality of sync frames, and the sync code has a plurality of types, and each sync frame in the sector depends on an arrangement pattern of the sync codes in one sector. Although the arrangement position can be identified, one synchronization code of the same type used for the arrangement pattern is further used in the head sync frame constituting each sector, and each of the synchronization codes is used . The number of bits of the synchronization code is 24 bits, a common fixed code and a variable code are arranged in each of the synchronization codes, and the fixed code A code for detecting a synchronization position, wherein the bit sequence includes a portion in which 12 is followed by 0, 1 is placed, 2 is followed by 0, and 1 is placed. The basic configuration is that at least “00100 *”, “00010 *”, or “00 * 010” (where * is a DC suppression bit) is used as the type.

  According to the above means, the synchronization position can be accurately detected while effectively using the bits of the synchronization code, and the beginning of the first recording unit can be easily detected.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  First, the characteristic way of thinking of the present invention will be described below.

  Point [1]: The data size of the synchronization code is reduced from 32 bits of conventional DVD to 24 bits to improve the reliability of synchronization code detection [described in the number of used bits described below in FIGS. 27 to 35].

  This effect is as follows.

  In the current DVD, a corresponding pattern is selected from 32 types of patterns by a pattern matching method for all 32 channel bits of a synchronization code (SYNC Code). As the size (number of bits) of the pattern matching pattern increases, not only does the pattern matching take time and complexity, but also bit errors caused by defects (scratches, dust, etc.) in the information storage medium 9 are mixed. Since the probability increases, the detection reliability for the synchronization code decreases.

  In the present invention, the data size of the synchronization code is reduced from 32 bits of conventional DVD to 24 bits to reduce the pattern size (number of bits) for pattern matching, thereby greatly saving time required for pattern matching. This not only simplifies the pattern matching process, but also improves the detection reliability by suppressing factors that lower the detection reliability caused by defects in the information storage medium 9.

  Point [2]... The synchronization code is divided by function, and information corresponding to each function can be extracted by extracting data from only the divided part [figure in FIG. 2 and g in FIG. ].

  In other words, the synchronization code is divided into the fixed code area 111 and the variable code areas 112 and 113, and the variable code areas 112 and 113 are further recorded in the “conversion table selection code 122 at the time of modulation” and “sync frame position identification”. The recording location of the code 123 "and the recording location of the" DC suppression polarity reversal pattern 124 "are subdivided into a structure (including the combined and combined use of some recording locations).

  This effect is as follows.

  As described above, in the present invention, the synchronization code is divided into functions, and each pattern is uniquely matched for each function. This not only greatly saves the time required for each pattern matching and simplifies the process, but also improves the reliability of detection by suppressing factors that lower the reliability of detection caused by defects in the information storage medium 9. I am letting.

  That is, only one type of synchronization position detection code 121 pattern is recorded in the fixed code area 111, and the synchronization position detection code detection unit 182 formed of a comparator circuit as shown in FIG. The position of the entire synchronization code 110 is detected only by detecting the position. As described above, since the sync code position is detected by detecting only the fixed code area 111 which is a part of the sync code 110 instead of the pattern matching of the entire sync code 110, the processing time is greatly saved and the processing is simplified. In addition to this, it is possible to improve the reliability of detection by suppressing factors that lower the reliability of detection caused by defects in the information storage medium 9.

  In addition, compared with the conventional DVD in which pattern matching of a plurality of 32 types of candidates is performed for synchronous code detection, in the embodiment of the present invention, only a comparator circuit (synchronous position detection code detection unit 182) is used. Since the position of the synchronization code 110 is detected only by detecting the presence or absence of the synchronization position detection code 121, the position detection method of the synchronization code 110 is greatly simplified, and the detection accuracy is improved.

  Further, in the present invention, the synchronization code is divided into functions, and each function is independently subjected to pattern matching. Therefore, any of the conversion table selection code 122 after modulation, the sync frame position identification code 123, and the DC polarity inversion pattern 124 is selected. Even if it takes a look, as shown in FIGS. 23 to 26, the number of selection candidates is small, and identification of each code / pattern is easy, and processing in a short time becomes possible. As a result, each detection reliability is also improved.

  Point [3]: A pattern that can be easily identified as a synchronization position detection code pattern in the synchronization code and a pattern that can restore the PLL at high speed are configured in pairs [see h in FIG. 2].

  That is, when user record data (general data: sync frame data 106) is modulated according to the (d, k; m, n) modulation rule, “k + 2” “0” s are consecutively included in the code pattern for synchronization position detection. A subsequent pattern is arranged, and immediately after that, a pattern in which “2” continues continuously is arranged.

  This effect is as follows.

  By providing a pattern that cannot exist in the user recording data (general data: sync frame data 106) in the synchronization position detection code pattern, the synchronization code and other (modulated) user recording data (general data: The sync frame data 106) can be identified very easily. General data (sync frame data 106) is changed to (d, k; m, n) modulation rule [the channel bit pattern after modulation is set to “d” at the minimum in the range where “0” continues and “k” at the maximum. When the modulation is performed according to the above, “(0, 0)” cannot be continued in the (d, k; m, n) modulation rule. However, “k + 2” continuous patterns are provided. As a result, the information reproducing apparatus or the information recording / reproducing apparatus can very easily detect the position of the synchronization position detecting code by searching for a pattern in which “0” continues for “k + 2”.

  In recent optical disc recording technology, data is recorded on an information storage medium by an NRZI (Non Return to Zero Invert) method. Therefore, with respect to the channel bit data recorded on the information storage medium 9, the phase of the detection signal of the channel bit data (data reproduced from the information storage medium 9) and the reference clock 198 at the data “1”. A phase shift with respect to the phase of the (information reproduction apparatus or clock in the information recording / reproduction apparatus) is detected, and the frequency and phase of the reference clock are corrected. This is called so-called PLL (Phase Lock Loop) correction.

  Accordingly, if a pattern in which “0” continues for a long time continues in the synchronization position detection code, PLL correction (phase alignment) performed at “1” is not performed for a long period of time, and PLL deviation tends to occur. Once the PLL is out of phase, detection data bit shift occurs and a detection data error (bit shift error) occurs for a long time. For this reason, a bit shift error is likely to occur where a long continuous pattern of “0” continues, and the reproduction reliability of the synchronization position detection code 121 is greatly reduced.

  For this reason, the current DVD has a structure in which a pattern in which “0” is “3 consecutive” is recorded immediately after 13 “0” continues.

  However, in the current DVD standard, data reproduction reliability due to a bit shift error is not ensured. As described above, PLL correction (phase alignment correction) can be performed only at the location of “1”. Therefore, the smaller the number of consecutive “0”, the shorter the period in which PLL correction (phase alignment correction) can be performed. Shift errors are difficult to occur.

  Therefore, in the present invention, the number of consecutive “0” s in the pattern immediately after “k + 2 consecutive patterns” in “0” is 1 as compared with the “three consecutive” patterns in the conventional DVD standard. The pattern is reduced to a “only two continuous” pattern, which makes it difficult for bit shift errors to occur and improves the reliability of synchronization detection.

  In addition, when the modulated bit length is shortened with the aim of higher density and PRML is used in the data reproduction system with “d = 1”, the reproduction signal amplitude from a place where only “0” is one is very large. Small and stable binarization is impossible.

  Therefore, binarization is performed by arranging a pattern in which “0” is not a single pattern but “2” continues in succession, and the reproduced signal amplitude is small and the reliability of the binarized signal is low. The subsequent signal is stabilized (detectable with high accuracy).

  Point [4]... The value of the sync frame position detection code 123 arranged at the beginning of the same physical sector is matched with the value of the sync frame position detection code 123 arranged at another location in the same physical sector.

  That is, not only “SY0” in FIG. 35 or “FR0” in FIG. 34 is arranged at the first position in the same physical sector, but the same “SY0” or “FR0” is set at another location (second, fifth, (7th, 14th, 15th, 18th, 20th).

  This effect is as follows.

  In the current DVD standard, “SY0” of the synchronization code (SYNC Code) arranged first in one sector is arranged only at the head position in the same sector. When the synchronization code pattern of “SY0” is arranged only at one place in the same sector, the types of synchronization code patterns to be arranged at other plural places in the same sector are inevitably increased.

  When identifying the contents of each synchronization code pattern (the contents of “SY0” or “SY1”) or the value of the sync frame position number 115 of the present invention (see FIGS. 23 to 26), the identification is performed only by the brute force pattern matching method. I can't do it. Then, as the number of types of synchronization code patterns or the number of types of assigned sync frame position numbers 115 increases, the time required for identification by pattern matching increases and the identification becomes more complicated, so that the reliability of the identification decreases.

  In the present invention, “SY0” of the synchronization code (SYNC Code) arranged first in the same sector or “FR0” of the sync frame position number 115 is changed to another place in the same sector (in the embodiment shown in FIGS. 34 and 35). (2nd, 5th, 7th, 14th, 15th, 18th, 20th). As a result, the number of types of synchronization code patterns arranged in the same sector or the number of types of sync frame position numbers 115 to be used can be greatly reduced.

  In the current DVD standard, eight types from “SY0” to “SY7” are reduced to only three types from “SY0” or “FR0” to “SY2” or “FR2” in the embodiment of FIGS. ing. For this reason, since the number of types of patterns to be identified or the number of types of sync frame position numbers 115 to be used is small, the identification time by round-robin pattern matching is greatly reduced and the identification is simplified. The deterioration of the reliability of identification that occurs is also suppressed.

  Point [5]... At the time of reproduction, a plurality of pieces of synchronization code information that are sequentially reproduced are read, and the position in the physical sector at the current reproduction location is determined from the connection of information between the pieces of synchronization code information [FIGS. 36 and 42 Description].

  This effect is as follows.

  In the conventional DVD, the position of “SY0” positioned at the head in the sector is detected, and the data ID 1-0 information immediately after that is reproduced to check the current reproduction location. Therefore, when reproducing from the middle of the sector, the reproduction is continued until “SY0” is detected. However, in this method, for example, a partial error occurs in “SY0” due to a defect on the information storage medium 9 or the synchronization position detection code 121 as described in [Effect] of [3]. If a bit shift error occurs at this point and “SY0” cannot be accurately identified, it is necessary to wait until “SY0” of the next sector comes. For this reason, it often takes time to detect the playback location, and the detection reliability is low.

  In contrast, the embodiment of the present invention employs the method shown in the flowchart of FIG. 42 and the lower right of FIG. 36 (an example in which the sync frame position is calculated from the arrangement order of the sync frame position identification codes). That is, this is a method of reproducing information of a plurality of continuous synchronization codes 110 and determining the position of the currently reproduced synchronization code 110 in the same physical sector 5 from the arrangement order of the synchronization codes 110. By adopting this method, even if the synchronization code 110 cannot be accurately reproduced partially due to an error caused by a defect on the information storage medium 9 or a bit shift error, the sector data position is determined from the sequence of the preceding and following synchronization codes 110. It is possible to anticipate and correct this.

  Therefore, by adopting the embodiment of the present invention, the reliability of information reproduction from the synchronization code 110 or detection of the position of the synchronization code 110 is greatly improved. As a result, for example, even if the first synchronization code 110-0 in the physical sector data 5 cannot be reproduced, the connection of the preceding and following synchronization codes 110 is used without waiting for the next physical sector data 5 to arrive, as in the prior art. Thus, since the first synchronization code 110-0 position can be determined, the speed of the synchronization code 110 position detection can be increased.

  Embodiments of the present invention will be described with reference to FIGS.

  1 indicates a pack string such as the video pack 101a, the audio pack 102a,..., And the part b indicates logical sector information 103-0, 103a-1, 103 corresponding to each pack. -2... Further, in the part of the code c, one logical sector information 103-0 is scrambled and PI information is added to each row (12 rows in this example). Further, Data ID, IED, and CPR_MAI are added to the top line. The last line (13th line) of this logical sector information is PO information.

  1 is divided into sync frame data 105-0, 105-1,... (26 (= 13 × 2) in total). A sync code described later is added between the sync frame data. That is, a synchronization code is added to the head of each sync frame data.

  FIG. 2 shows a state in which a synchronization code is inserted between sync frame data as indicated by reference numerals d and c. The synchronization code is composed of, for example, a variable code area 112, a fixed code area 111, and a variable code area 113, as indicated by a symbol f, and each region is indicated by a symbol g and a symbol h in FIG. It is a content.

  The characteristic configuration will be described as follows.

  As shown in FIG. 1, the video information is recorded on the information storage medium 9 in the form of a video pack 101 and an audio pack 102 (portion a) in units of 2048 bytes. This 2048-byte recording unit is handled as the logical sector information 103 (part b).

  In the current DVD standard, Data ID 1-0, IED2-0 and CPR_MAI8-0 are added to this data, and PI (Parity of Inner-code) information and PO corresponding to the ECC structure shown in FIGS. The data to which (Parity of Outer-code) information is added is divided into 26 equal parts to form sync frame data 105-0 to 105-25 (part indicated by symbol d in FIGS. 1 and 2). In this case, the PO information is also divided into two.

  Each sync frame data 105 is modulated, and the synchronization code 110 of the present invention is inserted between the modulated sync frame data 106. The modulation method is generally represented by (d, k; m, n), and the meaning of this symbol is to convert the original data of “m bits” to “n channel bits”, and “0” is the continuous channel bit pattern after modulation. The minimum range is “d” and the maximum is “k”.

As an embodiment of the present invention, for example, a case where the modulation system shown in “JP 2000-332613” is employed is shown. In the modulation scheme, d = 1, k = 9, m = 4, n = 6.
It becomes. The synchronization code 110 is divided into a fixed code area 111 and variable code areas 112 and 113, and the variable code areas 112 and 113 are further recorded with the recording location of the “conversion table selection code 122 at the time of modulation” and “for sync frame position identification”. A major feature of the present invention is that the recording location of the code 123 "and the recording location of the" DC suppression polarity reversal pattern 124 "are subdivided into a structure (including merging / combining some recording locations).

  The modulation referred to here is conversion of input data into modulation data in accordance with the above modulation rule. In this case, this conversion processing employs a technique of selecting modulation data corresponding to input data from a large number of modulation data described in the conversion table. Here, a plurality of conversion tables are prepared. Accordingly, information indicating which table at the time of modulation is used to convert the modulated data is necessary, and this information is “a conversion table selection code 122 at the time of modulation”, which is immediately before the synchronization code. The conversion table which produced | generated the modulation data which comes after modulation data is represented.

  “Sync frame position identification code 123” is a code for identifying the position of the sync frame in the physical sector. In order to identify a frame, it can be identified by an arrangement pattern of a plurality of sync frame position identification codes before and after.

  As the specific contents of the synchronization position detection code 121, as shown by the symbol h in FIG. 2, a combination of a pattern in which “0” continues for “k + 1 or more” and a pattern in which “0” continues for two is included. There is a major feature of the present invention. In order to facilitate the position detection of the synchronization code 110, a code that cannot exist in the modulated sync frame data 106 is arranged in the synchronization position detection code 121. Since the modulated sync frame data 106 is modulated according to the (d, k; m, n) modulation rule, “0” cannot continue “k + 1” continuously in the modulated data. . Therefore, it is desirable to arrange a pattern in which “0” continues and “k + 1 or more” continues as a pattern in the synchronization position detection code 121.

  However, when a pattern in which “0 + 1” continues as “k + 1” is arranged as a pattern in the synchronization position detection code 121, one bit shift error occurs during reproduction of the modulated sync frame data 106 Then, there is a risk of erroneous detection as the synchronization position detection code 121. Therefore, it is desirable to arrange a pattern in which “0” continues and “k + 2” continues as a pattern in the synchronization position detection code 121. However, if a continuous pattern of “0” continues for a long time, a phase shift in the PLL circuit 174 is likely to occur.

  The current DVD uses a pattern of “0” followed by “k + 3” (the modulation rule of the current DVD is (2, 10; 8, 16)). Therefore, in order to suppress the occurrence of a bit shift error and to ensure the reliability of synchronization code 110 position detection and information reproduction as compared with the current DVD, in the present invention, the length followed by “0” needs to be “k + 3” or less. Desirably, “k + 2” is better.

  As shown in FIG. 8 of Japanese Patent Application No. 10-275358 (Japanese Patent Application Laid-Open No. 200-105981) and its explanatory text, the DSV (Digital Sum Value) value changes depending on the bit pattern after modulation. When the DSV value deviates greatly from 0, the DSV value can be brought close to 0 by changing the bit from “0” to “1” at the optimum bit pattern position.

  As described above, in the present invention, the synchronization code 110 has the DC suppression polarity inversion pattern 124 having a specific pattern for bringing the DSV value close to zero.

  Further, when the modulation scheme shown in “Japanese Patent Laid-Open No. 2000-332613” is adopted, “selection information of the conversion table adopted at the time of the modulation of 6-channel bit modulated data existing immediately after the 6-channel bit modulated data to be demodulated. ”Also needs to be used to demodulate 6 channel bits to be demodulated.

  Therefore, as shown by the symbol e in FIG. 2, a conversion table for 6 channel bits that should come next next to the last 6 channel bit data of the modulated sync frame data 106 arranged immediately before the synchronization code 110. The selection information is recorded in the conversion table selection code 122 at the time of conversion in the synchronization code 110. That is, the conversion table selection code 122 at the time of modulation exists in the synchronization code 110. The conversion table selection code 122 at the time of modulation is conversion table selection information for 6 channel bit data that should come after the last 6 channel bit data of the immediately preceding sync frame data 106. By referring to this conversion table information, a conversion table to be used can be determined when demodulating the next data.

  3 and 4 show the structure of the information reproducing apparatus or information recording / reproducing apparatus according to the present invention.

  FIG. 3 shows a recording system, and FIG. 4 shows a reproduction system. The control unit 143 controls the entire apparatus. Data ID, IED, CPR_MAI, and EDC adding unit 168 add Data ID, IED, CPR_MAI, and EDC to logical sector information 103 input from interface unit 142. The Data ID is generated from the Data ID generator 165 based on a predetermined rule. CPR_MAI is output from the CPR_MAI generator 167. The logical sector information 103 to which Data ID, IED, CPR_MAI, and EDC are added is input to the scramble circuit 157, and for example, the entire data is scrambled. The scrambled data is input to the ECC encoding circuit 161 and converted into an ECC block. The ECC block is shown at the position indicated by the symbols h and i in FIG.

  The ECC block is input to the modulation circuit 151 and modulated. This modulation process uses a conversion table stored in the conversion table storage unit 153 (for example, a conversion table from 4 bits to 6 bits). In order to select the modulation data of the table, the DSV calculation unit 148 calculates the DSV for the continuous modulation data, and the DC component is within a predetermined level (the number of consecutive 0s or the number of consecutive 1s is within a predetermined value). ) Is selected. Further, a polarity inversion pattern for DC suppression is selected according to the DSV calculation result. The sync frame position identification code generator 136 outputs a sync frame position identification code. The sync frame position identification code is a code for identifying a frame in one ECC block.

  Data after modulation (sync frame data) and modulation-related information (synchronization code: conversion table selection code, sync frame position identification code, information for selecting a DC suppression polarity inversion pattern, etc.) are stored in temporary storage section 150. Next, it is given to the synchronization code generation / addition unit 146. The synchronization code generation / addition unit 146 adds the code shown in the portion h in FIG. 2 to the synchronization code.

  The contents of the post-modulation data, modulation-related information temporary storage unit 150, and synchronization code generation / addition unit 146 are further illustrated in FIG.

  The data converted into the sync frame as described above is supplied to the information recording / reproducing unit 141 and recorded on the optical disc.

  Data reproduced from the optical disc is waveform-equivalent in the PR equivalent circuit 130 from the information recording / reproducing unit 141 and digitized by the AD converter 169. The digitized data is input to the synchronization code position extraction unit 145 and the shift register circuit 170 via the Viterbi decoder 156. In accordance with the synchronization position extraction result of the synchronization code position extraction unit 145, the modulation data of the shift register circuit 170 is input to the demodulation circuit 152 and demodulated using the conversion table of the demodulation conversion table recording unit 154 (for example, 6 Bit to 4 bit conversion). From the demodulated data, the Data ID and IED extraction unit 171 extracts the Data ID and IED. For the Data ID, the Data ID part error tick part 172 performs error tick using IED. Here, when there is no error, the ECC block has been reproduced normally. If there is an error, for example, the ECC block is re-read.

  The ECC block is input to the coding circuit 162 by ECC and subjected to error correction processing. The error-corrected data is descrambled by the descrambling unit 159 and becomes the original logical sector information, which is extracted by the logical sector extraction unit 173. The extracted logical sector is sent to a data decoding processing unit (not shown) via the interface unit 142.

  5, FIG. 6, and FIG. 7 show how the data string shown in the part c of FIG. 1 is constructed as an ECC block. 5 describes each row of the ECC block as data 0-0-0, 0-0-1, 0-0-2,... The physical sector data constructs a 13-line frame. PI information is added to each row of this physical sector, and the last row is a row of PO information. One ECC block is constructed by a plurality of physical sector data. The PO information is created in units of one ECC block constructed by a plurality of physical sectors, and is distributed by one line in each physical sector.

  As shown in FIG. 7, every other physical sector data is selected and distributed to the first small ECC block 7-0 and the second small ECC block 7-1.

  In this example, one physical sector data out of the physical sector data (the part of the code f) consists of 13 rows. Of these, one line is a part of the PO information. One small ECC block is composed of 31 physical sector data. 62 physical sector data (two small ECC blocks) are divided into, for example, even sector data and odd sector data, and PO information for each block of even sector data and odd sector data. Has been created.

  FIG. 7 shows the relationship between the physical sector data array, the physical sector data arrayed in this way, and the ECC blocks. FIG. 8 shows a state in which physical sector data is arranged on the information storage medium 9. The first and second small ECC blocks are constructed by taking every other physical sector data arranged on the track.

  In the embodiment of the present invention, the channel bit interval is shortened to the limit in order to increase the density of the information storage medium 9. As a result, for example, when a pattern “10101010101010101010101010”, which is a repetition of the pattern of d = 1, is recorded on the information storage medium 9, and the data is reproduced by the information recording / reproducing unit 141, the cutoff frequency of the MTF characteristic of the reproducing optical system Is approaching. For this reason, the signal amplitude of the reproduction signal is almost buried in noise.

  Therefore, the PRML (Partial Response Maximum Likelyhood) technique is used in the embodiment of the present invention as a method of reproducing the recording marks or pits whose density is close to the limit (cutoff frequency) of the MTF characteristic. That is, the signal reproduced from the information recording / reproducing unit 141 is subjected to reproduction waveform correction by the PR equalization circuit 130. An AD (analog / digital) converter 169 samples the signal after passing through the PR equalization circuit 130 in accordance with the timing of the reference clock 198 sent from the reference clock generation circuit 160 and converts it into a digital quantity, and a Viterbi decoder 156. Receive Viterbi decoding processing.

  The data after the Viterbi decoding process is processed as the same data as the data binarized at the conventional slice level. When the PRML technique is employed, the error rate of data after Viterbi decoding increases when the sampling timing in the AD converter 169 is shifted. Therefore, in order to increase the accuracy of the sampling timing, the information reproducing apparatus or information recording / reproducing apparatus of the present invention has a sampling timing extracting circuit (a combination of the Schmitt trigger binary circuit 155 and the PLL circuit 174).

  The information reproducing apparatus or information recording / reproducing apparatus of the present invention is characterized in that a Schmitt trigger binarization circuit 155 is used as the binarization circuit. This Schmitt trigger binarization circuit 155 gives a specific width (actually the forward voltage value of the diode) to the slice reference level for binarization, and is binarized only when the specific width is exceeded. Have the characteristics Therefore, for example, as described above, when the pattern “101010101010101010101010” is input, since the signal amplitude is very small, binarization switching does not occur, and a sparser pattern such as “1001001001001001001001” is input. The amplitude of the reproduced raw signal increases. Therefore, in the Schmitt trigger binarization circuit 155, the polarity of the output binarization signal is switched in accordance with the timing “1”. In the embodiment of the present invention, the NRZI (Non Return to Zero Invert) method is employed, and the position of “1” of the pattern coincides with the edge portion (boundary portion) of the recording mark or pit.

  The PLL circuit 174 detects a frequency and phase shift between the binarized signal output from the Schmitt trigger binarizing circuit 155 and the reference clock 198 signal sent from the reference clock generating circuit 160 to detect the PLL circuit 174. The frequency and phase of the output clock are changed. In the reference clock generation circuit 160, the output signal of the PLL circuit 174 and the decoding characteristic information of the Viterbi decoder 156 (specifically, although not shown, the convergence length in the path metric memory in the Viterbi decoder 156 (distance to convergence) ) Is used to feed back the reference clock 198 (frequency and phase) so that the error rate after Viterbi decoding is lowered.

The ECC encoding circuit 161, the ECC decoding circuit 162, the scramble circuit 157, and the descramble circuit 159 shown in FIG. When 1 byte data before modulation is modulated according to the (d, k; m, n) modulation rule, the length after modulation is 8n ÷ m (1)
It becomes.

Therefore, when the data processing unit in the above circuit is converted by the processing unit after modulation, it is given by equation (1). The processing unit of the modulated sync frame data 106 in the portion indicated by the symbol e in FIG. 2 is given by the equation (1). When the integration of the processing between 106 is directed, it is necessary to set the data size (channel bit size) of the synchronization code 110 to an integral multiple of the equation (1). Therefore, in the embodiment of the present invention, the size of the synchronization code 110 is 8Nn ÷ m (2)
Thus, a major feature of the present invention resides in that the integrity of processing between the synchronization code 110 and the modulated sync frame data 106 is ensured. (N in formula (2) means an integer value.)
As an embodiment of the present invention, d = 1, k = 9, m = 4, n = 6.
Therefore, if the value is substituted into the equation (2), the total data size of the synchronization code 110 is 12N (3)
It becomes.

  The sync code size of the current DVD is 32 channel bits. However, for the reason described in the description of the point [1] of the present invention and the effect thereof, the data processing is simplified and the reliability of position detection / information identification is improved by making the total data size of the synchronization code 110 smaller than 32 channel bits. Improves. Therefore, in the present invention, the total data size of the synchronization code 110 is preferably 24 channel bits.

  In FIG. 9, the generation of the synchronization code 110 according to the present invention, the addition of the synchronization code to the sync frame, and the creation of a data unit to be recorded (synchronization code generation / addition unit 146), the modulated data, and the modulation related information The details of the temporary storage unit 150 are shown. The operation of this part will be described later with reference to FIGS.

  FIG. 10 shows details of the synchronization code position extraction unit 145 and the demodulation circuit 152. The operation of this part will be described later with reference to FIG.

  The data size of the synchronization code 110 (and the data size of the modulated sync frame data 106) in each embodiment of the present invention is shown as a numerical value in FIGS.

  FIG. 11 shows the relationship between the operation of the PLL circuit 174 shown in FIGS. 3 and 4 and the pattern in the synchronization position detection code 121.

  11 represents the pattern contents around the synchronization position detection code 121, and the output waveform of the Schmitt trigger binarization circuit 155 based on the reproduction signal from the information storage medium 9 on which the pattern is recorded. It is shown in the part of the code | symbol b of FIG. In addition, the temporal change of the reference clock 198 output from the reference clock generation circuit 160 by the action of the PLL circuit 174 is shown in the reference numerals c to e in FIG.

  The PLL circuit 174 detects the frequency / phase shift amount with respect to the reference clock 198 only by the polarity switching timing of the input signal (the part b in FIG. 11) and applies feedback. Therefore, in the synchronization position detection code 121 where “0” continues continuously for a long time, the feedback of the PLL circuit 174 is not applied, and the phase of the reference clock 198 gradually shifts.

  Therefore, after “0” continues continuously for a long time in the synchronization position detection code 121, the phase shift “δ1” between the reference clocks 198 is detected and fed back to the reference clock 198 when “1” comes for the first time. It takes. However, once feedback is applied at this position, phase comparison cannot be performed until the next "1" comes, so the time until the next "1" is long (that is, until the next "1" comes). If the number of “0” inserted between them is large), the feedback is excessively applied, and conversely, it becomes easy to cause out of phase.

  For the above reason, the pattern of the synchronization position detection code 121 is a pattern in which “0” continues for a long time and “1” comes in with as few “0” as possible immediately after “1” comes. Thus, the present invention is characterized in that the phase / frequency shift correction performance of the PLL circuit 174 is improved.

  In the present invention, in order to improve the phase / frequency deviation correction performance of the PLL circuit 174 over the “10001” pattern of the current DVD, the number of “0” s arranged between “1” and “1” is set to two or less. Yes. In the present invention, since the reproduction signal of the close-packed pattern “101” is in the vicinity of the cutoff frequency of the MTF characteristic with the aim of increasing the density of the information storage medium 9, the Schmitt trigger binarization is performed to improve the detection characteristic of the reproduction signal. The circuit 155 is devised so that a binarized signal causing polarity inversion cannot be obtained from the close-packed pattern “101”. Therefore, for the above reason, a pattern in which two “0” s are included between “1” and “1” is adopted as the pattern in the synchronization position detection code 121.

  FIG. 12A to FIG. 22C show the structure in the synchronization code in the present invention.

In the embodiment of FIG. 12A, the synchronization code 110 is set as synchronization information (SY), the conversion table selection code 122 at the time of modulation and the synchronization position detection code 121 are arranged, and the frame information (FR) is
This is an example in which a DC suppression polarity inversion pattern 124 and a sync frame position identification code 123 are arranged in order.

  In the embodiment of FIG. 12B, a conversion table selection code 122, a DC suppression polarity inversion pattern 124, and a synchronization position detection code 121 at the time of modulation are arranged as synchronization information (SY) in the synchronization code 110. In this example, sync frame position identification codes 123 are sequentially arranged as frame information (FR).

  In the embodiment of FIG. 13 (A), in the synchronization code 110, as the frame information (FR), a conversion table selection code 122 at the time of modulation and a sync frame position identification code 123 are arranged in order, and as synchronization information (SY). In this example, a synchronization position detection code 121 and a DC suppression polarity reversal pattern 124 are arranged in order.

  In the embodiment of FIG. 13B, a conversion table selection code 122, a DC suppression polarity inversion pattern 124, and a sync frame position identification code 123 are arranged in order as frame information (FR) in the synchronization code 110. In this example, the synchronization position detection code 121 is arranged as the synchronization information (SY).

  In the embodiment of FIG. 13C, in the synchronization code 110, as frame information (FR), a conversion table selection code 122 at the time of modulation, a sync frame position identification code 123, a DC suppression polarity inversion pattern 124, a sync frame In this example, the position identification code 123 is arranged in order, and the synchronization position detection code 121 is arranged as the synchronization information (SY).

In the embodiment of FIG. 14A, a conversion table selection code 122 and a synchronization position detection code 121 at the time of modulation are arranged as synchronization information (SY) in the synchronization code 110, and as frame information (FR),
In this example, the sync frame position identification code 123 and the DC suppression polarity reversal pattern 124 are integrated.

  In the embodiment of FIG. 14B, a synchronization position is detected by a pattern in which a conversion table selection code 122 and a DC suppression polarity inversion pattern 124 are integrated as synchronization information (SY) in the synchronization code 110. This is an example in which a sync code 121 is arranged and sync frame position identification code 123 is arranged as frame information (FR).

  In the embodiment of FIG. 15A, a pattern in which a conversion table selection code 122 at the time of modulation and a sync frame position identification code 123 are integrated is arranged in the synchronization code 110 as frame information (FR). In this example, a synchronization position detection code 121 and a DC suppression polarity reversal pattern 124 are arranged as information (SY).

  In the embodiment of FIG. 15B, the sync code 110 includes, as frame information (FR), a pattern in which the conversion table selection code 122 at the time of modulation and the DC reversal polarity inversion pattern 124 are integrated, and a sync frame. In this example, the position identification code 123 is arranged, the pattern is arranged, and the synchronization position detection code 121 is arranged as the synchronization information (SY).

  In the embodiment of FIG. 16A, a pattern in which a conversion table selection code 122 and a sync frame position identification code 123 at the time of modulation are integrated as frame information (FR) in the synchronization code 110, and DC suppression. In this example, the polarity reversal pattern 124 is arranged, and the synchronization position detection code 121 is arranged as the synchronization information (SY).

  In the embodiment shown in FIG. 16B, the sync code 110 includes, as frame information (FR), a conversion table selection code 122 at the time of modulation, a sync frame position identification code 123, and a DC suppression polarity inversion pattern 124. Are arranged, and the synchronization position detection code 121 is arranged as the synchronization information (SY).

  In the embodiment of FIG. 17A, a conversion table selection code 122, a sync frame position identification code 123, and a DC suppression polarity inversion pattern 124 are integrated as frame information (FR) in the synchronization code 110. In this example, the synchronization position detection codes 121 are arranged as synchronization information (SY).

  In the embodiment of FIG. 17B, the synchronization code 110 includes synchronization table selection code 122, sync frame position identification code 123, DC suppression polarity inversion pattern 124, and synchronization position as synchronization information (SY). In this example, the detection codes 121 are arranged as an integrated pattern.

  The embodiment of FIG. 18A arranges the conversion table selection code 122 at the time of modulation and the sync frame position identification code 123 as an integrated pattern in the synchronization code 110 as frame information (FR), In this example, the synchronization position detection code 121 and the DC suppression polarity inversion pattern 124 are arranged as an integrated pattern as the synchronization information (SY).

  In the embodiment of FIG. 18B, a modulation table selection code 122 and a sync frame position identification code 123 at the time of modulation are arranged as frame information (FR) in the synchronization code 110 to obtain synchronization information (SY). In this example, the synchronization position detection code 121 and the DC suppression polarity reversal pattern 124 are arranged as an integrated pattern.

  In the embodiment of FIG. 19A, a conversion table selection code 122 at modulation and a polarity reversal pattern 124 for DC suppression are arranged as synchronization information (SY) in the synchronization code 110, and this is followed by synchronization. This is an example in which a pattern in which the position detection code 121 and the sync frame position identification code 123 are integrated is arranged.

  In the embodiment of FIG. 20A, in the synchronization code 110, a conversion table selection code 122 at the time of modulation, a synchronization position detection code 121, and a DC suppression polarity inversion pattern 124 are included as synchronization information (SY). In this example, the modulated sync frame position identification codes 125 are arranged as frame information (FR).

  In the embodiment of FIG. 20B, the synchronization table 110 includes a modulation table selection code 122, a DC suppression polarity inversion pattern 124, and a synchronization position detection code 121 as synchronization information (SY) in the synchronization code 110. In this example, the modulated sync frame position identification codes 125 are arranged as frame information (FR).

  In the embodiment of FIG. 21, a pattern in which the conversion table selection code 122 at the time of modulation and the DC reversal polarity inversion pattern 124 are integrated is arranged as synchronization information (SY) in the synchronization code 110, and then synchronized. In this example, a position detection code 121 is arranged, and a modulated sync frame position identification code 125 is arranged as frame information (FR).

  In the embodiment of FIG. 22A, only the synchronization information (SY) is included in the synchronization code 110, the conversion table selection code 122 at the time of modulation, the synchronization position detection code 121, and the DC suppression polarity inversion pattern 124, Is an example in which

  In the embodiment of FIG. 22B, only the synchronization information (SY) is included in the synchronization code 110, the conversion table selection code 122 at the time of modulation, the DC reversal polarity inversion pattern 124, the synchronization position detection code 121, Is an example in which

  In the embodiment of FIG. 22C, the synchronization code 110 includes only the synchronization information (SY), and a pattern in which the conversion table selection code 122 at the time of modulation and the DC suppression polarity inversion pattern 124 are integrated is arranged. This is an example in which a synchronization position detection code 121 is arranged next.

  As described above, in the present invention, as an example of the synchronization code 110, the modulation conversion table selection code 122, the synchronization position detection code 121, the sync frame position identification code 123, and the DC suppression polarity inversion pattern 124 are also used. Without having a separate arrangement.

  In addition, a structure in which a part is combined and combined is possible.

  20A, 20B, and 21 show a structure in which the modulated sync frame position identification code 125 is modulated, thereby reducing the channel bit size of the non-modulated data area 108 and improving the synchronization code detection performance. Can be improved.

  FIG. 22 shows a specific structure of only “SY” information used in FIGS. 29 to 32, FIG. 35 and the like which will be described later. By adopting this structure, the information storage medium 9 will be described later. User data usage efficiency can be improved.

  Next, specific bit pattern examples in the synchronization code 110 are shown in FIGS.

  Each shows a specific bit pattern corresponding to the structure of the synchronization code 110 shown in FIGS. 14 (A), 14 (B), 15 (A), and 17 (A). “*” In FIGS. 23 to 26 means that “0” or “1” is appropriately selected so that the DSV value approaches “0”.

  The example of FIG. 23 is characterized in that “0” is continued by “k + 2” by combining the conversion table selection code 122 and the synchronization position detection code at the time of modulation. The portion indicated by the symbol a is the same as the content shown in FIG. There are two patterns as the conversion table selection code 122 at the time of modulation, and 0 or 1 is set as the conversion table number (the part indicated by the symbol c). Further, 12 bits, 18 bits, or 24 bits are assigned as the synchronization position detection code 121 (portion indicated by symbol b). Six bits are assigned as a pattern in which the sync frame position identification code and the DC reversal polarity reversal pattern are combined (part indicated by a symbol d).

  The pattern 00010 * means frame 0, the pattern 00100 * means frame 1, the pattern 00010 * means frame 2, and the pattern 0010 * means frame 3 If the pattern is 00 * 010 or 0 * 0010, it means frame 4.

  As described above, the pattern of the synchronization position detection code 121 has a portion where the interval of “1” and “1” is 1) longer than the maximum length that can be generated by the modulation rule. 2) The closest density that can be generated by the modulation rule ( (Minimum) Does not include length (because it is advantageous for PLL correction in the case of the smallest next long pattern), 3) k + 2 “0” by combining the conversion table selection code and the synchronization position detection code at the time of modulation Has a continuing part.

The conditions such as are satisfied.

  The example of FIG. 24 shows a specific bit pattern corresponding to the structure of the synchronization code 110 shown in FIG. In this example, a pattern in which a conversion table selection code at the time of modulation and a DC suppression polarity inversion pattern are combined is used before the synchronization position detection code 121.

As the pattern, 100 * 1 is set as the pattern of the table number 0, and 010 * 01 is set as the pattern of the table number 1 (the portion indicated by the symbol c). The synchronization position detection code 121 employs 12 bits, 18 bits, or 24 bits, as described in the portion indicated by the symbol b. Furthermore, 6 bits are allocated to the sync frame position identification code 1123, and 8 patterns among the 12 patterns are adopted (part indicated by reference sign d).

  This example also has a rule that the interval of “1” and “1” is 1) has a part longer than the maximum length that can be generated by the modulation rule, and 2) does not include the closest (minimum) length that can be generated by the modulation rule.

  The example of FIG. 25 shows a specific bit pattern corresponding to the structure of the synchronization code 110 shown in FIG. In this example, a pattern (6-bit allocation) in which a conversion table selection code 122 and a sync frame position identification code 123 at the time of modulation are integrated is arranged as frame information (FR), and synchronization information (SY) is synchronized. This is an example in which a position detection code 121 (12, 18 or 24 bits) and a DC suppression polarity inversion pattern 124 (6 bits) are arranged.

  As sync frame position numbers, six patterns when the conversion table 0 is used and six patterns when the conversion table 1 is used are set (portion indicated by symbol c).

  As the synchronization position detection code 121, any of the codes shown in the portion indicated by the symbol b is adopted. Further, as the DC suppression polarity inversion pattern 124, 6 bits are assigned and 10010 * is used.

  In this example, the pattern of the synchronization position detection code 121 is set so that the interval between “1” and “1” is 1) longer than the maximum length that can be generated by the modulation rule (in this example, “0” is followed by “k + 2”). ing). 2) A pattern in which “0” is continued by “2” is configured by combining the synchronization position detection code and the DC suppression polarity determination pattern. There is a rule.

  The example of FIG. 26 shows a specific bit pattern corresponding to the structure of the synchronization code 110 shown in FIG. In this example, a pattern (8) in which a conversion table selection code 122 at the time of modulation, a sync frame position identification code 123, and a DC suppression polarity inversion pattern 124 are integrated in the synchronization code 110 as frame information (FR). Bit) (part indicated by symbol c), and synchronization position detection code 121 (part indicated by symbol b) is arranged as synchronization information (SY).

  As the sync frame position number, 14 patterns when the conversion table 0 is used and 14 patterns when the conversion table 1 is used are set (portion indicated by reference symbol c). The conversion tables 0 and 1 have a classification of DC pattern A (7 types) and DC pattern B (7 types).

  Also in this embodiment, the pattern of the synchronization position detection code 121 has an interval between “1” and “1” being 1) longer than the maximum length that can be generated by the modulation rule (in this example, “0” is “k + 2”). in the process of). 2) Does not include the closest (minimum) length that can occur in the modulation rule (constitutes a pattern that continues “0” by “2”). There is a rule.

  27 to 35 show various embodiments of the method for arranging synchronous codes in one physical sector in the present invention. FIGS. 27 to 35 b show the arrangement of the synchronization code 110 and the modulated sync frame data 106 described on the straight line shown in the part e of FIG. 2 in a matrix form for easy viewing. is there.

  As an application example of the embodiment of the present invention, the structure in the synchronization code takes various structures as shown in FIGS. In order to take correspondence between the specific structure in the synchronization code 110 used in FIGS. 27 to 35 and the structure shown in FIGS. 12 to 22, the respective parts in each structure shown in FIGS. 12 to 22 are integrated. The groups “SY”, “SY *”, and “FR *” (* represents a number) are summarized, and the correspondence between each part and the group is shown in FIGS.

  For example, since the portions of the synchronization code 110 in FIG. 27 are arranged in the order of “SY” and “FR *”, FIG. 12 (A), FIG. 12 (B), FIG. 14 (A), FIG. All the structures shown in FIGS. 20A, 20B, and 21 correspond to the structures in the synchronization code 110 shown in FIG.

  In the case of the structure shown in FIGS. 27 and 33, since “FR *” comes after “SY”, the synchronization position detection code detection unit 182 shown in FIG. After the detection, “FR *” immediately after that is transferred to the identification unit 185 of the sync frame position identification code content via the variable code transfer unit 184. As a result, the position of the synchronization code 110 in the physical sector is determined.

  In the case of the structure shown in FIG. 28, “FR *” is arranged before “SY”, so that it is transferred via the variable code transfer unit 183 to the code frame identification unit 185 for sync frame position identification, and the synchronization code. 110 positions in the physical sector are determined.

  In the case of the structure of FIGS. 29 to 32, half of the synchronization code 110 is only “SY” information that does not include the sync frame position identification code. Here, only the DSV value correction for the modulated data is performed by the built-in DC control polarity inversion pattern 124.

  In the case of the structure of FIGS. 29 to 32 described above, the size of the “SY” portion is set to 24 bits, which is the same as that of the other synchronization codes 110. However, since the function of “SY” is limited, the size of this portion is reduced to reduce the total number of bits used for the synchronization code 110 in one physical sector. Thereby, there is an effect that the use efficiency of user data to the information storage medium 9 can be improved (the occupation rate of the modulated sync frame data 106 in one physical sector can be improved). As another application example of the present invention, in order to further enhance the effect of improving the utilization efficiency, the number of synchronization codes 110 to be inserted in one physical sector in a conventional DVD is reduced to half as shown in FIG. There is.

  FIG. 34 and FIG. 35 show another embodiment relating to the synchronization code arrangement method in one physical sector in the present invention.

  The structure of FIG. 35 has the structure in the synchronization code shown in FIG. 17B, FIG. 19A, or FIG. 19B, and the structure of FIG. ~ (C), Fig. 15 (A), Fig. 15 (B), Fig. 16 (A), Fig. 16 (B), 17 (A), Fig. 18 (A), Fig. 18 (B) It has. However, the structure of FIG. 35 and the structure of FIG. 34 have the same combination / arrangement order of sync position numbers 115 corresponding to the sync frame position identification code 123 (which is also used as another code / pattern). Is.

  Not only “SY0” in FIG. 35 or “FR0” in FIG. 34 is arranged at the first position in the same physical sector, but the same “SY0” or “FR0” is placed in another location (second, fifth, seventh). , 14th, 15th, 18th, 20th) is a major feature of the present invention. Further, when one physical sector is completely divided into two parts (two parts with the last part of the modulated sync frame data 106-12 as a boundary), the arrangement position of “SY0” or “FR0” is completely the same before and after the two divisions. The following features are in place.

  That is, “SY0” or “FR0” is present immediately before the modulated sync frame data 106-0, and “SY0” or “FR0” is present immediately before the modulated sync frame data 106-13. . Further, “SY0” or “FR0” exists immediately before the modulated sync frame data 106-1, and “SY0” or “FR0” exists corresponding to the modulated sync frame data 106-14. . Furthermore, “SY0” or “FR0” is present immediately before the modulated sync frame data 106-4, and “SY0” or “FR0” is present immediately before the modulated sync frame data 106-17. .

  When “SY0” or “FR0” is symmetrically arranged before and after dividing one physical sector into two in this way, when “SY0” or “FR0” is detected at an arbitrary position in the physical sector, The range of the arrangement position of the modulated sync frame data 106 after modulation is not 26 in the prior art, but is 13 in that half. This means that the arrangement position determining process of the modulated sync frame data 106 is simplified.

  In addition, the arrangement of “SY1” or “FR1” and “SY2” or “FR2” is symmetrical and reversed before and after being divided into two at the same time. In other words, “SY1” or “FR1” exists immediately before the modulated sync frame data 106-2, and 1 and 2 are swapped immediately before the modulated sync frame data 106-15 at the corresponding symmetrical position. “SY2” or “FR2” exists. Also, “SY2” or “FR2” exists immediately before the modulated sync frame data 106-11, and 2 and 1 are now displayed immediately before the modulated sync frame data 106-24 at the corresponding symmetrical position. There is a replaced “SY1” or “FR1”.

  In this way, when the physical sector is divided into two and looking at the front and rear arrangement, “SY0” or “FR0” is arranged in a symmetrical position in the front and rear, and “SY1” or “FR1” and “SY2” or “FR2” are front and rear And are arranged at positions where 1 and 2 are interchanged. By taking this arrangement, only three types of “SY0”, “SY1”, “SY2” or only three types of “FR0”, “FR1”, “FR2” are arranged, and the sequential arrangement order of the synchronization code 110 is examined. It is possible to determine the position of the modulated sync frame data 106 currently being reproduced.

  Next, with respect to the synchronization code arrangement method shown in FIGS. 34 and 35, a method for determining the position in the physical sector of the data currently being reproduced using the sequence of information before and after the plurality of synchronization codes 110 is shown in FIG. This will be described with reference to FIG. 37 to 41, an example of the operation of the apparatus shown in FIGS. 3 and 4 has been described. This will be described later.

  The output data of the Viterbi decoder 156 (see FIG. 4) as shown in FIG. 36 is transferred to the synchronization code position detection unit 145 (step ST51 in FIG. 42), where the position of the synchronization code 110 is detected. Is done. In other words, the position of the synchronization position detection code 121 is detected by the pattern matching method by the synchronization position detection code detection unit 182 including a comparator (step ST52 in FIG. 42).

  Thereafter, the detected information of the synchronization code 110 is sequentially stored in the memory unit 175 via the control unit 143 as shown in FIG. That is, by using the detection timing of step ST52, the information about the sync frame position identification code 123 is extracted by the identification units 185 and 1865 of the sync shake no-position identification code contents and extracted to the memory unit 175 via the control unit 143. History information is recorded (step ST53 in FIG. 42).

  If the position of the synchronization code 110 is known, only the sync frame data 106 after the modulation in the data output from the Viterbi decoder 156 can be extracted and transferred to the shift register circuit 170. In other words, only the modulated sync frame data 106 is extracted using the timing of step ST52, and the modulated sync frame data 106 is transferred to the shift register circuit 170 in order to delay and match the timing (step ST54 of FIG. 42). ).

  Next, the control unit 143 reads the history information of the synchronization code 110 recorded in the memory unit 175, and identifies the arrangement order of the sync frame position identification codes (step ST55 in FIG. 42). Then, the position in the physical sector of the modulated sync frame data 106 temporarily stored in the shift register circuit 170 is determined (step ST56 in FIG. 42). That is, in the control unit 143, for example, the modulated sync signals transferred to the shift register circuit 170 from the data in the arrangement order shown in FIG. 34 or 35 with respect to the arrangement order of the identified sync frame position identification codes. The position of the frame data 106 in the physical sector is determined.

  Next, if necessary, the modulated sync frame data 106 transferred to the shift register circuit 170 is transferred to the demodulation circuit 152, and demodulation is started (step ST57).

  For example, as shown in FIG. 36, if the sequence of the synchronization codes 110 stored in the memory unit 175 is “FR0 → FR2 → FR1” or “SY0 → SY2 → SY1”, the “modulation” is immediately after “FR0” or “SY0”. If the subsequent sync frame data 106-6 exists, and if “FR0 → FR0 → FR1” or “SY0 → SY0 → SY1”, “FR0” or “SY0” is immediately followed by “modulated sync frame data 106-0”. It is possible to find out if "" exists.

  When the position in the physical sector is determined in this way and it is confirmed that the modulated sync frame data 106 at the desired position has been input into the shift register circuit 170, the data is transferred to the demodulation circuit 152. Demodulation is started (ST57 in FIG. 30).

  FIG. 37 shows data conversion processing when the synchronization code as shown in FIGS. 11 to 13 is employed.

  In step ST1, the logical sector information 103 to be recorded is received by the interface unit 142. In the next step ST2, the Data ID generator 165 generates Data ID information and IED information for each sector. In the next step ST3, the data ID shown in the part c in FIG. 1 or the part c in FIG. 5 is created by the Data ID, IED, CPR_MAI, EDC adding unit 168.

  In step ST4, the scramble circuit 157 performs scramble processing on the logical sector information 103. In step ST5, the ECC encoding circuit 161 configures an ECC block having the structure shown in FIGS.

  Next, in step ST6, the physical sector constituting the ECC block created in the ECC encoding circuit 161 is divided into 26 or 13 and divided into sync frame data 105 as indicated by a symbol d in FIG.

  In the next step ST8, modulation is performed in units of sync frame data 105 in the modulation circuit 151, and the result is transferred to the temporary storage unit 139 of the modulated data.

  (1) At the time of modulation, the DSV value calculation unit 148 sequentially calculates DSV values, selects a table to be used for modulation from the conversion table storage unit 153 at the time of modulation, and converts the conversion table selection information 192 into The data is transferred to the conversion table selection information storage unit 133 employed at the time of modulation.

  (2) At the same time, among the DSV value information 191 calculated at the time of modulation, the difference value for each sync frame data 105 is transferred to the DSV difference history storage unit 131 in sync frame data 105 units.

  In the next step ST9, the conversion table selection code 122 at the time of modulation is set in the conversion table selection code generator 134 at the time of modulation based on the data transferred from the conversion table selection information storage unit 133 employed at the time of modulation.

  In the next step ST10, the synchronization position detection code generator 136 generates the synchronization position detection code 121.

  In step ST11, the DSV calculation result (DSV value calculation unit 149 output) and the sync frame data 105 unit DSV difference history storage unit 131 for the data to be recorded by the information record generation unit 141 after being synthesized by the recording data synthesis unit 138. The DC suppression polarity inversion pattern 124 is set in the DC suppression polarity inversion pattern determination unit 132 on the basis of the output result.

  In the next step ST12, the sync frame position identification code generator 135 generates the sync frame position identification code 123.

  In the next step ST13, the synchronization code 110 is generated by synthesizing the data generated in ST9 to ST12 by the synchronization code 110 generation unit 137.

  In the next step ST14, the data generated by the synchronization code 110 generation unit 137 in the recording data combining unit 138 and the data recorded in the temporary storage unit 139 of the modulated data are combined, and the part indicated by the symbol e in FIG. The data arrangement shown in FIGS. 26 to 32 is created.

  Next, the data created in step ST14 is transferred to the information recording / reproducing unit 141 and transferred to the information storage medium 9, and the DSV value calculation unit 149 sequentially calculates the DSV value for the data, and the result is This is transferred to the DC suppression polarity inversion pattern determination unit 132.

  FIG. 38 is a diagram for explaining the data conversion process when the synchronization code as shown in FIGS. 14 to 19 is employed.

  In step ST1, the logical sector information 103 to be recorded is received by the interface unit 142. In step ST2, Date ID generation unit 165 generates Date ID information and IED information for each sector. In the next step ST3, the data ID, IED, CPR_MAI, EDC adding unit 168 creates a data arrangement shown in the part indicated by reference sign c in FIG. 1 or the part indicated by reference sign c in FIG.

  In step ST4, the scramble circuit 157 performs scramble processing on the logical sector information 103. In the next step ST5, the ECC encoding circuit 161 configures an ECC block having a structure indicated by a part c shown in FIG. 5 and parts h and i shown in FIGS.

  In the next step ST6, the physical sector constituting the ECC block created in the ECC encoding circuit 161 is divided into 26 or 13 to divide into the sync frame data 105 as shown by the part d in FIG. .

  In step ST7, the portion indicated by symbol e in FIG. 2 or the portion indicated by reference symbol b in FIG. 26, as shown in FIGS. 27 to 31 and FIG. 32, the sync frame data 106 after each modulation in one physical sector. The sync frame position identification code generation unit 136 generates a sync frame position identification code corresponding to the position of the sync frame. This sync frame position identification code is arranged at the head of each sync frame data 105 in the portion indicated by the symbol d in FIG.

  In the next step ST8 ′, modulation processing is performed including the sync frame position identification code arranged at the head of the sync frame data 105 in the modulation circuit 151.

(1) At the time of modulation, the DSV value calculation unit 148 sequentially calculates DSV values, selects a table to be used for modulation from the conversion table storage unit 153 at the time of modulation, and converts the conversion table selection information 192 into Then, the data is transferred to the storage unit 133 as conversion table selection information adopted at the time of modulation.

(2) At the same time, among the DSV value information 191 calculated at the time of modulation, the difference value for each sync frame data 105 is transferred to the DSV difference history storage unit 131 in sync frame data 105 units.

  In the next step ST9, the conversion table selection code 122 at the time of modulation is set in the conversion table selection code generator 134 at the time of modulation based on the data transferred from the conversion table selection information storage unit 133.

  In step ST10, the synchronization position detection code generator 136 generates the synchronization position detection code 121.

  In step ST11, the DSV calculation result (DSV value calculation unit 149 output) and sync frame data 105 units for the data combined by the recording data combining unit 138 and recorded by the information recording / reproducing unit 141 The DC suppression polarity inversion pattern 124 is set based on the output result of the DSV difference history storage unit 131. The DC suppression polarity inversion pattern 124 is set in the DC suppression polarity inversion pattern determination unit 132.

  In step ST13, the synchronization code 110 generation unit 137 combines the data generated in steps ST9 to ST11 to generate the synchronization code 110.

  In step ST14, the recording data synthesizing unit 138 synthesizes the data generated by the synchronization code 110 generating unit 137 and the data recorded in the temporary storage unit 139 of the modulated data, and the part indicated by the symbol e in FIG. The data arrangement shown in FIGS. 26 to 32 is created.

  In step ST15, the data created in step ST14 is transferred to the information recording / reproducing unit 141, transferred to the information storage medium 9, and the DSV value calculation unit 149 sequentially calculates the DSV value for the data. The result is transferred to the DC suppression polarity inversion pattern determination unit 132.

  FIG. 39 shows a data conversion process when information is simply reproduced in the apparatus of the present invention.

  In step ST21, the interface unit 142 receives an instruction for a range to be reproduced from the information storage medium 9. In the next step ST22, the information recording / reproducing unit 141 reproduces the data in which the sync frame data 106 after the synchronization code 110 modulation indicated by the symbol e in FIG. 2 is mixed, and the reproduced data is directly used as the shift register circuit 181. Forward to. In the next step ST23, the synchronization position detection code detector 182 configured by a comparator circuit detects the timing at which the synchronization position detection code 121 is transferred.

  In step ST24, based on the detection timing in step ST23, the variable code transfer unit 183 extracts the conversion table selection code 122 at the time of modulation and transfers it to the conversion table selection code identification unit 187 at the time of modulation.

  In step ST25, the conversion table selection code identification unit 187 at the time of modulation decodes the conversion table selection information 196 from the conversion table selection code 122 and transfers the decoding result to the demodulation conversion table selection / transfer unit 189.

  In step ST26, the identification unit (identification of sync frame position identification code contents) 185, 186 in the synchronization code position extraction unit 145 or the demodulation circuit 152 for the data transferred from the information recording / reproducing unit 141, Based on the detection timing of step ST23, the information of the sync frame position identification code 123 is read. Then, the position of the modulated sync frame data 106 is determined by the method shown in FIG. 42, and demodulation processing is performed using the data transferred in step ST24.

  In step ST27, the ECC decoding circuit 62 performs error correction. In step ST28, the descrambling circuit 159 performs descrambling processing.

  In step ST29, Data ID, IED, CPR_MAI, and EDC are deleted in the logical sector information extraction unit 173, and only the logical sector information 103 is transferred to the outside via the interface unit 142.

  FIG. 40 shows the control operation when the synchronization code as shown in FIGS. 11 to 13 is adopted and a predetermined position of the information recording medium is accessed.

  In step ST31, the interface unit 142 receives an instruction of a range to be reproduced from the information storage medium 9. In step ST32, the value of Data ID 1 corresponding to the reproduction start sector on the information storage medium 9 is calculated based on the information received in step ST31 in the control unit 143.

  In step ST33, the control unit 143 controls the information recording / reproducing unit 41 to start information reproduction from an approximate reproduction start position on the information storage medium 9. In the next step ST34, the information recording / reproducing unit 141 reproduces data in which the synchronization code 110 of the portion indicated by symbol e in FIG. 2 and the modulated sync frame data 106 are mixed, and the reproduced data is directly used as a shift register. Transfer to circuit 181.

  In the next step ST35, the synchronization position detection code detector 182 detects the timing at which the synchronization position detection code 121 is transferred. In step ST36, using the detection timing of step ST35, the conversion table selection code identifying unit 187 at the time of modulation decodes the conversion table selection information 196 and transfers the decoding result to the demodulation conversion table selection / transfer unit 189. .

  In step ST37, information on the sync frame position identification code 123 existing in the variable code transfer unit 183 or 184 is read using the detection timing in step ST35. 42, it is determined in which position in the physical sector the sync frame data 106 currently being reproduced exists, and the result is transferred to the control unit 143.

  In the next step ST40, it is determined whether or not it is the position of the first sync frame data 106-1 in the physical sector.

If the determination result is high, in step ST41, using the detection timing of step ST35, the Data ID 1-0 and IED2-0 information existing at the head position of the first sync frame data 105-0 in the physical sector are obtained. The data ID part and the IED part extraction part 171 are transferred. If a determination result is no, it will return to step ST34.

  In step ST42, the error check unit 172 of the Data ID unit checks whether there is an error in the Data ID1 information detected using the information of IDE 2.

  Then, whether or not there is an error in Data ID 1 is determined in Step ST43, and if there is, in Step ST44, the ECC decoding circuit 162 extracts Data ID 1 after error correction processing. If there is no error in Data ID 1, it is determined in step ST45 whether or not the scheduled track on the information storage medium 9 is being traced. If the determination result is yes, information reproduction from the information storage medium 9 is started in step ST46. On the other hand, in the case of No, in step ST47, the control unit 143 determines the track shift amount on the information storage medium 9 from the difference value between the data ID 1 value of the reproduction result and the data ID 1 of the reproduction start sector. Calculate and return to step ST33.

  FIG. 41 shows the control operation when the synchronization code as shown in FIGS. 14 to 19 is adopted and a predetermined position of the information recording medium is accessed.

  In step ST31, the interface unit 142 receives an instruction of a range to be reproduced from the information storage medium 9. In step ST32, the value of Data ID 1 corresponding to the reproduction start sector on the information storage medium 9 is calculated in the control unit 143 based on the information received in step ST31.

  In step ST33, the control unit 143 controls the information recording / reproducing unit 41 to start information reproduction from an approximate reproduction start position on the information storage medium 9.

  In the next step ST34, the information recording / reproducing unit 141 reproduces data in which the synchronization code 110 of the part e in FIG. 2 and the modulated sync frame data 106 are mixed, and the reproduced data is directly used as a shift register circuit. Forward to 181.

  In step ST35, the synchronization position detection code detector 182 detects the timing at which the synchronization position detection code 121 is transferred.

  In step ST36, using the detection timing of step ST35, the conversion table selection information 196 is decoded by the conversion table selection code identification 187 at the time of modulation, and the decoding result is transferred to the demodulation conversion table selection / transfer unit 189.

  In the next step ST38, demodulation is performed from the head of the modulated sync frame data 106 in the demodulation circuit 152 using the detection timing in step ST35 and the conversion table selection information 196 obtained in step ST36. At this time, as shown in FIG. 14A, FIG. 14B, and FIG. 15A, the data is demodulated from the “modulated sync frame position identification code 125” at the head of the data area 107 after modulation.

  Next, in step ST39, the content of the demodulated sync frame position identification code 123 is interpreted in the sync frame position identification code content identification section 186, and the position of the sync frame data 106 is determined by the method shown in FIG. .

  In step ST40, it is determined whether the determined position is the position of the first sync frame data 106-1 in the physical sector. If they are different, the process returns to step ST34. If the determination result is yes, using the detection timing of step ST35, the Data ID 1-0 and IED 2-0 information existing at the head position of the first sync frame data 105-0 in the physical sector is replaced with the Data ID 1 part. It transfers to the IED part extraction part 171 (step ST41).

  Next, in step ST42, the error check unit 172 of the Data ID unit checks whether there is an error in the Data ID 1 information detected using the information of the IDE2.

  In step ST43, it is determined whether or not there is an error in Data ID 1. If there is an error, in step ST44, the ECC decoding circuit 162 extracts Data ID 1 after the error correction processing. If there is no error in step ST44, it is determined whether or not the scheduled track on the information storage medium 9 is being traced. If the scheduled track is being traced, information reproduction from the information storage medium 9 is started (step ST46).

  The amount of track deviation on the information storage medium 9 is calculated in the control unit 143 from the difference value between the value of Data ID 1 of the reproduction result in Step ST46 and the Data ID 1 of the sector scheduled to start reproduction (Step ST47). .

  As described above, according to the present invention, “the synchronization code is divided into codes having a plurality of contents”. That is, information is recorded on the information storage medium in the first recording unit (physical sector 5), and a plurality of synchronization codes are arranged in the first recording unit. The synchronization code has a fixed code area (111) common in the plurality of synchronization codes and a variable code area (112, 113) that differs between at least two synchronization codes, and the fixed code area (121). Is recorded with a synchronization position detection code (121), and at least one of a conversion table selection code (122) and a sync frame position identification code (123) at the time of modulation is recorded in the variable code area (112, 113). Is recorded.

  As a result, compared with the conventional DVD that needs to detect the synchronization code by 32 types of pattern matching with respect to the 32 types of synchronization code patterns, in the present invention, only one type of code pattern for detecting the synchronization position in the fixed code area is used. The synchronization code can be detected simply by detecting the. Therefore, the detection of the synchronization code is very simple and easy and can be performed at high speed. In the present invention, since the variable code area is also divided into conversion table selection code and sync frame position identification code, conversion table selection information and sync frame position information can be extracted easily and at high speed. As a result, it is possible to increase the reproduction processing speed for the data recorded on the information storage medium (because it is easy to extract various codes) and to reduce the price of the information reproduction apparatus or the information recording / reproduction apparatus.

Further, according to the present invention, “the pattern for detecting only two“ 0 ”s is included in the synchronization position detection code”. That is, the user information is recorded on the information storage medium in the first recording unit (physical sector 5) after being modulated according to the modulation rule of (d, k; m, n). Also, a plurality of synchronization codes are arranged in the first recording unit, and the synchronization code is a fixed code area (111) common in the plurality of synchronization codes and a variable code area (different between at least two synchronization codes ( 112, 113). In the fixed code area (121), a synchronization position detection code (121) is recorded,
Further, the synchronization position detection code (121) includes a combination pattern of a pattern in which k + 2 “0” s are continuous and a pattern in which two “0s” are continuous.

  Thus, when the modulated user information is recorded on the information storage medium according to the modulation rule of (d, k; m, n), “0” that cannot exist in the modulated user information is k + 2. By adopting the “continuous pattern” as the synchronization position detection code, it becomes easy to identify the synchronization code and the modulated user information data. However, when the number of consecutive “0” s increases, the PLL (Phase Lock Loop) in the information reproducing apparatus is easily disconnected. For this reason, the PLL shift can be corrected at high speed by arranging a pattern in which only two “0” s follow immediately after “a pattern in which“ 0 ”is k + 2 consecutive”.

  In addition, when the modulated bit length is shortened with the aim of higher density and PRML is used in the data reproduction system with “d = 1”, the reproduction signal amplitude from a place where only “0” is one is very large. Small and stable binarization is impossible. Therefore, a pattern in which two “0” s continue in succession is arranged.

  As a result, (1) the amplitude of the reproduced signal from this position is large to some extent, and the binarized signal is stabilized (detectable with high accuracy). (2) It becomes possible to correct the phase shift amount of the PLL caused by “0” continuing for a long time at high speed.

  In the apparatus of the present invention, it is also easy to monitor the arrangement order of the synchronization codes and to provide an abnormality detection function such as track off.

  FIG. 43 shows an example thereof. This can also be performed by an algorithm provided in the control unit 143. In step ST61, an instruction for the range to be reproduced from the information recording medium is received by the interface by an external operation input or control input. Then, according to the flow shown in FIG. 40 or 41, access to the reproduction start position on the information recording medium is executed, and data reproduction is started (step ST62). Next, continuous reproduction is executed according to the procedure shown in FIG. 39 (step ST63). Next, in the control unit 143, the continuation combination of the synchronization code 110 scheduled to be detected next is predicted (step ST64). The history information of the synchronization code 110 is read by the method according to the flow of FIG. 42 and compared with the combination predicted at step ST64 (step ST66). Here, if the comparison and history information match the predicted combination, it is determined that the scheduled track on the information storage medium is being traced, and the process returns to step ST63. If not, the process returns to step ST62.

  As a prediction content of a synchronization code to be reproduced next, there is a method of predicting frame information, that is, a method of predicting a combination of codes indicating a frame position.

  The present invention is not limited to the above embodiment. It has been described that the content of the synchronization code, in particular, the fixed area (synchronization position detection code) is always handled by the recording / reproducing apparatus with the same content. However, as if there were a recording device and a playback device, a plurality of types of synchronization position detection codes may be switched and used. For example, the recording / reproducing apparatus may be provided with a default setting function and a selection setting function for the synchronization position detection code so that only a specific user can select the synchronization position detection code. Normally, the default synchronization position detection code is used. In this way, since only a specific user knows the used synchronization position detection code, reproduction information can be obtained.

Explanatory drawing of the component of the sync frame data based on this invention. Explanatory drawing which shows the example of the data structure when the synchronization code is added to the sync frame data, and the content of the synchronization code. Explanatory drawing which shows the recording system of the information recording / reproducing apparatus concerning this invention. Explanatory drawing which shows the reproduction | regeneration system of the information recording / reproducing apparatus concerning this invention. Explanatory drawing shown in order to demonstrate the structure of physical sector data which is data concerning this invention. Explanatory drawing which shows the relationship between the said physical sector data and an ECC block. Explanatory drawing which shows the relationship between the said physical sector data and an ECC block. Explanatory drawing which shows the relationship between the said physical sector data and an information recording medium. Explanatory drawing which shows the structure of the synchronous code production | generation / addition part of the information recording / reproducing apparatus concerning this invention. Explanatory drawing which shows the structure around the synchronous code position detection part of the information recording / reproducing apparatus concerning this invention. Explanatory drawing of the code | cord | chord for a synchronous code position detection in this invention. Explanatory drawing which shows the example of the structure of the synchronous code which concerns on this invention. Explanatory drawing which shows the other example of the structure of the synchronous code which concerns on this invention. Explanatory drawing which shows the further another example of the structure of the synchronous code based on this invention. Explanatory drawing which shows the other example of the structure of the synchronous code concerning this invention. Explanatory drawing which shows the further another example of the structure of the synchronous code based on this invention. Explanatory drawing which shows the other example of the structure of the synchronous code concerning this invention. Explanatory drawing which shows the further another example of the structure of the synchronous code based on this invention. Explanatory drawing which shows the other example of the structure of the synchronous code concerning this invention. Explanatory drawing which shows the further another example of the structure of the synchronous code based on this invention. Explanatory drawing which shows the other example of the structure of the synchronous code concerning this invention. Explanatory drawing which shows the further another example of the structure of the synchronous code based on this invention. Explanatory drawing which shows the example of the concrete bit pattern of the synchronous code based on this invention. Explanatory drawing which shows the other example of the concrete bit pattern of the synchronous code based on this invention. Explanatory drawing which shows the further another example of the specific bit pattern of the synchronous code based on this invention. Explanatory drawing which shows the other example of the concrete bit pattern of the synchronous code based on this invention. Explanatory drawing which shows the example of the arrangement | sequence relationship between the synchronous code concerning this invention, and the sync frame data after modulation | alteration. Explanatory drawing which shows the other example of the arrangement | sequence relationship of the synchronous code concerning this invention, and the sync frame data after modulation | alteration. Explanatory drawing which shows the further another example of the arrangement | sequence relationship between the synchronous code which concerns on this invention, and the sync frame data after modulation | alteration. Explanatory drawing which shows the other example of the arrangement | sequence relationship between the synchronous code which concerns on this invention, and the sync frame data after modulation | alteration. Explanatory drawing which shows the further another example of the arrangement | sequence relationship between the synchronous code which concerns on this invention, and the sync frame data after modulation | alteration. Explanatory drawing which shows the other example of the arrangement | sequence relationship between the synchronous code which concerns on this invention, and the sync frame data after modulation | alteration. Explanatory drawing which shows the further another example of the arrangement | sequence relationship between the synchronous code which concerns on this invention, and the sync frame data after modulation | alteration. Explanatory drawing which shows the other example of the arrangement | sequence relationship of the synchronous code concerning this invention, and the sync frame data after modulation | alteration. Explanatory drawing which shows the further another example of the arrangement | sequence relationship between the synchronous code concerning this invention, and the sync frame data after modulation | alteration. Explanatory drawing shown in order to demonstrate the method of calculating | requiring the sync frame position in 1 physical sector from the arrangement | sequence order of the sync frame position identification code in the synchronous code based on this invention. The flowchart shown in order to demonstrate the data conversion process at the time of employ | adopting a synchronous code as shown in FIGS. The flowchart shown in order to demonstrate the data conversion process at the time of employ | adopting a synchronous code as shown in FIGS. The flowchart shown in order to demonstrate the data conversion process when reproducing | regenerating information simply in the apparatus of this invention. The flowchart shown in order to demonstrate the control operation | movement when employ | adopting a synchronous code as shown in FIGS. 11-13 and accessing to the predetermined position of an information recording medium. The flowchart shown in order to demonstrate the control operation | movement when employ | adopting the synchronous code as shown in FIGS. 14-19 and accessing to the predetermined position of an information recording medium. 6 is a flowchart showing a method for determining a sync frame in a physical sector from the arrangement order of a plurality of synchronization codes in the information recording / reproducing apparatus according to the present invention. The flowchart shown in order to demonstrate the abnormality detection method, such as track | truck out from the arrangement | sequence order of several synchronous code in the information recording / reproducing apparatus which concerns on this invention.

Explanation of symbols

103-0, 103-1, 103-30, 103-31 ... Logical sector information, 105-0 to 105-3, 105-23 to 105-25 ... Sync frame data, 110-0 to 110-3, 110- 23 to 110-25 ... synchronization code, 122 ... conversion table selection code during modulation, 121 ... synchronization position detection code, 123 ... sync frame position identification code, 124 ... polarity reversal pattern for DC suppression, 130 ... PR equalization Circuit: 136: Code generation unit for sync frame position identification, 141: Information recording / playback unit, 142: Interface unit, 143: Control unit, 145: Synchronization code position extraction unit, 146: Synchronization code generation / addition unit, 150: Modulation Temporary storage unit for post-data and modulation related information, 151... Modulation circuit, 152... Demodulation circuit, 153. 154 ... Demodulation conversion table recording unit, 155 ... Schmitt trigger binarization circuit, main unit 156 ... Viterbi decoder, 157 ... scramble circuit, 159 ... descramble circuit, 160 ... reference clock generation circuit, 162 ... coding with ECC Circuit, 165... Data ID generation unit, 167... CPR_MAI data generation unit, 168... Data ID, IED, CPR_MAI, EDC addition unit, 170... Shift register circuit, 171. Circuit, 175... Memory unit, 173... Logical sector information extraction unit.

Claims (5)

One ECC block is divided into first and second small ECC blocks,
The first and second small ECC blocks are included in a group of sectors,
The first and second small ECC blocks respectively generate first and second PO information for error correction,
When the plurality of sectors are recorded in each sector of a recording track, a synchronization code and user data are included in the plurality of sectors.
A part of the first PO information generated by the first small ECC block and a part of the second PO information generated by the second small ECC block are connected in the sector. Are set to be alternately arranged,
The user data is modulated according to a (d, k; m, n) modulation rule, and d = 1 and is reproduced by a PRML reproduction system,
Each sector is composed of a plurality of sync frames, and each of the plurality of sync frames includes the synchronization code and user data.
There are a plurality of types of synchronization codes, and each sync code arrangement position in the sector can be identified by the arrangement pattern of each synchronization code in one sector. Are used in the first sync frame that constitutes each sector.
The number of bits of each synchronization code is 24 bits, and a common fixed code and variable code are arranged in each synchronization code,
The fixed code is a synchronization position detection code, and the bit sequence includes a portion in which 12 is followed by 0, 1 is placed next, 2 is followed by 0, and 1 is placed next,
The variable code uses at least “00100 *”, “00010 *”, or “00 * 010” (where * is a direct current suppression bit) as the pattern type. One ECC block is divided into first and second small ECC blocks,
The first and second small ECC blocks are included in a group of sectors,
The first and second small ECC blocks respectively generate first and second PO information for error correction,
A synchronization code and user data are included in the plurality of sectors.
A part of the first PO information generated by the first small ECC block and a part of the second PO information generated by the second small ECC block are connected in the sector. Are set to be alternately arranged,
The user data is modulated according to a (d, k; m, n) modulation rule, and d = 1 and is reproduced by a PRML reproduction system,
Each sector is composed of a plurality of sync frames, and each of the plurality of sync frames includes the synchronization code and user data.
There are a plurality of types of synchronization codes, and each sync code arrangement position in the sector can be identified by the arrangement pattern of each synchronization code in one sector. Are used in the first sync frame that constitutes each sector.
The number of bits of each synchronization code is 24 bits, and a common fixed code and variable code are arranged in each synchronization code,
The fixed code is a synchronization position detection code, and the bit sequence includes a portion in which 12 is followed by 0, 1 is placed next, 2 is followed by 0, and 1 is placed next,
The variable code uses at least “00100 *”, “00010 *”, or “00 * 010” (where * is a DC suppression bit) as a pattern type. In the information storage medium, one ECC block is divided into first and second small ECC blocks,
The first and second small ECC blocks are included in a group of sectors,
The first and second small ECC blocks respectively generate first and second PO information for error correction,
When the plurality of sectors are recorded in each sector of a recording track, a synchronization code and user data are included in the plurality of sectors.
A part of the first PO information generated by the first small ECC block and a part of the second PO information generated by the second small ECC block are connected in the sector. Are set to be alternately arranged,
The user data is modulated according to a (d, k; m, n) modulation rule, and d = 1 and is reproduced by a PRML reproduction system,
Each sector is composed of a plurality of sync frames, and each of the plurality of sync frames includes the synchronization code and user data.
There are a plurality of types of synchronization codes, and each sync code arrangement position in the sector can be identified by the arrangement pattern of each synchronization code in one sector. Are used in the first sync frame that constitutes each sector.
The number of bits of each synchronization code is 24 bits, and a common fixed code and variable code are arranged in each synchronization code,
The fixed code is a synchronization position detection code, and the bit sequence includes a portion in which 12 is followed by 0, 1 is placed next, 2 is followed by 0, and 1 is placed next,
The variable code uses at least “00100 *”, “00010 *”, or “00 * 010” (where * is a DC suppression bit) as the pattern type,
A method of reproducing the information of the first data unit read from the information storage medium,
The data of the first data unit is taken into a shift register, the pattern of the synchronization position detection code is detected by pattern comparison,
An information reproduction method in which a sync frame position identification code representing the position of the sync frame is detected by combining data before or after the synchronization position detection code at the detection timing. In the information storage medium, one ECC block is divided into first and second small ECC blocks,
The first and second small ECC blocks are included in a group of sectors,
The first and second small ECC blocks respectively generate first and second PO information for error correction,
When the plurality of sectors are recorded in each sector of a recording track, a synchronization code and user data are included in the plurality of sectors.
A part of the first PO information generated by the first small ECC block and a part of the second PO information generated by the second small ECC block are connected in the sector. Are set to be alternately arranged,
The user data is modulated according to a (d, k; m, n) modulation rule, and d = 1 and is reproduced by a PRML reproduction system,
Each sector is composed of a plurality of sync frames, and each of the plurality of sync frames includes the synchronization code and user data.
There are a plurality of types of synchronization codes, and each sync code arrangement position in the sector can be identified by the arrangement pattern of each synchronization code in one sector. Are used in the first sync frame that constitutes each sector.
The number of bits of each synchronization code is 24 bits, and a common fixed code and variable code are arranged in each synchronization code,
The fixed code is a synchronization position detection code, and the bit sequence includes a portion in which 12 is followed by 0, 1 is placed next, 2 is followed by 0, and 1 is placed next,
The variable code uses at least “00100 *”, “00010 *”, or “00 * 010” (where * is a DC suppression bit) as the pattern type,
A playback device that plays back the information of the first data unit read from the information storage medium,
Means for capturing data of the first data unit into a shift register, and detecting a pattern of the synchronization position detection code by pattern comparison;
An information reproducing apparatus comprising: means for detecting a sync frame position identification code representing a position of the sync frame by combining data before or after the synchronization position detection code at the detection timing. A method of recording information on an information storage medium as a first data unit of a plurality of sync frames including user data and a synchronization code,
One ECC block is divided into first and second small ECC blocks,
The first and second small ECC blocks are included in a group of sectors,
The first and second small ECC blocks respectively generate first and second PO information for error correction,
When the plurality of sectors are recorded in each sector of the recording track, the synchronization code and user data are included in the plurality of sectors.
A part of the first PO information generated by the first small ECC block and a part of the second PO information generated by the second small ECC block are connected in the sector. Are set to be alternately arranged,
The user data is modulated according to a (d, k; m, n) modulation rule, and d = 1 and is reproduced by a PRML reproduction system,
Each sector is composed of a plurality of sync frames, and each of the plurality of sync frames includes the synchronization code and user data.
There are a plurality of types of synchronization codes, and each sync code arrangement position in the sector can be identified by the arrangement pattern of each synchronization code in one sector. Are used in the first sync frame that constitutes each sector.
The number of bits of each synchronization code is 24 bits, and a common fixed code and variable code are arranged in each synchronization code,
The fixed code is a synchronization position detection code, and the bit sequence includes a portion in which 12 is followed by 0, 1 is placed next, 2 is followed by 0, and 1 is placed next,
The variable code uses at least “00100 *”, “00010 *”, or “00 * 010” (where * is a DC suppression bit) as a pattern type.

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