JP4108875B2

JP4108875B2 - Semiconductor circuit

Info

Publication number: JP4108875B2
Application number: JP13371999A
Authority: JP
Inventors: 枢山崎; 紀之本間; 博昭南部; 一男金谷; 武志楠
Original assignee: Renesas Technology Corp
Current assignee: Renesas Technology Corp
Priority date: 1999-05-14
Filing date: 1999-05-14
Publication date: 2008-06-25
Anticipated expiration: 2019-05-14
Also published as: JP2000322888A

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体回路に係り、特にその相補信号線プリチャージ回路に関する。
【０００２】
【従来の技術】
図１は従来例を示す図であり、従来の半導体回路の構成を示す。相補信号線対ＳＰ／ＳＮをプリチャージする相補信号線プリチャージ回路、ＳＰ／ＳＮの一方を放電する放電回路で構成され、プリチャージ回路はＰＭＯＳトランジスタＭＰ１〜ＭＰ３で構成される。なお、ＭＰ１〜ＭＰ３のゲート幅はそれぞれＷ１〜Ｗ３であり、Ｗ３＝Ｗ２＝Ｗ１である。ＳＰにはＳＮ以外に対するＳＰの配線容量とＳＰに接続する素子（ＭＰ１、ＭＰ３、放電回路を構成する素子など）の寄生容量との合成容量である容量Ｃ１が等価的に接続されていると見なせ、ＳＮにはＳＰ以外に対するＳＮの配線容量とＳＮに接続する素子（ＭＰ２、ＭＰ３、放電回路を構成する素子など）の寄生容量との合成容量である容量Ｃ２が等価的に接続されているとみなせ、Ｃ２の容量値はＣ１と等しいと見なせ（Ｃ２＝Ｃ１）、ＳＰとＳＮとの間には配線間結合容量である容量Ｃ３が等価的に接続されていると見なせる。なお、Ｃ１およびＣ２の他端は電源ＶＳＳとなっているが、電源ＶＤＤ、他の電源、ＳＰ／ＳＮ以外の低インピーダンスで電位一定の信号線でも同様である。
【０００３】
以上の構成において、図１の従来回路の動作を図２を用いて説明する。クロック信号ＣＫがＶＤＤの電位に等しい判定期間（ｔ２〜ｔ１０）で、ＳＰは放電回路により放電されＶＤＤよりΔＶＬ低い電位になる。この時、ＳＮはＣ３による結合ノイズによりＶＤＤよりΔＶＤ低い電位になる。ＣＫがＶＳＳの電位に等しいプリチャージ期間（ｔ１０〜ｔ１８）で、ＳＰ／ＳＮはＭＰ１〜ＭＰ３によってプリチャージされ、ＶＤＤの電位に等しくなる。ここで、プリチャージ開始からＶＤＤとＳＰとの電位差がある電位差ΔＶＰに達するまでの時間をプルアップ時間（ｔ１０〜ｔ１６）、プリチャージ開始からＳＮとＳＰとの電位差がΔＶＰに達するまでの時間をイコライズ時間（ｔ１０〜ｔ１３）、プルアップ時間とイコライズ時間とで大きい方をリカバリ時間と定義する。図２の場合、プルアップ時間の方が大きいので、リカバリ時間はプルアップ時間と等しくなる。
【０００４】
【発明が解決しようとする課題】
半導体回路の高速化は動作サイクル時間の短縮によって達成できる。図２において半導体回路の動作サイクル時間（時刻ｔ２〜ｔ１８）は判定期間（時刻ｔ２〜ｔ１０）とプリチャージ期間（時刻ｔ１０〜ｔ１８）とにより決まる。したがって、動作サイクル時間を短縮するには判定期間、プリチャージ期間の少なくとも一方を短縮する必要がある。ここで、プリチャージ期間を短縮する場合について考える。プリチャージ期間はリカバリ時間（ｔ１０〜ｔ１６）とマージン（ｔ１６〜ｔ１８）とから決まる。マージンは電源、温度、回路を構成する素子の特性等がばらついても確実にプリチャージできるようにするために短縮できない。したがって、プリチャージ期間を短縮するためにはＳＰ／ＳＮのリカバリ時間を短縮する必要がある。
【０００５】
しかしながら、従来の半導体回路では、リカバリ時間を短縮するためＣ１に対するＣ３の容量の比である結合容量比ｋｃ（＝Ｃ３／Ｃ１）に関係なく、ＭＰ１およびＭＰ２に対するＭＰ３のコンダクタンスの比、すなわちＷ１およびＷ２（＝Ｗ１）に対するＷ３の比ｋｇ（＝Ｗ３／Ｗ１）を１と一定にしたままＷ１〜Ｗ３の和ＷＴを大きくしていた。しかし、ＷＴを大きくするとＣＫを駆動する駆動回路の負荷が大きくなるためプリチャージ期間の開始が遅くなる、すなわち判定期間が長くなり動作サイクル時間としては逆に長くなる場合があるという問題があった。
【０００６】
本発明の目的は、相補信号線対をプリチャージする相補信号線プリチャージ回路と前記相補信号線対の一方を放電する放電回路とを有し、判定時に相補信号線対の一方の信号線が放電される際に他方の信号線で結合ノイズによる電位降下が起きる半導体回路において、判定期間を長くすることなくプリチャージ期間を短縮し、動作サイクル時間を短縮することにある。
【０００７】
【課題を解決するための手段】
上記目的を達成するため、ＣＫを駆動する駆動回路の負荷を一定、すなわちＷ１〜Ｗ３の和ＷＴを一定にして、コンダクタンス比ｋｇを結合容量比ｋｃに対してＳＰ／ＳＮのリカバリ時間が最短になるとみなせる最適範囲に設定する。
【０００８】
【発明の実施の形態】
図３は、本発明の第１の実施例を示す図であり、図１に示す従来の半導体回路と回路構成は同じであるが、唯一異なる点はコンダクタンス比ｋｇ（＝Ｗ３／Ｗ１）が１ではなく、結合容量比ｋｃに対してＳＰ／ＳＮのリカバリ時間が最短になるとみなせる最適範囲の値をとることである。
【０００９】
以上の構成におけるｋｃとｋｇの最適範囲との関係式を図３の等価回路である図４を用いて導き出す。相補信号線プリチャージ回路の等価回路はコンダクタンスＧ１〜Ｇ３、スイッチＳＷ１、ＳＷ２で構成される。Ｇ１〜Ｇ３はそれぞれＭＰ１〜ＭＰ３のゲート電位がＶＳＳの電位に等しい時の等価素子で、ＳＷ１、ＳＷ２は同期して動作するスイッチで、それぞれが開くと判定状態で、それぞれが閉じるとプリチャージ状態になる。一方、放電回路の等価回路はコンダクタンスＧ４、Ｇ５、スイッチＳＷ３、ＳＷ４で構成される。Ｇ４、Ｇ５は相補信号線ＳＰ、ＳＮをそれぞれ放電する素子の等価素子で、ＳＷ３、ＳＷ４は非活性時には両方が開いており、活性時には一方が閉じる。Ｃ１〜Ｃ３は容量で、それぞれ図３のＣ１〜Ｃ３に相当する。ｖ１、ｖ２はそれぞれＶＳＳに対するＳＰ、ＳＮの電位で、ｖ３はＳＰに対するＳＮの電位である。図４の回路は図５に示すように動作し、各時刻における関係式からｋｃとｋｇの最適範囲の関係式を導出する過程を以下に示す。
【００１０】
時刻ｔ＜０は判定期間でＳＷ１、ＳＷ２はそれぞれ開いており、ｔ＜ｔｄ１の時、つまり放電前のｖ１〜ｖ３は数１〜数３で表せる。
【００１１】
ｖ１（ｔ＜ｔｄ１）＝ＶＤＤ−ＶＳＳ数１
ｖ２（ｔ＜ｔｄ１）＝ＶＤＤ−ＶＳＳ数２
ｖ３（ｔ＜ｔｄ１）＝０数３
時刻ｔ＝ｔｄ１の時にＳＷ３が閉じ放電回路は活性になりＳＰは放電され、ｔ＝ｔｄ２の時にＳＷ３が開き放電回路は非活性になり放電が完了する。ｔｄ２≦ｔ＜０の時、つまり放電後のｖ１〜ｖ３は数４〜数６で表せる。
【００１２】
ｖ１（ｔｄ２≦ｔ＜０）＝ＶＤＤ−ΔＶＬ−ＶＳＳ数４
ｖ２（ｔｄ２≦ｔ＜０）＝ＶＤＤ−ΔＶＤ−ＶＳＳ数５
ｖ３（ｔｄ２≦ｔ＜０）＝ΔＶＬ−ΔＶＤ数６
ここで、放電前（ｔ＜ｔｄ１）と放電後（ｔｄ２≦ｔ＜０）とでＣ２、Ｃ３に蓄えられている電荷の和は不変であることから、数７が成り立つ。
【００１３】
Ｃ２・ｖ２（ｔ＜ｔｄ１）＋Ｃ３・ｖ３（ｔ＜ｔｄ１）
＝Ｃ２・ｖ２（ｔｄ２≦ｔ＜０）＋Ｃ３・ｖ３（ｔｄ２≦ｔ＜０）数７
時刻ｔ≧０はプリチャージ期間でｔ＝０の時にＳＷ１、ＳＷ２がそれぞれ閉じるとプリチャージが開始し、ＳＰ／ＳＮはＧ１〜Ｇ３によってプリチャージされＶＤＤの電位に等しくなる。ここで、プルアップ時間ｔｕをｔ＝０からｖ１がＶＤＤ−ΔＶＰ−ＶＳＳに等しくなるまでの時間、イコライズ時間ｔｅをｔ＝０からｖ３がΔＶＰに等しくなるまでの時間と定義する。なお、ΔＶＰはプルアップおよびイコライズが完了したと判断する基準である。また、ｔ≧０の過渡応答については数８〜数１６の節点方程式が成り立つ。
【００１４】
Ｃ１・ｄｖ１（ｔ）／ｄｔ＝ｉ１（ｔ）数８
Ｃ２・ｄｖ２（ｔ）／ｄｔ＝ｉ２（ｔ）数９
Ｃ３・ｄｖ３（ｔ）／ｄｔ＝ｉ３（ｔ）数１０
Ｇ１・（ＶＤＤ−ＶＳＳ−ｖ１（ｔ））＝ｉ４（ｔ）数１１
Ｇ２・（ＶＤＤ−ＶＳＳ−ｖ２（ｔ））＝ｉ５（ｔ）数１２
Ｇ３・ｖ３（ｔ）＝ｉ６（ｔ）数１３
ｖ３（ｔ）＝ｖ２（ｔ）−ｖ１（ｔ）数１４
ｉ１（ｔ）＝ｉ３（ｔ）＋ｉ４（ｔ）＋ｉ６（ｔ）数１５
ｉ５（ｔ）＝ｉ２（ｔ）＋ｉ３（ｔ）＋ｉ６（ｔ）数１６
さらに、数１〜数１６の式の変数および定数の間には数１７〜数２４の関係式が成り立つとする。なお、数１７は図３の回路においてＷ１〜Ｗ３の和は一定にするという条件式であり、数２３はΔＶＬがＶＤＤ−ＶＳＳのｋｖ倍であることを示しており、数２４はΔＶＰがΔＶＬのｋｐ倍であることを示している。
【００１５】
ＧＴ＝Ｇ１＋Ｇ２＋Ｇ３（ＧＴは定数）数１７
Ｇ２＝Ｇ１＝Ｇ数１８
Ｇ３＝ｋｇ・Ｇ１＝ｋｇ・Ｇ（ｋｇ≧０）数１９
Ｃ２＝Ｃ１＝Ｃ（Ｃは定数）数２０
Ｃ３＝ｋｃ・Ｃ１＝ｋｃ・Ｃ（ｋｃ≧０）数２１
ＶＤＤ−ＶＳＳ＝Ｖ（Ｖは定数）数２２
ΔＶＬ＝ｋｖ・（ＶＤＤ−ＶＳＳ）（０＜ｋｖ≦１）数２３
ΔＶＰ＝ｋｐ・ΔＶＬ（０＜ｋｐ＜１）数２４
数１〜数２４を解くと、ｖ１（ｔ）〜ｖ３（ｔ）は数２５〜数３１で表せる。
【００１６】

プルアップ時間ｔｕ、イコライズ時間ｔｅについてはそれぞれ数３２、数３３の関係式が成り立ち、数２２〜数３１を用いると数３４、数３５を得る。なお、数３４、数３５はｋｖ、Ｖに依存しない。したがって、数３４、数３５においてｋｐを設定し定数Ｃ、ＧＴを与えると、任意のｋｃ、ｋｇに対するｔｕ、ｔｅを求めることができる。また、リカバリ時間はｔｕ、ｔｅの大きい方で決まるので、任意のｋｃに対してリカバリ時間が最短になるｋｇの最適値を求めることもできる。また、逆に任意のリカバリ時間からｋｇの値を求めることもできる。なお、ｋｇの最適値はｋｐを設定すればＣ、ＧＴに依存せずｋｃだけに対して決まる。以上により、図４の回路におけるｋｃとｋｇの最適範囲の関係式を求めることができる。
【００１７】
ｖ１（ｔｕ）＝ＶＤＤ−ΔＶＰ−ＶＳＳ数３２
ｖ３（ｔｅ）＝ΔＶＰ数３３
２・ｋｐ・（１＋ｋｃ）
＝（１＋２・ｋｃ）・ｅｘｐ（α・ｔｕ）＋ｅｘｐ（β・ｔｕ）数３４
ｋｐ・（１＋ｋｃ）＝ｅｘｐ（β・ｔｅ）数３５
図６は図３の回路のシミュレーション結果で、ＶＤＤ−ＶＳＳ＝１．８Ｖ、ΔＶＬ＝１．８Ｖ、ΔＶＰ＝５０ｍＶ、Ｃ＝１ｐＦ、ＭＰ１〜ＭＰ３のゲート幅の和ＷＴをＷＴ＝１５ｕｍと一定にし、ｋｃ＝０．０５、０．２０、０．８０に対してｋｇを変化させた時のｔｕ、ｔｅを示している。図６からリカバリ時間が最短になるｋｇの最適値はｋｃ＝０．０５、０．２０、０．８０に対してそれぞれｋｇ＝０．２６、０．３３、０．６１になる。なお、ｋｇの最適値はＣ、ＷＴを変えても不変である。
【００１８】
図７は図４の回路の解析結果で数３４、数３５の式においてｋｐ（＝ΔＶＰ／ΔＶＬ）＝１／３６、Ｃ＝１ｐＦ、ＧＴ＝０．００２Ｓとし、ｋｃ＝０．０５、０．２０、０．８０に対してｋｇを変化させた時のｔｕ、ｔｅを示している。図７からリカバリ時間が最短になるｋｇの最適値はｋｃ＝０．０５、０．２０、０．８０に対してそれぞれｋｇ＝０．２１、０．２９、０．５２になる。なお、ｋｇの最適値はＣ、ＧＴ、ｋｖを変えても不変である。
【００１９】
図８は図３の回路、図４の回路のそれぞれの場合についてｋｃに対するｋｇの最適値ｋｇ（０％）、ｋｇ＝ｋｇ（０％）の時よりリカバリ時間が１％大きくなる時のｋｇの値ｋｇ（１％＋）、ｋｇ（１％−）を図６、図７から求めた結果で、ｋｃ＝０．１０、０．４０の場合のデータも追加している。なお、ｋｇ（１％−）＜ｋｇ（０％）＜ｋｇ（１％＋）である。また、回帰分析によりｋｃに対するｋｇ（０％）、ｋｇ（１％＋）、ｋｇ（１％−）の関係式を求めた。図３の回路における関係式をそれぞれ数３６〜数３８に、図４の回路における関係式をそれぞれ数３９〜数４１に示す。
【００２０】
ｋｇ（０％）＝０．４７・ｋｃ＋０．２３数３６
ｋｇ（１％＋）＝０．４６・ｋｃ＋０．３８数３７
ｋｇ（１％−）＝０．５９・ｋｃ＋０．１０数３８
ｋｇ（０％）＝０．４１・ｋｃ＋０．２０数３９
ｋｇ（１％＋）＝０．４７・ｋｃ＋０．３１数４０
ｋｇ（１％−）＝０．４９・ｋｃ＋０．０８数４１
これから、図４の回路においてリカバリ時間が最短になるとみなせるｋｇの最適範囲は数４０、数４１を用いて数４２で表せる。また、図３の回路のｋｇ（０％）、ｋｇ（１％−）は数４２に含まれることがわかる。したがって、ｋｖ（＝ΔＶＬ／（ＶＤＤ−ＶＳＳ））＝１の時数４２は図３の回路においてもリカバリ時間が最短になるとみなせるｋｇの最適範囲になる。
【００２１】
０．４９・ｋｃ＋０．０８≦ｋｇ≦０．４７・ｋｃ＋０．３１数４２
図９は図８と同様にして求めた結果で、ＶＤＤ−ＶＳＳ＝１．８Ｖ、ΔＶＬ＝０．１８Ｖ、ΔＶＰ＝５ｍＶとした場合を示している。図３の回路における関係式をそれぞれ数４３〜数４５に示す。図４の回路における関係式はｋｖに依存しないので数３９〜数４１と同じである。
【００２２】
ｋｇ（０％）＝０．４１・ｋｃ＋０．２０数４３
ｋｇ（１％＋）＝０．４７・ｋｃ＋０．３１数４４
ｋｇ（１％−）＝０．４９・ｋｃ＋０．０８数４５
これから、数４３〜数４５はそれぞれ数３９〜数４１に一致することがわかる。したがって、ｋｖ＝０．１の時も数４２は図３の回路においてリカバリ時間が最短になるとみなせるｋｇの最適範囲になる。
【００２３】
以上のことから、図４の回路同様、図３の回路ではｋｖに関係なく数４２がリカバリ時間が最短になるとみなせるｋｇの最適範囲になる。
【００２４】
以上述べてきたように、Ｗ１〜Ｗ３の和ＷＴが一定の下でＷ１〜Ｗ３を数４２を満たすｋｇで決めることによりＳＰ／ＳＮのリカバリ時間をほぼ最短にでき、判定期間を長くすることなくプリチャージ期間を短縮し、動作サイクル時間を短縮できる。
【００２５】
図１０は、本発明の第２の実施例を示す図で、図３において放電回路を差動入力形のＮＭＯＳ論理回路で構成した場合である。ＩＰ１／ＩＮ１〜ＩＰｎ／ＩＮｎは相補論理入力対、ＳＰ／ＳＮは相補論理出力対が接続する相補信号線対である。ＳＰにはＳＮ以外に対するＳＰの配線容量とＳＰに接続する素子（ＭＰ１、ＭＰ３およびＮＭＯＳ論理回路を構成する素子）の寄生容量との合成容量である容量Ｃ１が等価的に接続しているとみなせ、ＳＮにはＳＰ以外に対するＳＮの配線容量とＳＮに接続する素子（ＭＰ２、ＭＰ３およびＮＭＯＳ論理回路を構成する素子）の寄生容量との合成容量である容量Ｃ２が等価的に接続しているとみなせ、Ｃ２の容量値はＣ１と等しいとみなせ（Ｃ２＝Ｃ１）、ＳＰとＳＮとの間に配線間結合容量である容量Ｃ３が等価的に接続されているとみなせ、
Ｃ３＝ｋｃ・Ｃ１である。なお、Ｃ１およびＣ２の他端はＶＳＳとなっているが、ＶＤＤ、他の電源、ＳＰ／ＳＮ以外の低インピーダンスで電位一定の信号線でも同様である。
【００２６】
以上の構成において、Ｗ１〜Ｗ３の和ＷＴが一定の下でＷ１〜Ｗ３を数４２を満たすｋｇで決めることによりＳＰ／ＳＮのリカバリ時間をほぼ最短にでき、判定期間を長くすることなくプリチャージ期間を短縮し、動作サイクル時間を短縮できる。
【００２７】
図１１は、図１０のＮＭＯＳ論理回路の構成例を示す図である。ＭＮＰ１／ＭＮＮ１〜ＭＮＰｎ／ＭＮＮｎはＮＭＯＳトランジスタである。ＩＰ１／ＩＮ１〜ＩＰｎ／ＩＮｎは相補論理入力対、ＳＰ／ＳＮは相補論理出力対でＳＰにはＩＰ１〜ＩＰｎのＮＯＲ論理信号が出力され、ＳＮにはＩＰ１〜ＩＰｎのＯＲ論理信号が出力される。
【００２８】
図１２は、本発明の第３の実施例を示す図で、半導体メモリ装置のビット線対に適用した場合を示している。ＭＣ［１、ｋ−１］〜ＭＣ［１、ｋ＋１］、ＭＣ［２、ｋ−１］〜ＭＣ［２、ｋ＋１］はメモリセル、ＷＬ１、ＷＬ２はワード線、ＢＬ［ｋ−１］／ＢＲ［ｋ−１］〜ＢＬ［ｋ＋１］／ＢＲ［ｋ＋１］はビット線対、ＰＣ［ｋ−１］〜ＰＣ［ｋ＋１］はビット線プリチャージ回路、ＣＫ［ｋ−１］〜ＣＫ［ｋ＋１］はビット線プリチャージ信号である。ビット線プリチャージ回路はＰＭＯＳトランジスタＭＰ１〜ＭＰ３で構成される。ＢＬ［ｋ］にはＢＲ［ｋ−１］、ＢＲ［ｋ］以外に対するＢＬ［ｋ］の配線容量と、ＢＬ［ｋ］に接続する素子（ＰＣ［ｋ］のＭＰ１、ＭＰ３、ＭＣ［１、ｋ］およびＭＣ［２、ｋ］内のそれぞれのＭＮ１など）の寄生容量との合成容量であるＣｂ１が等価的に接続されているとみなせる。ＢＲ［ｋ］にはＢＬ［ｋ］、ＢＬ［ｋ＋１］以外に対するＢＲ［ｋ］の配線容量と、ＢＲ［ｋ］に接続する素子（ＰＣ［ｋ］のＭＰ２、ＭＰ３、ＭＣ［１、ｋ］およびＭＣ［２、ｋ］内のそれぞれのＭＮ２など）の寄生容量との合成容量であるＣｂ２が等価的に接続されているとみなせ、Ｃｂ２はＣｂ１と等しいとみなせる（Ｃｂ２＝Ｃｂ１）。ＢＬ［ｋ］とＢＲ［ｋ］との間には配線間結合容量であるＣｂ３が等価的に接続されているとみなせる。ＢＲ［ｋ−１］とＢＬ［ｋ］との間には配線間結合容量であるＣｂ４が等価的に接続されているとみなせる。ＢＲ［ｋ］とＢＬ［ｋ＋１］との間には配線間結合容量であるＣｂ５が等価的に接続されているとみなせ、Ｃｂ５はＣｂ４と等しいとみなせる（Ｃｂ５＝Ｃｂ４）。なお、Ｃｂ１、Ｃｂ２の他端はＶＳＳとなっているが、ＶＤＤ、他の電源、ビット線以外の低インピーダンスで電位一定の信号線でも同様である。
【００２９】
以上の構成において、ＭＣ［１、ｋ］に対して読み出しを行う場合について説明する。最初ＣＫ［ｋ−１］〜ＣＫ［ｋ＋１］、ＷＬ１、ＷＬ２はＶＳＳの電位と等しく、ＢＬ［ｋ−１］／ＢＲ［ｋ−１］〜ＢＬ［ｋ＋１］／ＢＲ［ｋ＋１］は全てＶＤＤの電位と等しいプリチャージ状態にある。読み出し時になると、ＷＬ１、ＣＫ［ｋ］がＶＤＤの電位と等しくなり、ＢＬ［ｋ］／ＢＲ［ｋ］では判定状態になる。ただし、ＢＬ［ｋ−１］／ＢＲ［ｋ−１］、ＢＬ［ｋ＋１］／ＢＲ［ｋ＋１］ではＣＫ［ｋ−１］、ＣＫ［ｋ＋１］がＶＳＳの電位と等しいためプリチャージ状態である。次にＢＬ［ｋ］／ＢＲ［ｋ］で一方のビット線がＭＣ［１、ｋ］により放電され電位差が生じ読み出しが行われる。なお、この時他方のビット線は結合ノイズによりＶＤＤより低電位になる。読み出し終了後にはＣＫ［ｋ］、ＷＬ１はＶＳＳの電位と等しくなりプリチャージ状態になるため、ＢＬ［ｋ］／ＢＲ［ｋ］はＶＤＤの電位と等しくなる。
【００３０】
以上の構成および動作において、ＢＬ［ｋ］／ＢＲ［ｋ］は図３のＳＰ／ＳＮに相当し、ＰＣ［ｋ］は図３の相補信号線プリチャージ回路に相当し、ＣＫ［ｋ］は図３のＣＫに相当し、ＭＣ［１、ｋ］は図３の放電回路に相当する。また、Ｃｂ１＋Ｃｂ４は図３のＣ１に相当し、Ｃｂ２＋Ｃｂ５は図３のＣ２に相当し、Ｃｂ３は図３のＣ３に相当し、Ｃ２＝Ｃ１、ｋｃ＝Ｃ３／Ｃ１である。
【００３１】
したがって、ＭＰ１〜ＭＰ３のゲート幅の和ＷＴが一定の下で、ＭＰ１〜ＭＰ３のゲート幅Ｗ１〜Ｗ３を数４２を満たすｋｇで決めることにより、ＢＬ［ｋ］／ＢＲ［ｋ］のリカバリ時間をほぼ最短にでき、判定期間を長くすることなくプリチャージ期間を短縮し、半導体メモリ装置の動作サイクル時間を短縮できる。
【００３２】
図１３は、本発明の第４の実施例を示す図で、図１２の半導体メモリ装置の各ビット線対にビット線書き込み回路を設け、ビット線対に適用した場合を示している。ＷＣ［ｋ−１］〜ＷＣ［ｋ＋１］はビット線書き込み回路、ＹＷ［ｋ−１］〜ＹＷ［ｋ＋１］は書き込みＹ選択信号、ＤＩはデータ入力信号である。
【００３３】
なお、Ｃｂ１、Ｃｂ２にはＷＣ［ｋ］を構成しＢＬ［ｋ］、ＢＲ［ｋ］にそれぞれ接続する素子の寄生容量が含まれ、Ｃｂ２はＣｂ１と等しいとみなせる（Ｃｂ２＝Ｃｂ１）。
【００３４】
以上の構成において、ＭＣ［１、ｋ］に対して読み出しおよび書き込みを行う場合について説明する。最初ＣＫ［ｋ−１］〜ＣＫ［ｋ＋１］、ＷＬ１、ＷＬ２はＶＳＳの電位と等しく、ＢＬ［ｋ−１］／ＢＲ［ｋ−１］〜ＢＬ［ｋ＋１］／ＢＲ［ｋ＋１］は全てＶＤＤの電位と等しいプリチャージ状態にある。読み出し時および書き込み時になると、ＷＬ１、ＣＫ［ｋ］がＶＤＤの電位と等しくなり、ＢＬ［ｋ］／ＢＲ［ｋ］では判定状態になる。ただし、ＢＬ［ｋ−１］／ＢＲ［ｋ−１］、ＢＬ［ｋ＋１］／ＢＲ［ｋ＋１］ではＣＫ［ｋ−１］、ＣＫ［ｋ＋１］がＶＳＳの電位と等しいためプリチャージ状態である。次に、読み出し時にはＢＬ［ｋ］／ＢＲ［ｋ］で一方のビット線がＭＣ［１、ｋ］により放電され電位差が生じ読み出しが行われる。また、書き込み時にはＢＬ［ｋ］／ＢＲ［ｋ］の一方がＷＣ［ｋ］により放電され、ＭＣ［１、ｋ］に書き込みが行われる。なお、この時、読み出しおよび書き込みのいずれにおいても他方のビット線は結合ノイズによりＶＤＤより低電位になる。読み出し終了後および書き込み終了後にはＣＫ［ｋ］、ＷＬ１はＶＳＳの電位と等しくなりプリチャージ状態になるため、ＢＬ［ｋ］／ＢＲ［ｋ］はＶＤＤの電位と等しくなる。
【００３５】
以上の構成および動作において、ＢＬ［ｋ］／ＢＲ［ｋ］は図３のＳＰ／ＳＮに相当し、ＰＣ［ｋ］は図３の相補信号線プリチャージ回路に相当し、ＣＫ［ｋ］は図３のＣＫに相当し、読み出し時にはＭＣ［１、ｋ］、また書き込み時にはＷＣ［ｋ］は図３の放電回路に相当する。また、Ｃｂ１＋Ｃｂ４は図３のＣ１に相当し、Ｃｂ２＋Ｃｂ５は図３のＣ２に相当し、Ｃｂ３は図３のＣ３に相当し、Ｃ２＝Ｃ１、ｋｃ＝Ｃ３／Ｃ１である。したがって、ＭＰ１〜ＭＰ３のゲート幅の和ＷＴが一定の下で、ＭＰ１〜ＭＰ３のゲート幅Ｗ１〜Ｗ３を数４２を満たすｋｇで決めることにより、ＢＬ［ｋ］／ＢＲ［ｋ］のリカバリ時間をほぼ最短にでき、判定期間を長くすることなくプリチャージ期間を短縮し、半導体メモリ装置の動作サイクル時間を短縮できる。
【００３６】
図１４は、本発明の第５の実施例を示す図で、図１２、図１３のメモリセルの構成例でスタティック形の場合を示している。ＩＮＶ１、ＩＮＶ２はインバータで、ＭＮ１、ＭＮ２はＮＭＯＳトランジスタである。ＩＮＶ１、ＩＮＶ２はフリップフロップを構成している。メモリセルは、ＷＬがＶＳＳの電位と等しい非選択時にＢＬ／ＢＲをいずれも高インピーダンスにし、ＷＬがＶＤＤの電位と等しい選択時に記憶している情報に応じてＢＬ／ＢＲの一方を放電し他方を高インピーダンスにする。
【００３７】
図１５は、本発明の第６の実施例を示す図で、図１４のメモリセルの構成例を示している。ＭＮ１、ＭＮ２、ＭＮＤ１、ＭＮＤ２はＮＭＯＳトランジスタ、ＭＰＬ１、ＭＰＬ２はＰＭＯＳトランジスタ、ＷＬはワード線、ＢＬ／ＢＲはビット線対である。ＭＮＤ１、ＭＰＬ１で構成されるインバータは図１４のＩＮＶ１に相当し、ＭＮＤ２、ＭＰＬ２で構成されるインバータは図１４のＩＮＶ２に相当する。
【００３８】
図１６は、本発明の第７の実施例を示す図で、図１２の半導体メモリ装置の各ビット線対にＹ選択回路を設け、コモンデータ線対、コモンデータ線プリチャージ回路、コモンデータ線書き込み回路を設け、コモンデータ線対に適用した場合を示している。
【００３９】
ＹＳ［ｋ−１］〜ＹＳ［ｋ＋１］はＹ選択回路、Ｙ［ｋ−１］〜Ｙ［ｋ＋１］はＹ選択信号、ＢＬ［ｋ−１］／ＢＲ［ｋ−１］〜ＢＬ［ｋ＋１］／ＢＲ［ｋ＋１］はビット線対、ＤＬ／ＤＲはコモンデータ線対、ＣＫはコモンデータ線プリチャージ信号、ＭＰ１〜ＭＰ５はＰＭＯＳトランジスタ、ＷＥは書き込み制御信号、ＤＩはデータ入力信号である。コモンデータ線プリチャージ回路はＭＰ１〜ＭＰ３で構成され、Ｙ選択回路はＭＰ４、ＭＰ５で構成される。ＤＬにはＤＲ以外に対するＤＬの配線容量とＤＬに接続する素子（ＭＰ１、ＭＰ３、ＹＳ［ｋ−１］〜ＹＳ［ｋ＋１］内のそれぞれのＭＰ４、コモンデータ線書き込み回路を構成する素子など）の寄生容量との合成容量であるＣ１が等価的に接続されているとみなせる。ＤＲにはＤＬ以外に対するＤＲの配線容量とＤＲに接続する素子（ＭＰ２、ＭＰ３、ＹＳ［ｋ−１］〜ＹＳ［ｋ＋１］内のそれぞれのＭＰ５、コモンデータ線書き込み回路を構成する素子など）の寄生容量との合成容量であるＣ２が等価的に接続されているとみなせ、Ｃ２はＣ１と等しいとみなせる（Ｃ２＝Ｃ１）。ＤＬとＤＲとの間には配線間結合容量であるＣ３が等価的に接続されているとみなせ、Ｃ３＝ｋｃ・Ｃ１である。なお、Ｃ１およびＣ２の他端はＶＳＳとなっているが、ＶＤＤ、他の電源、ＤＬ／ＤＲ以外の低インピーダンスで電位一定の信号線でも同様である。
【００４０】
以上の構成において、ＢＬ［ｋ］／ＢＲ［ｋ］に対して読み出しおよび書き込みを行う場合について説明する。最初ＣＫはＶＳＳの電位と等しく、Ｙ［ｋ−１］〜Ｙ［ｋ＋１］はＶＤＤの電位と等しく、ＤＬ／ＤＲはＶＤＤの電位と等しいプリチャージ状態にある。読み出し時および書き込み時になると、ＣＫがＶＤＤの電位と等しく、Ｙ［ｋ］がＶＳＳの電位と等しくなりＤＬ／ＤＲは判定状態になる。次に、読み出し時にはＢＬ［ｋ］／ＢＲ［ｋ］で一方のビット線が選択されたメモリセルにより放電され電位差が生じ、それに伴いＤＬ／ＤＲにも電位差が生じ読み出しが行われる。また、書き込み時にはＤＬ／ＤＲの一方がコモンデータ線書き込み回路により放電され、それに伴いＢＬ［ｋ］／ＢＲ［ｋ］の一方が低電位になり、ＢＬ［ｋ］／ＢＲ［ｋ］で選択されたメモリセルに書き込みが行われる。なお、この時、読み出しおよび書き込みのいずれにおいても他方のコモンデータ線は結合ノイズによりＶＤＤより低電位になる。読み出し終了後および書き込み終了後にはＹ［ｋ］がＶＤＤの電位と等しくなり、ＣＫがＶＳＳの電位と等しくなりプリチャージ状態になるため、ＤＬ／ＤＲはＶＤＤの電位と等しくなる。
【００４１】
以上の構成および動作において、ＤＬ／ＤＲは図３のＳＰ／ＳＮに相当し、コモンデータ線プリチャージ回路は図３の相補信号線プリチャージ回路に相当し、読み出し時には選択されたメモリセル、また書き込み時にはコモンデータ線書き込み回路は図３の放電回路に相当する。また、Ｃ１〜Ｃ３はそれぞれ図３のＣ１〜Ｃ３に相当し、Ｃ２＝Ｃ１、ｋｃ＝Ｃ３／Ｃ１である。したがって、ＭＰ１〜ＭＰ３のゲート幅の和ＷＴが一定の下で、ＭＰ１〜ＭＰ３のゲート幅Ｗ１〜Ｗ３を数４２を満たすｋｇで決めることにより、ＤＬ／ＤＲのリカバリ時間をほぼ最短にでき、判定期間を長くすることなくプリチャージ期間を短縮し、半導体メモリ装置の動作サイクル時間を短縮できる。
【００４２】
図１７は、本発明の第８の実施例を示す図で、図１３の半導体メモリ装置の各ビット線対にＹ選択回路を設け、コモンデータ線対、コモンデータ線プリチャージ回路を設け、コモンデータ線対に適用した場合の構成を示している。
【００４３】
ＹＳ［ｋ−１］〜ＹＳ［ｋ＋１］はＹ選択回路、Ｙ［ｋ−１］〜Ｙ［ｋ＋１］はＹ選択信号、ＢＬ［ｋ−１］／ＢＲ［ｋ−１］〜ＢＬ［ｋ＋１］／ＢＲ［ｋ＋１］はビット線対、ＤＬ／ＤＲはコモンデータ線対、ＣＫはコモンデータ線プリチャージ信号、ＭＰ１〜ＭＰ５はＰＭＯＳトランジスタである。コモンデータ線プリチャージ回路はＭＰ１〜ＭＰ３で構成され、Ｙ選択回路はＭＰ４、ＭＰ５で構成される。ＤＬにはＤＲ以外に対するＤＬの配線容量とＤＬに接続する素子（ＭＰ１、ＭＰ３、ＹＳ［ｋ−１］〜ＹＳ［ｋ＋１］内のそれぞれのＭＰ４など）の寄生容量との合成容量であるＣ１が等価的に接続されているとみなせる。ＤＲにはＤＬ以外に対するＤＲの配線容量とＤＲに接続する素子（ＭＰ２、ＭＰ３、ＹＳ［ｋ−１］〜ＹＳ［ｋ＋１］内のそれぞれのＭＰ５など）の寄生容量との合成容量であるＣ２が等価的に接続されているとみなせ、Ｃ２はＣ１と等しいとみなせる（Ｃ２＝Ｃ１）。ＤＬとＤＲとの間には配線間結合容量であるＣ３が等価的に接続されているとみなせ、Ｃ３＝ｋｃ・Ｃ１である。なお、Ｃ１およびＣ２の他端はＶＳＳとなっているが、ＶＤＤ、他の電源、ＤＬ／ＤＲ以外の低インピーダンスで電位一定の信号線でも同様である。
【００４４】
以上の構成において、ＢＬ［ｋ］／ＢＲ［ｋ］に対して読み出しを行う場合について説明する。最初、ＣＫはＶＳＳの電位と等しく、Ｙ［ｋ−１］〜Ｙ［ｋ＋１］はＶＤＤの電位と等しく、ＤＬ／ＤＲはＶＤＤの電位と等しいプリチャージ状態にある。読み出し時になると、ＣＫがＶＤＤの電位と等しく、Ｙ［ｋ］がＶＳＳの電位と等しくなりＤＬ／ＤＲは判定状態になる。次にＢＬ［ｋ］／ＢＲ［ｋ］で一方のビット線が選択されたメモリセルにより放電され電位差が生じ、それに伴いＤＬ／ＤＲにも電位差が生じ読み出しが行われる。なお、この時他方のコモンデータ線は結合ノイズによりＶＤＤより低電位になる。読み出し終了後にはＹ［ｋ］がＶＤＤの電位と等しくなり、ＣＫがＶＳＳの電位と等しくなりプリチャージ状態になるため、ＤＬ／ＤＲはＶＤＤの電位と等しくなる。
【００４５】
以上の構成および動作において、ＤＬ／ＤＲは図３のＳＰ／ＳＮに相当し、コモンデータ線プリチャージ回路は図３の相補信号線プリチャージ回路に相当し、選択されたメモリセルは図３の放電回路に相当する。また、Ｃ１〜Ｃ３はそれぞれ図３のＣ１〜Ｃ３に相当し、Ｃ２＝Ｃ１、ｋｃ＝Ｃ３／Ｃ１である。したがって、ＭＰ１〜ＭＰ３のゲート幅の和ＷＴが一定の下で、ＭＰ１〜ＭＰ３のゲート幅Ｗ１〜Ｗ３を数４２を満たすｋｇで決めることにより、ＤＬ／ＤＲのリカバリ時間をほぼ最短にでき、判定期間を長くすることなくプリチャージ期間を短縮し、半導体メモリ装置の動作サイクル時間を短縮できる。
【００４６】
図１８は、本発明の第９の実施例を示す図で、図１３（図１６）のビット線（コモンデータ線）書き込み回路の構成例を示している。ＩＮＶはインバータ、ＭＮＷ１〜ＭＮＷ４はＮＭＯＳトランジスタ、ＹＷ（ＷＥ）は書き込みＹ選択信号（書き込み制御信号）、ＤＩはデータ入力信号、ＢＬ（ＤＬ）／ＢＲ（ＤＲ）はビット線対（コモンデータ線対）である。ＹＷ（ＷＥ）がＶＤＤの電位が等しい時に書き込み動作を行い、ＤＩがＶＳＳの電位と等しい場合ＢＲ（ＤＲ）が放電され、ＤＩがＶＤＤの電位と等しい場合ＢＬ（ＤＬ）が放電される。
【００４７】
なお、以上の実施例において、ＮＭＯＳトランジスタとＰＭＯＳトランジスタとを逆にし、ＶＤＤとＶＳＳとを入れ替え各電位の高低関係を逆にしても、全く同様であることは明らかである。
【００４８】
【発明の効果】
以上述べてきたように、本発明の回路では、相補信号線対をプリチャージする相補信号線プリチャージ回路を有し、判定時に相補信号線対の一方の信号線が放電される際に他方の信号線で結合ノイズによる電位降下が起きる場合に、相補信号線プリチャージ回路を構成するＰＭＯＳトランジスタＭＰ１〜ＭＰ３のゲート幅の和ＷＴが一定の下で、相補信号線対の結合容量比ｋｃに対して数４２で決まるコンダクタンス比ｋｇの範囲でＭＰ１〜ＭＰ３のゲート幅Ｗ１〜Ｗ３を決めることにより、相補信号線対のリカバリ時間をほぼ最短にでき、判定期間を長くすることなくプリチャージ期間を短縮し、動作サイクル時間を短縮できる。例えばｋｃ＝０．０５の場合ではｋｇは０．１０５≦ｋｇ≦０．３３４になり従来（ｋｇ＝１）に比べリカバリ時間を１３〜１４％短縮でき、リカバリ時間の短縮分だけプリチャージ期間、動作サイクル時間をそれぞれ短縮できる。
【図面の簡単な説明】
【図１】従来例を示す図。
【図２】図１の動作波形を示す図。
【図３】本発明の第１の実施例を示す図。
【図４】図３の等価回路で、ｔ＝ｔｄ１〜ｔｄ２の時にＳＰが放電され、ｔ＝０の時にプリチャージが開始する場合を示す図。
【図５】図４の動作波形を示す図。
【図６】図３の回路におけるコンダクタンス比ｋｇとプルアップ時間およびイコライズ時間との関係を示す図。
【図７】図４の回路におけるコンダクタンス比ｋｇとプルアップ時間およびイコライズ時間との関係を示す図。
【図８】図３及び図４の回路における相補信号線対の結合容量比ｋｃとコンダクタンス比ｋｇの最適値との関係を示し、ＶＤＤ−ＶＳＳ＝１．８Ｖ、ΔＶＬ＝１．８Ｖ、ΔＶＰ＝５０ｍＶの場合の図。
【図９】図３及び図４の回路における相補信号線対の結合容量比ｋｃとコンダクタンス比ｋｇの最適値との関係を示し、ＶＤＤ−ＶＳＳ＝１．８Ｖ、ΔＶＬ＝０．１８Ｖ、ΔＶＰ＝５ｍＶの場合の図。
【図１０】本発明の第２の実施例を示し、図３において放電回路を差動入力形のＮＭＯＳ論理回路で構成した図。
【図１１】図１０のＮＭＯＳ論理回路の構成例を示す図。
【図１２】本発明の第３の実施例を示し、半導体メモリ装置のビット線対に適用した図。
【図１３】本発明の第４の実施例を示し、図１２において各ビット線対にビット線書き込み回路を設け、ビット線対に適用した図。
【図１４】本発明の第５の実施例を示し、図１２、図１３のメモリセルの構成例でスタティック形の場合を示す図。
【図１５】本発明の第６の実施例を示し、図１４のメモリセルの構成例を示す図。
【図１６】本発明の第７の実施例を示し、図１２において各ビット線対にＹ選択回路を設けた他、コモンデータ線対、コモンデータ線プリチャージ回路及びコモンデータ線書き込み回路を設け、コモンデータ線対に適用した場合の図。
【図１７】本発明の第８の実施例を示し、図１３において各ビット線対にＹ選択回路を設けた他、コモンデータ線対及びコモンデータ線プリチャージ回路を設け、コモンデータ線対に適用した場合の図。
【図１８】本発明の第９の実施例を示し、図１３のビット線・図１６のコモンデータ線の各書き込み回路の構成例を示す図。
【符号の説明】
ＭＰ１〜ＭＰ３……ＰＭＯＳトランジスタ、Ｃ１〜Ｃ３……容量、
ＶＤＤ、ＶＳＳ……電源、ＣＫ……クロック信号、ＳＰ／ＳＮ……相補信号線対、Ｗ１〜Ｗ３……ＭＰ１〜ＭＰ３のゲート幅、
ｋｇ……ＭＰ１に対するＭＰ３のコンダクタンス比（＝Ｗ３／Ｗ１）、
ｋｃ……Ｃ１に対するＣ３の容量比（＝Ｃ３／Ｃ１）。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor circuit, and more particularly to a complementary signal line precharge circuit thereof.
[0002]
[Prior art]
FIG. 1 is a diagram showing a conventional example, and shows a configuration of a conventional semiconductor circuit. A complementary signal line precharge circuit for precharging the complementary signal line pair SP / SN and a discharge circuit for discharging one of SP / SN are formed, and the precharge circuit is composed of PMOS transistors MP1 to MP3. The gate widths of MP1 to MP3 are W1 to W3, respectively, and W3 = W2 = W1. The SP is assumed to be equivalently connected to a capacitance C1 that is a combined capacitance of the wiring capacitance of the SP other than SN and the parasitic capacitance of the elements (MP1, MP3, elements constituting the discharge circuit, etc.) connected to the SP. At the same time, a capacitance C2 that is a combined capacitance of the wiring capacitance of the SN other than the SP and the parasitic capacitance of the elements (MP2, MP3, elements constituting the discharge circuit, etc.) connected to the SN is equivalently connected to the SN. It can be considered that the capacitance value of C2 is equal to C1 (C2 = C1), and it can be assumed that a capacitance C3 which is a coupling capacitance between wirings is equivalently connected between SP and SN. The other ends of C1 and C2 are the power supply VSS. However, the same applies to signal lines with a low impedance and a constant potential other than the power supply VDD, other power supplies, and SP / SN.
[0003]
With the above configuration, the operation of the conventional circuit of FIG. 1 will be described with reference to FIG. In the determination period (t2 to t10) in which the clock signal CK is equal to the potential of VDD, SP is discharged by the discharge circuit and becomes a potential that is ΔVL lower than VDD. At this time, SN becomes a potential lower by ΔVD than VDD due to coupling noise caused by C3. In a precharge period (t10 to t18) in which CK is equal to VSS, SP / SN is precharged by MP1 to MP3 and becomes equal to VDD. Here, the time from the start of precharge until the potential difference ΔVP reaches a certain potential difference ΔVP is pulled up (t10 to t16), and the time from the start of precharge until the potential difference between SN and SP reaches ΔVP The larger of the equalization time (t10 to t13), the pull-up time and the equalization time is defined as the recovery time. In the case of FIG. 2, since the pull-up time is longer, the recovery time becomes equal to the pull-up time.
[0004]
[Problems to be solved by the invention]
The speeding up of the semiconductor circuit can be achieved by shortening the operation cycle time. In FIG. 2, the operation cycle time (time t2 to t18) of the semiconductor circuit is determined by a determination period (time t2 to t10) and a precharge period (time t10 to t18). Therefore, in order to shorten the operation cycle time, it is necessary to shorten at least one of the determination period and the precharge period. Here, consider a case where the precharge period is shortened. The precharge period is determined from the recovery time (t10 to t16) and the margin (t16 to t18). The margin cannot be shortened in order to ensure precharge even if the power supply, temperature, characteristics of elements constituting the circuit, etc. vary. Therefore, in order to shorten the precharge period, it is necessary to shorten the SP / SN recovery time.
[0005]
However, in the conventional semiconductor circuit, the MP3 conductance ratio to MP1 and MP2, that is, W1 and W1, regardless of the coupling capacitance ratio kc (= C3 / C1) which is the ratio of the capacitance of C3 to C1 in order to shorten the recovery time. While the ratio kg (= W3 / W1) of W3 to W2 (= W1) was kept constant at 1, the sum WT of W1 to W3 was increased. However, when WT is increased, the load on the driving circuit for driving CK increases, so that the start of the precharge period is delayed, that is, the determination period becomes longer and the operation cycle time may be longer. .
[0006]
An object of the present invention is to have a complementary signal line precharge circuit that precharges a complementary signal line pair and a discharge circuit that discharges one of the complementary signal line pairs. In a semiconductor circuit in which a potential drop due to coupling noise occurs in the other signal line when discharged, the precharge period is shortened and the operation cycle time is shortened without lengthening the determination period.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, the load of the drive circuit for driving CK is constant, that is, the sum WT of W1 to W3 is constant, and the conductance ratio kg is set to the shortest recovery time of SP / SN with respect to the coupling capacitance ratio kc. Set to the optimum range that can be considered.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 3 is a diagram showing a first embodiment of the present invention. The circuit configuration is the same as that of the conventional semiconductor circuit shown in FIG. 1, except that the conductance ratio kg (= W3 / W1) is 1. Rather, it is to take a value in the optimum range where the SP / SN recovery time can be regarded as the shortest with respect to the coupling capacity ratio kc.
[0009]
The relational expression between kc and kg optimum range in the above configuration is derived using FIG. 4 which is an equivalent circuit of FIG. An equivalent circuit of the complementary signal line precharge circuit includes conductances G1 to G3 and switches SW1 and SW2. G1 to G3 are equivalent elements when the gate potentials of MP1 to MP3 are equal to the potential of VSS, respectively. SW1 and SW2 are synchronously operated switches. When they are opened, they are in a judgment state, and when each is closed, a precharge state is established. become. On the other hand, the equivalent circuit of the discharge circuit is composed of conductances G4 and G5 and switches SW3 and SW4. G4 and G5 are equivalent elements of elements for discharging the complementary signal lines SP and SN, respectively. SW3 and SW4 are both open when inactive, and one is closed when active. C1 to C3 are capacities and correspond to C1 to C3 in FIG. v1 and v2 are the potentials of SP and SN with respect to VSS, respectively, and v3 is the potential of SN with respect to SP. The circuit of FIG. 4 operates as shown in FIG. 5, and the process of deriving the relational expression of the optimum range of kc and kg from the relational expression at each time is shown below.
[0010]
At time t <0, SW1 and SW2 are open during the determination period, and when t <td1, that is, v1 to v3 before discharging can be expressed by equations 1 to 3.
[0011]
v1 (t <td1) = VDD−VSS number 1
v2 (t <td1) = VDD−VSS number 2
v3 (t <td1) = 0 number 3
At time t = td1, SW3 is closed and the discharge circuit is activated and SP is discharged. At t = td2, SW3 is opened and the discharge circuit is deactivated and discharge is completed. When td2 ≦ t <0, that is, v1 to v3 after discharge can be expressed by Equations 4 to 6.
[0012]
v1 (td2 ≦ t <0) = VDD−ΔVL−VSS number 4
v2 (td2 ≦ t <0) = VDD−ΔVD−VSS number 5
v3 (td2 ≦ t <0) = ΔVL−ΔVD Number 6
Here, since the sum of charges stored in C2 and C3 is unchanged before discharge (t <td1) and after discharge (td2 ≦ t <0), Equation 7 is established.
[0013]
C2 · v2 (t <td1) + C3 · v3 (t <td1)
= C2 · v2 (td2 ≦ t <0) + C3 · v3 (td2 ≦ t <0) Equation 7
Time t ≧ 0 is a precharge period, and when t = 0, when SW1 and SW2 are closed, precharge starts, and SP / SN is precharged by G1 to G3 and becomes equal to the potential of VDD. Here, the pull-up time tu is defined as the time from t = 0 until v1 becomes equal to VDD-ΔVP-VSS, and the equalization time te is defined as the time from t = 0 to v3 equal to ΔVP. Note that ΔVP is a reference for determining that pull-up and equalization have been completed. For the transient response of t ≧ 0, the nodal equations of Equations 8 to 16 are established.
[0014]
C1 · dv1 (t) / dt = i1 (t) Number 8
C2 · dv2 (t) / dt = i2 (t) Number 9
C3 · dv3 (t) / dt = i3 (t) Equation 10
G1 · (VDD−VSS−v1 (t)) = i4 (t) Equation 11
G2 · (VDD−VSS−v2 (t)) = i5 (t) Equation 12
G3 · v3 (t) = i6 (t) Equation 13
v3 (t) = v2 (t) −v1 (t) Equation 14
i1 (t) = i3 (t) + i4 (t) + i6 (t) Equation 15
i5 (t) = i2 (t) + i3 (t) + i6 (t) Equation 16
Furthermore, it is assumed that the relational expressions of Formulas 17 to 24 hold between the variables and constants of Formulas 1 to 16. Equation 17 is a conditional expression that the sum of W1 to W3 is constant in the circuit of FIG. 3, Equation 23 shows that ΔVL is kv times VDD−VSS, and Equation 24 expresses ΔVP as ΔVL. It is shown that it is kp times.
[0015]
GT = G1 + G2 + G3 (GT is a constant)
G2 = G1 = G Number 18
G3 = kg · G1 = kg · G (kg ≧ 0) Equation 19
C2 = C1 = C (C is a constant) Number 20
C3 = kc · C1 = kc · C (kc ≧ 0) Equation 21
VDD-VSS = V (V is a constant) Formula 22
ΔVL = kv · (VDD−VSS) (0 <kv ≦ 1) Equation 23
ΔVP = kp · ΔVL (0 <kp <1) Number 24
Solving Equations 1 to 24, v1 (t) to v3 (t) can be expressed by Equations 25 to 31.
[0016]

For the pull-up time tu and the equalization time te, the relational expressions of Expressions 32 and 33 are established, respectively, and Expressions 34 and 35 are obtained when Expressions 22 to 31 are used. Note that Equations 34 and 35 do not depend on kv or V. Therefore, when kp is set in Equations 34 and 35 and constants C and GT are given, tu and te for arbitrary kc and kg can be obtained. In addition, since the recovery time is determined by the larger of tu and te, it is possible to obtain the optimum value of kg that minimizes the recovery time for an arbitrary kc. Conversely, the value of kg can be obtained from an arbitrary recovery time. Note that the optimum value of kg is determined only for kc without depending on C and GT if kp is set. From the above, the relational expression of the optimum range of kc and kg in the circuit of FIG. 4 can be obtained.
[0017]
v1 (tu) = VDD−ΔVP−VSS number 32
v3 (te) = ΔVP number 33
2 ・ kp ・ (1 + kc)
= (1 + 2 · kc) · exp (α · tu) + exp (β · tu) Number 34
kp · (1 + kc) = exp (β · te) number 35
FIG. 6 is a simulation result of the circuit of FIG. 3. VDD−VSS = 1.8 V, ΔVL = 1.8 V, ΔVP = 50 mV, C = 1 pF, and the gate width sum WT of MP1 to MP3 is kept constant at WT = 15 μm. , Kc = 0.05, 0.20, 0.80, tu and te when kg is changed are shown. As shown in FIG. 6, the optimum values of kg that give the shortest recovery time are kg = 0.26, 0.33, and 0.61 for kc = 0.05, 0.20, and 0.80, respectively. Note that the optimum value of kg does not change even if C and WT are changed.
[0018]
FIG. 7 is an analysis result of the circuit of FIG. 4. In the equations of Equations 34 and 35, kp (= ΔVP / ΔVL) = 1/36, C = 1 pF, GT = 0.002S, kc = 0.05, 0. Tu and te when kg is changed with respect to 20, 0.80 are shown. From FIG. 7, the optimum values of kg that give the shortest recovery time are kg = 0.21, 0.29, and 0.52 for kc = 0.05, 0.20, and 0.80, respectively. Note that the optimum value of kg does not change even if C, GT, and kv are changed.
[0019]
FIG. 8 shows the optimum value of kg with respect to kc in the case of the circuit of FIG. 3 and the circuit of FIG. 4 (0%), kg when the recovery time is 1% larger than when kg = kg (0%). The values kg (1% +) and kg (1% −) are obtained from FIG. 6 and FIG. 7, and data for kc = 0.10 and 0.40 are also added. Note that kg (1% −) <kg (0%) <kg (1% +). Moreover, the relational expression of kg (0%), kg (1% +), and kg (1% −) with respect to kc was obtained by regression analysis. The relational expressions in the circuit of FIG. 3 are shown in Expressions 36 to 38, respectively, and the relational expressions in the circuit of FIG. 4 are shown in Expressions 39 to 41, respectively.
[0020]
kg (0%) = 0.47 · kc + 0.23 Number 36
kg (1% +) = 0.46.kc + 0.38 Number 37
kg (1%-) = 0.59.kc + 0.10 Number 38
kg (0%) = 0.41 · kc + 0.20 Number 39
kg (1% +) = 0.47 · kc + 0.31 Number 40
kg (1%-) = 0.49.kc + 0.08 Number 41
From this, the optimum range of kg that can be regarded as the shortest recovery time in the circuit of FIG. 4 can be expressed by Equation 42 using Equations 40 and 41. Further, it can be seen that kg (0%) and kg (1% −) of the circuit of FIG. Therefore, the number of hours 42 when kv (= ΔVL / (VDD−VSS)) = 1 is the optimum range of kg that can be regarded as the shortest recovery time even in the circuit of FIG.
[0021]
0.49 · kc + 0.08 ≦ kg ≦ 0.47 · kc + 0.31 Number 42
FIG. 9 shows the results obtained in the same manner as in FIG. 8, and shows a case where VDD−VSS = 1.8V, ΔVL = 0.18V, and ΔVP = 5 mV. The relational expressions in the circuit of FIG. Since the relational expression in the circuit of FIG. 4 does not depend on kv, it is the same as Expressions 39 to 41.
[0022]
kg (0%) = 0.41 · kc + 0.20 Number 43
kg (1% +) = 0.47 · kc + 0.31 Number 44
kg (1%-) = 0.49.kc + 0.08 Number 45
From this, it can be seen that Equations 43 to 45 coincide with Equations 39 to 41, respectively. Therefore, even when kv = 0.1, Equation 42 is in the optimum range of kg that can be regarded as the shortest recovery time in the circuit of FIG.
[0023]
From the above, as in the circuit of FIG. 4, in the circuit of FIG. 3, Equation 42 is the optimum range of kg that can be regarded as the shortest recovery time regardless of kv.
[0024]
As described above, when the sum WT of W1 to W3 is constant and W1 to W3 are determined by kg satisfying Equation 42, the recovery time of SP / SN can be made almost shortest, without increasing the determination period. The precharge period can be shortened and the operation cycle time can be shortened.
[0025]
FIG. 10 is a diagram showing a second embodiment of the present invention, and shows a case where the discharge circuit in FIG. 3 is constituted by a differential input type NMOS logic circuit. IP1 / IN1 to IPn / INn are complementary logic input pairs, and SP / SN is a complementary signal line pair to which a complementary logic output pair is connected. The SP can be regarded as equivalently connected to a capacitance C1 which is a combined capacitance of the wiring capacitance of the SP other than SN and the parasitic capacitance of the elements connected to the SP (elements constituting the MP1, MP3 and NMOS logic circuit). , SN is connected to a capacitance C2, which is a combined capacitance of the wiring capacitance of SN with respect to other than SP and the parasitic capacitance of elements connected to SN (elements constituting MP2, MP3 and NMOS logic circuit). It can be considered that the capacitance value of C2 is equal to C1 (C2 = C1), and it can be considered that a capacitance C3 which is a coupling capacitance between wirings is equivalently connected between SP and SN.
C3 = kc · C1. The other ends of C1 and C2 are VSS, but the same applies to a signal line having a low impedance and a constant potential other than VDD, another power source, and SP / SN.
[0026]
In the above configuration, the SP / SN recovery time can be substantially minimized by determining W1 to W3 with kg satisfying Equation 42 under the condition that the sum WT of W1 to W3 is constant, and precharging is performed without lengthening the determination period. The period can be shortened and the operation cycle time can be shortened.
[0027]
FIG. 11 is a diagram illustrating a configuration example of the NMOS logic circuit of FIG. MNP1 / MNN1 to MNPn / MNNn are NMOS transistors. IP1 / IN1 to IPn / INn are complementary logic input pairs, SP / SN is a complementary logic output pair, and NOR logic signals of IP1 to IPn are output to SP, and OR logic signals of IP1 to IPn are output to SN. .
[0028]
FIG. 12 is a diagram showing a third embodiment of the present invention, and shows a case where it is applied to a bit line pair of a semiconductor memory device. MC [1, k−1] to MC [1, k + 1], MC [2, k−1] to MC [2, k + 1] are memory cells, WL1 and WL2 are word lines, and BL [k−1] / BR [K−1] to BL [k + 1] / BR [k + 1] are bit line pairs, PC [k−1] to PC [k + 1] are bit line precharge circuits, and CK [k−1] to CK [k + 1] are This is a bit line precharge signal. The bit line precharge circuit is composed of PMOS transistors MP1 to MP3. BL [k] includes the wiring capacity of BL [k] relative to other than BR [k−1] and BR [k], and the elements connected to BL [k] (PC1, MP3, MC [1,. Cb1, which is a combined capacitance with the parasitic capacitance of each of MN1 and the like in k] and MC [2, k], can be regarded as equivalently connected. In BR [k], the wiring capacity of BR [k] with respect to other than BL [k] and BL [k + 1] and the elements connected to BR [k] (PC2, MP3, MC [1, k] of PC [k]) Cb2 that is a combined capacitance with the parasitic capacitance of each MN2 in MC [2, k] and the like can be regarded as equivalently connected, and Cb2 can be regarded as equal to Cb1 (Cb2 = Cb1). Between BL [k] and BR [k], it can be considered that Cb3 which is a coupling capacitance between wirings is equivalently connected. Between BR [k−1] and BL [k], it can be considered that Cb4, which is a coupling capacitance between wirings, is equivalently connected. Between BR [k] and BL [k + 1], it can be considered that Cb5, which is a coupling capacitance between wirings, is equivalently connected, and Cb5 can be regarded as equal to Cb4 (Cb5 = Cb4). The other ends of Cb1 and Cb2 are VSS, but the same applies to a signal line having a low impedance and a constant potential other than VDD, another power source, and a bit line.
[0029]
A case where reading is performed on MC [1, k] in the above configuration will be described. First, CK [k−1] to CK [k + 1], WL1, and WL2 are equal to the potential of VSS, and BL [k−1] / BR [k−1] to BL [k + 1] / BR [k + 1] are all VDD. The precharge state is equal to the potential. At the time of reading, WL1 and CK [k] are equal to the potential of VDD, and a determination state is set at BL [k] / BR [k]. However, in BL [k−1] / BR [k−1] and BL [k + 1] / BR [k + 1], CK [k−1] and CK [k + 1] are precharged because they are equal to the potential of VSS. Next, at BL [k] / BR [k], one bit line is discharged by MC [1, k], a potential difference is generated, and reading is performed. At this time, the other bit line becomes lower than VDD due to coupling noise. After reading is completed, CK [k] and WL1 are equal to the potential of VSS and are in a precharged state, so that BL [k] / BR [k] is equal to the potential of VDD.
[0030]
In the above configuration and operation, BL [k] / BR [k] corresponds to SP / SN in FIG. 3, PC [k] corresponds to the complementary signal line precharge circuit in FIG. 3, and CK [k] 3 corresponds to CK in FIG. 3, and MC [1, k] corresponds to the discharge circuit in FIG. Cb1 + Cb4 corresponds to C1 in FIG. 3, Cb2 + Cb5 corresponds to C2 in FIG. 3, Cb3 corresponds to C3 in FIG. 3, and C2 = C1 and kc = C3 / C1.
[0031]
Therefore, the recovery time of BL [k] / BR [k] is determined by determining the gate widths W1 to W3 of MP1 to MP3 with kg satisfying Equation 42 under the constant sum WT of the gate widths of MP1 to MP3. The precharge period can be shortened without lengthening the determination period, and the operation cycle time of the semiconductor memory device can be shortened.
[0032]
FIG. 13 is a diagram showing a fourth embodiment of the present invention, and shows a case where a bit line write circuit is provided in each bit line pair of the semiconductor memory device of FIG. 12 and applied to the bit line pair. WC [k−1] to WC [k + 1] are bit line write circuits, YW [k−1] to YW [k + 1] are write Y selection signals, and DI is a data input signal.
[0033]
Note that Cb1 and Cb2 include WC [k] and include parasitic capacitances of elements connected to BL [k] and BR [k], respectively. Cb2 can be regarded as equal to Cb1 (Cb2 = Cb1).
[0034]
A case where reading and writing are performed on MC [1, k] in the above configuration will be described. First, CK [k−1] to CK [k + 1], WL1, and WL2 are equal to the potential of VSS, and BL [k−1] / BR [k−1] to BL [k + 1] / BR [k + 1] are all VDD. The precharge state is equal to the potential. At the time of reading and writing, WL1 and CK [k] are equal to the potential of VDD, and a determination state is set at BL [k] / BR [k]. However, in BL [k−1] / BR [k−1] and BL [k + 1] / BR [k + 1], CK [k−1] and CK [k + 1] are precharged because they are equal to the potential of VSS. Next, at the time of reading, one bit line is discharged by MC [1, k] at BL [k] / BR [k], and a potential difference is generated and reading is performed. At the time of writing, one of BL [k] / BR [k] is discharged by WC [k], and writing is performed on MC [1, k]. At this time, in both reading and writing, the other bit line becomes a potential lower than VDD due to coupling noise. After reading and writing, CK [k] and WL1 are equal to the potential of VSS and in a precharged state, so that BL [k] / BR [k] is equal to the potential of VDD.
[0035]
In the above configuration and operation, BL [k] / BR [k] corresponds to SP / SN in FIG. 3, PC [k] corresponds to the complementary signal line precharge circuit in FIG. 3, and CK [k] 3 corresponds to CK in FIG. 3, and MC [1, k] at the time of reading and WC [k] at the time of writing correspond to the discharging circuit of FIG. Cb1 + Cb4 corresponds to C1 in FIG. 3, Cb2 + Cb5 corresponds to C2 in FIG. 3, Cb3 corresponds to C3 in FIG. 3, and C2 = C1 and kc = C3 / C1. Therefore, the recovery time of BL [k] / BR [k] is determined by determining the gate widths W1 to W3 of MP1 to MP3 with kg satisfying Equation 42 under the constant sum WT of the gate widths of MP1 to MP3. The precharge period can be shortened without lengthening the determination period, and the operation cycle time of the semiconductor memory device can be shortened.
[0036]
FIG. 14 is a diagram showing a fifth embodiment of the present invention, and shows a static type configuration example of the memory cell of FIG. 12 and FIG. INV1 and INV2 are inverters, and MN1 and MN2 are NMOS transistors. INV1 and INV2 constitute a flip-flop. The memory cell sets BL / BR to a high impedance when WL is not equal to the potential of VSS, and discharges one of BL / BR according to the information stored when WL is equal to the potential of VDD. To high impedance.
[0037]
FIG. 15 is a diagram showing a sixth embodiment of the present invention, and shows a configuration example of the memory cell of FIG. MN1, MN2, MND1, and MND2 are NMOS transistors, MPL1 and MPL2 are PMOS transistors, WL is a word line, and BL / BR is a bit line pair. The inverter composed of MND1 and MPL1 corresponds to INV1 in FIG. 14, and the inverter composed of MND2 and MPL2 corresponds to INV2 in FIG.
[0038]
FIG. 16 is a diagram showing a seventh embodiment of the present invention, wherein each bit line pair of the semiconductor memory device of FIG. 12 is provided with a Y selection circuit, a common data line pair, a common data line precharge circuit, a common data line. A case where a writing circuit is provided and applied to a common data line pair is shown.
[0039]
YS [k−1] to YS [k + 1] are Y selection circuits, Y [k−1] to Y [k + 1] are Y selection signals, and BL [k−1] / BR [k−1] to BL [k + 1]. / BR [k + 1] is a bit line pair, DL / DR is a common data line pair, CK is a common data line precharge signal, MP1 to MP5 are PMOS transistors, WE is a write control signal, and DI is a data input signal. The common data line precharge circuit is composed of MP1 to MP3, and the Y selection circuit is composed of MP4 and MP5. DL includes the wiring capacitance of DL other than DR and elements connected to DL (MP1, MP3, MP4 in YS [k−1] to YS [k + 1], elements constituting a common data line writing circuit, etc.) It can be considered that C1, which is the combined capacitance with the parasitic capacitance, is equivalently connected. DR includes the wiring capacitance of DR other than DL and the elements connected to DR (MP2, MP3, MP5 in YS [k-1] to YS [k + 1], elements constituting the common data line writing circuit, etc.) It can be considered that C2, which is a combined capacitance with the parasitic capacitance, is equivalently connected, and C2 can be regarded as equal to C1 (C2 = C1). It can be considered that C3 which is a coupling capacitance between wirings is equivalently connected between DL and DR, and C3 = kc · C1. The other ends of C1 and C2 are VSS, but the same applies to signal lines having a low impedance and a constant potential other than VDD, other power supplies, and DL / DR.
[0040]
A case where reading and writing are performed on BL [k] / BR [k] in the above configuration will be described. First, CK is equal to the potential of VSS, Y [k−1] to Y [k + 1] are equal to the potential of VDD, and DL / DR is in a precharge state equal to the potential of VDD. At the time of reading and writing, CK is equal to the potential of VDD, Y [k] is equal to the potential of VSS, and DL / DR enters a determination state. Next, at the time of reading, one bit line is discharged by BL [k] / BR [k] and a potential difference is generated, and accordingly, a potential difference is also generated in DL / DR and reading is performed. At the time of writing, one of DL / DR is discharged by the common data line writing circuit, and accordingly, one of BL [k] / BR [k] becomes a low potential and is selected by BL [k] / BR [k]. Data is written to the memory cell. At this time, in both reading and writing, the other common data line becomes lower than VDD due to coupling noise. After reading and writing are finished, Y [k] becomes equal to the potential of VDD, CK becomes equal to the potential of VSS, and a precharge state is established, so DL / DR becomes equal to the potential of VDD.
[0041]
In the above configuration and operation, DL / DR corresponds to SP / SN in FIG. 3, the common data line precharge circuit corresponds to the complementary signal line precharge circuit in FIG. 3, and the memory cell selected at the time of reading, At the time of writing, the common data line writing circuit corresponds to the discharging circuit of FIG. C1 to C3 correspond to C1 to C3 in FIG. 3, respectively, and C2 = C1 and kc = C3 / C1. Therefore, by determining the gate widths W1 to W3 of MP1 to MP3 with kg satisfying Equation 42 under the constant gate width WT of MP1 to MP3, the DL / DR recovery time can be substantially shortened and the determination is made. The precharge period can be shortened without lengthening the period, and the operation cycle time of the semiconductor memory device can be shortened.
[0042]
FIG. 17 is a diagram showing an eighth embodiment of the present invention. In the semiconductor memory device of FIG. 13, each bit line pair is provided with a Y selection circuit, a common data line pair and a common data line precharge circuit are provided, A configuration when applied to a data line pair is shown.
[0043]
YS [k−1] to YS [k + 1] are Y selection circuits, Y [k−1] to Y [k + 1] are Y selection signals, and BL [k−1] / BR [k−1] to BL [k + 1]. / BR [k + 1] is a bit line pair, DL / DR is a common data line pair, CK is a common data line precharge signal, and MP1 to MP5 are PMOS transistors. The common data line precharge circuit is composed of MP1 to MP3, and the Y selection circuit is composed of MP4 and MP5. DL has a capacitance C1 which is a combined capacitance of the wiring capacitance of DL other than DR and the parasitic capacitance of the elements (MP1, MP3, MPS in YS [k−1] to YS [k + 1], etc.) connected to DL. It can be regarded as equivalently connected. DR includes C2 which is a combined capacitance of the wiring capacitance of DR other than DL and the parasitic capacitance of elements connected to DR (MP2, MP3, MPS in YS [k−1] to YS [k + 1], etc.). It can be regarded as being equivalently connected, and C2 can be regarded as being equal to C1 (C2 = C1). It can be considered that C3 which is a coupling capacitance between wirings is equivalently connected between DL and DR, and C3 = kc · C1. The other ends of C1 and C2 are VSS, but the same applies to signal lines having a low impedance and a constant potential other than VDD, other power supplies, and DL / DR.
[0044]
A case where reading is performed on BL [k] / BR [k] in the above configuration will be described. Initially, CK is equal to the potential of VSS, Y [k−1] to Y [k + 1] are equal to the potential of VDD, and DL / DR is in a precharge state equal to the potential of VDD. At the time of reading, CK is equal to the potential of VDD, Y [k] is equal to the potential of VSS, and DL / DR enters a determination state. Next, one bit line at BL [k] / BR [k] is discharged by the memory cell selected to generate a potential difference, and accordingly, a potential difference is also generated at DL / DR and reading is performed. At this time, the other common data line has a potential lower than VDD due to coupling noise. After reading is completed, Y [k] becomes equal to the potential of VDD, CK becomes equal to the potential of VSS, and the precharge state is established. Therefore, DL / DR becomes equal to the potential of VDD.
[0045]
In the above configuration and operation, DL / DR corresponds to SP / SN in FIG. 3, the common data line precharge circuit corresponds to the complementary signal line precharge circuit in FIG. 3, and the selected memory cell is in FIG. It corresponds to a discharge circuit. C1 to C3 correspond to C1 to C3 in FIG. 3, respectively, and C2 = C1 and kc = C3 / C1. Therefore, by determining the gate widths W1 to W3 of MP1 to MP3 with kg satisfying Equation 42 under the constant gate width WT of MP1 to MP3, the DL / DR recovery time can be substantially shortened and the determination is made. The precharge period can be shortened without lengthening the period, and the operation cycle time of the semiconductor memory device can be shortened.
[0046]
FIG. 18 is a diagram showing a ninth embodiment of the present invention, and shows a configuration example of the bit line (common data line) write circuit of FIG. 13 (FIG. 16). INV is an inverter, MNW1 to MNW4 are NMOS transistors, YW (WE) is a write Y selection signal (write control signal), DI is a data input signal, BL (DL) / BR (DR) is a bit line pair (common data line pair) ). A write operation is performed when YW (WE) has the same VDD potential. When DI is equal to VSS, BR (DR) is discharged, and when DI is equal to VDD, BL (DL) is discharged.
[0047]
In the above-described embodiments, it is clear that even if the NMOS transistor and the PMOS transistor are reversed and VDD and VSS are exchanged and the level relationship of each potential is reversed, the same is true.
[0048]
【The invention's effect】
As described above, the circuit of the present invention has the complementary signal line precharge circuit for precharging the complementary signal line pair, and when one signal line of the complementary signal line pair is discharged at the time of determination, When a potential drop due to coupling noise occurs in the signal line, the gate width sum WT of the PMOS transistors MP1 to MP3 constituting the complementary signal line precharge circuit is constant, with respect to the coupling capacitance ratio kc of the complementary signal line pair. By determining the gate widths W1 to W3 of MP1 to MP3 within the conductance ratio kg determined by Equation 42, the recovery time of the complementary signal line pair can be made the shortest, and the precharge period can be shortened without lengthening the judgment period. The operation cycle time can be shortened. For example, in the case of kc = 0.05, kg is 0.105 ≦ kg ≦ 0.334, so that the recovery time can be reduced by 13 to 14% compared to the conventional case (kg = 1), and the precharge period, Each operation cycle time can be shortened.
[Brief description of the drawings]
FIG. 1 is a diagram showing a conventional example.
FIG. 2 is a diagram illustrating operation waveforms of FIG.
FIG. 3 is a diagram showing a first embodiment of the present invention.
4 is a diagram showing a case where SP is discharged when t = td1 to td2 and precharge is started when t = 0 in the equivalent circuit of FIG. 3;
5 is a diagram showing operation waveforms of FIG. 4;
6 is a diagram showing the relationship between conductance ratio kg, pull-up time, and equalization time in the circuit of FIG. 3;
7 is a diagram showing the relationship between conductance ratio kg, pull-up time, and equalization time in the circuit of FIG. 4;
8 shows the relationship between the coupling capacitance ratio kc of the complementary signal line pair and the optimum value of the conductance ratio kg in the circuits of FIG. 3 and FIG. 4, and VDD−VSS = 1.8V, ΔVL = 1.8V, ΔVP = The figure in the case of 50 mV.
9 shows the relationship between the coupling capacitance ratio kc of the complementary signal line pair and the optimum value of the conductance ratio kg in the circuits of FIG. 3 and FIG. 4, and VDD−VSS = 1.8V, ΔVL = 0.18V, ΔVP = The figure in the case of 5 mV.
10 is a diagram showing a second embodiment of the present invention, in which the discharge circuit in FIG. 3 is configured by a differential input type NMOS logic circuit. FIG.
11 is a diagram showing a configuration example of the NMOS logic circuit of FIG.
FIG. 12 is a diagram showing a third embodiment of the present invention applied to a bit line pair of a semiconductor memory device.
13 is a diagram showing a fourth embodiment of the present invention, in which a bit line write circuit is provided in each bit line pair in FIG. 12 and applied to the bit line pair.
14 is a diagram showing a fifth embodiment of the present invention and showing a static type in the configuration example of the memory cell of FIGS. 12 and 13; FIG.
15 is a diagram showing a configuration example of the memory cell of FIG. 14 according to the sixth embodiment of the present invention.
16 shows a seventh embodiment of the present invention. In FIG. 12, each bit line pair is provided with a Y selection circuit, and a common data line pair, a common data line precharge circuit, and a common data line write circuit are provided. The figure when applied to a common data line pair.
17 shows an eighth embodiment of the present invention. In FIG. 13, each bit line pair is provided with a Y selection circuit, a common data line pair and a common data line precharge circuit are provided, and the common data line pair is provided. Figure when applied.
18 is a diagram showing a configuration example of each write circuit of the bit line in FIG. 13 and the common data line in FIG. 16 according to the ninth embodiment of the present invention.
[Explanation of symbols]
MP1 to MP3: PMOS transistor, C1 to C3: capacitance,
VDD, VSS: power supply, CK: clock signal, SP / SN: complementary signal line pair, W1 to W3: gate widths of MP1 to MP3,
kg ... Conductance ratio of MP3 to MP1 (= W3 / W1)
kc: Capacity ratio of C3 to C1 (= C3 / C1).

Claims

A complementary signal line precharge circuit for precharging a complementary signal line pair composed of a first signal line and a second signal line, and a circuit for discharging or charging any one of the complementary signal line pairs (Hereinafter, a charge / discharge circuit) and a first and second power source,
A first capacitor, which is a combined capacitor of the wiring capacitance of the first signal line and the parasitic capacitance of the element connected to the first signal line, other than the second signal line is equivalently connected to the first signal line. The second signal line has a second capacitance that is a combined capacitance of the wiring capacitance of the second signal line other than the first signal line and the parasitic capacitance of the element connected to the second signal line. A third capacitor, which is an inter-wiring coupling capacitor, is equivalently connected between the first signal line and the second signal line.
The complementary signal line precharge circuit includes a first PMOS (or NMOS) transistor having a clock signal as a gate input, one end connected to a first signal line and the other end connected to a second power supply, and the clock signal As a gate input, a second PMOS (or NMOS) transistor having one end connected to a second signal line and the other end connected to a second power supply, and the clock signal as a gate input and one end being a first signal line And a third PMOS (or NMOS) transistor whose other end is connected to the second signal line.
In the output pair connected to the complementary signal line pair in the charge / discharge circuit, both outputs have a high impedance when inactive, and when activated, one of the outputs is discharged (or charged) and the other output is high. Become impedance,
When the clock signal is precharged approximately equal to the potential of the first power supply, the charge / discharge circuit is inactive, and the complementary signal line precharge circuit causes both signal lines of the complementary signal line pair to be at the potential of the second power supply. When the charge / discharge circuit is activated when it is determined that the clock signal is substantially equal to the potential of the second power supply, one signal line of the complementary signal line pair is discharged (or charged) by the charge / discharge circuit. And the potential of the second power source is lower or higher than the potential of the second power source, and the other signal line is lower or higher than the potential of the second power source due to the coupling noise caused by the third capacitor, and the complementary signal. When the voltage becomes higher or lower than one signal line of the line pair, the charge / discharge circuit becomes inactive, and the clock signal is precharged substantially equal to the potential of the first power supply. Both the signal lines of the complementary signal line pair by the complementary signal-line precharge circuit is approximately equal to the second power supply potential,
When the first capacitor and the second capacitor can be regarded as approximately equal, and the conductance of the first PMOS (or NMOS) transistor and the conductance of the second PMOS (or NMOS) transistor can be regarded as approximately equal. Is
When the conductance ratio of the third PMOS (or NMOS) transistor to the first PMOS (or NMOS) transistor is kg and the ratio of the third capacitance to the first capacitance is kc,
0.49 · kc + 0.08 ≦ kg ≦ 0.47 · kc + 0.31
A semiconductor circuit characterized by the above.

2. The semiconductor circuit according to claim 1, wherein the charge / discharge circuit is a differential input type NMOS (or PMOS) logic circuit having the complementary signal line pair as a complementary logic output pair.

The semiconductor circuit includes a semiconductor memory device having a memory cell array including a plurality of memory cells arranged in a matrix in a row direction and a column direction,
Each memory cell row is provided with one word line for selecting a memory cell corresponding to the row, and each memory cell column has a set of bit line pairs for transmitting information of the memory cell corresponding to the column. A bit line precharge circuit for precharging the bit line pair;
In the output pair connected to the bit line pair in the bit line precharge circuit, both outputs become high impedance at the time of determination, and both outputs become substantially equal to the potential of the second power source at the time of precharge,
As for the output pair connected to the bit line pair in the memory cell, both outputs have high impedance when not selected, and when selected, either output is discharged (or charged) and the other output becomes high impedance. ,
Before reading, the memory cell row and the memory cell column are not selected, the memory cell is not selected, and the bit line precharge circuit is in a precharged state in the memory cell column. In the memory cell column selected at the time of reading, the bit line precharge circuit is in the determination state, and when only one memory cell row is selected, the only memory cell is almost equal to the power supply potential. Is selected, one bit line of the pair of bit lines in the only selected memory cell column is discharged (or charged) by the only selected memory cell, and reading is performed. And the memory cell column are deselected, the memory cell is deselected, and the bit line precharge circuit is in a precharged state. If made as a result the pair of bit lines both bit lines is substantially equal to the second power supply potential,
Functionally, in the only selected memory cell column, the bit line pair corresponds to the complementary signal line pair, the bit line precharge circuit corresponds to the complementary signal line precharge circuit, and is only selected. The semiconductor circuit according to claim 1, wherein the memory cell corresponds to the charge / discharge circuit.

Each of the memory cell columns is provided with a bit line write circuit for charging / discharging any one of the corresponding bit line pairs.
The output pair connected to the bit line pair in the bit line write circuit has both outputs in a high impedance state when inactive, and when activated, either one of the outputs is charged / discharged and the other output has a high impedance. ,
Before reading and writing, the memory cell row and column are not selected, the memory cell is not selected, the bit line write circuit is inactive, and the bit line precharge circuit is not preselected in the memory cell column. Since the bit line pair is almost equal to the potential of the second power supply because it is in the charged state, the bit line precharge circuit is in the determination state in the memory cell column selected at the time of reading and writing. When the memory cell row is selected, the memory cell is selected, and at the time of reading, one bit line of the pair of bit lines in the only selected memory cell column is discharged (or charged) by the selected memory cell. The bit line is written in the memory cell column selected only at the time of reading and writing. The circuit becomes active, and one bit line of the bit line pair is discharged (or charged), and writing is performed on the only selected memory cell. After reading and writing, the memory cell row and the memory cell row Since the memory cell column is not selected, the memory cell is not selected, the bit line write circuit is inactivated, and the bit line precharge circuit is in a precharge state, so that both bit lines of the bit line pair are When it is almost equal to the potential of the second power supply,
In the only selected memory cell column, functionally, the bit line pair corresponds to the complementary signal line pair, and the bit line precharge circuit corresponds to the complementary signal line precharge circuit. 4. The semiconductor circuit according to claim 3, wherein the memory cell thus formed corresponds to the charge / discharge circuit, and the bit line write circuit corresponds to the charge / discharge circuit at the time of writing.

The memory cell is a static memory cell composed of first and second inverters and fourth and fifth NMOS (or PMOS) transistors, and the output of the first inverter is connected to the input of the second inverter. The output of the second inverter is connected to the input of the first inverter, the fourth NMOS (or PMOS) transistor has a gate input connected to the word line corresponding to the memory cell, and one end connected to the memory cell. One of the corresponding bit line pairs is connected, the other end is connected to the output of the first inverter, and a fifth NMOS (or PMOS) transistor has a gate input connected to the word line corresponding to the memory cell. One end is connected to the other of the bit line pair corresponding to the memory cell, and the other end is connected to the output of the second inverter. 3 or 4 semiconductor circuit according.

The first inverter has a gate input as an input of the first inverter, one end connected to the first power supply, and the other end connected to one end of a sixth PMOS (or NMOS) transistor. Or a PMOS) transistor and a sixth PMOS (or NMOS) transistor having the input of the first inverter as the gate input and the other end connected to the second power supply,
The second inverter has a gate input as an input of the second inverter, one end connected to the first power supply, and the other end connected to one end of an eighth PMOS (or NMOS) transistor. The semiconductor circuit according to claim 5, further comprising: an eighth (PMOS) transistor and an eighth PMOS (or NMOS) transistor having the input of the second inverter as a gate input and the other end connected to a second power supply.

Each of the memory cell columns is provided with a Y selection circuit, the memory cell array is provided with a common data line pair, and the common data line pair includes a common data line precharge circuit and a common data line write circuit. Provided,
The Y selection circuit has a first input / output pair and a second input / output pair, the first input / output pair is connected to the corresponding bit line pair, and the second input / output pair is connected to the common data line. Connected to the pair, the impedance between the first input / output pair and the second input / output pair is increased when not selected, and the impedance between the first input / output pair and the second input / output pair is selected when selected. Lower
In the output pair connected to the common data line pair in the common data line precharge circuit, both outputs become high impedance at the time of determination, and both outputs become substantially equal to the potential of the second power source at the time of precharge,
The output pair connected to the common data line pair in the common data line writing circuit has a high impedance when it is inactive, and when activated, one of the outputs is discharged (or charged) and the other output is Become high impedance,
Before reading and writing, the Y selection circuit is not selected and the common data line precharge circuit is in a precharged state, so that the common data line pair is substantially equal to the potential of the second power supply. In addition, only one memory cell column and only one memory cell row are selected at the time of writing, and a Y selection circuit corresponding to the selected memory cell row is selected, and the common data line precharge circuit enters a determination state, and reading is performed. Sometimes one common data line of the common data line pair is discharged (or charged) by the only selected memory cell to perform reading, and at the time of writing, the common data line writing circuit becomes active and the common data line pair One is discharged (or charged), and one bit of the bit line pair of the selected memory cell column is selected. The data line is discharged (or charged), and the only selected memory cell is written, and after reading and writing, the Y selection circuit is deselected and the common data line precharge circuit When both common data lines of the common data line pair are substantially equal to the potential of the second power supply because of the precharge state,
Functionally, the common data line pair corresponds to the complementary signal line pair, the common data line precharge circuit corresponds to the complementary signal line precharge circuit, and the memory cell selected only at the time of reading is the charge cell. The semiconductor circuit according to claim 3, wherein the semiconductor circuit corresponds to a discharge circuit, and the common data line write circuit corresponds to the charge / discharge circuit during writing.

Each of the memory cell columns is provided with the Y selection circuit, the memory cell array is provided with one set of the common data line pair, and the common data line pair is provided with the common data line precharge circuit,
Before reading, the Y selection circuit is not selected and the common data line precharge circuit is in a precharged state, so that the common data line pair is substantially equal to the potential of the second power supply. When the memory cell column and the only memory cell row are selected, and the only memory cell is selected, the corresponding Y selection circuit is selected, and the common data line precharge circuit enters the determination state, and the common data One common data line of the line pair is discharged (or charged) by the selected memory cell, and reading is performed. After the reading is completed, the Y selection circuit is deselected and the common data line precharge circuit is When both common data lines of the common data line pair are substantially equal to the potential of the second power supply because of the precharge state,
Functionally, the common data line pair corresponds to the complementary signal line pair, the common data line precharge circuit corresponds to the complementary signal line precharge circuit, and the only selected memory cell is the charge / discharge circuit. The semiconductor circuit according to claim 4, corresponding to.

The bit line writing circuit or the common data line writing circuit includes a third inverter and tenth to thirteenth NMOS (or PMOS) transistors, and a tenth NMOS (or PMOS) transistor has a gate input as the bit line. A write control signal for activating the write circuit or the common data line write circuit, one end of which is connected to one of the corresponding bit line pair or the common data line pair, and the other end is an eleventh NMOS (or PMOS). The eleventh NMOS (or PMOS) transistor is connected to one end of the transistor, the gate input is a data input signal, the other end is connected to the first power supply, and the twelfth NMOS (or PMOS) transistor has a gate input. The write control signal, one end corresponding to the bit line pair or The other end of the common data line pair is connected, the other end is connected to one end of a thirteenth NMOS (or PMOS) transistor, and the gate input of the thirteenth NMOS (or PMOS) transistor is an inverted signal of the data input signal. The semiconductor circuit according to claim 4, wherein the other end is connected to the first power source.