JP4099343B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device such as a high frequency amplification FET.
[0002]
[Prior art]
The dependence of the gate current (Igs) on the high-frequency input power in the power amplifier is shown in FIG. When the input power becomes larger than the input power P, the gate current starts to flow. Therefore, when power larger than the P is inputted, the transistor deteriorates. Also, the linearity of the transistor is impaired at input power greater than P. This example is a power amplifier using an FET, but the same can be said for a multiplier and a frequency converter. Further, the basic element is not limited to the FET.
[0003]
FIG. 2 shows a protection circuit disclosed in Japanese Patent Laid-Open No. 8-172188, and its operation description is cited from the same publication.
“The semiconductor device 10 includes an N-type MOS transistor 20 whose gate end, source end, drain end, and substrate are connected to the external terminals 12, 14, 16, and 18 for measurement, and an input end that is grounded and an output end. Is connected in series with the PN junction diode 22 connected to the gate terminal 12 of the N-type MOS transistor 20 in the same direction, its input terminal is connected to the gate terminal 12 of the N-type MOS transistor 20, and its output terminal is grounded. It has a plurality of PN junction diodes 24. Here, the PN junction diodes 22 and 24 are protection circuits for protecting the N-type MOS transistor 20 which is a monitoring transistor. In addition, the following description will be continued assuming that the forward drop voltage of the PN junction diode 22 is 0V.
[0004]
In this semiconductor device 10, when a voltage lower than the ground voltage is applied to the external terminal 12 at the gate end of the N-type MOS transistor 20, the PN junction diode 22 is turned on, and from the ground side to the outside of the gate end through the PN junction diode 22. Since the current is discharged to the terminal 12 side, the gate terminal of the N-type MOS transistor 20 is fixed to the ground voltage. Similarly, when a voltage larger than the forward drop voltage of the PN junction diode 24 is applied to the external terminal 12 at the gate end of the N-type MOS transistor 20, the PN junction diode 24 is turned on, and the external terminal 12 side of the gate end Since the current is discharged from the first through the PN junction diode 24 to the ground side, the gate terminal of the N-type MOS transistor 20 is fixed to the forward voltage drop of the PN junction diode 24.
[0005]
As described above, by providing the protection circuit at the gate end of the N-type MOS transistor 20, the current can be discharged through the PN junction diodes 22 and 24. Therefore, since the voltage at the gate end of the N-type MOS transistor 20 is clamped within the range of the ground voltage and the forward drop voltage of the PN junction diode 24, the number of the PN junction diodes 24 is appropriately selected, and the forward drop voltage is selected. Is made smaller than the breakdown voltage of the gate oxide film of the N-type MOS transistor 20, the N-type MOS transistor 20 which is a monitoring transistor can be protected. Further, since the gate end of the N-type MOS transistor 20 can be changed within the range of the ground voltage to the forward drop voltage of the PN junction diode 24, the electrical measurement of the N-type MOS transistor 20 can be performed without any problem. it can. "
[0006]
Japanese Patent Application Laid-Open No. 6-21356 also discloses a protection circuit for a MOS transistor in which a diode is connected to the gate.
[0007]
[Problems to be solved by the invention]
However, all of these publications are protection against an excessive input voltage, and the signal is a DC voltage or a transient signal of several KHz, and the protection against an excessive input power (power) at a high frequency such as 0.1 GHz to 100 GHz. There wasn't.
[0008]
The present invention provides a semiconductor device capable of protecting elements such as FETs from excessive input power.
[0009]
[Means for Solving the Problems]
The invention according to claim 1 is characterized in that a circuit whose impedance decreases as the applied high frequency power increases is connected to the input portion of the semiconductor device to protect against excessive input. As a circuit, it can be realized with a simple diode connected in reverse parallel.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Fig. 3 shows a 50Ω resistor connected to one side of a diode pair (APDP: Anti-Parallel-Diode-Pair) with anti-parallel connection of diodes. A high frequency of 1 Hz is applied from one terminal and the input When the power was increased from 0 mW to 40 mW, the change in impedance Z at that terminal was measured. The measurement results are shown in FIG. In the chart of FIG. 4, the horizontal axis is a resistance R value axis, and the vertical axis is a complex plane indicating the reactor component X.
[0011]
As can be seen from this chart, it can be understood that the impedance decreases as the input power increases (approaching a pure resistance of 50Ω, that is, the impedance of the APDP itself gradually decreases). The same tendency is shown even in the case of a high frequency of 0.1 to 100 GHz.
[0012]
Therefore, if the APDP is connected to the gate of the transistor to be protected, if the input power to the gate increases, the impedance of the APDP decreases, and the power flowing through the APDP increases, so that the input to the gate is reduced. It is reduced and functions as a transistor protection circuit. The protection circuit is not limited to APDP as long as the impedance is reduced by an increase in input power.
[0013]
Embodiment 1
FIG. 5 shows a first embodiment of the present invention. A capacitor 2 for blocking DC current is connected between the gate of the transistor 1 and the input terminal IN, and an APDP in which two diodes 3 are connected in antiparallel as a protection circuit is inserted between the input terminal IN and GND. Is done.
[0014]
In this way, if the APDP whose impedance decreases as the input power increases is connected to the gate, the impedance of the APDP decreases when the input power increases, so that a part of the input is connected to the GND through the APDP. Current, the input power of transistor 1 is reduced, and the transistor is protected from excessive input.
[0015]
Embodiment 2
In the second embodiment shown in FIG. 6, the APDP shown in FIG. 5 is connected in two stages. If APDP is made two stages in this way, the impedance at this point becomes twice that in the case of FIG. 5, and the supply input to the gate also changes. Therefore, the gate input can be adjusted by connecting two or more stages, and the input power P at which the gate current in FIG. 1 starts flowing can be arbitrarily changed.
[0016]
Embodiment 3
In the third embodiment shown in FIG. 7, APDPs are connected in two stages as in FIG. 6, but a bias application terminal X for applying a bias to the connection point of the two APDPs is provided. Provided. By applying a desired bias to the bias application terminal X, the power to be supplied to these APDPs can be varied arbitrarily, so that the input to the gate can be freely adjusted. According to this circuit, input adjustment is possible even after chip fabrication.
[0017]
Embodiment 4
In the fourth embodiment shown in FIG. 8, two diodes are connected in antiparallel (that is, two APDPs are connected in parallel) (denoted as APDP_X2). Thereby, when the anode width of the diode 3 is substantially changed, the power flowing in the APDP_X2 is changed, so that the input to the gate can be adjusted.
[0018]
Embodiment 5
In the fifth embodiment shown in FIG. 9, the input is made by the capacitor 5 inserted between the input end of the APDP and the input terminal IN and the inductor 6 for current path connected between the input end and GND. A matching circuit is formed. By forming this input matching circuit, the power flowing through the APDP can be adjusted, and therefore the input to the gate can be adjusted.
[0019]
Embodiment 6
In the sixth embodiment shown in FIG. 10, a bridge formed by two diodes 3 and two capacitors (referred to as APDP_BG) is used, and the other two nodes are used as bias application terminals Y1 and Y2. By applying a desired bias to these bias application terminals Y1 and Y2, the power to flow through these APDPs can be varied arbitrarily, and the input to the gate can be freely adjusted. With this circuit, input adjustment is possible even after chip fabrication.
[0020]
Embodiment 7
Each circuit described above is used as a protection circuit for incorporation into the amplifying element, but can also be used as a single protection circuit.
[0021]
【The invention's effect】
According to the first aspect of the present invention, since the circuit whose impedance decreases with the increase of the applied high frequency power is connected to the input portion of the semiconductor device, when the input to the input portion becomes excessive, the circuit becomes low impedance. As a result, part of the input flows into the circuit, so that the semiconductor device can be protected from an excessive input, and the linearity of the input / output relationship can be maintained.
[0022]
According to the second aspect of the present invention, the circuit is realized by connecting the diodes in reverse parallel, and the semiconductor device can be protected with a very simple configuration and at a low cost.
[0023]
In the invention of claim 3, since the circuit is connected in multiple stages, the input to the input section can be adjusted according to the number of stages.
[0024]
According to the fourth aspect of the present invention, since the bias application terminal is provided at the connection point between the circuits connected in multiple stages, the power flowing into the circuit according to the magnitude of the bias applied to the terminal even after the chip is manufactured. The semiconductor device can be freely set for protection by adjusting the value.
[0025]
According to the fifth aspect of the present invention, since the anode width of the diode used in the circuit is changed, the power flowing into the circuit can be adjusted, and thus the semiconductor device can be freely set for protection.
[0026]
According to the sixth aspect of the present invention, since the input matching circuit including the current path inductor and the DC blocking capacitor for the above circuit is used in combination, the semiconductor device can be protected with a higher degree of freedom.
[0027]
According to the seventh aspect of the present invention, since a bias application terminal is provided for each of the diodes used in the circuit, the power flowing into the circuit is adjusted depending on the magnitude of the bias applied to the terminal even after the chip is manufactured. Thus, the semiconductor device can be freely set for protection.
[Brief description of the drawings]
FIG. 1 is a diagram showing a change in gate current (Igs) with respect to a change in high-frequency input power. FIG. 2 is a protection circuit diagram disclosed in the publication. FIG. 3 is a circuit configuration used for measuring the impedance of APDP. FIG. 4 is a diagram showing changes in impedance of APDP measured by the circuit of FIG. 3. FIG. 5 is a circuit diagram of the semiconductor device showing the first embodiment of the present invention. FIG. 7 is a circuit diagram of a semiconductor device showing a third embodiment of the present invention. FIG. 8 is a circuit diagram of a semiconductor device showing a fourth embodiment of the present invention. 9 is a circuit diagram of a semiconductor device showing a fifth embodiment of the present invention. FIG. 10 is a circuit diagram of a semiconductor device showing a sixth embodiment of the present invention.
1 transistor, 2 capacitor, 3 diode, 5 capacitor, 6 reactor, APDP diode pair

Claims (7)

A semiconductor device including a semiconductor element,
A DC blocking capacitor connected to the input terminal of the semiconductor element;
A circuit in which impedance decreases with an increase in applied high-frequency power, the circuit being connected between the input side of the capacitor and ground;
A semiconductor device comprising: a. The semiconductor device according to claim 1, wherein the circuit is a diode pair connected in antiparallel . 3. The semiconductor device according to claim 2, wherein the circuit is connected in multiple stages to adjust the input to the input unit of the semiconductor device.   4. The semiconductor device according to claim 3, wherein a bias application terminal is provided at a connection point between the circuits connected in multiple stages.   The semiconductor device according to claim 2, wherein an input to the input unit is adjusted by changing an anode width of the diode. Further connected to the circuit, according to any of claims 2-5 having an input matching circuit composed of a second DC blocking capacitor connected to the input of the grounded inductor and said semiconductor device Semiconductor device. The semiconductor device according to claim 2 , wherein a capacitor is inserted in series with each diode of the circuit, and a bias application terminal is provided at each connection point between the diode and the capacitor .

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