JP4094405B2 - AD converter circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to supply of a bias current to a functional circuit such as an AD conversion circuit, and more particularly to supply of a bias current to an AD conversion circuit having a parallel AD conversion unit.
[0002]
[Prior art]
As an example of a functional circuit in the prior art, a circuit diagram of a parallel AD converter circuit is shown in FIG. Voltages obtained by equally dividing the high voltage level VRH and the low voltage level VRL with the eight voltage dividing resistors RF110 to RF180 are used as reference voltages V110 to V170, and the voltage values of the input voltage VIN are simultaneously applied to the seven comparators C110 to C170. The comparison operation is performed. Output signals OUT110 to OUT170 obtained as digital signals as comparison results are divided into a high level and a low level, with a predetermined output signal as a boundary, according to the voltage level of the input voltage VIN. A 3-bit digital signal can be obtained by encoding the output signals OUT110 to OUT170.
[0003]
Each of the comparators C110 to C170 is the same circuit unit. Further, in order for each of the comparators C110 to C170 to perform the comparison operation, it is necessary to supply a predetermined bias current. When the parallel AD converter circuit performs an AD conversion operation, a predetermined bias current is supplied to all the comparators C110 to C170. Current consumption occurs for each comparator.
[0004]
[Patent Document 1]
JP 55-115724 A
[Patent Document 2]
JP-A-56-89128
[0005]
[Problems to be solved by the invention]
However, the input voltage VIN is an analog voltage, and the amount of voltage variation of the input voltage VIN in the AD conversion operation performed at every predetermined timing is limited. That is, in the AD conversion operation for the input voltage VIN that is an analog voltage signal, the voltage value of the input voltage VIN may be detected only by a comparator within a voltage range that may fluctuate at adjacent conversion timings. For this reason, even in a comparator having a voltage value in a voltage range that is not likely to be input at an adjacent conversion timing as a reference voltage, the conventional technique in which a bias current is constantly supplied is a comparator that is unnecessary for AD conversion operation. Unnecessary current consumption occurs, which is a problem.
[0006]
In addition to the AD conversion circuit, a similar problem may exist in a functional circuit that includes a plurality of circuit units and performs a circuit operation by supplying a bias current to each of the circuit units. That is, for example, for a functional circuit in which the operation state of each circuit unit is switched according to the bias current setting and the next operation state is determined according to the current operation state, it can be predicted in advance. It is sufficient to supply the bias current only to the circuit unit. However, in the prior art, the bias current is always supplied to all the circuit units, which causes unnecessary current consumption. is there.
[0007]
The present invention has been made to solve at least one of the problems of the prior art, and secures a necessary bias current in an AD converter circuit having a parallel AD converter and a functional circuit having a plurality of circuit units. Can reduce unnecessary bias current while maintaining circuit performance. A An object is to provide a D conversion circuit.
[0008]
[Means for Solving the Problems]
[0009]
[0010]
Contract Claim 1 The AD conversion circuit according to the present invention has a parallel AD conversion unit configured to include a plurality of comparators, a bias current supply unit that supplies a bias current to a comparator provided for each comparator, and a bias current A bias current setting terminal that is provided for each supply unit and sets a bias voltage for adjusting a bias current, and a resistance element that connects adjacent bias current setting terminals are provided.
[0011]
Claim 1 In the AD conversion circuit, a bias current is supplied to each of the plurality of comparators constituting the parallel AD conversion unit of the AD conversion circuit by the bias current supply unit. It is set according to the bias voltage to the bias current setting terminal provided for each.
[0012]
Thus, the bias current is determined for each bias current supply unit by setting the bias voltage for each bias current setting terminal, and the bias current can be adjusted for each circuit unit or each comparator. A bias current adapted to the operating state of the circuit unit or the comparator can be supplied. In addition, since the bias current setting terminals are connected by a resistive element, the bias current setting terminals between which the bias voltage is set and the bias current setting terminals where the bias voltage is not set are also determined from each bias voltage. The voltage via the resistance element is set. A bias current corresponding to the voltage value set at the bias current setting terminal can also be supplied to circuit units or comparators sandwiched between circuit units or comparators having different operating states.
[0013]
[0014]
Claims 2 An AD conversion circuit according to claim 1 In the AD converter circuit described in the above, a predetermined bias voltage is set for a bias current setting terminal from at least both ends including both ends to a predetermined position among three or more bias current setting terminals connected in series by a resistance element. It is characterized by that. Claims 3 An AD conversion circuit according to claim 1 In the AD converter circuit described in the above, a bias current setting terminal from at least both ends including at both ends to a predetermined position and a bias current setting terminal at an intermediate position among four or more bias current setting terminals connected in series by a resistive element. On the other hand, a predetermined bias voltage is set.
[0015]
Contract Claim 2 In the AD converter circuit, a bias current setting terminal for which a predetermined bias voltage is not set among three or more bias current setting terminals is , Contract Claim 3 In the AD converter circuit, a bias voltage is set via a resistive element directly connected in series for a bias current setting terminal to which a predetermined bias voltage is not set among four or more bias current setting terminals.
[0016]
Thus, since the bias current setting terminals are connected in series by the resistance element, the bias current setting terminals that are not set with the predetermined bias voltage sandwiched between the bias current setting terminals with the predetermined bias voltage set are respectively A voltage obtained by dividing the predetermined bias voltage by the resistance element is set. For a circuit unit or comparator sandwiched between circuit units or comparators having different operating states, an intermediate bias current between bias currents of a predetermined bias voltage can be supplied.
[0017]
If a predetermined bias voltage is set for the bias current setting terminals including both ends with respect to three or more bias current setting terminals, it is possible to supply three or more types of bias currents for each circuit unit or comparator. If a predetermined bias voltage is set for the bias current setting terminal including both ends and the bias current setting terminal at the intermediate position with respect to four or more bias current setting terminals, four or more types of bias currents are provided for each circuit unit or comparator. Can be supplied.
[0018]
Claims 4 An AD conversion circuit according to claim 1 Thru 3 The AD conversion circuit according to any one of the above, wherein each bias current setting terminal includes a switch unit that controls setting / non-setting of a bias voltage. Claims 5 An AD conversion circuit according to claim 1 Thru 4 The AD conversion circuit according to any one of the above, wherein two or more types of bias voltages having different voltage values are provided, and the switch unit is provided for each bias voltage. Thereby, the bias voltage can be set for each bias current setting terminal by controlling the switch unit.
[0019]
Claims 6 An AD conversion circuit according to claim 1 In the AD converter circuit described in the above, when two bias current setting terminals for setting two types of bias voltages having different voltage values and a bias current setting terminal at an intermediate position are connected in series by a resistor element, The offset voltage, which is set by the bias voltage and the apportioned voltage divided by the resistive element with respect to the bias current setting terminal at the intermediate position, caused by the difference in bias current between adjacent comparators is the voltage resolution in the AD converter circuit. It is characterized by being relatively small. As a result, the offset voltage between adjacent comparators is smaller than the voltage resolution in the AD conversion circuit, so that no erroneous conversion occurs in the AD conversion operation.
[0020]
Claims 7 An AD conversion circuit according to claim 1 The bias current setting of at least one first comparator in which the comparison operation is performed with respect to a reference voltage included in a predetermined voltage region including the voltage value of the input voltage among the plurality of comparators. For the terminal, a first set voltage is set, and for the bias current setting terminal of the second comparator excluding the first comparator and a predetermined number of intermediate comparators adjacent to the first comparator, The second set voltage is set.
[0021]
Claim 7 In the AD converter circuit, the first setting voltage is set to the bias current setting terminal of the first comparator, and the comparison operation is performed as a comparator included in a predetermined voltage region including the voltage value of the input voltage. A second set voltage is set to the bias current setting terminal of the second comparator. A bias voltage is applied to the bias current setting terminal of the intermediate comparator existing between the first and second comparators by a resistance element connecting the bias current terminals.
[0022]
As a result, the first comparator that performs the comparison operation with respect to the predetermined voltage region including the voltage value of the input voltage can be maintained in the normal comparison operation state by the first set voltage to ensure a quick comparison operation. it can. In addition, since it is not necessary to maintain a normal comparison operation state for the second comparator that performs a comparison operation with respect to a voltage value outside the predetermined voltage region, the bias current is reduced by the second set voltage to save power It can be.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention A A specific embodiment of the D conversion circuit will be described in detail with reference to the drawings based on FIGS.
[0024]
FIG. 1 is a circuit block diagram of an AD conversion circuit according to an embodiment of the present invention. As a comparator for AD conversion, it is a parallel AD conversion circuit provided with 15 comparators C1 to C15 in parallel. Here, the comparators C1 to C15 are differential comparators described later.
[0025]
An input terminal (VIN) to which an input voltage VIN is input is connected to one input terminal (Vin) of each of the comparators C1 to C15. Further, reference voltages V1 to V15 obtained by equally dividing the input voltage range set as the low voltage level VRL to the high voltage level VRH into 16 equal parts are input to the reference voltage terminal (Ref) which is the other input terminal. Output signals of the comparators C1 to C15 are connected to output terminals (OUT1) to (OUT15). The reference voltages V1 to V15 are generated by voltage dividing resistors RF1 to RF16 sandwiched between the input voltage ranges VRH and VRL.
[0026]
Each of the comparators C1 to C15 compares the magnitude relationship of the input voltage VIN with respect to the reference voltages V1 to V15, and outputs the comparison results as output signals OUT1 to OUT15. Therefore, as shown in FIG. 2, it is detected which of the voltage ranges obtained by dividing the input voltage VIN from the voltage levels VRL to V1 to V15 to VRH is 16. Since each voltage range is identified by the output codes 0 to 15, a 4-bit digital signal can be output as an AD conversion result by encoding the output codes 0 to 15.
[0027]
Each of the comparators C1 to C15 includes bias current supply circuits B1 to B15, and supplies a bias current to the comparators. Each of the bias current supply circuits B1 to B15 is provided with a bias current setting terminal (Vb), and is individually provided in each of the switch units SW-A and SW-B as the bias voltage lines N1 to N15. Connected to one side of the circuit. Further, the bias voltage lines N1 to N15 are connected to each other by resistance elements R1 to R14 between adjacent wirings, and all the bias voltage lines N1 to N15 are connected in series. The other ends of the switch circuits constituting the switch units SW-A and SW-B are grouped for each switch unit and connected to bias voltage terminals (VA) and (VB), respectively.
[0028]
In FIG. 1, a pair of comparators C21 to C35 and bias current supply circuits B21 to B35 are further provided in parallel. The comparators C21 to C35 are differential comparators similar to the comparators C1 to C15, and the input voltage VIN and the reference voltage are input to the input terminal (Vin) terminal and the reference voltage terminal (Ref) similarly to the comparators C1 to C15. V1 to V15 are input. The output signal is input to the bias voltage control circuit BC, and control signals CTA and CTB for performing opening / closing control of each switch circuit of the switch units SW-A and SW-B are output based on a conversion table described later. Similarly to the bias current supply circuits B1 to B15, the bias current supply circuits B21 to B35 supply a bias current to the comparators C21 to C35. In the bias current supply circuits B21 to B35, a common bias voltage V0 is set to the bias current setting terminal (Vb), and the same bias current is supplied between the comparators. The comparators C21 to C35 function as monitors for setting bias currents for the AD conversion comparators C1 to C15. Therefore, the bias current supplied to the comparators C21 to C35 is generally limited to the minimum necessary current level that allows the monitoring operation.
[0029]
FIG. 3 is a circuit diagram of a circuit for generating the bias voltages VA and VB supplied to the bias voltage terminals (VA) and (VB). The generation circuits for the bias voltages VA and VB have the same circuit configuration. The current sources IA and IB are connected to the drain terminals (NA) and (NB) of the NMOS transistors MA and MB connected between the drain and gate terminals, and the source terminals are connected to the ground voltage. The drain / gate terminals (NA) and (NB) are biased to a predetermined voltage in accordance with the current values IA and IB supplied from the current sources IA and IB. The predetermined voltages are received by the buffer circuits BA and BB, and the bias voltages VA and VB are output. In FIG. 3, the buffer circuits BA and BB are configured as voltage follower circuits, and the bias voltages VA and VB are equivalent to the predetermined voltages at the drain / gate terminals (NA) and (NB).
[0030]
Here, specific circuit configurations of the differential comparator Cx and the bias current supply circuit Bx used in the AD conversion circuit of FIG. 1 will be described with reference to FIG. 4, and the circuit operation will be described with reference to FIG.
[0031]
The comparator Cx includes a differential amplifying unit 10 and a synchronizing unit 20 that outputs the output signal in synchronization with the clock signals C1 and C2. The differential amplifying unit 10 includes NMOS transistors M1 and M2, which are differential pair transistors for differential comparison between the input terminal (Vin) and the reference voltage terminal (Ref) for differential comparison, and active on the drain side thereof. And a load circuit having a current mirror circuit configuration including PMOS transistors M3 and M4 connected as loads.
[0032]
The comparison result signal DO from the differential amplifier 10 is output from a connection point DO between the transistor M2 and the transistor M4 and input to the synchronization unit 20. In the synchronization unit 20, the comparison result signal DO input via the switch circuit SW1 is latched by a latch unit having a two-stage inverter gate configuration configured by conduction of the switch circuit SW2. The switch circuits SW1 and SW2 are controlled by complementary clock signals C1 and C2, and the comparison result signal DO captured when the switch circuit SW1 is turned on by the clock signal C1 is turned on by the clock signal C2. And latched. The output signal is output from an output terminal (OUTx) via an inverter gate from the latch unit.
[0033]
The bias current supply circuit Bx includes an NMOS transistor M5 connected between the connection point of the NMOS transistors M1 and M2 and the ground voltage. The gate terminal of the transistor M5 is connected to the bias current setting terminal (Vb). The NMOS transistor M5 is turned on in accordance with a bias voltage at a predetermined voltage level from the bias current setting terminal (Vb), so that a predetermined bias current is supplied to the differential amplifier unit 10. By applying bias voltages VA and VB to the gate terminal of the NMOS transistor M5, the NMOS transistor M5 and the NMOS transistors MA and MB in the circuit for generating the bias voltages VA and VB constitute a current mirror circuit, and each current source IA , A bias current corresponding to the current value supplied from IB is supplied from the NMOS transistor M5 to the differential amplifier section 10.
[0034]
The circuit operation of the comparator Cx will be described based on the operation waveform of FIG. The logical level of the comparison result signal DO is inverted according to the magnitude relationship between the reference voltage Vx set at the reference voltage terminal (Ref) and the input voltage VIN input at the input terminal (Vin). That is, when the input voltage VIN is lower than the reference voltage Vx, a low level voltage is output, and when the input voltage VIN is higher than the reference voltage Vx, a high level voltage is output. The comparison result signal DO is captured and latched in the synchronization unit 20 by complementary clock signals C1 and C2.
[0035]
Assuming that the switch circuits SW1 and SW2 are turned on by the high level signals of the clock signals C1 and C2, the comparison result signal DO taken into the synchronization unit 20 due to the high level transition of the clock signal C1 is a two-stage inverter gate. Via the output terminal (OUTx). Thereafter, the logic levels of the clock signals C1 and C2 are inverted, and the logic level of the clock signal C2 becomes a high level, so that the fetched comparison result signal DO is latched in the latch unit. Therefore, the same comparison result signal DO is output to the output terminal (OUTx) from the high level transition of the clock signal C1 to the high level period of the clock signal C2. The signal output from the output terminal (OUTx) is updated at every high level transition of the clock signal C1. Thereby, AD conversion operation | movement synchronized with the clock signals C1 and C2 is performed.
[0036]
Next, setting of the bias current supplied to each of the comparators C1 to C15 will be described. The supply of the bias current is performed by setting a bias voltage to the bias current supply circuits B1 to B15. Here, the setting of the bias voltage is performed by controlling the conduction of the individual switch circuits in the switch units SW-A and SW-B in accordance with the control signals CTA and CTB output from the bias voltage control circuit BC. . A summary of this control is shown in FIG.
[0037]
In the control of the bias current shown in FIG. 6, when the AD conversion operation is performed every predetermined period such as a clock signal, the allowable voltage fluctuation range of the input voltage VIN between adjacent AD conversion operations is set to output codes 0 to This is performed based on the premise that there are 15 output codes (see FIG. 2). That is, the voltage value of the input voltage VIN in the AD conversion operation at a certain point in time is a voltage fluctuation for one comparator as compared with the input voltage VIN in the AD conversion operation performed in the AD conversion operation one cycle before. It is based on the premise that This premise is that the input voltage VIN is an analog voltage signal that continuously fluctuates. Therefore, it is possible to make the conditions appropriate by appropriately adjusting the voltage width set as the output code, the period of the AD conversion operation, and the like. Needless to say, you can.
[0038]
If the input voltage VIN is in the voltage range of the voltage levels V8 to V9 during the AD conversion operation, the voltage level that may fluctuate as the input voltage VIN in the next conversion operation is a voltage expanded by one output code. Possible levels are V7-V10.
[0039]
Therefore, among the comparators C7 to C10 provided for the voltage levels V7 to V10, a sufficient bias current is supplied to the comparators C8 and C9 by setting the bias voltage to the comparators C8 and C9 to the bias voltage VB. Is preferred.
[0040]
On the other hand, for the comparators C1 to C5 and C12 to C15 provided for the voltage levels VRL to V5 and V12 to VRH that are not likely to vary as the input voltage VIN in the next conversion operation, the bias current Can be limited. This is because there is no possibility that the output signals OUT1 to OUT5 and OUT12 to OUT15 of the comparators C1 to C5 and C12 to C15 are inverted in the next conversion operation, and it is not necessary to ensure a rapid circuit operation. By setting the bias voltage to the comparators C1 to C5 and C12 to C15 to a bias voltage VA that is lower than the bias voltage VB, the bias current to the comparators C1 to C5 and C12 to C15 is limited. Current value. Current consumption in the comparators C1 to C5 and C12 to C15 can be reduced.
[0041]
Here, the bias voltage is not directly set for the comparators C6 and C7, and C10 and C11 from the outside. Bias voltage lines N1 to N15 connected to the bias current setting terminals (Vb) of the bias current supply circuits B1 to B15 are connected in series by resistance elements R1 to R15. For this reason, the bias voltage set for the comparators C6, C7, and C10, C11 is a voltage value obtained by dividing the bias voltages VA and VB by the resistance elements R5 to R7 and R9 to R11. The operation is performed with an intermediate bias current supplied.
[0042]
With the bias current setting described above, a more limited current value is supplied to the comparators C7 and C10 among the comparators C7 to C10 within the range of the voltage fluctuation of the input voltage VIN during the AD conversion operation. It becomes. However, it can be determined by the two inner comparators C8 and C9 among the four comparators C7 to C10 whether the input voltage VIN is in the voltage range V7 to V10, which is the range of voltage fluctuation. . Therefore, it is only necessary to supply a sufficient bias current only to the comparators C8 and C9 among the comparators C7 to C10.
[0043]
These settings are made by providing comparators C21 to C35 having the same configuration as the comparators C1 to C15 and outputting the same comparison results, and inputting these output signals OUT21 to OUT35 to the bias voltage control circuit BC. Is called. That is, based on the AD conversion result at a certain time, supply of the bias current to each of the comparators C1 to C15 in the next AD conversion operation can be set. This setting may be performed during one cycle of the clock signals C1 and C2, and it is sufficient that the operation performance is lower than that of the comparators C1 to C15 that perform the AD conversion operation. Accordingly, the bias current supplied to the comparators C21 to C35 can be limited, and the comparators C21 to C35 can be operated with low current consumption.
[0044]
The bias current to each of the comparators C1 to C15 described above is illustrated in FIG. In FIG. 7, the bias currents supplied by the bias voltages VA and VB are 20 μA and 50 μA, respectively. The horizontal axis shows the types of the comparators C1 to C15, and the vertical axis shows the bias current.
[0045]
A bias current of 50 μA is supplied to the comparators C8 and C9 to which the bias voltage VB is set. On the other hand, a bias current of 20 μA is supplied to the comparators C1 to C5 and C12 to C15 to which the bias voltage VA is set. For the comparators C6, C7, and C10, C11 for which the bias voltage is not directly set, the bias voltages VA, VB are equally divided, so that the bias current is also equally divided. . Therefore, a bias current of 30 μA is supplied to the comparators C6 and C11, and a bias current of 40 μA is supplied to the comparators C7 and C10.
[0046]
It should be noted here that there is an offset voltage due to a difference in bias current supplied to the comparator. It is generally known that when the bias currents supplied to the two comparators are different, an offset voltage is generated between the comparators. This state is shown in FIG. It can be seen that the offset voltage increases according to the bias current difference. If this offset voltage exceeds one output code, a correct output code cannot be output and a miscode occurs.
[0047]
In the embodiment of FIG. 1, the voltage obtained by dividing the input voltage range from the low voltage level VRL to the high voltage level VRH by 16 is the voltage range of one output code. For example, when VRH = 2V and VRL = 0.5V, the voltage range of one output code is (2-0.5) ÷ 16≈94 mV. The offset voltage at which no miscode occurs needs to be 94 mV or less. From FIG. 8, it is necessary that the bias current difference between adjacent comparators is about 15 μA or less.
[0048]
Therefore, an embodiment in which there are two comparators C6, C7, C10, and C11 sandwiched between comparators C1 to C5, C12 to C15, and C8 and C9 whose bias currents are set to 20 μA and 50 μA ( In FIG. 6, the bias current difference between adjacent comparators is 10 μA. From FIG. 8, the offset voltage is 62.5 mV. An offset voltage of 94 mV or less at which a miscode occurs is generated, and a miscode accompanying an AD conversion operation does not occur.
[0049]
Here, if the number of comparators for which the bias voltage is not set directly from the outside is further increased from two, the bias current difference is further reduced, and the offset voltage can be improved.
[0050]
If adjustment is made according to the low voltage level VRL, the high voltage level VRH, and the number of output codes, it is possible to appropriately set the voltage range for one output code and prevent the occurrence of a miscode. For a comparator that is within the range of the voltage fluctuation amount of the input voltage VIN between AD conversion operations, a sufficient bias current is secured to maintain the conversion speed, and a comparator that is outside the voltage fluctuation range of the input voltage VIN is used. On the other hand, the bias current is limited. The low current consumption operation can be performed together with the comparators C21 to C35 in which the low bias current operation is performed. At the same time, the occurrence of an offset voltage between the comparators can be suppressed, and miscoding in the AD conversion operation can be prevented.
[0051]
In the above description, the case where the input voltage VIN is in the voltage range of the voltage levels V8 to V9 has been described as an example at the time of the AD conversion operation, but it can be set similarly in the case of other voltage levels. Needless to say.
[0052]
FIG. 9 shows a modification of the AD conversion circuit according to the embodiment of the present invention. In this configuration, the comparators C21 to C35 and the bias current supply circuits B21 to B35 in FIG. 1 are omitted. Instead of the output signals OUT21 to OUT35 of the comparators C21 to C35, the output signals OUT1 to OUT15 of the comparators C1 to C15 are input to the bias voltage control circuit BC. In FIG. 1, comparators C1 to C15 and comparators C21 to C35 are similar differential comparators, and input similar signals (input voltage VIN and reference voltages V1 to V15). This is possible. In addition, a switch unit SW-C controlled by a control signal CTC with respect to the third bias voltage VC is provided.
[0053]
Since the switch section SW-C is provided in addition to the switch sections SW-A and SW-B and the bias voltage VC is set to the bias voltage lines N1 to N15 selected by the control signal CTC, three types of biases are provided. The voltages VA to VC can be set. By setting the bias voltages VA to VC to the bias voltage lines N1 and N15 at both ends from the bias voltage lines to the predetermined position and the intermediate bias voltage lines, the bias voltage lines to which the bias voltages VA to VC are not set directly are set. Including four or more types of bias currents can be supplied.
[0054]
Further, since the comparators C21 to C35 and the bias current supply circuits B21 to B35 are not provided, a further low power consumption operation can be performed. In addition, the circuit scale can be advantageously reduced.
[0055]
As described in detail above, the present embodiment A In the D converter circuit, since the bias current setting terminals (Vb) are connected in series by the resistance elements R1 to R15, the bias current setting terminals (Vb) are sandwiched between the bias current setting terminals (Vb) to which the predetermined bias voltages VA and VB are set. For the bias current setting terminal (Vb) to which the predetermined bias voltages VA and VB are not set, voltages obtained by dividing the predetermined bias voltages VA and VB by the resistance elements R1 to R15 are set. The comparators C1 to C15 sandwiched between the comparators C1 to C15, which are comparators having different operating states, can supply an intermediate bias current between bias currents of predetermined bias voltages VA and VB.
[0056]
Comparing C8 and C9 as an example of a first comparator that performs a comparison operation on a predetermined voltage region including the voltage value of the input voltage VIN in a voltage range in which the voltage fluctuates during the next AD conversion operation. Can be maintained in the normal comparison operation state by the bias voltage VB which is the first set voltage to ensure a quick comparison operation. In addition, the comparators C1 to C5 and C12 to C15 as examples of the second comparator that performs the comparison operation with respect to the voltage value outside the predetermined voltage range do not need to be maintained in the normal comparison operation state. The bias current can be reduced by the bias voltage VA which is the set voltage, and a power saving state can be obtained.
[0057]
For a comparator within the range of the voltage fluctuation amount of the input voltage VIN during the AD conversion operation, a sufficient bias current is secured to maintain the conversion speed, and for a comparator outside the voltage fluctuation range of the input voltage VIN. Therefore, the bias current is limited, and the low current consumption operation can be performed together with the comparators C21 to C35 in which the low bias current operation is performed. At the same time, the occurrence of an offset voltage between the comparators can be suppressed, and miscoding in the AD conversion operation can be prevented.
[0058]
Here, prevention of a miscode in the AD conversion operation is realized by adjusting according to the low voltage level VRL, the high voltage level VRH, the number of output codes, and appropriately setting the voltage range for one output code. Can do.
[0059]
If predetermined bias voltages VA and VB are set to the bias current setting terminal (Vb) including both ends with respect to three or more bias current setting terminals (Vb), three or more types of bias currents are provided for each of the comparators C1 to C15. Can be supplied. If predetermined bias voltages VA to VC are set to the bias current setting terminal (Vb) including both ends and the bias current setting terminal (Vb) at the intermediate position with respect to four or more bias current setting terminals (Vb), the comparator Four or more types of bias currents can be supplied for each of C1 to C15.
[0060]
The bias voltages VA to VC can be set by controlling the switch unit with the control signals CTA to CTC.
[0061]
Further, the offset voltage between the adjacent comparators C1 to C15 can be set smaller than the voltage resolution in the AD conversion circuit, and no erroneous conversion occurs in the AD conversion operation.
[0062]
The present invention is not limited to the above-described embodiment, and it goes without saying that various improvements and modifications can be made without departing from the spirit of the present invention.
For example, in the present embodiment, the AD conversion circuit is described as an example of the functional circuit, but the present invention is not limited to this. Even in a functional circuit other than the AD converter circuit, for example, a functional circuit in which the operating state of each circuit unit is switched according to the setting of the bias current and the next operating state is determined according to the current operating state. On the other hand, a bias current capable of ensuring sufficient circuit operation is supplied only to a circuit unit whose circuit operation is predicted in the next operation in advance, and the bias current is limited in a circuit unit where circuit operation is not predicted. The present invention which performs a low current consumption operation can be applied. Circuit units that are not directly related to circuit operation can be operated with low current consumption while maintaining circuit operation performance.
[0063]
Further, although two or three types of bias voltages VA to VC for setting the bias current have been described as examples, it is possible to set four or more types of bias voltages by further providing a switch unit.
[0064]
Also, the case where there are two comparators sandwiched between the comparators to which the bias voltages VA and VB are set has been described. However, the low voltage level VRL and the high voltage level VRH are further increased according to the offset voltage accompanying the bias current difference. The bias current difference can be adjusted by appropriately setting the number of comparators according to the voltage range for one output code corresponding to the number of output codes. Thereby, the offset voltage between the comparators can be adjusted.
[0065]
Here, means for solving the problems in the prior art based on the technical idea of the present invention are listed below.
(Supplementary note 1) A current supply circuit for supplying a bias current to a functional circuit including a plurality of circuit units,
A bias current supply unit that is provided for each circuit unit and supplies a bias current;
A bias current setting terminal that is provided for each of the bias current supply units and sets a bias voltage for adjusting the bias current;
A current supply circuit comprising: a resistance element that connects adjacent bias current setting terminals.
(Supplementary Note 2) Among the three or more bias current setting terminals connected in series by the resistance element, a predetermined bias voltage is set for a bias current setting terminal from at least both ends including the both ends to a predetermined position. The current supply circuit according to appendix 1, wherein the current supply circuit is characterized.
(Supplementary Note 3) Of the four or more bias current setting terminals connected in series by the resistive element, with respect to a bias current setting terminal from at least both ends including at both ends to a predetermined position and a bias current setting terminal at an intermediate position The current supply circuit according to appendix 1, wherein a predetermined bias voltage is set.
(Supplementary note 4) The current supply circuit according to any one of supplementary notes 1 to 3, further comprising a switch unit that controls setting / non-setting of the bias voltage for each bias current setting terminal.
(Supplementary note 5) The current according to at least one of Supplementary notes 1 to 4, wherein two or more types of the bias voltages having different voltage values are provided, and the switch unit is provided for each bias voltage. Supply circuit.
(Additional remark 6) It is an AD conversion circuit which has a parallel type AD conversion part comprised including a some comparator, Comprising:
A bias current supply unit provided for each comparator, for supplying a bias current to the comparator;
A bias current setting terminal that is provided for each of the bias current supply units and sets a bias voltage for adjusting the bias current;
An AD conversion circuit comprising: a resistance element connecting adjacent bias current setting terminals.
(Supplementary Note 7) Of the three or more bias current setting terminals connected in series by the resistance element, setting a predetermined bias voltage for bias current setting terminals from at least both ends including both ends to a predetermined position The AD conversion circuit according to appendix 6, which is characterized.
(Supplementary Note 8) Among the four or more bias current setting terminals connected in series by the resistance element, with respect to a bias current setting terminal from at least both ends including the both ends to a predetermined position and a bias current setting terminal at an intermediate position The AD converter circuit according to appendix 6, wherein a predetermined bias voltage is set.
(Supplementary note 9) The AD conversion circuit according to any one of supplementary notes 6 to 8, further comprising a switch unit configured to control setting / non-setting of the bias voltage for each bias current setting terminal.
(Supplementary Note 10) The AD according to any one of Supplementary Notes 6 to 9, wherein two or more types of bias voltages having different voltage values are provided, and the switch unit is provided for each bias voltage. Conversion circuit.
(Supplementary Note 11) When the two bias current setting terminals for setting two types of the bias voltages having different voltage values and the bias current setting terminal at an intermediate position are connected in series by the resistance element, An offset voltage caused by the difference in bias current between adjacent comparators, which is set by a bias voltage and an apportioned voltage divided by the resistance element with respect to the bias current setting terminal at the intermediate position, is the AD conversion. The AD converter circuit according to appendix 6, which is smaller than the voltage resolution in the circuit.
(Supplementary Note 12) When the two bias current setting terminals for setting two types of bias voltages having different voltage values and the bias current setting terminal at an intermediate position are connected in series by the resistance element, Appendix 6 wherein the offset voltage caused by the bias current difference between the comparators set by the two types of bias voltages having different voltage values is larger than the voltage resolution in the AD converter circuit. The AD conversion circuit described in 1.
(Supplementary Note 13) Among the plurality of comparators,
A comparison operation is performed with respect to a reference voltage included in a predetermined voltage region including a voltage value of the input voltage. A first setting voltage is set for the bias current setting terminal of at least one first comparator,
A second set voltage is set for the bias current setting terminal of the second comparator excluding the first comparator and a predetermined number of intermediate comparators adjacent to the first comparator. The AD conversion circuit according to appendix 6, which is characterized.
(Supplementary Note 14) The predetermined number of the intermediate comparators is
The intermediate comparator has an apportioned voltage between the first set voltage and the second set voltage, which is apportioned by the resistor element connecting the bias current setting terminals of the first and second comparators in series. The AD converter circuit according to appendix 6, wherein an offset voltage caused by the bias current difference set between the bias current setting terminals is a number smaller than a voltage resolution in the AD converter circuit. .
[0066]
【The invention's effect】
According to the present invention, in an AD conversion circuit having a parallel AD conversion unit including a plurality of comparators, a circuit that ensures a necessary bias current for a comparator whose comparison state changes during an AD conversion operation. For comparators that maintain performance but do not change the comparison state, the bias current can be reduced. A A D conversion circuit can be provided.
[Brief description of the drawings]
FIG. 1 is a circuit block diagram of an embodiment.
FIG. 2 is an AD conversion table in the circuit configuration of the embodiment.
FIG. 3 is a circuit diagram of a bias voltage generation circuit.
FIG. 4 is a circuit diagram of a differential comparator.
FIG. 5 is an operation waveform diagram of the differential comparator.
FIG. 6 is a setting table of bias voltages to each comparator.
FIG. 7 is a diagram illustrating bias currents of the respective comparators when the input voltage VIN is in a voltage region of voltages V8 to V9.
FIG. 8 is a diagram illustrating a relationship of an offset voltage with respect to a bias current difference between comparators.
FIG. 9 is a circuit block diagram showing a modification of the embodiment.
FIG. 10 is a circuit diagram showing a conventional AD converter circuit.
[Explanation of symbols]
(Vb) Bias current setting terminal
B1 to B15, B21 to B35
Bias current supply circuit
BC Bias voltage control circuit
C1 to C15, C21 to C35
comparator
CTA, CTB, CTC control signal
N1 to N15 Bias voltage line
R1 to R14 resistance elements
RF1 to RF16 Voltage divider resistor
SW-A, SW-B, SW-C
Switch part
OUT1 to OUT15, OUT21 to OUT35
Output signal
V1 to V15 reference voltage
VA, VB, VC Bias voltage
VIN input voltage
VRH high voltage level
VRL low voltage level

Claims (7)

An AD converter circuit having a parallel AD converter configured to include a plurality of comparators,
A bias current supply unit provided for each comparator, for supplying a bias current to the comparator;
A bias current setting terminal that is provided for each of the bias current supply units and sets a bias voltage for adjusting the bias current;
An AD conversion circuit comprising: a resistance element connecting adjacent bias current setting terminals. A predetermined bias voltage is set to a bias current setting terminal from at least both ends including at least both ends to a predetermined position among the three or more bias current setting terminals connected in series by the resistance element. Item 2. The AD conversion circuit according to Item 1 . Among the four or more bias current setting terminals connected in series by the resistance element, a predetermined bias voltage is applied to a bias current setting terminal from both ends including at least both ends to a predetermined position and a bias current setting terminal at an intermediate position. The AD conversion circuit according to claim 1 , wherein: Wherein each bias current setting terminal, AD conversion circuit according to at least any one of claims 1 to 3, characterized in that a switch unit for setting and control of non-setting of the bias voltage. Comprising two or more different the bias voltage of the voltage value with each other, wherein the switch unit, AD conversion circuit according to at least any one of claims 1 to 4, characterized in that provided for each of the bias voltage. When the two bias current setting terminals for setting two types of bias voltages having different voltage values and the bias current setting terminal at an intermediate position are connected in series by the resistance element, the bias voltage, The offset voltage caused by the bias current difference between adjacent comparators set by the apportioned voltage divided by the resistance element with respect to the bias current setting terminal at the intermediate position is a voltage resolution in the AD converter circuit. The AD conversion circuit according to claim 1 , wherein the AD conversion circuit is smaller than the AD conversion circuit. Among the plurality of comparators,
A comparison operation is performed with respect to a reference voltage included in a predetermined voltage region including a voltage value of the input voltage. A first setting voltage is set for the bias current setting terminal of at least one first comparator,
A second set voltage is set for the bias current setting terminal of the second comparator excluding the first comparator and a predetermined number of intermediate comparators adjacent to the first comparator. The AD conversion circuit according to claim 1 , wherein:

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