JP4091520B2 - Frequency synthesizer - Google Patents

Description

  The present invention relates to a frequency synthesizer used in a wireless device such as a mobile communication device.

  This type of conventional frequency synthesizer shortens the time until the reference signal and phase are locked by switching the frequency (hereinafter referred to as lock-up time). The loop band can be changed by switching the loop band with a switch in the switching transient state and the steady state when the phase is locked, or by adding or using a buffer circuit or charge pump circuit controlled to operate only in the transient state. Speeding up.

  FIG. 4 is a circuit diagram showing an example of a conventional frequency synthesizer. In FIG. 4, 1 is a voltage controlled oscillator, 2 is a variable frequency divider, 3 is a phase comparator that receives the reference signal and the output signal of the variable frequency divider 2, 4 is a main buffer circuit that operates in a steady state, 7 Is a sub-buffer circuit that operates only in a transient state, and 12 is a loop filter.

  The output of the voltage controlled oscillator 1 is branched into two and one is input to the variable frequency divider 2. The phase comparator 3 inputs the reference signal and the signal from the variable frequency divider 2 and outputs them to the main buffer circuit 4 and the sub buffer circuit 7. The outputs of the main buffer circuit 4 and the sub buffer circuit 7 are input to input terminals 14 and 15 of the loop filter 12, respectively. The loop filter 12 includes a lag lead filter 13, and the lag lead filter 13 includes a resistor 17, a resistor 18, and a capacitor 19. One of the resistors 17 is connected to the input terminal 14, and the other is connected to the resistor 18 and the output terminal. 16 and the other end of the resistor 18 is grounded via a capacitor 19. The resistor 18 is divided into two resistors 18 a and 18 b, and the divided contact is connected to the input terminal 15.

  The main buffer circuit 4 includes a Pch MOS transistor 5 and an Nch MOS transistor 6, the source of the Pch MOS transistor 5 is connected to the power supply, the gate is connected to the gate of the Nch MOS transistor 6, and is connected to the phase comparator 3, and the drain is NchMOS. It is connected to the drain of the transistor 6 and to the input terminal 14, and the source of the Nch MOS transistor 6 is grounded.

The sub-buffer circuit 7 includes a Pch MOS transistor 8, an Nch MOS transistor 9, a switch 10 and a switch 11. The source of the Pch MOS transistor 8 is connected to a power source, and the gate is connected to a switch 10 whose input is switched to a phase comparator and a power source. The drain is connected to the drain of the Nch MOS transistor 9 and connected to the input terminal 14, the source of the Nch MOS transistor 9 is grounded, and the gate is connected to the phase comparator 3 and the switch 11 whose input is switched to the ground. is there.
Japanese Patent Laid-Open No. 5-48454

  However, in the frequency synthesizer having such a configuration, when an exclusive logic type phase comparator is used, a phenomenon occurs in which the frequency in the convergence process is once again separated from the frequency of the convergence setting due to the discontinuity at the time of switching the loop band, As a result, there is a problem that the lock-up time becomes long.

  Hereinafter, it demonstrates using drawing. In FIG. 4, the voltage controlled oscillator 1 outputs a frequency corresponding to the input voltage from the loop filter 12, is input to the variable frequency divider 2, and the signal divided by the variable frequency divider 2 is sent to the phase comparator 3. Entered. In the case of a frequency synthesizer using an exclusive logic type phase comparator, the phase comparator 3 outputs a phase difference signal obtained by comparing the divided signal and the reference signal as a duty ratio of a continuous rectangular wave.

  FIG. 5 is a timing chart showing the operation of the exclusive logic type phase comparator. The exclusive logic type phase comparator divides the reference signal and the frequency-divided signal by 2, respectively, and outputs an exclusive OR (EXOR). The output signal is a continuous rectangular wave, and the duty ratio is a phase difference signal.

  The phase difference signal is input to the loop filter 12 through each buffer circuit. The loop filter 12 smoothes the rectangular wave of the phase difference signal and outputs it as an average voltage to the voltage controlled oscillator 1 to constitute a phase locked loop.

  As can be seen from the operation described above, in the case of a frequency synthesizer using an exclusive logic type phase comparator, the phase of the divided signal is a value determined by the frequency characteristic with respect to the input voltage of the voltage controlled oscillator from the phase of the reference signal. Is fixed.

  In order to shorten the lock-up time of the frequency synthesizer, it is necessary to widen the loop band. However, if the loop band is widened, phase noise (hereinafter referred to as C / N) deteriorates. Therefore, the frequency synthesizer shown in FIG. 4 operates the sub-buffer circuit 7 only in a transient state until the phase is switched by switching the frequency, thereby widening the loop band and shortening the lock-up time.

  However, since the input to the loop filter 12 becomes discontinuous at the time of switching the loop band, in the case of a rectangular wave having a continuous phase difference signal, a change in average voltage becomes large, and voltage control that outputs a frequency according to the voltage. The frequency of the oscillator 1 is moved away from the target frequency, and the lockup time becomes longer.

  Hereinafter, the operation will be described in detail. Before switching the loop band, both the main buffer circuit 4 and the sub buffer circuit 7 output, so the loop filter 12 has a time constant due to the resistor 18b and the capacitor 19, and the loop band is widened. The C / N is degraded but the response is fast. .

  After switching the loop band, the output of the sub-buffer circuit 7 is opened and only the main buffer circuit 4 is output, so that the resistors 17 and 18 and the capacitor 19 are effective in the loop filter 12, and the loop band is narrowed by this time constant. The response becomes slower but the C / N is improved.

  The average voltage that is output after being smoothed by a filter comprising a resistor and a capacitor is determined by the amount of charge that is charged and discharged to the capacitor through the resistor. The resistance value is equivalently changed before and after the loop band switching. For this reason, the current charged and discharged by the rectangular wave changes and the average voltage changes.

  FIG. 6 shows input / output signals of the loop filter 12 when the loop band is switched. The average voltage output from the loop filter 12 changes from a certain initial value so as to become a target frequency set by the voltage controlled oscillator 1. In order to shorten the lock-up time, the loop band is switched when the value approaches the steady state to some extent.

  Since the signal input from the sub-buffer circuit 7 disappears at the time of switching and the circuit is opened, the amount of charge charged and discharged to the capacitor 19 decreases, and the average voltage changes in the direction opposite to the direction of convergence immediately after the switching timing.

  This change is fed back in the loop system and operates in the direction of convergence again, but after switching it is a narrow loop band, and the amount of change in the average voltage is large, so it takes time to converge again. become longer.

  The present invention is directed to solving the problems of the prior art, and an object of the present invention is to provide a frequency synthesizer that can reduce the lock-up time with a simple configuration.

To achieve this object, a frequency synthesizer according to claim 1 of the present invention includes a voltage-controlled oscillator whose output frequency is controlled by an applied voltage, and a variable that divides the output frequency signal of the voltage-controlled oscillator. input a frequency divider, and exclusive type phase comparator for outputting a signal corresponding to the phase difference by comparing the phase of the divided signal and the reference signal of the variable frequency divider, a signal output of the phase comparator At least three buffer circuits, and a loop filter that smoothes the input from the buffer circuit and outputs it to the voltage controlled oscillator, wherein the at least three buffer circuits are configured by inverters of MOS transistors, and the phase comparison A main buffer circuit that outputs a signal corresponding to the phase difference signal output from the device, and a MOS transistor inverter having a switch at the input end. A first sub-buffer circuit configured to output a signal corresponding to the phase difference signal output from the phase comparator in a transient state during frequency switching, and an output current value at the output terminal having a switch at the input terminal Comprising a second sub-buffer circuit that outputs a signal corresponding to the phase difference signal output from the phase comparator in a transient state at the time of frequency switching. The loop filter has one end connected to the output end of the main buffer circuit and the other end connected to the control input end of the voltage controlled oscillator, and the other end of the first resistor connected to one end. A lag lead filter having a second resistor and a capacitor having one end connected to the other end of the second resistor and the other end grounded, and the second resistor being divided into two The divided contact was split, at least two of the first, connects the output terminal of the second sub-buffer circuit, in the course of phase from the transient state to lock the phase shifts into locked steady state, the current capacity Control is performed to stop in the order from the first sub-buffer circuit to the second sub-buffer circuit from the larger to the smaller .

A frequency synthesizer according to a second aspect is the frequency synthesizer according to the first aspect, wherein the first and second sub-buffer circuits are replaced with a charge pump circuit capable of changing a current value, and the loop filter includes a first synthesizer. a capacitor which is grounded at the other end to connect the divided contact and one end of a second resistor, in the process of transition from the transient state to the steady state for locking the phase, have small current value of the charge pump circuit stepwise values and performing control to switch to.
The frequency synthesizer according to claim 3 is a voltage-controlled oscillator whose output frequency is controlled by an applied voltage, a variable frequency divider that divides an output frequency signal of the voltage-controlled oscillator, and the variable frequency divider An exclusive logic type phase comparator that outputs a signal corresponding to the phase difference between the frequency-divided signal and the reference signal, at least three buffer circuits that input a signal output from the phase comparator, and an input from the buffer circuit A loop filter for smoothing and outputting to the voltage controlled oscillator, wherein the at least three buffer circuits output a signal corresponding to the phase difference signal output from the phase comparator, and an input terminal A first sub-buffer circuit that outputs a signal corresponding to the phase difference signal in a transient state at the time of frequency switching, and a switch at the input terminal for output And a second sub-buffer circuit that outputs a signal corresponding to the phase difference signal to a transient state at the time of frequency switching, and the loop filter has one end output from the main buffer circuit. A first resistor having a second end connected to the control input of the voltage controlled oscillator, a second resistor having a second end connected to the other end of the first resistor, and the second resistor. An output of at least two or more of the first and second sub-buffer circuits is formed by a capacitor having one end connected to the other end and the other end grounded, and the second resistor divided into two. In the process of transitioning from the transient state where the phase is locked and the phase is locked to the steady state where the phase is locked, the first sub-buffer circuit is changed from the first sub-buffer circuit to the smaller one in the current capacity. Stop in order And performing control to.

  According to the above configuration, the lock-up time can be shortened by a simple configuration that switches in stages using a plurality of sub-buffer circuits and charge pump circuits that limit the current value to be small.

  As described above, according to the present invention, there is an effect that the lockup time can be shortened with a simple configuration in which the current value is switched stepwise by a circuit that limits the current value to be small.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a circuit diagram showing a configuration of a frequency synthesizer according to Embodiment 1 of the present invention. Here, components having substantially the same functions corresponding to the components described in FIG. 4 showing the conventional example will be denoted by the same reference numerals, and different components will be described.

  In FIG. 1, 1 is a voltage controlled oscillator, 2 is a variable frequency divider, 3 ′ is an exclusive logic type phase comparator that receives a reference signal and an output signal of the variable frequency divider 2, and 4 operates at least in a steady state. The main buffer circuit 7 and 21 are sub-buffer circuits that operate only in a transient state, and 12 is a loop filter.

  The output of the voltage controlled oscillator 1 is branched into two and one is input to the variable frequency divider 2. The phase comparator 3 ′ inputs the reference signal and the phase difference signal from the variable frequency divider 2 and outputs them to the main buffer circuit 4 and the sub buffer circuits 7 and 21. The output of the main buffer circuit 4 is input to the input terminal 14 of the loop filter 12, and the outputs of the sub buffer circuits 7 and 21 are input to the input terminal 15 of the loop filter 12.

  The sub-buffer circuit 21 includes a Pch MOS transistor 22, an Nch MOS transistor 23, a switch 24, and a switch 25. The source of the Pch MOS transistor 22 is connected to the power source, and the gate is connected to the phase comparator 3 'and the switch 24 that is switched to the power source. The drain is connected to the drain of the Nch MOS transistor 23 and is connected to the input terminal 15, the source of the Nch MOS transistor 23 is grounded, and the gate is connected to the phase comparator 3 'and the switch 25 whose input is switched to the ground. Has been.

  The MOS transistors 5, 6, 8, and 9 constituting the main buffer circuit 4 and the sub buffer circuit 7 have a gate size that allows a current sufficiently larger than the input / output current to the loop filter 12 determined by the power supply voltage and the resistors 17 and 18 to flow. By suppressing the distortion of the rectangular wave due to the ON resistance of the MOS transistor, the lock-up time is prevented from becoming long.

  The MOS transistors 22 and 23 constituting the sub-buffer circuit 21 have a gate size that can flow about half of the current flowing through the resistor 18b when half the potential of the power supply voltage is applied in order to reduce the change in the average voltage at the time of switching. . This assumes one half of the current flowing through the sub-buffer circuit when the average voltage input to the voltage controlled oscillator 1 is the middle point of the control range.

  The operation of the frequency synthesizer configured as described above in the first embodiment will be described with reference to FIG. FIG. 2 shows an input signal at the input terminal 14, input signals to the input terminal 15 output from the sub-buffer circuits 7, 21, an input signal to the input terminal 15 that combines them, and an output at the output terminal 16. A signal is shown.

  As shown in FIG. 2, in the process of shifting from the transient state in which the phase is locked to the steady state in which the phase is locked, the sub-buffer circuit 7 is stopped in order to switch the loop band at the first switching timing in which the phase is pulled to some extent, The sub-buffer circuit 21 is stopped in order to obtain a steady-state loop band at the second switching timing at which the phase is again pulled to some extent.

  Since the output voltage of the loop filter 12 is an average voltage, the change in the output voltage after switching is determined by the difference between the input signals before and after the switching timing. Since the sub-buffer circuit 21 is operating after the first switching timing, the change in the average voltage is sufficiently small as compared with the case where the sub-buffer circuit 7 is completely stopped from the state where it is operating alone.

  Further, since the sub-buffer circuit 21 is also configured to limit the input / output current at the second switching timing, the output average voltage fluctuates as compared with the case where the sub-buffer circuit 7 is completely stopped from the state where it operates independently. Is small. Since the voltage controlled oscillator 1 outputs a frequency according to the voltage, the frequency fluctuation is also reduced. Thus, when the fluctuation of the frequency becomes small, the time until the phase is drawn again becomes short.

  As described above, the lock-up time can be shortened with a simple configuration in which switching is performed step by step using a sub-buffer circuit with a limited current.

  In addition, a configuration in which a plurality of sub-buffer circuits having the same configuration as the sub-buffer circuit 21 and different current-limiting gate sizes are connected to the input terminal 15 of the loop filter 12 and sequentially switched from a larger current capacity to a smaller one is also possible. Conceivable.

  FIG. 3 is a circuit diagram showing the configuration of the frequency synthesizer according to the second embodiment of the present invention. In FIG. 3, 1 is a voltage-controlled oscillator, 2 is a variable frequency divider, 3 ′ is an exclusive logic type phase comparator that receives a reference signal and a frequency-divided output signal, and 4 is a main buffer circuit that operates at least in a steady state. , 31 is a charge pump circuit that operates only in a transient state, and 12 is a loop filter.

  The charge pump circuit 31 shown in FIG. 3 includes a Pch MOS transistor 32, an Nch MOS transistor 33, switches 34 and 35, and current sources 36 and 37. The source of the Pch MOS transistor 32 is connected to the power supply via the current source 36, and the gate is The input is connected to the phase comparator 3 ′ and a switch 34 that is switched to the power source, the drain is connected to the drain of the Nch MOS transistor 33 and the input terminal 15, and the source of the Nch MOS transistor 33 is connected via the current source 37. The gate is connected to a switch 35 whose input is switched to the phase comparator 3 'and ground.

  The loop filter 12 includes a lag lead filter 13 and a capacitor 38. One of the capacitors 38 is connected to the divided contact of the resistor 18 and connected to the input terminal 15, and the other is grounded.

  The current sources 36 and 37 are configured such that at least two or more current values can be changed by an external signal, and the current values are switched in stages when the phase is pulled to some extent.

  The operation will be described below. The capacitor 38 is charged and discharged by the current input / output from the charge pump circuit 31 and has a potential. The capacitor 19 is charged / discharged by this current and the current flowing by the potential of the other end of the resistor 18b to generate an average voltage.

  Compared with the case where the loop band is switched once, the change amount of the average voltage is reduced by stepwise switching by the charge pump circuit 31, and the sub-buffer circuit 21 in which the current value is limited in the first embodiment is used. The lock-up time can be shortened by the same action as that of the case.

The first and second embodiments of the present invention have the effect of reducing fluctuations in the average voltage output of the loop filter 12 that occur at the time of switching the loop band, so the lockup time is shortened even if the configuration of the loop filter 12 is changed. The effect to do is equivalent. For example, a loop filter configured by including a lag reed filter in the subsequent stage of the lag reed filter can be considered.

  From the above, the lock-up time can be shortened by switching the current value to be smaller step by step.

  The frequency synthesizer according to the present invention can reduce the lock-up time with a simple circuit configuration that switches the current value in small steps, and is useful for wireless devices such as mobile communication devices.

1 is a circuit diagram showing a frequency synthesizer in Embodiment 1 of the present invention. Timing chart showing operation of frequency synthesizer in Embodiment 1 of the present invention The circuit diagram which shows the frequency synthesizer in Embodiment 2 of this invention Circuit diagram showing a conventional frequency synthesizer Timing chart showing operation of exclusive logic type phase comparator Timing chart showing the operation of a conventional frequency synthesizer

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Voltage control oscillator 2 Variable frequency divider 3, 3 'Phase comparator 4 Main buffer circuits 5, 8, 22, 32 Pch MOS transistors 6, 9, 23, 33 Nch MOS transistors 7, 21 Sub buffer circuits 10, 11, 24 25, 34, 35 Switch 12 Loop filter 13 Lug reed filter 14, 15 Input terminal 16 Output terminals 17, 18, 18a, 18b Resistors 19, 38 Capacitor 31 Charge pump circuit 36, 37 Current source

Claims (3)

A voltage-controlled oscillator whose output frequency is controlled by the applied voltage, a variable frequency divider that divides the output frequency signal of the voltage-controlled oscillator, and a phase comparison between the frequency-divided signal of the variable frequency divider and the reference signal An exclusive logic type phase comparator that outputs a signal corresponding to a phase difference, at least three buffer circuits that input a signal output from the phase comparator, and an input from the buffer circuit that is smoothed to the voltage controlled oscillator Loop filter to output,
The at least three buffer circuits are constituted by inverters of MOS transistors, and a main buffer circuit that outputs a signal corresponding to a phase difference signal output from the phase comparator;
A first sub-buffer circuit having a switch at the input end, configured by an inverter of a MOS transistor, and outputting a signal corresponding to the phase difference signal output from the phase comparator in a transient state at the time of frequency switching;
Consists of a MOS transistor inverter that has a switch at the input end and the output current value at the output end is limited by the gate size, and outputs a signal corresponding to the phase difference signal output from the phase comparator in a transient state at the time of frequency switching And a second sub-buffer circuit that
The loop filter has a first resistor having one end connected to the output end of the main buffer circuit and the other end connected to the control input end of the voltage controlled oscillator, and the other end connected to the other end of the first resistor. A lag reed filter having a second resistor and a capacitor that connects the other end and one end of the second resistor and grounds the other end,
A steady contact whose phase is locked from a transient state in which the phase is locked by connecting at least two or more output terminals of the first and second sub-buffer circuits to the divided contact obtained by dividing the second resistor into two. A frequency synthesizer characterized in that, in the process of shifting to a state, control is performed to stop in order from the first sub-buffer circuit to the second sub-buffer circuit from the larger current capacity to the smaller current capacity . The first and second sub-buffer circuits are replaced with a charge pump circuit capable of varying a current value, and the loop filter includes a capacitor having one end connected to the second contact of the second resistor and the other end grounded,
In the process of transition from the transient state of locking the phase to the steady state, the frequency synthesizer of claim 1, wherein the performing control for switching the stages have small value a current value of the charge pump circuit. A voltage-controlled oscillator whose output frequency is controlled by an applied voltage, a variable frequency divider that divides the output frequency signal of the voltage-controlled oscillator, and a phase difference between the frequency-divided signal of the variable frequency divider and a reference signal An exclusive logic type phase comparator for outputting a signal, at least three buffer circuits for inputting a signal output from the phase comparator, and a loop filter for smoothing the input from the buffer circuit and outputting it to the voltage controlled oscillator And
The at least three buffer circuits have a main buffer circuit that outputs a signal corresponding to the phase difference signal output from the phase comparator, and a switch at an input terminal, and the frequency of the signal corresponding to the phase difference signal is switched. A first sub-buffer circuit that outputs to a transient state of the first and a switch that has a switch at the input end and limits the output current value at the output end, and outputs a signal corresponding to the phase difference signal to the transient state at the time of frequency switching. 2 sub-buffer circuits,
The loop filter has a first resistor having one end connected to the output end of the main buffer circuit and the other end connected to the control input end of the voltage controlled oscillator, and the other end connected to the other end of the first resistor. A second resistor, and a capacitor that connects the other end and one end of the second resistor and grounds the other end,
A steady contact whose phase is locked from a transient state in which the phase is locked by connecting at least two or more output terminals of the first and second sub-buffer circuits to the divided contact obtained by dividing the second resistor into two. A frequency synthesizer characterized in that, in the process of shifting to a state, control is performed to stop in order from the first sub-buffer circuit to the second sub-buffer circuit from the larger current capacity to the smaller current capacity.

Images