JP4082439B2 - Parallel computer - Google Patents

Description

  The present invention relates to a parallel computer that divides a single task into a plurality of execution units and processes each execution unit in parallel with a plurality of processors, while maintaining the processing capability of the entire parallel computer, The present invention relates to a technology for saving power consumption.

  Furthermore, the present invention relates to a technique for saving the power consumption of the entire parallel computer while satisfying the restriction on the processing completion time imposed on each task.

  Mobile information devices such as mobile phones and notebook computers are required to be lightweight. However, these devices often incorporate a large-capacity battery in order to drive a processor having a high operating frequency for a long time. A battery with a large capacity is heavy, which is a big problem in reducing the weight of the portable information device.

  A technique is known in which the operating frequency of a processor is changed in accordance with the type and content of processing in order to extend the duration while reducing the battery capacity and weight. This is based on the principle that power consumption can be saved by operating the processor at a low operating frequency.

  By the way, portable information devices are also requested to perform time-constrained processing such as multimedia data processing, and real-time processing is often required like embedded systems. As a power saving technique for appropriately changing the operating frequency while aiming at a process having a restriction on the processing time as described above, for example, Japanese Unexamined Patent Application Publication No. 2002-99432 (hereinafter referred to as Patent Document 1) is known.

  This technology performs task scheduling while determining whether the processing time requirement of each task with processing time constraints is satisfied, and if there is room in the processing time requirement of the entire task, the operation of the processor This is to save power by changing the frequency and power supply voltage.

  As a technique for speeding up the processing, in addition to operating the processor at a high operating frequency, a method of performing parallel processing by combining a plurality of processors is often used. For example, Japanese Patent Application Laid-Open No. 2002-215599 (hereinafter referred to as Patent Document 2) is known as a technique for saving power by controlling the operating frequency of each processor constituting such a multiprocessor system. .

  In the method in Patent Document 2, when a plurality of processors are used to process a plurality of tasks, when some of the processors complete processing earlier than the other processors, the operating frequency and power supply voltage of the processor are changed. The power consumption is reduced by keeping it low according to the processing completion time of the processor.

  However, the method in Patent Document 2 is based on the processing completion time of another processor, and is not based on the time constraint of the processing itself. Therefore, the method disclosed in Patent Document 2 cannot be applied to a system that has time constraints on processing.

  On the other hand, the method in Patent Document 1 is based on a system composed of a single processor, and when applied to a multiprocessor system, there is no dependency between tasks that are the minimum processing unit. It is clear that it cannot be applied unless the condition that the influence of the dependency relationship can be ignored is satisfied.

  In the field of parallel computers, parallel computing algorithms in which each processor cooperates to solve a single problem (task) have been widely studied. However, even if the method of Patent Document 1 or the method of Patent Document 1 and the method of Patent Document 2 are combined, these research results cannot be used.

  The present invention has been made to solve such a problem, and an object thereof is to provide a computer that completes a single task by parallel processing within a required processing time while reducing power consumption. .

In a parallel computer according to the present invention, a task is divided into a plurality of processing units, and the divided processing units are executed in parallel.
Task dividing means for dividing the task into a plurality of processing units that can be executed by individual processors, and outputting the divided processing units as a plurality of subtasks;
A subtask attribute information file that holds attribute information of the subtask divided by the task dividing means;
A plurality of processors configured to control power consumption from the outside and executing the subtask divided by the task dividing unit;
Based on the subtask attribute information held in the subtask attribute information file, the subtask divided by the task dividing means is distributed to the plurality of processors to instruct execution of the subtask, and the power consumption of the plurality of processors Processor control means for controlling
It is equipped with.

  In the above, the concept of subtask includes a partial instruction code sequence formed by dividing a part of the instruction code sequence constituting the task, but it is not limited to this. Instead of dividing the constituent instruction code itself, the processing unit may be divided into a plurality of units by dividing the data to be processed by the task into a plurality of units.

  Thus, according to the parallel computer according to the present invention, the power consumption of each processor is controlled while distributing the subtask to a plurality of processors based on the attribute information of the subtask divided from the task. A reduction in power consumption can be achieved while satisfying the task execution time constraint.

FIG. 2 is a block diagram showing a configuration of a parallel computer according to Embodiment 1 of the present invention; The figure which shows the characteristic of the processor of the parallel computer which concerns on Embodiment 1 of this invention, The flowchart of the parallel computer which concerns on Embodiment 1 of this invention, The figure for demonstrating the method to select the execution system which concerns on Embodiment 1 of this invention, A diagram showing the relationship of boundary values to be considered when selecting various execution methods, It is the figure which showed the relationship between the number of processors and power consumption.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing the configuration of a parallel computer according to Embodiment 1 of the present invention. In the figure, a task input terminal 10 is an input terminal for inputting a task to be processed by the parallel computer. Here, a task refers to a unit of work inside a central processing unit (hereinafter referred to as CPU). The term "work" as used herein refers to a predetermined processing unit configured by combining a plurality of computer instruction codes and is easy to understand or handle from the perspective of a computer operator or system administrator. Therefore, the task size is often determined. However, the features of the present invention are not lost no matter what processing unit constitutes one task.

  In the figure, it is assumed that a task is input from the outside by providing the task input terminal 10. However, the computer may be configured to autonomously acquire a task stored in an external storage device under the control of the operating system. Computer systems having such a configuration are very common and need not be described again here.

  The task dividing means 11 is a part that divides a single task input from the task input terminal 10 into a plurality of subtasks.

  The subtask attribute information file 12 is a file for storing additional information about each subtask, and is stored by a random access memory (RAM), a fixed disk device or other storage device or storage element, or a storage circuit. It is data. Note that it is not necessary for the subtask attribute information file 12 to physically exist alone. For example, a task executable file (instruction code and static data stored in the task input terminal 10 is stored). The program may be stored in a binary program file) and handled as the subtask attribute information file 12.

  The control processor 13 as the processor control means distributes the subtask divided by the task dividing means 11 to a plurality of processors including the arithmetic processors 14-1 to 14-N while referring to the subtask attribute information file 12. This is a part for instructing the processor to which the subtask is distributed to process the subtask. In addition, the control processor 13 has a feature of controlling the power consumption of the arithmetic processors 14-1 to 14-N, and is intended to reduce power consumption while satisfying the task execution time constraint. .

  In addition, the configuration of subtasks can be divided into a configuration in which a task instruction code sequence is divided into instruction code sequences having a smaller number of steps, and a configuration in which data to be processed by a task is divided into smaller size data. It is done. When a subtask is configured by dividing an instruction code string, it should be expressed as executing a subtask, and when a subtask is configured by dividing data, it should be expressed as processing a subtask. However, here, in order to simplify the notation, the expression “process subtask” is used uniformly. However, the expression “process subtask” includes the meaning of “execute subtask”.

  The arithmetic processors 14-1 to 14 -N are arithmetic devices or circuits that process each subtask divided by the task dividing unit 11. Furthermore, the arithmetic processors 14-1 to 14-N can control power consumption from the outside. As a method of controlling the power consumption, the arithmetic processors 14-1 to 14-N themselves have an interface for directly changing the power consumption, and the power consumption is changed through this interface. In addition, when the instruction code of each subtask is decoded and executed based on an externally input clock signal, the power consumption is changed through the change of this clock signal. You can do that.

  FIG. 2 is a diagram showing an example of characteristics of the arithmetic processors 14-1 to 14-N. As shown in the figure, the arithmetic processors 14-1 to 14-N can select at least three operation states of "high-speed operation state", "standard operation state", and "idle state". When in the high-speed operation state, the arithmetic processors 14-1 to 14-N operate at a voltage of 1.8V with an operating frequency of 380 MHz and consume 0.5 W of power. In the standard operation state, the arithmetic processors 14-1 to 14-N operate at an operating frequency of 152 MHz and a voltage of 1.0 V, and the power consumption is 0.053 W. Further, when operating in an idle state, the operating frequency is 33 MHz, the voltage is 1.0 V, and the power consumption is 0,0115 W.

  As can be seen from the characteristics shown in this figure, it is generally known that in an electronic circuit, the power consumption per unit time increases as the operating frequency increases. The relationship between the power consumption P, the operating frequency F, and the power supply voltage V is given by Equation (1) when the leakage power is ignored. Here, t is a signal transition rate and C is a capacitance.

P = t · C · F · V ² (1)

  Note that the arithmetic processors 14-1 to 14-N have a configuration in which three operation states including a “high-speed operation state”, a “standard operation state”, and an “idle state” change as an example. The processor that can be used in the present invention is not limited to such an example.

  Since the clock speed can vary depending on the temperature of the environment in which the computer is located, a practical commercially available processor has a margin for the variation of the external clock. Such a commercially available processor operates faster as the external clock speed increases, and operates slower as the external clock speed decreases. Therefore, unlike the processor shown in the above example, even when using a commercially available processor that does not actively support multiple operating states, the margin for external clock fluctuations should be actively used. Thus, the features of the present invention can be used. Recently, processors that can reduce power consumption have been widely used in mobile applications and are well known in the art, and will not be discussed in further detail here.

  Note that the arithmetic processors 14-1 to 14-N should not be interpreted in a limited way as being independent LSI components, for example. For example, the vector processor is a single arithmetic device, but can execute a plurality of operations in parallel. The configuration of the computer shown in FIG. 1 includes such a configuration. It goes without saying that the control processor 13 and the arithmetic processors 14-1 to 14-N can be replaced with a completed computer such as a personal computer or a workstation. That is, the present invention can also be applied to a parallel computing system in which a plurality of computers are combined.

  The task dividing means 11 may be configured as an independent control circuit or control device, or may be configured as a computer program executed by the control processor 13.

  Further, if the control processor 13 is regarded as a fetch circuit and a decoder in a general processor architecture, and a task and a subtask are regarded as an instruction code and a microcode at the machine language level in the processor, the entire system shown in FIG. Can be considered to represent a single processor. In this case, array processing by vector operation is regarded as a task, and processing of each element of the array is regarded as a plurality of subtasks. Further, the task decomposing means 11 will be a compiler (language processor) corresponding to an optimization process for generating a vector operation instruction called a vectorization compiler, and a decoder for decoding the vector operation instruction into microcode. . Such compiler technology is already known. Further, instead of the processing unit determined at the level of the processor architecture, the relationship between the process and the thread may be considered to correspond to the relationship between the task and the subtask. In this case, the relationship between tasks and subtasks is flexibly defined based on the system design. Thus, the configuration of FIG. 1 can be applied at various levels.

  Subsequently, the operation of the parallel computer according to the first embodiment of the present invention will be described. FIG. 3 is a flowchart showing the operation of this parallel computer. When a task to be executed is input from the task input terminal 10, the task dividing unit 11 divides the task into subtasks (step S101). Subsequently, the control processor 13 acquires a task processing time limit T (step S102). The processing time limit T is a value predetermined by the system.

  For example, in the case of a process and a thread, T is determined from the purpose of the user or the system. If the system is intended to perform signal processing of an input signal (for example, some observation value) generated every fixed time (sampling time), the sampling time which is a period for acquiring these signals is the processing time limit T. Would fall under.

  In some cases, the processing time limit T is determined from the configuration of the parallel computer without determining the processing time limit from the external specification. For example, when configuring a processor that completes most instructions within one clock with an external clock, a time corresponding to one external clock is the processing limit time T.

  Subsequently, the control processor 13 calculates a task processing time tmin when the arithmetic processors 14-1 to 14-N are set to the high-speed operation state (step ST103). In order to realize this process, it is required that the estimated process completion time of each subtask is known in advance. Therefore, for example, the processing time in the high-speed operation state and the standard state of each subtask by any one of the arithmetic processors 14-1 to 14-N is measured in advance and stored in the subtask attribute information file. Then, the control processor 13 obtains the processing time of the subtask according to the type of the subtask, and calculates the processing time tmin of the task.

  Note that the subtask processing time is measured only in either the high-speed operating state or the standard operating state, and is multiplied by the ratio between the operating frequency of the measured operating time and the operating frequency of the other operating state. The other processing time may be approximated.

  As a result, when tmin falls below the processing time limit T (step ST104: Yes), it means that the parallel processing capability of the arithmetic processors 14-1 to 14-N exceeds the processing amount of the subtask to be processed. Since there is a margin in processing capacity, the process proceeds to the power saving process after step ST105.

  On the other hand, when tmin does not fall below the processing time limit T, it is necessary to focus on speeding up processing rather than saving power consumption, so the arithmetic processors 14-1 to 14-N are set to a high-speed operation state. (Step ST106: execution method 1). Then, the process proceeds to step ST111. The processing after step ST111 will be described later.

  In step ST105, the control processor 13 sets any one of the arithmetic processors 14-1 to 14-N to the standard operation state, and executes all subtasks only with the processor set to the standard operation state. The task processing time tstd is calculated. Also in this case, tstd is calculated based on the processing time of the subtask in the same manner as the calculation of tmin in step ST103. If this tstd exceeds T (ST107: Yes), the processing by only one of the arithmetic processors 14-1 to 14-N satisfies the request to complete the task within the processing time limit T. Therefore, the process proceeds to parallel processing using a plurality of processors after step ST109.

  On the other hand, if tstd does not exceed T, the request to complete the task within the processing time limit T can be satisfied even with only one processor, and therefore any one of the arithmetic processors 14-1 to 14-N. One processor, for example, the arithmetic processor 14-1, is set to the standard operation state (step ST108). In addition, the other processors excluding the arithmetic processor 14-1, that is, the arithmetic processors 14-2 to 14-N are set in an idle state.

By doing so, it is possible to simultaneously achieve a reduction in power consumption while satisfying the requirement for real-time processing of completing task processing within a predetermined processing time limit.
On the other hand, when tstd exceeds T, one of the following processing methods (execution method 3 and execution method 4) is selected based on the properties of the subtasks and the properties (operation frequency and power consumption) of each processor. Based on the processing method, the number n of arithmetic processors used for subtask processing and the operating frequency are calculated. (Step ST109).

Execution method 3 :
One of the arithmetic processors 14-1 to 14-N is selected, and the operating frequency of the selected arithmetic processor is set to the operating frequency β in the high-speed operation state. Perform subtasks. Arithmetic processors other than the selected arithmetic processor are set in an idle state.

Execution method 4 :
The n arithmetic processors are selected from the arithmetic processors 14-1 to 14-N, and the selected n processors (2 ≦ n) are selected with the operating frequency of the selected arithmetic processor as the operating frequency α in the standard operating state. ≦ N). Arithmetic processors other than the selected n arithmetic processors are set in an idle state.

Execution method 5 :
Among the arithmetic processors 14-1 to 14-N, m (m <n) arithmetic processors are selected, and the selected m (2 ≦ m <n ≦ N). All but the selected m processors are set in an idle state.

  Next, a method for selecting one of execution method 3, execution method 4, and execution method 5 will be described.

  FIG. 4 shows a time chart example of the execution method 3 and the execution method 4 within the processing constraint time (T). Since the difference between the two is the portion within the thick line frame, it is only necessary to compare the power consumption amounts for this portion. In the case of FIG. 4, the processing constraint time (T) can be expressed as in equation (2) because the processing time of execution method 4 is longer than that of execution method 3. Here, Tc (= TS + TR) is the time required for one communication process, and is the sum of the transmission processing time TS and the reception processing time TR. Tα is an execution time when one piece of processing data is processed by one processor at the operating frequency α. N indicates the number of processors.

    T = (n-1) .TC + T.alpha. / N (2)

  Equation (3) shows the power consumption C2 [W · s] by the execution method 3 in this case. Here, the first term of equation (3) is the amount of power consumed to perform data processing at the operating frequency β, and the remaining second term is an idle processor (FIG. 4: processor 14 for computation). -1 to computing processor 14-N) and the power consumption of the processor (FIG. 4: computing processor 14-1) during the period when the data processing is completed and the processor is idle. Further, k = α / β.

C2 = Pβ · k · Tα + k · Pγ · Tα · (n−1)
+ N · Pγ · [Tα · (1 / n−k) + (n−1) · Tc]
= Pβ · k · Tα + Pγ · [(1-k) · Tα + n · (n-1) · Tc] (3)

  Similarly, Equation (4) shows the power consumption C3 [W · s] by the execution method 4 in this case. Here, the first term of Equation (4) is the sum of the power consumption required for communication processing and the power consumption in all idle states, and the second term represents the power consumption required for data processing. Is.

C3 = (n-1) .P.alpha..Tc + (1 / n) .P.alpha..T.alpha.
+ (N−1) · [Pα · Tc + (1 / n) · Pα · Tα + (n−2) · Pγ · Tc]
= (N-1) · [2 · Pα + (n-2) · Pγ] · Tc + Pα · Tα (4)

  Here, assuming that C2 = C3, Expression (5) can be derived from Expression (3) and Expression (4). The case where C2 = C3 is satisfied is the case where the power consumption by these two execution methods is equal, and the value of each parameter satisfying C2 = C3 becomes a boundary value and takes a parameter value other than this boundary value. Any one of these execution methods is advantageous. Here, ρ represents a ratio (Tc / Tα) of processing time of communication processing to data processing.

  ρ = {k · Pβ−Pα + Pγ · (1−k)} / {2 · (n−1) (Pα−Pγ)} (5)

  Comparing ρ obtained based on this equation (5) with ρ3 for execution of power saving selected by execution method 2, the superiority or inferiority of execution methods 3 and 4 can be determined. If ρ <ρ3, the execution method It can be seen that execution method 4 should be applied if 3 is ρ> ρ3. The discussion so far relates to the case where the processing time of the execution method 4 is longer than that of the execution method 3 based on FIG. 4, but in the opposite case, the expressions (3) and (4) Are different, but the same equation (5) is derived. However, in the case of n = 2, 3, depending on the magnitude relationship between the transmission processing time Ts and the reception processing time TR, for example, the arithmetic processor 14-1 of the execution method 4 shown in FIG. There is a case that it will be scratched. However, assuming Ts = TR, ρ is given by equation (5) even when n = 2,3.

  FIG. 5 shows the value of ρ with respect to the number of arithmetic processors (n ≧ 2) when the values in FIG. 2 are given to the parameters on the right side of equation (5). Execution methods 3 and 4, and superiority and inferiority of 1 and 4 can be obtained by analyzing the target task and obtaining the optimal number of processors and the value of ρ in that case for the energy saving in execution method 4. It can be determined from FIG.

  FIG. 6 shows the ratio (E3 / E4) of the power consumption with respect to the execution method 4 when the execution method 3 is selected / executed with respect to an appropriate ρ (≦ 0.05). If ρ ≦ 0.05, the effect of parallel processing is always obtained within the range of 2 to 20 processors. From this result (FIG. 6), when the value of ρ is constant, the ratio decreases as the number of processors increases, but conversely, it can be confirmed that the ratio increases as ρ decreases. Therefore, if ρ becomes smaller as the number of arithmetic processors increases, the rate of reduction of this ratio becomes smaller during that state.

  In this way, the relationship between the number of processors and ρ as shown in FIG. 5 is obtained in advance based on the ratio of communication processing and processing time, and the operating frequency and power consumption of the arithmetic processor. Is stored in a storage area such as In step S109, the control processor 13 selects one of the execution method 3 and the execution method 4 from the relationship of the expression (5).

  In the above example, an example of communication processing for distributing the subtasks to the arithmetic processors 14-1 to 14-N has been described as the dependency relationship between the subtasks. It is easy to derive a relationship corresponding to 3) to Equation (5).

  Moreover, regarding the selection of execution methods 3 and 5, since both methods have the same operating frequency, execution method 3 is selected if both methods are completed within the time limit. This is because power saving can be executed when the number of processors used is small.

  Further, regarding the selection of execution methods 4 and 5, if the execution method 4 requires more processing time than the execution method 5, the power consumption C5 of the execution method 5 is as follows.

C5 = (m−1) · [2 · Pβ + (m−2) · Pγ] · k · Tc + Pβ · Tβ
+ Pγ · {Tc · [n · (n−1) −k · m · (m−1)] + Tα · (1−k)} (6)

  Here, the first term and the second term of the expression (6) are the power consumption of the processor to which the processing is assigned, and the third term and the fourth term are assigned to the idle processor and the processing. Shows the power consumption of the processor that is in an idle state because the process is in a wait state.

  Therefore, the difference C5-C3 in power consumption between execution method 4 and execution method 5 is

C5-C3 = Tc. {2.k. (m-1) (P.beta.-P.gamma.)-2. (n-1). (P.alpha.-P.gamma.)}
+ Tα · {k · (Pβ−Pγ) − (Pα−Pγ)} (7)

It becomes. What is necessary is just to determine the superiority / inferiority of the execution method 4 and the execution method 5 using this Formula (7). Even if execution method 5 requires more processing time than execution method 4, equation (6) is different, but the same equation (7) is derived.

  Finally, the control processor 13 distributes the subtasks to the arithmetic processors 14-1 to 14-N based on the execution method determined in step S109, and instructs the execution of the subtasks (step ST110).

  As described above, according to the parallel computer of the first embodiment of the present invention, a task is divided into subtasks, and one of execution methods 1 to 4 is selected based on the subtask dependency, and the task is selected. Are executed in parallel, so that the total power consumption of the plurality of processors can be reduced while satisfying the task processing constraint time.

  In the above description, the control processor 13 is a dedicated processor for distributing subtasks. However, the control processor 13 may have a lower load than the arithmetic processors 14-1 to 14-N. The functions of the arithmetic processors 14-1 to 14-N may be combined.

The present invention can be widely applied to a computer processing system for parallel operations such as a parallel computer system having a plurality of computers in a cluster configuration or a parallel processing processor having a plurality of operation instruction processing units.

Claims (2)

In a parallel computer that divides a task into multiple subtasks and executes the divided subtasks,
Task dividing means for dividing the task into a plurality of subtasks executable by the processor;
A subtask information file that holds information on the processing time of the subtask based on the operating frequency of the processor;
A plurality of processors for executing subtasks divided by the task dividing means;
Information related to the processing time of the subtask based on the operating frequency of the processor, the processing time limit for the task determined in advance, information related to the time required for communication processing between the plurality of processors, and power consumption based on the operating frequency of the processor Processor control means for selecting the number of processors and the operating frequency based on the information on the quantity and distributing the subtasks divided by the task dividing means to the processors;
With
Said processor control means acquires information about the processing time of the subtasks based on the operating frequency of the processor from the subtask information file, all of the subtasks at every processor that high-speed operation state of operating faster than the standard operating conditions A parallel computer that calculates a task processing time when processing is performed and distributes all the subtasks to all the processors when the task processing time is longer than a task processing time limit. In a parallel computer that divides a task into multiple subtasks and executes the divided subtasks,
Task dividing means for dividing the task into a plurality of subtasks executable by the processor;
A subtask information file that holds information on the processing time of the subtask based on the operating frequency of the processor;
A plurality of processors for executing subtasks divided by the task dividing means;
Information related to the processing time of the subtask based on the operating frequency of the processor, the processing time limit for the task determined in advance, information related to the time required for communication processing between the plurality of processors, and power consumption based on the operating frequency of the processor Processor control means for selecting the number of processors and the operating frequency based on the information on the quantity and distributing the subtasks divided by the task dividing means to the processors;
With
Said processor control means acquires information about the processing time of the subtasks based on the operating frequency of the processor from the subtask information file, all of the subtasks at every processor that high-speed operation state of operating faster than the standard operating conditions The task processing time when processing is calculated, the task processing time is shorter than the task processing time limit, and the task processing time when all the subtasks are processed by one processor in the standard state is calculated. When the processing time is longer than the task processing time limit, information on the subtask processing time based on the processor operating frequency, information on power consumption based on the processor operating frequency, and communication processing between multiple processors Power consumption based on information about the time required for Parallel computer select the number and the operating frequency of the processor to reduce the amount of power, characterized by distributing the subtasks processor.

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