JP4082014B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an insulating film formed on a metal wiring.
[0002]
[Prior art]
FIG. 21 is a cross-sectional view of a main part of a conventional semiconductor device. Here, a cross-sectional view of the main part of a lateral power MOSFET with a withstand voltage of 750 V is shown.
A p-well region 2 and an n-well region 3 are formed in contact with a surface layer of a p-type high-resistance silicon substrate 1 of about 125 Ω · cm.⁺Source region 4 and p⁺The region 5 is formed in contact with the surface layer of the n-well region 3 and n⁺A drain region 6 is formed. n⁺On the p well region 2 sandwiched between the source region 4 and the n well region 3, a gate electrode is formed via a gate oxide film 8a. p-well region 2 and n⁺A field oxide film 7a is formed on the surface of n well region 3 sandwiched between drain regions 6, and n⁺Source region 4 and p⁺A source electrode 10 is formed on the region 5 and n⁺A drain electrode 11 is formed on the drain region 6. The gate electrode 8b is formed so as to project on the field oxide film 7, and the source electrode 10 and the drain electrode 11 are formed so as to project on the field oxide film via the insulating film 9. An interlayer insulating film 12a is formed on the source electrode 10, the drain electrode 9, and the insulating film 9, and a TEOS oxide film 22 (which may be a TMS oxide film) is formed on the interlayer insulating film 12a. A passivation film 23 made of a silicon nitride film is formed thereon.
[0003]
This horizontal power MOSFET chip (hereinafter referred to as a MOSFET chip) is packaged with a plastic mold resin (not shown) to complete a horizontal power MOSFET. TEOS is Tetraethyl-Ortho-Silicate, Si (C₂H_FiveO)_FourTMS is Tri-Methoxy-Silane, and HSi (CH_ThreeO)_ThreeThat is.
[0004]
N of this element⁺Source region 4 and n⁺When a reverse bias of less than about 700 V is applied between the drain regions 6, the depletion layer extends in a well-balanced manner at the pn junction between the p-type high-resistance silicon substrate 1 and the n-well region 3, thereby relaxing the electric field and increasing the electric field. Achieves pressure resistance.
However, in a high withstand voltage lateral power MOSFET in which a MOSFET chip having a withstand voltage of 700 V or more is packaged with a plastic mold resin, when a high voltage is applied, due to the influence of movable ions and charges 24 (electrons) in the mold resin, This affects the elongation of the depletion layer formed in the p-well region 3 under the field oxide film 7 and causes a problem that the breakdown voltage of the lateral power MOSFET is lowered.
[0005]
This is because plasma is formed using an oxide film, especially an organic silane such as TEOS or TMS, which constitutes a MOSFET chip, as a raw material gas, as shown in the figure, by moving voltages and charges 24 in a mold resin (not shown) induced by an applied voltage. The oxide film 22 is polarized by the movable ions and charges 24. This is because electric charges 25 are induced in the plasma oxide film 22 due to this polarization, and the electric field intensity distribution inside the device fluctuates due to the electric charges 25.
[0006]
In order to prevent this, in a high breakdown voltage device such as a lateral power MOSFET having a high breakdown voltage of 700 V or higher, monosilane (which is relatively less likely to be polarized) is used instead of a plasma oxide film using organic silane which is easily polarized as a source gas. SiH_Four) Is used as a source gas.
This plasma oxide film is used to improve the water resistance of the plasma nitride film used as the passivation film 23, to reduce the base step formed when forming the metal wiring or the like, and as the interlayer insulating film of the multilayer wiring The film is formed by a general parallel plate type plasma CVD apparatus, and is used in combination with a resist etch back method, a SOG (Spin on glass) etch back method or anisotropic etching for planarization.
[0007]
In recent years, in order to increase the functionality of devices, development of one-chip power ICs in which a high breakdown voltage device and a low breakdown voltage device for a control circuit that controls the high breakdown voltage device are formed on the same chip has been actively conducted. In order to reduce the power consumption and increase the functionality of the low voltage device for the control circuit, miniaturization and multilayer wiring are progressing. Along with this, the planarization process of the interlayer insulating film is indispensable also in the high breakdown voltage device portion of this one-chip power IC.
[0008]
However, in the plasma oxide film formed using monosilane as a source gas in the conventional parallel plate type plasma CVD apparatus as described above, the step coverage shape in the low breakdown voltage device portion and the high breakdown voltage device portion is not sufficient. Even when combined with the resist etch back method, the SOG etch back method, or the anisotropic etching, filling between finely processed wirings of the submicron rule and flattening of the interlayer insulating film are insufficient.
[0009]
Therefore, high-density plasma CVD apparatus using monosilane, which is widely used as a flattening process in the submicron rule device process, as a source gas, and using ECR (Electron Cyctron Resonance), IPC (Inductive Coupled Plasma), and helicon wave as a plasma source. A flattening process in which an interlayer insulating film is formed by using a CMP and then polished by CMP (Chemical Mechanical Polishing) has been studied. Generally, a high-density plasma CVD apparatus and a CMP apparatus have low throughput and cost. There was a problem that it was difficult to down.
[0010]
On the other hand, in a one-chip power IC in which high-voltage devices less than 700 V are integrated, a planarization process in which an oxide film formed by atmospheric pressure ozone TEOS CVD method or quasi-atmospheric pressure ozone TEOS CVD method is applied to an interlayer insulating film is also studied. Has been done. Since these thermal CVD processes using TEOS as a raw material gas are generally excellent in embeddability and flatness, they are widely used as a flattening process in current LSIs and have a relatively high throughput. It is expected to reduce the manufacturing cost.
[0011]
However, when these oxide films using TEOS (or TMS) as a source gas are applied to a high-voltage power MOSFET exceeding 700 V, the polarization of the oxide film is similar to the plasma TEOS oxide film (or TMS oxide film) described above. There was a problem that the breakdown voltage of the high breakdown voltage device was reduced.
Also, as a means to suppress the influence of mobile ions and charges in the mold resin, a structure that shields a high voltage device with something like aluminum wiring has been proposed, and it is known that there is a certain effect in stabilizing the voltage resistance. It has been. However, when an oxide film using TEOS or TMS as a source gas is used for a high breakdown voltage device having a breakdown voltage of 700 V or more, such a shield structure alone is insufficient.
[0012]
[Problems to be solved by the invention]
As described above, when a TEOS oxide film or TMS oxide film formed by a plasma CVD method or a thermal CVD method is applied to a surface protection film formed on a metal wiring or an interlayer insulating film of a multilayer wiring in a high voltage device of 700 V or higher Under the influence of movable ions and electric charges in the mold resin, polarization occurs in these surface protective films and interlayer insulating films, and the breakdown voltage of the high breakdown voltage device is lowered.
[0013]
An object of the present invention is to provide a method for manufacturing a high breakdown voltage semiconductor device that solves the above-described problems and can prevent a decrease in breakdown voltage at low cost.
[0014]
[Means for Solving the Problems]
  To achieve the above objective,A first conductivity type well region and a second conductivity type well region formed in contact with each other on the surface layer of the first conductivity type high-resistance silicon substrate;
A source region of a second conductivity type formed in contact with a surface layer of the well region of the first conductivity type, and a high concentration region of the first conductivity type;
A second conductivity type drain region formed in a surface layer of the second conductivity type well region;
A gate electrode formed on the first conductivity type well region sandwiched between the source region and the second conductivity type well region via a gate oxide film;
A field oxide film formed on a surface of the second conductivity type well region sandwiched between the first conductivity type well region and the drain region;
A source electrode made of metal formed on the source region and the high-concentration region of the first conductivity type;
A drain electrode made of a metal formed on the drain region,
The gate electrode is formed to protrude on the field oxide film, the gate electrode and the field insulating film are covered with a first insulating film, and the source electrode and the drain electrode are formed on the field oxide film. In a method of manufacturing a semiconductor device in which a passivation film is formed on a high breakdown voltage lateral power MOSFET formed so as to protrude through an insulating film 1,
A process gas obtained by gasifying TEOS (tetraethyl-ortho-silicate) on the first insulating film, the source electrode, and the drain electrode, and adding nitrogen to a source gas obtained by combining the gas and oxygen gas is used. Plasma CVD method (CVD: Chemical Vapor Forming a second insulating film to which nitrogen is added by Deposition);
Forming a third insulating film on the second insulating film after forming the second insulating film;
Removing the third insulating film and the surface layer of the second insulating film to planarize the second insulating film;
Forming a silicon nitride film as a passivation film on the planarized second insulating film;It is set as the manufacturing method which comprises.
[0015]
  Also,A first conductivity type well region and a second conductivity type well region formed in contact with each other on the surface layer of the first conductivity type high-resistance silicon substrate;
A source region of a second conductivity type formed in contact with a surface layer of the well region of the first conductivity type, and a high concentration region of the first conductivity type;
A second conductivity type drain region formed in a surface layer of the second conductivity type well region;
A gate electrode formed on the first conductivity type well region sandwiched between the source region and the second conductivity type well region via a gate oxide film;
A field oxide film formed on a surface of the second conductivity type well region sandwiched between the first conductivity type well region and the drain region;
A source electrode made of metal formed on the source region and the high-concentration region of the first conductivity type;
A drain electrode made of a metal formed on the drain region,
The gate electrode is formed to protrude on the field oxide film, the gate electrode and the field insulating film are covered with a first insulating film, and the source electrode and the drain electrode are formed on the field oxide film. A method of manufacturing a semiconductor device in which a passivation film is formed on a high breakdown voltage lateral power MOSFET formed so as to protrude through an insulating film of 1.
A process gas obtained by gasifying TEOS (tetraethyl-ortho-silicate) on the first insulating film, the source electrode, and the drain electrode, and adding nitrogen to a source gas obtained by combining the gas and oxygen gas is used. Forming a second insulating film to which nitrogen is added by the plasma CVD method,
Forming a third insulating film on the second insulating film after forming the second insulating film;
Removing the third insulating film and the surface layer of the second insulating film to planarize the second insulating film;
Forming a metal wiring functioning as a field plate on the planarized second insulating film, and then forming a silicon nitride film as a passivation film;It is set as the manufacturing method which comprises.
[0016]
As described above, by adding nitrogen to the TEOS oxide film, an interlayer insulating film having a lower specific resistance than that of a TEOS oxide film to which nitrogen is not added, in other words, a relatively high electric conductivity, can be formed.
This is because the specific resistance of an oxide film generally formed by CVD is 10¹⁵Although the resistivity is around Ω · cm, the resistivity of the nitride film is higher than this.¹⁴This is because the oxide film to which nitrogen is added, that is, the nitrogen oxide film has a specific resistance between the pure oxide film and the pure nitride film because it is around Ω · cm.
[0017]
Therefore, the TEOS oxide film added with nitrogen according to the present invention has a specific resistance lower than that without nitrogen added, so that a leakage current that cancels polarization flows, and mobile ions in the mold resin collected in the power MOSFET portion The interlayer insulating film is not polarized due to the influence of electric charges. As a result, there is no problem that reduces the breakdown voltage of the power MOSFET. Further, by using a structure that shields a high voltage device such as an aluminum wiring, it becomes possible to manufacture a higher quality device.
[0018]
  Also,A first conductivity type well region and a second conductivity type well region formed in contact with each other on the surface layer of the first conductivity type high-resistance silicon substrate;
A source region of a second conductivity type formed in contact with a surface layer of the well region of the first conductivity type, and a high concentration region of the first conductivity type;
A second conductivity type drain region formed in a surface layer of the second conductivity type well region;
A gate electrode formed on the first conductivity type well region sandwiched between the source region and the second conductivity type well region via a gate oxide film;
A field oxide film formed on a surface of the second conductivity type well region sandwiched between the first conductivity type well region and the drain region;
A source electrode made of metal formed on the source region and the high-concentration region of the first conductivity type;
A drain electrode made of a metal formed on the drain region,
The gate electrode is formed to protrude on the field oxide film, the gate electrode and the field insulating film are covered with a first insulating film, and the source electrode and the drain electrode are formed on the field oxide film. A method of manufacturing a semiconductor device in which a passivation film is formed on a high breakdown voltage lateral power MOSFET formed so as to protrude through an insulating film of 1.
Forming a second insulating film on the first insulating film, the source electrode, and the drain electrode;
Nitrogen is added to the second insulating film by a thermal CVD method using a process gas in which TEOS (Tetraethyl-Ortho-Silicate) is gasified and nitrogen is added to a raw material gas combined with the gas and oxygen gas. Forming a third insulating film;
Forming a silicon nitride film as a passivation film on the third insulating film.
[0019]
  Also,A first conductivity type well region and a second conductivity type well region formed in contact with each other on the surface layer of the first conductivity type high-resistance silicon substrate;
A source region of a second conductivity type formed in contact with a surface layer of the well region of the first conductivity type, and a high concentration region of the first conductivity type;
A second conductivity type drain region formed in a surface layer of the second conductivity type well region;
A gate electrode formed on the first conductivity type well region sandwiched between the source region and the second conductivity type well region via a gate oxide film;
A field oxide film formed on a surface of the second conductivity type well region sandwiched between the first conductivity type well region and the drain region;
A source electrode made of metal formed on the source region and the high-concentration region of the first conductivity type;
A drain electrode made of a metal formed on the drain region,
The gate electrode is formed to protrude on the field oxide film, the gate electrode and the field insulating film are covered with a first insulating film, and the source electrode and the drain electrode are formed on the field oxide film. A method of manufacturing a semiconductor device in which a passivation film is formed on a high breakdown voltage lateral power MOSFET formed so as to protrude through an insulating film of 1.
Forming a second insulating film on the first insulating film and on the first metal wiring;
Nitrogen is added to the second insulating film by a thermal CVD method using a process gas in which TEOS (Tetraethyl-Ortho-Silicate) is gasified and nitrogen is added to a raw material gas combined with the gas and oxygen gas. Forming a third insulating film;
And forming a silicon nitride film as a passivation film after forming a metal wiring functioning as a field plate on the third insulating film.
[0020]
  In addition, a manufacturing method in which ammonia is added instead of nitrogen added to the raw material gas.
Moreover, it is set as the manufacturing method which adds nitrogen dioxide instead of nitrogen added to the said source gas.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
In the following description, the same parts as those in FIG. The p-type and n-type may be reversed.
FIG. 1 to FIG. 5 are cross-sectional views of the main part manufacturing process shown in the order of steps in the semiconductor device manufacturing method according to the first embodiment of the present invention.
[0025]
As shown in FIG. 1, a p-type well region 2 and an n-type well region 3 are formed in contact with a surface layer of a p-type high-resistance silicon substrate 1 of about 125 Ω · cm.⁺Source region 4 and p⁺The region 5 is formed in contact with the surface layer of the n-well region 3 and n⁺A drain region 6 is formed. n⁺On the p well region 2 sandwiched between the source region 4 and the n well region 3, a gate electrode is formed through a gate oxide film 8a. p-well region 2 and n⁺A field oxide film 7a is formed on the surface of n well region 3 sandwiched between drain regions 6, and n⁺Source region 4 and p⁺A source electrode 10 is formed on the region 5 and n⁺A drain electrode 11 is formed on the drain region 6. The gate electrode 8b is formed to project on the field oxide film 7, and the source electrode 10 and the drain electrode 11 are formed to project on the field oxide film through the insulating film 9. N⁺Source region 4 and n⁺The interval between the drain regions 5 is about 80 μm. In the figure, reference numeral 7b denotes a LOCOS oxide film (selective oxide film) which is formed simultaneously with the field oxide film 7a.
[0026]
As shown in FIG. 2, an oxide film 12 to which nitrogen is added is formed by plasma CVD using a process gas to which TEOS and oxygen are used as source gases and nitrogen is added. The refractive index of the oxide film 12 to which nitrogen is added is larger than 1.5. Further, TMS may be used as the source gas instead of TEOS.
As shown in FIG. 3, after applying SOG (Spin On Glass), the oxide film 13 is formed by curing (curing) at 400 ° C., for example.
[0027]
As shown in FIG. 4, the entire surface is etched back by an oxide film etcher (an apparatus for etching an oxide film). At this time, in order to prevent moisture remaining in the SOG film from affecting the device, it is desirable to remove all of the oxide film 13.
As shown in FIG. 5, a passivation film 14 which is a nitride film is formed by plasma CVD.
[0028]
In this way, by using the oxide film 13 as a sacrificial film and improving the flatness on the metal wiring that becomes the source electrode 10 and the drain electrode 11, the water resistance of the nitride film as the passivation film 14 can be greatly improved. At the same time, by using a plasma TEOS oxide film added with nitrogen as the planarized oxide film 12 added with nitrogen, conventional monosilane (SiH_FourThe oxide film 12 to which nitrogen is added significantly improves the step coverage, and the planarization on the metal wiring is easy even in the sub-micron rule microfabricated device. become. Further, the TEOS oxide film to which nitrogen is added does not cause polarization due to the influence of movable ions and electric charges in the mold resin gathered in the power MOSFET portion to which a high voltage is applied, so that the breakdown voltage of the high breakdown voltage MOSFET does not decrease. . A TMS oxide film may be used instead of the TEOS oxide film.
[0029]
FIGS. 6 to 11 are cross-sectional views of the main part manufacturing process shown in the order of steps in the method of manufacturing the semiconductor device according to the second embodiment of the present invention.
As shown in FIG. 6, a p-well region 2 and an n-well region 3 are formed in contact with a surface layer of a p-type high-resistance silicon substrate 1 having a resistance of about 125 Ω · cm.⁺Source region 4 and p⁺The region 5 is formed in contact with the surface layer of the n-well region 3 and n⁺A drain region 6 is formed. n⁺On the p well region 2 sandwiched between the source region 4 and the n well region 3, a gate electrode is formed through a gate oxide film 8a. p-well region 2 and n⁺A field oxide film 7a is formed on the surface of n well region 3 sandwiched between drain regions 6, and n⁺Source region 4 and p⁺A source electrode 10 is formed on the region 5 and n⁺A drain electrode 11 is formed on the drain region 6. The gate electrode 8b is formed so as to project on the field oxide film 7, and the source electrode 10 and the drain electrode 11 are formed so as to project on the field oxide film via the insulating film 9. N⁺Source region 4 and n⁺The interval between the drain regions 5 is about 80 μm. In the figure, reference numeral 7b denotes a LOCOS oxide film (selective oxide film) which is formed simultaneously with the field oxide film 7a. The source electrode 10 and the drain electrode 11 are first metal wirings.
[0030]
As shown in FIG. 7, an oxide film 12 to which nitrogen is added is formed by plasma CVD using a process gas in which TEOS and oxygen are used as source gases and nitrogen or ammonia is added. The refractive index of the oxide film 12 to which nitrogen is added is larger than 1.5. In addition, TMS may be used instead of TEOS as the source gas.
As shown in FIG. 8, after applying SOG, the oxide film 13 is formed by curing at 400 ° C., for example. This oxide film 13 becomes a sacrificial film.
[0031]
As shown in FIG. 9, the entire surface is etched back with an oxide film etcher. At this time, in order to prevent moisture remaining in the SOG film from affecting the device, it is desirable to remove all of the oxide film 13.
As shown in FIG. 10, the second metal wiring 15 functioning as a field plate is formed.
[0032]
As shown in FIG. 11, a passivation film 23 is formed of a nitride film by plasma CVD.
As described above, by using the oxide film 13 as a sacrificial film and improving the flatness on the first metal wiring that becomes the source electrode 10 and the drain electrode 11, the water resistance of the passivation film 23 formed of the nitride film is greatly improved. At the same time, by using a plasma TEOS oxide film to which nitrogen is added to the planarized oxide film 12 to which nitrogen is added, nitrogen is added as compared with a conventional oxide film using monosilane. Since the oxide film 12 significantly improves the step coverage, it is easy to planarize the first metal wiring to be the source electrode 10 and the drain electrode 11 even in a sub-micron rule microfabricated device. Further, the TEOS oxide film to which nitrogen is added does not cause polarization due to the influence of movable ions and electric charges in the mold resin gathered in the power MOSFET portion to which a high voltage is applied, so that the breakdown voltage of the high breakdown voltage MOSFET does not decrease. .
[0033]
Further, by using a structure that shields the high breakdown voltage device with the field plate formed of the second metal wiring 15, it becomes possible to manufacture a higher quality device.
12 to 15 are cross-sectional views of the main part manufacturing process shown in the order of steps in the method of manufacturing the semiconductor device according to the third embodiment of the present invention.
[0034]
As shown in FIG. 12, a p-type well region 2 and an n-type well region 3 are formed in contact with a surface layer of a p-type high-resistance silicon substrate 1 of about 125 Ω · cm.⁺Source region 4 and p⁺The region 5 is formed in contact with the surface layer of the n-well region 3 and n⁺A drain region 6 is formed. n⁺On the p well region 2 sandwiched between the source region 4 and the n well region 3, a gate electrode is formed through a gate oxide film 8a. p-well region 2 and n⁺A field oxide film 7a is formed on the surface of n well region 3 sandwiched between drain regions 6, and n⁺Source region 4 and p⁺A source electrode 10 is formed on the region 5 and n⁺A drain electrode 11 is formed on the drain region 6. The gate electrode 8b is formed so as to project on the field oxide film 7, and the source electrode 10 and the drain electrode 11 are formed so as to project on the field oxide film via the insulating film 9. N⁺Source region 4 and n⁺The interval between the drain regions 5 is about 80 μm. In the figure, reference numeral 7b denotes a LOCOS oxide film (selective oxide film) which is formed simultaneously with the field oxide film 7a.
[0035]
As shown in FIG. 13, a plasma oxide film 17 is formed by plasma CVD using monosilane as a source gas.
As shown in FIG. 14, an oxide film 18 is formed by a CVD method of atmospheric pressure ozone TEOS using ozone and TEOS as source gases and using a process gas to which nitrogen is added. The refractive index of the oxide film 18 to which nitrogen is added is greater than 1.5. Also, TMS may be used as the source gas instead of TEOS.
[0036]
As shown in FIG. 15, a passivation film 19 is formed of a nitride film by plasma CVD.
Thus, by improving the flatness on the metal wiring that becomes the source electrode 10 and the drain electrode 11 with the oxide film 18, the water resistance of the passivation film 19 formed of the nitride film can be greatly improved. By using an oxide film in which nitrogen is added to the planarizing film, the step coverage of the oxide film 18 can be greatly improved as compared with the conventional process using monosilane. Even in such a device, flattening on the metal wiring to be the source electrode 10 and the drain electrode 11 becomes easy. Further, the TEOS oxide film to which nitrogen is added does not cause polarization due to the influence of movable ions and electric charges in the mold resin gathered in the power MOSFET portion to which a high voltage is applied, so that the breakdown voltage of the high breakdown voltage MOSFET does not decrease. .
[0037]
16 to 20 show the present invention.4thFIG. 4 is a cross-sectional view of a main part manufacturing process illustrating a method of manufacturing a semiconductor device according to an embodiment and illustrated in the order of processes; As shown in FIG. 16, p well region 2 and n well region 3 are formed in contact with the surface layer of p-type high resistance silicon substrate 1 of about 125 Ω · cm, and n + is formed on the surface layer of p well region 2. A source region 4 and a p + region 5 are formed in contact with each other, and an n + drain region 6 is formed in the surface layer of the n well region 3. A gate electrode is formed on p well region 2 sandwiched between n @ + source region 4 and n well region 3 via a gate oxide film 8a. A field oxide film 7a is formed on the surface of n well region 3 sandwiched between p well region 2 and n + drain region 6, source electrode 10 is formed on n + source region 4 and p + region 5, and n + A drain electrode 11 is formed on the drain region 6. The gate electrode 8b is formed so as to project on the field oxide film 7, and the source electrode 10 and the drain electrode 11 are formed so as to project on the field oxide film via the insulating film 9. The interval between the n + source region 4 and the n + drain region 5 is about 80 μm. In the figure, reference numeral 7b denotes a LOCOS oxide film (selective oxide film) which is formed simultaneously with the field oxide film 7a. The source electrode 10 and the drain electrode 11 are first metal wirings. The source electrode 10 and the drain electrode 11 are first metal wirings.
[0038]
As shown in FIG. 17, a plasma oxide film 17 is formed by a plasma CVD method using monosilane as a source gas.
As shown in FIG. 18, an oxide film 18 to which nitrogen is added is formed by the atmospheric pressure ozone TEOS CVD method using ozone and TEOS as source gases. As a method of adding nitrogen to the oxide film 18, a method of using a process gas in which nitrogen or ammonia gas is added to a plasma CVD source gas is used. The refractive index of the oxide film 12 to which nitrogen is added is larger than 1.5. In addition, TMS may be used instead of TEOS as the source gas.
[0039]
As shown in FIG. 19, the second metal wiring 20 functioning as a field plate is formed.
As shown in FIG. 20, a nitride film 21 which is a passivation film is formed by plasma CVD.
Thus, by improving the flatness on the metal wiring that becomes the source electrode 10 and the drain electrode 11 with the oxide film 18, the water resistance of the nitride film as the passivation film can be greatly improved, and at the same time, the flattening film Compared with the conventional process using monosilane, the step coverage of the oxide film 18 can be greatly improved by using the oxide film with nitrogen added to the source. Flattening on the first metal wiring that becomes the electrode 10 and the drain electrode 11 is facilitated. Further, the TEOS oxide film to which nitrogen is added does not cause polarization due to the influence of movable ions and electric charges in the mold resin gathered in the power MOSFET portion to which a high voltage is applied, so that the breakdown voltage of the high breakdown voltage MOSFET does not decrease. .
[0040]
Further, by using a structure that shields the high breakdown voltage device with the field plate formed of the second metal wiring 20, it is possible to manufacture a higher quality device.
In the first to fourth embodiments, it goes without saying that nitrogen can be added to the insulating film even when nitrogen dioxide is added as nitrogen to be added to the process gas, and the same effect can be obtained. .
[0041]
【The invention's effect】
According to the present invention, when a semiconductor device such as a monolithic power IC in which a high breakdown voltage power MOSFET is formed on a chip is packaged with a plastic mold resin, the movable in the mold resin gathered in the power MOSFET portion to which a high voltage is applied. Interlayer insulation film that does not cause defects that lower the breakdown voltage of high voltage MOSFETs due to polarization of oxide film used for planarization inside the device due to the influence of ions and charges, has excellent embeddability and flatness The parallel plate type plasma CVD method, atmospheric pressure CVD method, and quasi-atmospheric pressure CVD method using TEOS as a source gas can be provided at a low cost without greatly increasing the number of steps.
[0042]
In addition, a TEOS oxide film or a TMS oxide film to which nitrogen is added is formed by using a parallel plate type plasma CVD method or a thermal CVD method, thereby manufacturing a high breakdown voltage semiconductor device that can prevent a decrease in breakdown voltage at low cost. A method can be provided.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a main part manufacturing process of a semiconductor device according to a first embodiment of the invention.
2 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the first embodiment of the present invention continued from FIG. 1;
3 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the first embodiment of the present invention continued from FIG. 2;
4 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the first embodiment of the invention, following FIG. 3;
5 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the first embodiment of the invention, following FIG. 4;
FIG. 6 is a cross-sectional view of a main part manufacturing process of a semiconductor device according to a second embodiment of the invention.
7 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the second embodiment of the invention, following FIG. 6;
8 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the second embodiment of the invention, following FIG. 7;
9 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the second embodiment of the invention, following FIG. 8;
FIG. 10 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the second embodiment of the invention, following FIG. 9;
FIG. 11 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the second embodiment of the invention, following FIG. 11;
FIG. 12 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the third embodiment of the present invention;
13 is a fragmentary cross-sectional view of the manufacturing process of the semiconductor device according to the third embodiment of the invention, following FIG. 12;
FIG. 14 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the third embodiment of the invention, following FIG. 13;
15 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the third embodiment of the invention, following FIG. 14;
FIG. 16 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the fourth embodiment of the invention;
FIG. 17 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the fourth embodiment of the invention, following FIG. 16;
FIG. 18 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the fourth embodiment of the invention, following FIG. 17;
FIG. 19 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the fourth embodiment of the invention, following FIG. 18;
FIG. 20 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the fourth embodiment of the invention, following FIG. 19;
FIG. 21 is a cross-sectional view of main parts of a conventional semiconductor device.
[Explanation of symbols]
1 High resistance silicon substrate (p-type)
2 p-well region
3 n-well region
4 n⁺Source area
5 p⁺region
6 n⁺Drain region
7a Field oxide film
7b LOCOS oxide film
8a Gate oxide film
8b Gate electrode (first metal wiring: first layer)
9 Insulating film
10 Source electrode
11 Drain electrode (first metal wiring: first layer)
12, 18 Nitrogen-added oxide film
12a Interlayer insulation film
13 Oxide film (sacrificial film)
14, 16, 21, 23 Passivation film
15, 20 Second metal wiring (second layer)
17 Plasma oxide film
22 TEOS oxide film
24 Mobile ions or charges induced in mold resin
25 Charges induced in oxide film

Claims (6)

A first conductivity type well region and a second conductivity type well region formed in contact with each other on the surface layer of the first conductivity type high-resistance silicon substrate;
A source region of a second conductivity type formed in contact with a surface layer of the well region of the first conductivity type, and a high concentration region of the first conductivity type;
A second conductivity type drain region formed in a surface layer of the second conductivity type well region;
A gate electrode formed on the first conductivity type well region sandwiched between the source region and the second conductivity type well region via a gate oxide film;
A field oxide film formed on a surface of the second conductivity type well region sandwiched between the first conductivity type well region and the drain region;
A source electrode made of metal formed on the source region and the high-concentration region of the first conductivity type;
A drain electrode made of a metal formed on the drain region,
The gate electrode is formed to protrude on the field oxide film, the gate electrode and the field insulating film are covered with a first insulating film, and the source electrode and the drain electrode are formed on the field oxide film. In a method of manufacturing a semiconductor device in which a passivation film is formed on a high breakdown voltage lateral power MOSFET formed so as to protrude through an insulating film 1,
A process gas obtained by gasifying TEOS (tetraethyl-ortho-silicate) on the first insulating film, the source electrode, and the drain electrode, and adding nitrogen to a source gas obtained by combining the gas and oxygen gas is used. Plasma CVD method (CVD: Chemical Vapor Forming a second insulating film to which nitrogen is added by Deposition);
Forming a third insulating film on the second insulating film after forming the second insulating film;
Removing the third insulating film and the surface layer of the second insulating film to planarize the second insulating film;
Forming a silicon nitride film as a passivation film on the planarized second insulating film . A method for manufacturing a semiconductor device, comprising: A first conductivity type well region and a second conductivity type well region formed in contact with each other on the surface layer of the first conductivity type high-resistance silicon substrate;
A source region of a second conductivity type formed in contact with a surface layer of the well region of the first conductivity type, and a high concentration region of the first conductivity type;
A second conductivity type drain region formed in a surface layer of the second conductivity type well region;
A gate electrode formed on the first conductivity type well region sandwiched between the source region and the second conductivity type well region via a gate oxide film;
A field oxide film formed on a surface of the second conductivity type well region sandwiched between the first conductivity type well region and the drain region;
A source electrode made of metal formed on the source region and the high-concentration region of the first conductivity type;
A drain electrode made of a metal formed on the drain region,
The gate electrode is formed to protrude on the field oxide film, the gate electrode and the field insulating film are covered with a first insulating film, and the source electrode and the drain electrode are formed on the field oxide film. A method of manufacturing a semiconductor device in which a passivation film is formed on a high breakdown voltage lateral power MOSFET formed so as to protrude through an insulating film of 1.
A process gas obtained by gasifying TEOS (tetraethyl-ortho-silicate) on the first insulating film, the source electrode, and the drain electrode, and adding nitrogen to a source gas obtained by combining the gas and oxygen gas is used. Forming a second insulating film to which nitrogen is added by the plasma CVD method,
Forming a third insulating film on the second insulating film after forming the second insulating film;
Removing the third insulating film and the surface layer of the second insulating film to planarize the second insulating film;
And forming a silicon nitride film as a passivation film after forming a metal wiring functioning as a field plate on the planarized second insulating film . A first conductivity type well region and a second conductivity type well region formed in contact with each other on the surface layer of the first conductivity type high-resistance silicon substrate;
A source region of a second conductivity type formed in contact with a surface layer of the well region of the first conductivity type, and a high concentration region of the first conductivity type;
A second conductivity type drain region formed in a surface layer of the second conductivity type well region;
A gate electrode formed on the first conductivity type well region sandwiched between the source region and the second conductivity type well region via a gate oxide film;
A field oxide film formed on a surface of the second conductivity type well region sandwiched between the first conductivity type well region and the drain region;
A source electrode made of metal formed on the source region and the high-concentration region of the first conductivity type;
A drain electrode made of a metal formed on the drain region,
The gate electrode is formed to protrude on the field oxide film, the gate electrode and the field insulating film are covered with a first insulating film, and the source electrode and the drain electrode are formed on the field oxide film. A method of manufacturing a semiconductor device in which a passivation film is formed on a high breakdown voltage lateral power MOSFET formed so as to protrude through an insulating film of 1.
Forming a second insulating film on the first insulating film, the source electrode, and the drain electrode;
Nitrogen is added to the second insulating film by a thermal CVD method using a process gas in which TEOS (Tetraethyl-Ortho-Silicate) is gasified and nitrogen is added to a raw material gas combined with the gas and oxygen gas. Forming a third insulating film;
Forming a silicon nitride film, which is a passivation film, on the third insulating film . A first conductivity type well region and a second conductivity type well region formed in contact with each other on the surface layer of the first conductivity type high-resistance silicon substrate;
A source region of a second conductivity type formed in contact with a surface layer of the well region of the first conductivity type, and a high concentration region of the first conductivity type;
A second conductivity type drain region formed in a surface layer of the second conductivity type well region;
A gate electrode formed on the first conductivity type well region sandwiched between the source region and the second conductivity type well region via a gate oxide film;
A field oxide film formed on a surface of the second conductivity type well region sandwiched between the first conductivity type well region and the drain region;
A source electrode made of metal formed on the source region and the high-concentration region of the first conductivity type;
A drain electrode made of a metal formed on the drain region,
The gate electrode is formed to protrude on the field oxide film, the gate electrode and the field insulating film are covered with a first insulating film, and the source electrode and the drain electrode are formed on the field oxide film. A method of manufacturing a semiconductor device in which a passivation film is formed on a high breakdown voltage lateral power MOSFET formed so as to protrude through an insulating film of 1.
Forming a second insulating film on the first insulating film and on the first metal wiring;
Nitrogen is added to the second insulating film by thermal CVD using a process gas obtained by gasifying TEOS (Tetraethyl-Ortho-Silicate ) and adding nitrogen to the source gas combined with the gas and oxygen gas. Forming a third insulating film formed;
And forming a silicon nitride film as a passivation film after forming a metal wiring functioning as a field plate on the third insulating film . The method for manufacturing a semiconductor device according to claim 1, wherein ammonia is added instead of nitrogen added to the source gas. 5. The method of manufacturing a semiconductor device according to claim 1, wherein nitrogen dioxide is added instead of nitrogen added to the source gas.

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