JP4081915B2 - Logic simulation method and apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a logic simulation method and apparatus for simulating the operation of a logic circuit.
[0002]
[Prior art]
Conventionally, as a method for simulating (simulating) the operation of a logic circuit, 30 to 200 parameters (for example, mobility, film thickness, etc.) that define the characteristics of each element such as a transistor constituting the circuit should be simulated. So-called analog simulation, which is set according to the conditions of the target circuit and solves equations that define the interrelationships between these parameters, etc., to obtain signal waveforms by sequentially calculating signal levels every minute time, and this analog simulation A so-called logic simulation is known in which the operation is reproduced at 0 and 1 levels in consideration of the delay time in each logic element (gate) instead of reproducing a precise waveform as described above.
[0003]
Among them, the former (analog simulation) can obtain the signal waveform precisely, but it requires a huge amount of calculation, so it is suitable for simulation with a relatively small circuit, while the latter (logic simulation). ) Can be obtained with a much smaller amount of calculation than the former, and is therefore suitable for simulation with a large-scale circuit such as an integrated circuit (up to several million gates in practice).
[0004]
In addition, in each gate constituting the logic circuit, self-heating occurs when a current flows, and this self-heating changes various parameters that define the characteristics of the gate, which affects the value of the current flowing through the gate, the signal delay time, and the like. However, conventionally, this self-heating is sufficiently small, and even if the simulation is performed while ignoring this, there is no particular problem.
[0005]
[Problems to be solved by the invention]
However, in recent years, due to the advent of SOI (Silicon On Insulator) type semiconductor devices and the significant improvement in the operating frequency of logic circuits, there is a tendency that the influence on various characteristics of logic circuits due to self-heating during operation increases. This self-heating effect cannot be ignored.
[0006]
That is, in an SOI device, each element such as a transistor constituting a gate is surrounded by a silicon insulating substrate and has low thermal conductivity. Therefore, when a current flows, heat generated by the current can be sufficiently dissipated. The logic circuit usually consumes power when the signal is inverted. However, if the operating frequency is improved, the number of signal inversions per unit time, that is, the power consumption increases. As a result, the amount of self-heating is increased.
[0007]
In addition, in order to maximize the performance of the logic circuit and operate at high speed, it is necessary to know the operation limit of the logic circuit. For that purpose, the delay time (operating frequency) of each gate and the entire logic circuit is required. Power consumption must be calculated accurately. On the other hand, as disclosed in, for example, Japanese Patent Laid-Open No. 5-226368, the temperature change due to self-heating is calculated, and the mobility, which is one of the parameters that define the characteristics of the element, is set as the temperature change. According to this, various simulations are performed, and an analog simulation that reflects the influence of self-heating is proposed. However, at present, no logic simulation reflecting the influence of such self-heating is performed.
[0008]
Therefore, in order to perform accurate simulation when self-heating is large, analog simulation must be used. However, as described above, it cannot be applied to a large-scale logic circuit in practice, and self-heating is not possible. There is a growing demand for logic simulations that reflect the effects of.
[0009]
Accordingly, an object of the present invention is to provide a logic simulation method and apparatus capable of obtaining accurate power consumption and delay time reflecting the effect of self-heating in order to solve the above-described problems.
[0010]
[Means for Solving the Problems]
In the logic simulation method according to claim 1, which is an invention made to achieve the above object, in the first procedure, in addition to a netlist and a test vector, a heating value and a delay time for each type of logic element, Using a library that defines the relationship between the power consumption per unit operation and the calorific value parameter set to specify the calorific value of each logical element, the delay time for each logical element constituting the logic circuit and Calculate power consumption, and in the second procedure, calculate the delay time and power consumption of the entire logic circuit based on the delay time and power consumption of each logic element calculated in the first procedure. Further, in the third procedure, the calorific value for each logic element is calculated based on the power consumption for each logic element calculated in the first procedure, and the first value is calculated based on the calculated value. Fever used in the procedure By setting the parameters, until a preset convergence condition is satisfied, to execute repeatedly the first and second steps.
[0011]
The unit operation is an operation of a minimum unit that involves power consumption, such as a rise or fall of a signal.
That is, at the start of simulation, it is impossible to know exactly how much the calorific value of each logic element will be, so the initial value is set appropriately assuming the calorific value parameter, and the first to third steps are executed. To do.
[0012]
As a result, the power consumption and delay time of each logic element and the entire logic circuit are calculated, and the amount of heat generated by each logic element, and hence the amount of heat generation parameter, is calculated according to the power consumption of each logic element. At this time, if the calorific value parameter assumed as the initial value is a reasonable value, the assumed value and the calculated value are approximately the same.
[0013]
However, if the initially set calorific value parameter value is too small, the power consumption calculated based on this setting will be larger than the actual value, the delay time will be smaller than the actual value, and conversely if the calorific value parameter value is too large. The power consumption is smaller than actual and the delay time is larger than actual.
[0014]
Accordingly, by repeating the process using the calorific value obtained based on the calculated power consumption, and thus the calorific value parameter, as a setting value when the first procedure is newly performed, the consumption calculated in the previous process is calculated. Power consumption, delay time, heat value (heat value parameter), and power consumption, delay time, heat value (heat value parameter) calculated in this process based on the heat value parameter calculated in the previous process The calculated value changes in the direction in which the deviation of the value converges.
[0015]
For this reason, by setting the convergence condition so that these deviations converge sufficiently, and repeatedly executing the process according to the above procedure until the convergence condition is satisfied, consumption that reflects the influence of self-heating of each logic element Power and delay time can be obtained with high accuracy.
[0016]
In particular, from the delay time, the limit of high-speed operation of the logic circuit can be obtained with high accuracy, so that the performance of the logic circuit can be maximized.
Next, in the logic simulation according to claim 2, in the actual logic circuit, the wiring connecting the logic elements has a wiring capacity. Therefore, in the first procedure, using the wiring information for defining the wiring capacity, The delay time and power consumption are calculated for each logical element that constitutes the circuit.
[0017]
For this reason, when the logic simulation method according to claim 2 is used, the power consumption and delay time of each logic element can be obtained with higher accuracy than the logic simulation method according to claim 1.
In the above-described logic simulation method, when the power consumption of each logic element is calculated using the test vector in the first procedure, the power consumption over the entire period of the test vector is calculated. The calculation is usually performed by reproducing the operation of each gate using a test vector, so that the number of transitions of each logic element can be known. Therefore, the number of transitions is multiplied by the power consumption required for each operation of the logic element. is doing.
[0018]
Here, the number of transitions is the number of times the above-described unit operation is performed.
Therefore, in the logic simulation method according to claim 3, in the first procedure, instead of the test vector, a state that defines the number of transitions of the logic transmitted by the wiring for each wiring connecting the logic elements. Using the transition information and the net list and library, the power consumption of each logic element is calculated, and the power consumption of the entire logic circuit is calculated.
[0019]
In this way, by using the state transition information input in advance, the power consumption of each logic element can be easily calculated in a short time without reproducing the operation of each gate using the test vector.
Considering the actual logic circuit design, there are several stages in designing a normal logic circuit. In the relatively early idea stage, the operation limit of a normal logic circuit is precisely defined. There is no need to know. However, it often happens that the logic circuit presented as an idea does not operate until reaching the final stage of design, and there may be a waste of time required for the design. It is required to design with some consideration of operating limits.
[0020]
Therefore, even in the idea stage, the power consumption etc. may be calculated after reproducing the operation of each gate using the test vector, but the number of logic circuits taken up in the idea stage is taken up in the final stage of the design. There are quite a lot of logic circuits compared to the number of things, and there are also logic circuits that have just come to mind, and it is unlikely that all of these logic circuits will be simulated to reproduce the behavior of individual gates using test vectors. The logic simulation methods described in claims 1 and 2 may be unsuitable for designing logic circuits at the idea stage.
[0021]
On the other hand, in designing an actual logic circuit, the operation of each logic element is usually performed in many cases.
Therefore, if the logic simulation method described in claim 3 is used, for example, in designing a logic circuit, the power consumption, which is a parameter for knowing the operation limit, can be easily obtained, and the operation limit is exceeded in the idea stage. Since the logic circuit is selected and eliminated, it is less likely that the logic circuit will not operate only after reaching the final design stage, and the logic circuit design can proceed efficiently. However, in the logic simulation method according to the third aspect, the power consumption can be accurately calculated by inputting an accurate number of transitions, so that it can be used at any stage of the design as well as the idea stage.
[0022]
In addition, if the logic simulation method according to claim 3 is used, a test vector cannot be prepared. For example, even in an application where the total power consumption consumed by the entire current logic circuit is simply obtained, an appropriate number of transitions is stored. It is possible to calculate it by just preparing the file.
[0023]
In addition, as in the ethical simulation method according to claim 4, in order to specify the amount of heat generated by each logic element using the wiring information that defines the wiring capacity of the wiring connecting each logic element in the first procedure. Based on the set calorific value parameter, the power consumption for each logic element constituting the logic circuit may be calculated.
[0024]
In this way, compared with the logic simulation according to the third aspect, it is possible to perform an accurate calculation of power consumption more in line with an actual logic circuit.
Next, in the logic simulation apparatus according to claim 5, the element information calculation means includes the relationship between the heat generation amount and the delay time for each type of logic element in addition to the net list and the test vector, and the heat generation amount and unit operation. The delay time and power consumption for each logic element that constitutes the logic circuit based on the calorific value parameter set to specify the calorific value of each logic element, using a library that defines the relationship with the per unit power consumption The overall information calculation means calculates the delay time and power consumption of the entire logic circuit based on the calculation result of the element information calculation means, and the heat generation amount calculation means is calculated by the element information calculation means. The heat generation amount for each logical element is calculated based on the power consumption for each logical element, and the activation control means sets the heat generation amount parameter based on the calculation result in the heat generation amount calculation means. It makes until preset convergence condition is satisfied, it starts repeatedly device information calculation means.
[0025]
The apparatus according to claim 5 implements the method according to claim 1, that is, the element information calculation means is the first procedure, the overall information calculation means is the second procedure, and the heat generation amount calculation means. In addition, the activation control means realizes the third procedure.
Therefore, if the logic simulation apparatus of the present invention is used, the same effect as that of the first aspect of the invention can be obtained.
[0026]
Next, in the logic simulation apparatus according to claim 6, the element information calculation means uses wiring information that defines the wiring capacity of the wiring connecting each logic element, in addition to the net list, the test vector, and the library. Based on the parameters, the delay time and power consumption for each logic element constituting the logic circuit are calculated.
[0027]
The device according to claim 6 realizes the method according to claim 2.
Therefore, if the logic simulation apparatus of the present invention is used, the same effects as those of the invention of the second aspect can be obtained.
By the way, as for the convergence condition used by the activation control means, for example, as described in claim 7, the delay time or power consumption of the entire logic circuit calculated by the overall information calculation means, or the activation control means. At least one of the calculated calorific value parameters is set as a determination parameter, and when the deviation from the previous calculation result is within a preset allowable range for the determination parameter, the convergence condition is satisfied. can do.
[0028]
In this case, by appropriately setting the size of the allowable range to be compared with the deviation, the calculated values (delay time, power consumption, heat generation amount parameter) used as the determination parameters can be obtained within a desired error.
Further, in the present invention, the convergence determination is performed not for each individual logic element but for the entire logic circuit, so that the processing amount is small, and therefore a simulation result can be obtained in a relatively short time.
[0029]
Note that the determination parameter may be any one of delay time, power consumption, and calorific value parameter, any two, or all three. In addition, when a plurality of determination parameters are set, all of them may satisfy the convergence condition only when they are within the respective allowable ranges, and if any one is within the allowable range, The convergence condition may be satisfied. The number of these determination parameters and the size of the allowable range may be appropriately set according to the required accuracy, the processing capability of the apparatus, the allowable processing time, and the like.
[0030]
By the way, as a convergence condition used in the activation control means, for example, if the process is repeated more than a certain number of times of restart, the deviation of the determination parameter can surely converge within an allowable range. If it is known, as described in claim 8, it may be considered that the convergence condition is satisfied when the element information calculation unit is restarted for a preset number of restarts.
[0031]
In this case, since the process for calculating and determining the deviation of the determination parameter as described above can be omitted, the process can be simplified.
Next, in the logic simulation apparatus according to claim 9, the activation control unit is configured to calculate the heat generation amount calculated by the heat generation amount calculation unit for each block obtained by dividing the logic circuit into one or more logical elements. An average value is obtained, and the average value of the heat generation amount is set as a heat generation amount parameter used in the element information calculation means.
[0032]
That is, when all the blocks are composed of one logical element, the calculated value by the calorific value calculation means is directly used as the calorific value parameter, and in the block composed of a plurality of logical elements, the average calorific value is It becomes a calorific value parameter common to the logic elements.
[0033]
In this way, by obtaining the heat generation amount parameter for each block, if the same logic element is present in the block, the power consumption per unit operation can be calculated in common, so that the processing amount is reduced. be able to.
Next, in the logic simulation device according to claim 10, the element information calculation means transmits the delay time and power consumption for each logic element for each wiring connecting each logic element. The present embodiment is different from the logic simulation apparatus according to claim 5 in that state transition information that defines the number of times of logic transition is used.
[0034]
The apparatus according to claim 10 realizes the method according to claim 3, that is, the element information calculation means is the first procedure, the overall information calculation means is the second procedure, and the calorific value calculation means. In addition, the activation control means realizes the third procedure.
Therefore, if the logic simulation apparatus of the present invention is used, the same effect as that of the invention of claim 3 can be obtained.
[0035]
Next, in the logic simulation device according to claim 11, the element information calculation means uses the wiring information that defines the wiring capacity of the wiring connecting each logic element in addition to the net list, the state transition information, and the library, and generates heat. Based on the quantity parameter, power consumption for each logic element constituting the logic circuit is calculated.
[0036]
The device according to claim 11 realizes the method according to claim 4.
Therefore, if the logic simulation apparatus of the present invention is used, the same effects as those of the invention of the fourth aspect can be obtained.
[0037]
Next, in the logic simulation device according to claim 12, the activation control unit includes at least one of the power consumption of the entire logic circuit calculated by the overall information calculation unit or the calorific value parameter calculated by the activation control unit. Any one is set as a determination parameter, and the convergence condition is satisfied for the determination parameter when a deviation from the previous calculation result is within a preset allowable range. In the logic simulation apparatus according to claim 13, the activation control means satisfies the convergence condition when the element information calculation means is restarted a preset number of times of restart. In the logic simulation device according to claim 14, the start-up control means includes an average value of the calorific values calculated by the calorific value calculation means for each block obtained by dividing the logic circuit into one or a plurality of logic elements. And the average value of the heat generation amount is set as the heat generation amount parameter.
[0038]
These logic simulation devices according to claims 12 to 14, respectively, except that the logic simulation is executed using the state transition information instead of the test vector and that the delay time cannot be used as the determination parameter. Since the same effects as those of the logic simulation devices of claims 9 to 9 (corresponding to claim 7 in claim 7, claim 13 in claim 8 and claim 14 in claim 9), the description thereof is omitted. To do.
[0039]
DETAILED DESCRIPTION OF THE INVENTION
[First embodiment]
A first embodiment of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing the overall configuration of a logic simulation apparatus 2 to which the present invention is applied.
[0040]
As shown in FIG. 1, the logic simulation apparatus 2 according to the present embodiment includes a storage device such as a floppy disk, a hard disk, and a magnetic tape, and includes types of logic elements (hereinafter referred to as gates) constituting a logic circuit to be simulated. A netlist NL that defines the connection relationship between the gates, a test vector VC that defines an input signal (hereinafter referred to as a test input) to the logic circuit when executing the simulation, a heat generation amount and a delay time for each gate type And a data storage unit 10 storing a library LB that defines the relationship between the amount of heat generation and the power consumption per unit operation, and an input device such as a keyboard, a mouse, a touch panel, etc. It consists of an input operation unit 12 for inputting various commands and a display such as LED, LCD, CRT, etc. A display unit 14 for displaying a procedure of an operation through the input operation unit 12 and a processing result for a command and the like, and a known microcomputer mainly composed of a CPU 16a, a ROM 16b, and a RAM 16c, are stored in the data storage unit 10. A simulation execution unit 16 that executes a process such as simulating a logic circuit in accordance with a command from the input operation unit 12 based on the netlist NL, test vector VC, and library LB, and displaying the processing result on the display unit 14; It has.
[0041]
Here, as shown in FIG. 2, the library LB includes types of gates such as a logical product circuit AND, a logical sum circuit OR, an exclusive logical sum circuit XOR... For each circuit INV), a logical expression (region M1) for generating an output (YB) for an input (A, B), an input capacitance (Ca, Cb) at an input terminal, and a drive capability at an output terminal R, power consumption per unit operation at the time of signal rise and fall (hereinafter referred to as unit gate power consumption) Pg, and delay time from when the signal input level changes until the output level changes (hereinafter, Various parameters (area M2) representing the characteristics of the gate such as Tg (referred to as gate delay time) are stored.
[0042]
The driving ability R, the unit gate power consumption Pg, and the gate delay time Tg are all functions fr (TH), fp (TH), ft having the self-heating value (hereinafter referred to as gate heating value) TH of the gate as parameters. Defined by (TH).
3A is an example of a graph showing the relationship between the gate heat generation amount TH and the unit gate power consumption Pg, and FIG. 3B is an example of a graph showing the relationship between the gate heat generation amount TH and the gate delay time Tg. As illustrated, the unit gate power consumption Pg decreases as the gate heat generation amount TH increases, while the gate delay time Tg increases as the gate heat generation TH increases. The functions fp and ft are defined so as to approximate these graphs obtained in advance through experiments or the like.
[0043]
In particular, the relationship between the gate heat generation amount TH and the unit gate power consumption Pg is that when the temperature rises due to self-heating, the junction leakage current (current leaking from the drain / source to the bulk) increases and the power consumption also increases. The graph does not necessarily have a downward-sloping graph as shown in FIG.
[0044]
Further, the netlist NL and the test vector VC are well-known ones conventionally used for this kind of simulation, and detailed description thereof is omitted here.
However, in the netlist NL, all the gates constituting the logic circuit are divided into a plurality of blocks composed of one or a plurality of gates, and the unit gate power consumption Pg and the gate delay time Tg are calculated using the library LB. When performing the above, a common heat generation amount parameter THp is used as the gate heat generation amount TH for each block.
[0045]
Next, simulation processing executed by the CPU 16a of the simulation execution unit 16 will be described with reference to the flowchart shown in FIG.
The program for this processing may be stored in the ROM 16b in advance, or may be loaded into the RAM 16c from an external storage device such as a floppy disk (not shown).
[0046]
This process is started when a command to start the simulation is input via the input operation unit 12, and first, in S100, an initial value of the heat generation amount parameter THp is set. This displays on the display unit 14 prompting the input of the initial value of the heat generation amount parameter THp, and when the value is input via the input operation unit 12, the input value is changed to the initial value of the heat generation amount parameter THp. This is done by setting as a value.
[0047]
Note that the initial value of the heat generation amount parameter THp may be automatically set to a fixed value (for example, 0) without being input from the outside.
In subsequent S110, unit gate power consumption Pg is calculated individually for all the gates constituting the logic circuit defined in the netlist NL according to the function fp defined in the library LB using the set calorific value parameter THp. Further, based on the unit gate power consumption Pg and the test vector VC, the power consumption (hereinafter referred to as gate power consumption) PW over the entire period of the test vector VC is calculated for each gate.
[0048]
In subsequent S120, the set heat generation amount parameter THp is used to calculate the gate delay time Tg individually for all the gates constituting the logic circuit defined in the netlist NL according to the function ft defined in the library LB.
In S130, power consumption (hereinafter referred to as total power consumption) Ph as the entire logic circuit is calculated by integrating all the gate power consumption PW calculated for each gate in S110, and in S140, Based on the gate delay time Tg calculated for each gate in the previous S120, the netlist NL, and the test vector VC, the input / output timing at each gate is calculated sequentially, thereby delaying the logic circuit as a whole. An output signal from the logic circuit for Th and the test vector VC (hereinafter referred to as total delay time) is obtained.
[0049]
In subsequent S150, based on the gate power consumption PW calculated in the previous S110, the following equation (1) is used to calculate the gate heat generation amount TH representing the magnitude of self-heating generated according to the power consumption PW. To do. However, a and b are constants determined by the physical properties of the substrate or the like on which the logic circuit is configured.
[0050]
TH = a · PW + b (1)
Note that the formula for calculating the gate heating value TH is not limited to the formula (1), and may be expressed by a formula other than the linear function. Further, the gate heat generation amount TH may be obtained using a table regardless of the calculation formula.
[0051]
Further, in S160, an average value is calculated for each block based on the gate heat generation amount TH obtained in S150, and this is set as the heat generation amount parameter THp.
In S170, if this step is executed for the first time after the start of this process, the total power consumption Ph, the total delay time Th, and the heat generation amount parameter THp calculated in S130, S140, and S160 are calculated as the previous calculated values. If the step has already been executed once or more after the activation of this process, that is, if the previous calculated value is stored, the total power consumption For all of Ph, total delay time Dh, and calorific value parameter THp, the difference between the current calculated value and the previous calculated value is calculated, and all of them are within a preset allowable range. Determine whether. If a negative determination is made, the current calculated value is stored as the previous calculated value, and then the process returns to S110. On the other hand, if an affirmative determination is made, the process proceeds to S180, and the simulation result shows the total power consumption Ph. , The total delay time Th, the output waveform (timing) for the test vector VC, and the like are displayed on the display unit 14, and then the present process is terminated.
[0052]
In S170, for example, when a negative determination is made continuously for a preset upper limit number of times, that is, when the determination parameter does not converge even if the process is repeated for the upper limit number of times, a message to that effect is displayed. 14 may be forcibly terminated.
[0053]
S110 and S120 correspond to the first procedure and element information calculation means, S130 and S140 correspond to the second procedure and overall information calculation means, and S150 to S170 correspond to the third procedure. , S160 corresponds to the calorific value calculation means, and S170 corresponds to the activation control means.
[0054]
Here, FIG. 5 is an explanatory diagram showing how the total power consumption Ph (that is, the heat generation amount TH) and the total delay time Th (that is, the operating frequency) that are sequentially calculated change by repeating the processing of S110 to S170. is there.
That is, as shown in the position of the number of iterations 0, if the initial value of the heat generation amount parameter THp is set to a value (for example, 0) smaller than the actual amount of heat generation (S100), based on this, the number of iterations 1 is set. As shown in the position, total power consumption Ph larger than actual and total delay time Th smaller than actual are calculated (S110 to S140). Based on the gate power consumption PW used to calculate the total power consumption Ph, the gate heat generation amount TH is calculated using the equation (1), and the heat generation amount parameter THp is calculated (S150, S160). In the first process, since the previous calculated value is not yet stored, the second process is performed based on the heat generation amount parameter THp without performing the convergence determination. Then, as shown in the position of the number of repetitions 2, the total power consumption Ph, the total delay time Th, and the heat generation amount parameter THp are calculated again (S110 to S160). At this time, the convergence determination is performed based on the deviations ΔP, ΔT, and ΔTHp from the previous calculated values. Here, since the deviations ΔP, ΔT, and ΔTHp do not fall within the allowable range, the third and subsequent times. Is performed.
[0055]
Thereafter, by repeating steps S110 to S170, it is determined that the deviation from the previous calculated value is all within the allowable range, that is, the convergence condition is satisfied (in FIG. 5, the number of iterations is 5). Is finished.
As described above, in the logic simulation device 2 of the present embodiment, the gate power consumption PG and the gate delay time Tg based on the set heat generation amount parameter THp, and further the determination parameters (total power consumption Ph, total delay time). Th, the calorific value parameter THp), and for each of these determination parameters Ph, Th, THp, until the deviation between the calculated value of the current process and the calculated value of the previous process becomes sufficiently small (within an allowable range). During this time, the above process is repeated using the newly calculated calorific value parameter THp.
[0056]
As a result, according to the logic simulation device of the present embodiment, the total power consumption Ph and the total delay time Th reflecting the influence of the self-heating (heat generation amount TH) of the gate are less than the allowable range used for the convergence determination. Thus, it can be obtained with high accuracy. Although it is limited to the combinational circuit, since the upper limit operating frequency of the logic circuit, that is, the limit of the operation speed of the logic circuit can be known from the total delay time Th, the performance of the logic circuit is maximized in terms of the operation speed. It can be pulled out.
[0057]
In this embodiment, the calorific value parameter THp is obtained for each block. Therefore, if the same type of gate is present in the block, the unit gate power consumption Pg and the gate delay time Tg can be calculated in common. The amount of processing can be reduced.
In addition, as for the block which becomes a calculation unit of the calorific value parameter THp, the whole logic circuit may be one block, or each gate may be one block. When each gate has one block, the gate heat generation amount TH calculated in S150 may be used as the heat generation amount parameter THp as it is.
[0058]
In the above embodiment, the unit gate power consumption Pg and the gate delay time Tg are calculated using the functions fp and ft defined in the library LB. Instead of these functions fp and ft, You may perform using the table showing a relationship (refer FIG. 3 (a) and (b)). When using a function, it may be difficult to maintain uniform accuracy in the entire area to be used, or the function may become complicated and increase the processing amount if an attempt is made to improve accuracy. If a table is used, it can be calculated with almost the same accuracy with the same processing amount over the entire area, no matter how complicated the graph representing the relationship to be realized.
By the way, in the above embodiment, the convergence determination at S170 is performed using all of the total power consumption Ph, the total delay time Th, and the heat generation amount parameter THp as determination parameters, and the previous calculated value and the current calculated value for all the determination parameters. Is determined to have converged when the deviation is within the allowable range, but if any one or only two of these three determination parameters fall within the allowable range, You may determine with having converged.
[0059]
Further, instead of using all three as determination parameters, any one or only two may be used.
In particular, when only the total delay time Th is used as a determination parameter, as shown in FIG. 6, the step of calculating the total power consumption Ph (S270) can be taken out of the processing loop and converged. Only when the determination is negative (S240-NO), the step (S250, S260) of calculating the calorific value parameter THp used for the next process has only to be executed, so the processing amount can be reduced. In the flowchart of FIG. 6, the processes of S200 to S230 and S250 to S280 are performed in the same manner only by partially rearranging the processes of S100 to S160 and S180, that is, S200 to S220 are S100 to S100. S120 and S230 are the same as S140, S250 to S260 are S150 to S160, S270 is S130, and S280 is S180.
[0060]
When only the total power consumption Ph is used as a determination parameter, the step of calculating the gate delay time Tg and the total delay time Th in FIG. 6 instead of the step of calculating the total power consumption Ph is shown in FIG. Just go outside.
Furthermore, when only the heat generation amount parameter THp is used as a determination parameter, as shown in FIG. 7, both steps (S360, S370) for calculating the total power consumption Ph and the total delay time Th are out of the processing loop. Therefore, the processing can be further reduced. S300 to S320 perform exactly the same processing as S100 to S120, S330 to S340 perform S150 to S160, S360 to S370 perform S130 to S140, and S380 perform S180.
[0061]
By the way, if it is known in advance that if the process is repeated a certain number of times or more, the deviation of the determination parameter falls within the allowable range, the number of repetitions may be set as the convergence condition without actually calculating the deviation of the determination parameter. it can.
In this case, as shown in FIG. 8, the steps (S450 to S470) for calculating the gate delay time Tg, the total power consumption Ph, and the total delay time Th can be taken out of the process loop and the convergence determination is performed. Only when the negative determination is made in (S420-NO), the calorific value parameter THp used for the next process may be calculated (S430, S440), and therefore the processing amount can be further reduced. S400 to S410 are the same as S100 to S110, S430 to S440 are S150 to S160, S450 to S470 are S120 to S140, and S480 is S180.
[0062]
In the above embodiment, the calculation of the gate power consumption PG and the gate delay time Tg (S110 and S120, S210 and S220, S310 and S320) is executed separately and sequentially, but these processes are performed simultaneously. May be executed. Similarly, the calculation of the total power consumption Ph and the total delay time Th (S130 and S140, S360 and S370, S460 and S470) may be executed simultaneously.
[Second Embodiment]
Next, a second embodiment of the present invention will be described.
[0063]
The wiring connecting the gates of the actual logic circuit has a considerable amount of wiring capacity. Therefore, the gate delay time Tg of the gate shown in the first embodiment is affected by this. Therefore, in the second embodiment, logic simulation is performed in consideration of the influence of the wiring capacity.
[0064]
Here, FIG. 9 is a block diagram showing the logic simulation device 2 of the second embodiment, and FIG. 10 is an explanatory diagram showing the contents of the wiring capacitance of each wiring.
The logic simulation device 2 of the present embodiment is different from the first embodiment in that the driving capability R, the gate delay time Tg, the unit gate power consumption Pg, and the like described above are calculated in consideration of the wiring capacity. Therefore, in the following description, only differences from the first embodiment will be described.
[0065]
First, in the overall configuration of the logic simulation device 2, as shown in FIG. 9, the data storage unit 10 stores the wiring information α in which the wiring capacitance LC of each wiring is stored in association with each wiring. Different from one embodiment. The wiring information α is input from the input operation unit 12. Specifically, for example, a logic circuit that performs simulation has two NOT circuits g1 and g2 and a NAND circuit g3 as shown in FIG. And the output side of the NOT circuits g1 and g2 is a logic circuit connected to the input side of the NAND circuit g3, as shown in FIG. 10B, the wiring connected to the input side of the NOT circuit g1 n1, a wiring n3 connected to the output side of the NOT circuit g1 and the input side of the NAND circuit g3, a wiring n2 connected to the input side of the NOT circuit g2, a connection to the output side of the NOT circuit g2 and the input side of the NAND circuit g3 Data relating to the wiring capacitance LC associated with each of the wiring n4 and the wiring n5 connected to the output side of the NAND circuit g3 (area M3). That.
[0066]
Next, in the present embodiment, the driving capability R, the gate delay time Tg, and the unit gate power consumption Pg include the function fr (TH, LC) using the wiring capacitance LC as a parameter in addition to the self-heating amount TH described above, It differs from the first embodiment in that it is defined in the library LB as fp (TH, LC) and ft (TH, LC). Incidentally, since the relationship between the wiring capacitance LC, the gate delay time Tg, and the unit gate power consumption Pg is generally well known for simulating the operation of the logic circuit, the description thereof is omitted in this embodiment. Of course, this relationship may be obtained in advance from experiments or the like.
[0067]
In this embodiment, based on the gate delay time Tg defined by the above-described function (fp (TH, LC), etc.), the process S110 and subsequent steps for calculating the gate power consumption PW in the flowchart shown in FIG. 4 are executed. It is doing.
When the logic simulation device 2 of the present embodiment having the above configuration is executed, in addition to the effects of the first embodiment, the gate power consumption PG, the total power consumption Ph, and the total delay time Th in consideration of the wiring capacitance LC are obtained. Therefore, compared with the logic simulation device 2 of the first embodiment, more accurate simulation can be performed in accordance with the actual situation.
[0068]
As the wiring information α, information calculated from an actual logic circuit may be used, or a virtual wiring capacity may be used.
In addition, the wiring information α is not limited to that input by the input operation unit 12, but may be loaded into the RAM 16c from an external device such as a floppy disk, or may be input in any manner.
[Third embodiment]
Next, a third embodiment of the present invention will be described.
[0069]
Here, FIG. 11 is a block diagram showing a schematic configuration of the logic simulation apparatus of this embodiment, FIG. 12 is an explanatory diagram for explaining the number of logic transitions for each wiring, and FIG. It is a flowchart showing the simulation process which the logic simulation apparatus 2 performs.
[0070]
In the following description, only differences from the first embodiment will be described.
In the following description, transition means that the signal level of the logic signal changes from 0 to 1, or 1 to 0, and the number of transitions means the number of times that the signal level has changed.
First, as shown in FIG. 11, the simulation apparatus 2 of the present embodiment is different from the first embodiment in that the state transition information β described above is stored in the data storage unit 10 instead of the test vector VC. A specific example of this state transition information β will be described for each wiring n1 to n5 as shown in FIG. 12 using the logic circuit shown in FIG. 10A illustrated in the second embodiment. (Region M5) defines the number of transitions (region M6) for each wiring.
[0071]
In the first embodiment, when the step of S110 is executed, the power consumption over the entire period of the test vector VC is calculated after calculating the number of logic transitions for each wiring connected to the gate. On the other hand, in the logic simulation device 2 of the present embodiment, in S510, the number of transitions of the logic signal transmitted by each wiring inputted in advance is multiplied by the unit gate power consumption Pg defined by fp (TH). The difference is that the gate power consumption PW is calculated. Specifically, for example, in the case of the gate g2 in FIG. 10A, the transition of the input side wiring n2 is 160 times and the transition of the output side n4 is 160 times, so that the gate power consumption for a total of 320 transitions. The calculation of PW = 320 fp (TH) is performed.
[0072]
Therefore, in the logic simulation device 2 of the present embodiment, the gate power consumption PW can be calculated without reproducing the operation of each gate using the test vector VC, so that the processing speed is remarkably increased.
Note that the logic simulation device 2 of this embodiment is different from the first embodiment in that the processing corresponding to S120 and S140 shown in FIG. 6 is not performed as shown in FIG. Among these, the processing corresponding to S120 is not performed because the gate delay time Tg calculated in S120 is used only for calculating the total delay time Dh, and is not used for calculating the total power consumption Ph. . Further, the reason why the processing corresponding to S140 is not performed is that it is necessary to reproduce the operation of each gate using the test vector VC only for that purpose, and the increased processing speed is suppressed by using the state transition information β. Because.
[0073]
However, since the gate delay time Tg of each gate does not need to reproduce the operation of the individual gate using the test vector VC, the gate delay time Tg is calculated by performing the process corresponding to S120 as necessary. May be.
In the processing of FIG. 13, S500 corresponds to S100, S510 corresponds to S110, S520 corresponds to S120, S530 corresponds to S130, S550 corresponds to S150, S560 corresponds to S160, S570 corresponds to S170, and S580 corresponds to S180. To do.
[0074]
When the logic simulation device 2 of the present embodiment described above is used, the gate power consumption PW is calculated without calculating the total delay time Dh and without reproducing the operation of each gate using the test vector VC. Therefore, the total power consumption Ph, which is a parameter for knowing the operation limit of the logic circuit, can be easily obtained in a short time.
[0075]
Therefore, if the logic simulation device 2 of the present embodiment is used, the logic circuit is excluded because the logic circuit exceeding the operation limit is found in the initial idea stage in the logic circuit design, so that the logic circuit operates only after reaching the final stage of the design. Since it is less likely that the user will not know, the logic circuit design can proceed efficiently.
[0076]
However, in the logic simulation device 2 of this embodiment, the total power consumption Ph can be accurately calculated by inputting an accurate number of transitions, so that it can be used at any stage of the design as well as the idea stage.
In addition, when the logic simulation device 2 of the present embodiment is used, a test vector VC cannot be prepared. For example, a file storing the number of transitions appropriate for the purpose of obtaining the total power consumption Ph consumed by the logic circuit is prepared. All that is required is to calculate the total power consumption Ph.
[0077]
The logical simulation apparatus 2 of this embodiment uses the library LB, the netlist NL, and the state transition information β to calculate the gate power consumption Pg in S510. However, as in the second embodiment, each gate The logic simulation may be executed using the wiring capacity of each wiring connecting the two.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a schematic configuration of a logic simulation apparatus according to a first embodiment.
FIG. 2 is an explanatory diagram showing the contents of a library in the first embodiment.
FIG. 3 is a graph showing the relationship between unit gate power consumption, gate delay, and self-heat generation in the first embodiment.
FIG. 4 is a flowchart showing the contents of simulation processing in the first embodiment.
FIG. 5 is an explanatory diagram illustrating a calculation process of total power consumption, total delay time, and the like when a simulation process is executed in the first embodiment.
FIG. 6 is a flowchart showing a modification of the simulation process in the first embodiment.
FIG. 7 is a flowchart showing a modification of the simulation process in the first embodiment.
FIG. 8 is a flowchart showing a modification of the simulation process in the first embodiment.
FIG. 9 is a block diagram illustrating a schematic configuration of a logic simulation apparatus according to a second embodiment.
FIG. 10 is an explanatory diagram showing the number of logical transitions for each wiring.
FIG. 11 is a block diagram illustrating a schematic configuration of a logic simulation apparatus according to a third embodiment.
FIG. 12 is an explanatory diagram showing the wiring capacity of each wiring.
FIG. 13 is a flowchart of logic simulation executed by the logic simulation apparatus of the third embodiment.
[Explanation of symbols]
2 ... Logic simulation device 10 ... Data storage unit
12 ... Input operation unit 14 ... Display unit 16 ... Simulation execution unit
Dh ... Total delay time LB ... Library NL ... Netlist
VC: test vector, α: wiring information, β: state transition information

Claims (14)

The operation of the logic circuit is simulated based on a netlist that defines the type of each logic element constituting the logic circuit and the connection relationship between the logic elements, and a test vector that defines a test input to the logic circuit. In the logic simulation method,
In addition to the netlist and test vector, a library that defines the relationship between the heat generation amount and the delay time for each type of the logic element and the relationship between the heat generation amount and the power consumption per unit operation is used. A first procedure for calculating a delay time and power consumption for each logic element constituting the logic circuit based on a calorific value parameter set for designating a calorific value;
A second procedure for calculating the delay time and power consumption of the entire logic circuit based on the delay time and power consumption of each logic element calculated in the first procedure;
The heat generation amount for each logical element is calculated based on the power consumption for each logical element calculated in the first procedure, and the heat generation amount parameter is set based on the calculated value. Until the convergence condition is satisfied, a third procedure for repeatedly executing the first and second procedures;
A logic simulation method comprising: In the first procedure, in addition to the net list, the test vector, and the library, wiring information that defines a wiring capacity of a wiring that connects the logic elements is used, and the logic circuit is configured based on the heat generation parameter. 2. The logic simulation method according to claim 1, wherein the delay time and the power consumption for each of the logic elements to be configured are calculated. In a logic simulation method for simulating the operation of a logic circuit, a netlist that defines the type of each logic element constituting the logic circuit and the connection relationship between each logic element, and each wiring that connects between each logic element, State transition information that defines the number of logic transitions transmitted by the wiring, the relationship between the heat generation amount and the delay time for each type of the logic element, and the relationship between the heat generation amount and the power consumption per unit operation A first procedure for calculating power consumption for each logical element constituting the logic circuit based on a calorific value parameter set for designating the calorific value of each logic element,
A second procedure for calculating the power consumption of the entire logic circuit based on the power consumption of each logic element calculated in the first procedure;
The heat generation amount for each logical element is calculated based on the power consumption for each logical element calculated in the first procedure, and the heat generation amount parameter is set based on the calculated value. Until the convergence condition is satisfied, a third procedure for repeatedly executing the first and second procedures;
A logic simulation method comprising: In the first procedure, in addition to the net list and the library, wiring information that defines wiring capacity of wirings connecting the logic elements is used, and each logic circuit is configured based on the heat generation parameter. 4. The logic simulation method according to claim 3, wherein the power consumption for each logic element is calculated. The operation of the logic circuit is simulated based on a netlist that defines the type of each logic element constituting the logic circuit and the connection relationship between the logic elements, and a test vector that defines a test input to the logic circuit. In logic simulation equipment,
In addition to the netlist and test vector, a library that defines the relationship between the heat generation amount and the delay time for each type of the logic element and the relationship between the heat generation amount and the power consumption per unit operation is used. Element information calculation means for calculating a delay time and power consumption for each logical element constituting the logic circuit based on a heat generation amount parameter set for designating a heat generation amount;
Overall information calculation means for calculating the delay time and power consumption of the entire logic circuit based on the calculation result of the element information calculation means;
A calorific value calculating means for calculating a calorific value for each logical element based on the power consumption for each logical element calculated by the element information calculating means;
By setting the heat generation amount parameter based on the calculation result of the heat generation amount calculation means, a start control means for repeatedly starting the element information calculation means until a preset convergence condition is satisfied,
A logic simulation apparatus comprising: In addition to the netlist, test vector, and library, the element information calculation means uses wiring information that defines the wiring capacity of the wiring that connects the logic elements, and based on the calorific value parameter, the element circuit calculates the logic circuit. 6. The logic simulation apparatus according to claim 5, wherein a delay time and power consumption for each of the logic elements constituting the same are calculated. The activation control means has at least one of the delay time or power consumption of the entire logic circuit calculated by the overall information calculation means, or the calorific value parameter calculated by the activation control means. The convergence parameter is satisfied when the deviation from a previous calculation result is within a preset allowable range for the determination parameter, wherein the convergence condition is satisfied. Logic simulation device. 7. The logic simulation according to claim 5, wherein the activation control unit satisfies the convergence condition when the element information calculation unit is restarted by a preset number of restarts. apparatus. The activation control unit obtains an average value of the heat generation amount calculated by the heat generation amount calculation unit for each block obtained by dividing the logic circuit into one or a plurality of logic elements, and calculates the average value of the heat generation amount 9 is set as the calorific value parameter, and the logic simulation apparatus according to claim 5. In a logic simulation that simulates the operation of a logic circuit, a netlist that defines the type of each logic element constituting the logic circuit and the connection relationship between the logic elements, and each wiring that connects the logic elements, State transition information that defines the number of logic transitions transmitted by wiring, a heat generation amount and a delay time for each type of the logic element, and a library that defines a relationship between the heat generation amount and power consumption per unit operation And element information calculation means for calculating power consumption for each logical element constituting the logic circuit based on a calorific value parameter set for designating the calorific value of each logical element,
Based on the calculation result of the element information calculation means, overall information calculation means for calculating the power consumption of the entire logic circuit;
A calorific value calculating means for calculating a calorific value for each logical element based on the power consumption for each logical element calculated by the element information calculating means;
By setting the heat generation amount parameter based on the calculation result of the heat generation amount calculation means, a start control means for repeatedly starting the element information calculation means until a preset convergence condition is satisfied,
A logic simulation apparatus comprising: The element information calculation means uses wiring information that defines wiring capacity of wirings connecting the logic elements in addition to the net list, state transition information, and library, and based on the calorific value parameter, the logic circuit The logic simulation apparatus according to claim 10, wherein the power consumption for each logic element constituting the circuit is calculated. The activation control means uses at least one of the power consumption of the entire logic circuit calculated by the overall information calculation means or the calorific value parameter calculated by the activation control means as a determination parameter. 12. The logic according to claim 10, wherein the convergence condition is satisfied when the deviation from the previous calculation result is within a preset allowable range for the determination parameter. Simulation device. 12. The logic simulation according to claim 10, wherein the start control means satisfies the convergence condition when the element information calculation means is restarted for a preset number of restarts. apparatus. The activation control unit obtains an average value of the heat generation amount calculated by the heat generation amount calculation unit for each block obtained by dividing the logic circuit into one or a plurality of logic elements, and calculates the average value of the heat generation amount 14. The logic simulation apparatus according to claim 10, wherein the heat generation amount parameter is set as the heat generation amount parameter.

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