JP4064635B2 - Semiconductor memory device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly to a semiconductor memory device having a fuse element (capacitor) for recording information for replacing a defective memory cell with a redundant memory cell. Furthermore, the present invention relates to a protection circuit technique for protecting a circuit from an overcurrent when the fuse element is destroyed.
[0002]
[Prior art]
2. Description of the Related Art A semiconductor memory device such as a dynamic RAM is composed of memory cells composed of MOSFETs (MOS field effect transistors) and capacitors arranged in a matrix, and each memory cell has a signal line (word line) in the row direction and a column direction. This can be selected by selecting both of the signal lines (bit lines). The manufacture of LSI memory requires an extremely clean environment, and there is a high possibility that defective memory cells are generated due to fine dust or the like. For this reason, redundant circuits are provided in many LSI memories, and defective memory cells are replaced using redundant memory cells. When a defective memory cell is found at the stage of the wafer probe test, the defective memory cell can be replaced with a redundant memory cell by the information recorded by cutting the laser phase, and the defective chip can be relieved.
[0003]
If a defective memory cell is found in the inspection stage after package sealing, the laser phase cannot be cut. Therefore, the trench capacitor constituting the memory cell, which is disclosed in the previous application (Japanese Patent Application No. 11-241778) by the applicant of the present application that has not yet been published at the time of filing the present application, is used as a fuse element, and the external power supply A technique for recording information on the fuse element can be used by applying an overvoltage to one of the electrodes to break the dielectric film.
[0004]
6A and 6B show a configuration of a conventional fuse element using a trench capacitor. FIG. 6A is a plan view, and FIG. 6B is a cross-sectional view taken along the line BB ′ in FIG. Indicates. As shown in FIG. 6B, an n well 58 to which an n-type impurity is added is disposed on the semiconductor substrate 57, and a trench is formed inside the n well 58. A trench internal electrode 61 is embedded inside the trench through a thin dielectric film 60. The trench capacitor includes a pair of electrodes including an n-well 58 and a trench internal electrode 61, and a dielectric film 60 disposed between these electrodes. It consists of and. Metal interconnections 72a and 72b are connected to the trench internal electrode 61 and the n-well 58, respectively. An oxide film 67 is buried above the trench. As shown in FIG. 6A, an n well 58 is exposed on the surface of the substrate 57 in a region where the metal wirings 72a and 72b are connected to the semiconductor substrate 57, and an STI (Shallow Trench) made of an oxide film in the other region. Isolation) 69 is formed.
[0005]
7 and 8 are main process sectional views showing a method of manufacturing the conventional fuse element shown in FIG. First, in FIG. 7A, after n-type impurities are diffused in the upper part of the semiconductor substrate 57 to form an n-well 58, RIE processing of the substrate 57 is performed using an oxide film 76 having a window in a region for forming a trench as a mask. The trench 74 is formed. At this time, etching proceeds in the lateral direction at the interface between the oxide film 76 and the substrate 57, and a shallow groove 75 is simultaneously formed.
[0006]
In FIG. 7B, a dielectric film 60 is formed inside the trench 74 and further polysilicon 61 is embedded. Then, the dielectric film 60 and the polysilicon 61 other than the inside of the trench 74 are removed by CDE (Chemical Dry Etching). Next, the substrate 57 is selectively removed by etching using the oxide film 77 having a window in a region where the STI 69 is formed as a mask.
[0007]
In FIG. 7C, an oxide film is deposited on the entire surface of the substrate 57 and planarized to form an STI 69 and an oxide film 67 embedded in the shallow trench 75 at the same time. 8A, an interlayer insulating film 71 is deposited on the substrate 57, and the interlayer insulating film 71 and the oxide film 67 in a region where the metal wirings 72a and 72b are connected are selectively etched away using a resist 78. To do. In FIG. 8B, grooves having the same pattern as the metal wirings 72 a and 72 b are formed in the interlayer insulating film 71, and the metal film 72 is deposited on the entire surface of the substrate 57. By performing planarization and forming the insulating film 73, the fuse element shown in FIG. 6 can be formed.
[0008]
[Problems to be solved by the invention]
When the above-described trench capacitor is used as a fuse element, a fuse circuit as shown in FIG. 9 is generally configured. That is, an external power supply 54 is connected to one electrode of the fuse element 51, and a transistor 55 for selecting the fuse element 51 and a transistor 56 for outputting information recorded in the fuse element 51 are connected to the other electrode. A control circuit unit 52 connected in parallel is connected. By applying an overvoltage higher than the dielectric film withstand voltage by the external power source 54, the dielectric film of the fuse element 51 selected by the transistor 55 is destroyed. By turning on the transistor 56, information is output depending on the resistance of the fuse element 51.
[0009]
In order to destroy the dielectric film, an overvoltage of about 5 to 10 V is usually required, and at the moment when the dielectric film is destroyed, the electric charge previously charged in the capacitor 51 becomes an overcurrent of about 5 to 30 mA at a time. It flows in the circuit. This overcurrent may destroy the junctions of the transistors 55 and 56 that are normally operated at a voltage of about 1 to 3 V and are disposed at the subsequent stage of the fuse element 51. Therefore, the overvoltage applied to the fuse element 51 may be reduced. It is necessary to keep it low. However, if the overvoltage is lowered, the dielectric film cannot be sufficiently destroyed, the resistance of the fuse element 51 after the destruction cannot be lowered sufficiently, and as a result, writing of information to the fuse element 51 is not possible. It will be enough.
[0010]
As described above, in the fuse circuit using the capacitor constituting the memory cell, the overvoltage applied from the external power supply 54 can sufficiently reduce the resistance of the fuse element 51 after being destroyed, and is disposed in the subsequent stage of the fuse element 51. Therefore, it is necessary to prevent an overcurrent from flowing through the control circuit unit 52.
[0011]
Further, the trench capacitor having the configuration shown in FIG. 6 and the manufacturing method shown in FIGS. 7 and 8 have many different points from the configuration and manufacturing method of the trench capacitor constituting the existing dynamic RAM memory cell. There is also a need to add new process steps.
[0012]
The present invention has been made to solve such problems of the prior art, and its object is to have no breakdown failure (conductivity failure) and to destroy a circuit connected to a fuse element. A semiconductor memory device and a method for manufacturing the same are provided.
[0013]
Specifically, by maintaining a high overvoltage at the time of dielectric film breakdown, the resistance of the fuse element after breakdown is sufficiently low, and an overcurrent that flows immediately after the dielectric film breakdown does not flow to the transistor connected to the fuse element. The present invention provides a semiconductor memory device having a fuse circuit and a method for manufacturing the same.
[0014]
[Means for Solving the Problems]
In order to achieve the above object, the first feature of the present invention is composed of a pair of electrodes and a dielectric film sandwiched between these electrodes, and an overvoltage is applied to one of the electrodes to destroy the dielectric film. The fuse element in which information is recorded, the control circuit unit connected to the other electrode of the fuse element, and the dielectric film was destroyed by being connected to the other electrode of the fuse element in the previous stage of the control circuit unit This is a semiconductor memory device having a fuse circuit provided with a protection circuit portion through which an overcurrent flowing through the fuse element flows immediately after.
[0015]
According to the first feature of the present invention, immediately after the dielectric film of the fuse element is broken, the electric charge charged in the fuse element flows as an overcurrent at a time, and this overcurrent is detected at the front stage of the control circuit unit. Therefore, even when a large overvoltage is applied to the fuse element, it does not flow to the transistor in the control circuit portion.
[0016]
In the first feature of the present invention, the protection circuit unit is a protection diode arranged in a reverse direction with respect to an overcurrent flow, and a threshold voltage (Zener breakdown voltage) of the Zener breakdown of the protection diode is set. It is desirable to be smaller than the overvoltage. Although the Zener breakdown occurs with respect to an overvoltage applied to the protection diode immediately after the dielectric film is broken, the Zener breakdown does not occur with respect to a normal voltage applied to output information recorded in the fuse element. Therefore, the overcurrent that flows through the fuse element immediately after the breakdown of the dielectric film flows through the protection diode, but for the normal voltage, no current flows through the protection diode and flows to the control circuit.
[0017]
Further, it is desirable that the fuse element is constituted by a capacitor having a trench structure, and a protective diode is formed inside the capacitor. By forming the protection diode inside the existing trench structure capacitor, the area occupied by the circuit can be reduced.
[0018]
Specifically, the capacitor and the protection diode are formed inside the semiconductor substrate, a first conductivity type semiconductor layer disposed at the bottom of the semiconductor substrate, a second conductivity type semiconductor layer disposed at the top of the semiconductor substrate, and the semiconductor substrate. A trench reaching the first conductivity type semiconductor layer even when the bottom is shallow, a first conductivity type diffusion layer disposed adjacent to the trench above the second conductivity type semiconductor layer, and the first conductivity type of the inner wall of the trench A dielectric film disposed in a portion where the semiconductor layer is exposed (referred to as “trench lower part”), a first conductor embedded inside the dielectric film, and the second conductive semiconductor layer on the inner wall of the trench are exposed. The insulating film disposed in the protruding portion (referred to as “trench middle portion”), the second conductor embedded inside the insulating film, and the portion where the diffusion layer on the inner wall of the trench is exposed (“trench upper portion”) 3rd lead embedded in It is preferable that at least consists of a body.
[0019]
Here, the capacitor includes a pair of electrodes including a first conductor embedded in the trench and a first conductivity type semiconductor layer disposed around the first conductor, and between these electrodes. This is a capacitor having a trench structure composed of a disposed dielectric film. The protective diode is formed of a PN junction between the diffusion layer, which is a component of the capacitor, and the second conductivity type semiconductor layer, and is formed inside the capacitor.
[0020]
Note that the concentration of the first conductivity type impurity added to the diffusion layer may be the same as the concentration of the diffusion layer such as the source / drain of the transistor constituting the memory cell in the semiconductor memory device.
[0021]
The second feature of the present invention is that
(1) a first step of forming a first conductive type semiconductor layer and a second conductive type semiconductor layer on a lower part and an upper part of a semiconductor substrate,
(2) a second step of forming a trench reaching the first conductivity type semiconductor layer even if the bottom is shallow, inside the semiconductor substrate;
(3) a third step of forming a dielectric film on a portion of the inner wall of the trench where the first conductivity type semiconductor layer is exposed (referred to as “trench lower part”);
(4) a fourth step of embedding the first conductor inside the dielectric film;
(5) a fifth step of forming an insulating film in a lower portion (referred to as “trench middle portion”) of the portion where the second conductivity type semiconductor layer on the inner wall of the trench is exposed;
(6) a sixth step of embedding the second conductor inside the insulating film;
(7) a seventh step of burying a third conductor in an upper portion (referred to as “trench upper portion”) of the portion where the second conductivity type semiconductor layer on the inner wall of the trench is exposed;
(8) an eighth step of forming a first conductivity type diffusion layer exposed on the surface of the semiconductor substrate in contact with the side surface of the third conductor;
A method for manufacturing a semiconductor memory device having at least Here, the eighth step may be performed simultaneously with the step of forming diffusion layers such as the source and drain of the transistors constituting the memory cells in the semiconductor device.
[0022]
In the second feature of the present invention, it is desirable that the third conductor embedded in the seventh step is doped with a first conductivity type impurity having a higher concentration than the first and second conductors. . The eighth step is preferably a step of performing a predetermined heat treatment to diffuse the first conductivity type impurity added to the third conductor into the second conductivity type semiconductor layer. The impurity concentration of the diffusion layer formed in the eighth step can be controlled independently from the concentration of the diffusion layer such as the source / drain of the transistor constituting the memory cell. Therefore, the threshold voltage for zener breakdown of the protective diode can be set lower than the junction breakdown voltage of the transistor, and the protective diode can be broken down (zener breakdown) before the transistor junction is destroyed. it can.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and width of the layers, the ratio of the thicknesses of the layers, and the like are different from the actual ones. In addition, it goes without saying that portions with different dimensional relationships and ratios are also included in the drawings.
[0024]
The semiconductor memory device according to the embodiment of the present invention is a dynamic RAM (DRAM) in which memory cells each composed of one transistor and one capacitor are arranged in a matrix. In addition to the memory cells, the DRAM further includes a redundant circuit for replacing defective memory cells with redundant memory cells, and a fuse circuit for recording replacement information. The defective memory cell found in the inspection stage after the package sealing is replaced with the redundant memory cell in the redundant circuit according to the replacement information recorded in the fuse circuit, and the defective chip is relieved.
[0025]
FIG. 1 is a circuit diagram showing a configuration of a fuse circuit in a DRAM. As shown in FIG. 1, the fuse circuit includes at least a fuse element 1, a control circuit unit 2, and a protection circuit unit 3.
[0026]
The fuse element 1 is a capacitor composed of a pair of electrodes (8, 11) and a dielectric film sandwiched between these electrodes. Replacement information is recorded in the capacitor 1 by applying an overvoltage to one electrode 8 of the capacitor 1 to break the dielectric film. The capacitor 1 constituting the fuse element can be formed simultaneously in the same process as the capacitor constituting the memory cell, and the element structure is substantially the same. An overvoltage for destroying the dielectric film is supplied by an external power supply 4 connected via an electrode pad in the semiconductor chip. In the case of a DRAM having a normal operating voltage of 1 to 3 V, an overvoltage of about 5 to 10 V is supplied from the external power supply 4 to one electrode 8 when the dielectric film is destroyed.
[0027]
The control circuit unit 2 includes a MOSFET (MOS type field effect transistor) 5 for selecting the capacitor 1 when destroying the dielectric film, and a MOSFET 6 for selecting the capacitor 1 when reading information recorded in the capacitor 1. It consists of and. The MOSFETs 5 and 6 are connected in parallel to the other electrode 11 of the capacitor 1. The other electrode of the MOSFET 5 is connected to the installation potential, and the information recorded in the capacitor 1 is output from the other electrode of the MOSFET 6. This information is input to a redundant circuit or the like, and replacement of a defective memory cell with a redundant memory cell is executed. The junction breakdown voltage of the source / drain of the MOSFETs 5 and 6 is larger than a normal operating voltage of about 1 to 3 V, but smaller than an overvoltage (5 to 10 V) for destroying the dielectric film.
[0028]
The protection circuit unit 3 is a circuit for flowing an overcurrent that flows through the capacitor immediately after the insulating film is destroyed. Specifically, the protection circuit unit is a protection diode 3 arranged in the reverse direction with respect to the overcurrent flow. The protection diode 3 is connected to the other electrode 11 of the capacitor 1 in the previous stage of the control circuit unit 2. The Zener breakdown withstand voltage of the protection diode 3 is smaller than the overvoltage (5 to 10 V) and larger than the normal operating voltage (1 to 3 V). The protection diode 3 is connected between the other electrode 11 of the capacitor 1 and the ground potential in the previous stage of the control circuit unit 2. In FIG. 1, since a positive overvoltage is applied to one electrode 8, an overcurrent flows from the capacitor 1 toward the ground potential immediately after the insulating film is broken. Therefore, the forward direction of the protective body odd 1 is directed from the ground potential to the capacitor 1.
[0029]
When recording information in the fuse circuit having the above-described configuration or reading the recorded information, the fuse circuit operates as follows. That is, when the transistor 5 is turned on, the other electrode 11 of the capacitor 1 is connected to the ground potential. Then, by applying a positive overvoltage (5 to 10 V) to one electrode 8 of the capacitor 1, the dielectric film is destroyed and information is recorded in the capacitor 1. Even if an overvoltage is applied while the transistor 5 is off, the dielectric film of the capacitor 1 is not destroyed.
[0030]
On the other hand, when reading the information recorded in the capacitor 1, a normal voltage (1 to 3 V) is applied to one electrode 8 of the capacitor 1 using the external power supply 4. Then, by turning on the transistor 6, information on the magnitude of the resistance of the capacitor 1 is read out. That is, since the resistance of the capacitor 1 whose dielectric film is broken is small, the applied normal voltage is output as it is. However, since the resistance of the capacitor 1 whose dielectric film is not broken is very large, a ground potential is output.
[0031]
Next, the operation of the protection diode 3 will be described. Immediately after the dielectric film of the capacitor 1 is destroyed, the charge charged in the other electrode 11 of the capacitor 1 flows as an overcurrent at a time, and the overvoltage supplied from the external power supply 4 is arranged in the subsequent stage of the capacitor 1. Applied to the protection diode 3 and the control circuit unit 2. Since the Zener breakdown withstand voltage of the protection diode 3 is smaller than the overvoltage (5 to 10 V), the protection diode 3 breaks down with respect to the overvoltage. Therefore, the overcurrent that flows immediately after the breakdown of the dielectric film flows through the protective diode 3 arranged in the previous stage of the control circuit unit 2. On the other hand, the Zener breakdown voltage of the protective diode 3 is higher than the normal voltage (1-3V). large Therefore, the zener breakdown does not occur for a normal voltage applied when reading recorded information. Therefore, no current flows through the protection diode 3 for a normal voltage, and the current flows to the control circuit unit 2.
[0032]
FIG. 2 is a diagram schematically showing the structure of the capacitor 1 and the protection diode 3 in the fuse circuit shown in FIG. 1. FIG. 2 (a) is a plan view, and FIG. Sectional drawing along the AA 'cut surface of a) is shown. As illustrated in FIG. 2B, the capacitor 1 includes a first conductor (first polysilicon) 11 embedded in a trench formed in the semiconductor substrate 7 and the periphery of the first polysilicon 11. A trench-structured capacitor comprising a pair of electrodes composed of a first conductivity type semiconductor layer (n-well) 8 disposed in the substrate and a dielectric film 10 disposed between these electrodes (11, 8) (Hereinafter referred to as “trench capacitor”). The protective diode 3 is formed of a PN junction between the diffusion layers (17, 20), which are constituent elements of the trench capacitor, and the second conductivity type semiconductor layer (p well) 9, and is formed inside the trench capacitor. Yes. Note that one electrode 8 of the capacitor 1 shown in FIG. 1 corresponds to the n-well 8 and the other electrode 11 corresponds to the first polysilicon 11.
[0033]
The n well 8 is buried under the semiconductor substrate 7, and the p well 9 is disposed on the n well 8. The p-well 9 is connected to the ground potential, but the breakdown voltage between the n-well 8 and the p-well 9 is larger than the overvoltage (5 to 10 V). The bottom 32 of the trench reaches the lower part of the n-well 8. An n-type diffusion layer (stain diffusion layer) 17 is disposed on the p-well 9 adjacent to the trench.
[0034]
A portion of the inner wall of the trench where the n-well 8 is exposed (the lower portion of the trench) 12a has a silicon nitride film (Si ₃ N ₄ Film) and silicon oxide film (SiO2) ₂ A thin film dielectric film 10 made of a laminated film (NO film) or the like is uniformly disposed, and a first polysilicon 11 is embedded inside the dielectric film 10. A thin insulating film 13 made of an oxide film or the like is uniformly arranged on a portion (bench middle portion) 12b where the p-well 9 is exposed on the inner wall of the trench, and a second conductor (second conductor) is formed inside the insulating film 13. (Polysilicon) 14 is embedded. A third conductor (third polysilicon) 15 is embedded in a portion (upper trench) 12c where the dyed diffusion layer 17 on the inner wall of the trench is exposed. A trench cap 16 made of an oxide or the like is embedded on the third polysilicon 15. The first polysilicon 11 is connected to the second polysilicon 14, and the second polysilicon 14 is connected to the third polysilicon 15. The third polysilicon 15 is connected to the dye diffusion layer 17.
[0035]
The first polysilicon 11 is insulated and separated from the n-well 8 by the dielectric film 10, and the second polysilicon 14 is insulated and separated from the p-well 9 by the insulating film 13. As described above, the trench capacitor is composed of the n-well 8, the first polysilicon 11, and the dielectric film 10, in order to reduce the capacitance between the p-well 9 and the second polysilicon 14. The insulating film 13 is formed thicker than the dielectric film 10. The n-type dye diffusion layer 17 is disposed adjacent to the third polysilicon 15 and the trench cap 16, is in contact with the side surface of the third polysilicon 15, and a part thereof is exposed on the surface of the semiconductor substrate 7. ing.
[0036]
An n-type extraction region 18 that reaches the n-well 8 from the surface of the semiconductor substrate 7 is disposed in a region different from the region where the trench capacitor is formed. Further, an STI 19 made of an oxide film for element isolation is buried in the upper portion of the semiconductor substrate 7 except for the region where the trench capacitor and the lead region 18 are disposed. Further, an n-type SD diffusion layer 20 formed simultaneously with the source / drain of the MOSFET constituting the memory cell is disposed on the semiconductor substrate 7 in the region where the trench capacitor and the extraction region 18 are disposed. The SD diffusion layer 20 is connected to the dyeing diffusion layer 17 and the extraction region 18 respectively. As described above, the protection diode 3 is composed of a PN junction between the diffusion layers (17, 20) and the p-well 9, but the Zener breakdown voltage of the protection diode 3 is the shape of the dye diffusion layer 17 or the SD diffusion layer 20. Alternatively, it is determined by the impurity concentration of the diffusion layers (17, 20) and the p-well 9.
[0037]
An interlayer insulating film 21 is disposed on the semiconductor substrate 7, and a metal wiring 22 a connected to the dyed diffusion layer 17 and the SD diffusion layer 20 is disposed on the interlayer insulating film 21 and connected to the extraction region 18. Metal wiring 22b is disposed. A protective film 23 is disposed on the metal wirings 22a and 22b. The control circuit unit 2 shown in FIG. 1 is connected to the metal wiring 22a, and the external power source 4 is connected to the metal wiring 22b.
[0038]
FIG. 2A shows the arrangement of the constituent members on the surface of the semiconductor substrate 7. As shown in FIG. 2A, a dyed diffusion layer 17 is disposed so as to surround the outer periphery of the trench cap 16 and the third polysilicon 15 embedded in the trench upper part 12 c, and is disposed outside the dyed diffusion layer 17. An SD diffusion layer 20 is disposed. The metal wiring 22 a is connected so as to straddle the dyeing diffusion layer 17 and the SD diffusion layer 20. In a region different from the region where the trench capacitor is formed, an extraction region 18 connected to the n-well 8 is disposed, and a metal wiring 22b is connected inside the extraction region 18. The metal wiring 22a only needs to be connected to at least one of the dye diffusion layer 17 and the SD diffusion layer 20, and the connection position of the metal wiring 22a is limited to the position shown in FIG. It is not something. Further, since the third polysilicon 15 is disposed under the trench cap 16, the third polysilicon 15 is not exposed on the surface of the semiconductor substrate 7, but the diffusion diffusion layer 17 is formed on the entire outer periphery of the third polysilicon 15. It is shown to show that it is arranged and connected.
[0039]
Note that the fuse element 1 shown in FIGS. 2A and 2B has substantially the same configuration as a trench capacitor that constitutes a memory cell in an existing DRAM. A trench capacitor constituting a memory cell is used as the fuse element 1 and the protection diode 3. Also, the fuse element 1 and the protection diode 3 shown in FIGS. 2A and 2B can be formed by substantially the same manufacturing process as the trench capacitor of the memory cell, as will be described later.
[0040]
Next, the operation of the trench capacitor 1 and the protection diode 3 shown in FIGS. 2A and 2B will be described. The overvoltage supplied from the external power supply 4 is applied to one electrode of the trench capacitor, that is, the n-well 8 through the metal wiring 22b, the SD diffusion layer 20, and the lead region 18. By turning on the transistor 5 in the control circuit section 2 shown in FIG. 1, the metal wiring 22 a, the diffusion regions (17, 20), the third polysilicon 15, and the second polysilicon 14 are used. A ground potential is applied to one polysilicon 11. Then, the dielectric film 10 disposed between the n-well 8 and the first polysilicon 11 is destroyed by overvoltage, and the n-well 8 and the first polysilicon 11 are in a conductive state (resistance is small).
[0041]
Immediately after the dielectric film 10 is destroyed, the charge charged in the first polysilicon 11 flows out toward the control circuit unit 2 at once as an overcurrent, and the overvoltage supplied from the external power supply 4 is The voltage is applied to the second polysilicon 14, the third polysilicon 15, the dyed diffusion layer 17, the SD diffusion layer 20, and the like connected to the subsequent stage of the polysilicon 11. As described above, since the ground potential is applied to the p-well 9, immediately after the dielectric film 10 is destroyed, an overvoltage is also applied to the PN junction 3 between the diffusion layers (17, 20) and the p-well 9. Is applied as a reverse bias. Since the Zener breakdown withstand voltage of the PN junction 3 is smaller than the overvoltage, the Zener breakdown occurs with respect to the overvoltage. Therefore, the overcurrent that flows immediately after the breakdown of the dielectric film 10 is a protection diode composed of the PN junction between the dye diffusion layer 17 and the SD diffusion layer 20 and the p-well 9 disposed before the control circuit unit 2. 3, no overcurrent flows through the MOSFET in the control circuit unit 2.
[0042]
3 to 5 show main steps in the method of manufacturing the trench capacitor 1 and the protection diode 3 according to the embodiment of the present invention shown in FIGS. 2A and 2B, respectively. It is sectional drawing. A method of manufacturing the trench capacitor 1 and the protection diode 3 shown in FIGS. 2A and 2B will be described with reference to the respective drawings of FIGS.
[0043]
(A) First, as shown in FIG. 3A, an n-well 8 and a p-well 9 are formed in the lower and upper portions of the semiconductor substrate 7, respectively. Specifically, a semiconductor substrate 7 having a p-type impurity concentration comparable to that of the p well 9 is first prepared. By using an ion implantation method, n-type impurity ions accelerated at high speed are implanted into the surface of the semiconductor substrate 7, and n-type impurities are buried under the p-type semiconductor substrate 7. The n-type impurity implanted by performing a predetermined heat treatment is activated, and an n-well 8 is formed under the semiconductor substrate 7. At the same time, a p-well 9 is formed on the n-well 8. Thereafter, the silicon oxide film on the semiconductor substrate 7 is removed by etching using hydrofluoric acid or the like.
[0044]
Next, a silicon oxide film having a window in a region where the extraction region 18 is formed is formed by photolithography and RIE. Then, n-type impurity ions are selectively implanted into the semiconductor substrate 7 using the silicon oxide film as a mask by an ion implantation method, and subjected to a predetermined heat treatment to a region reaching the n well 8 from the surface of the semiconductor substrate 7. An extraction region 18 to which an n-type impurity is added is formed.
[0045]
(B) Next, as shown in FIG. 3B, a trench (groove) 24 reaching the lower portion of the n-well 8 even if the bottom 32 is shallow is formed in the semiconductor substrate 7. Specifically, a silicon oxide film having a window in a region where the trench 24 is to be formed is formed on the semiconductor substrate 7 by using a photolithography method and an RIE method, and this silicon oxide film is used as a mask to select the silicon oxide film. The semiconductor substrate 7 is etched. The etching of the semiconductor substrate 7 ends when the trench depth reaches the lower part of the n-well 8. The trench 24 can be formed by removing the silicon oxide film on the semiconductor substrate 7.
[0046]
Next, a thin dielectric film 10 is uniformly formed on the inner wall of the trench 24 and the surface of the semiconductor substrate 7 using a CVD method (Chemical Vapor Deposition method). Specifically, first, Si ₃ N ₄ A film is formed by a CVD method. And SiO ₂ A film is formed. The dielectric film 10 is made of Si. ₃ N ₄ Film and SiO ₂ It consists of a laminated film with a film, and its film thickness is 3 to 5 nm.
[0047]
Next, using a spin coating method or the like, a resist solution is applied inside the trench and on the semiconductor substrate 7, and the entire resist surface is exposed and developed. Using an etching method having a larger selection ratio than the dielectric film 10 to the resist, the resist formed on the semiconductor substrate 7 is selectively removed, and the resist 25 embedded in the trench lower portion 12a is left and the trench is left. Other resists in the inside are removed. Here, the case where the upper end of the remaining resist 25 and the interface between the n-well 8 and the p-well 9 coincide is shown, but the present invention is not limited to this and the resist is not limited to this. The upper end of 25 may be disposed below the well interface, that is, on the bottom 32 side of the trench.
[0048]
(C) Next, the dielectric film 10 exposed on the semiconductor substrate 7 and inside the trench 24 is selectively removed using a wet etching method having a larger selection ratio than the resist 25 with respect to the dielectric film 10. Thereafter, the resist 25 buried in the trench lower portion 12a is removed by using the same method as the etching method for the resist 25 described above. As shown in FIG. 3C, the dielectric film 10 can be formed on the portion (the trench lower portion) 12a where the n-well 8 is exposed on the inner wall of the trench.
[0049]
Next, polysilicon (polycrystalline silicon) to which an n-type impurity is added is buried in the entire surface of the semiconductor substrate and inside the trench by using a CVD method. By using an etching method such as the CDE method, the polysilicon buried in the trench middle portion 12b and the trench upper portion 12c is removed while leaving the first polysilicon 11 buried in the trench lower portion 12a. As shown in FIG. 3C, the first polysilicon 11 can be embedded inside the dielectric film 10.
[0050]
Next, an insulating film 13 made of a silicon oxide film or the like is deposited on the entire surface of the semiconductor substrate 7 and the inner wall of the trench by using the CVD method. The insulating film 13 is formed thick enough to have a breakdown voltage greater than the overvoltage applied when the dielectric film 10 is destroyed. Although the case where the insulating film 13 is deposited by the CVD method is shown here, the insulating film 13 may be a thermal oxide film formed by a predetermined thermal oxidation process.
[0051]
(D) Next, the insulating film 13 formed on the semiconductor substrate and on the first polysilicon 11 is selectively etched by using an anisotropic etching method such as the RIE method. As shown in (d), an insulating film 13 is formed on the side wall of the trench middle portion 12b.
[0052]
Next, polysilicon to which n-type impurities are added is deposited on the entire surface of the semiconductor substrate 7 and inside the trenches 24 (12b, 12c) by CVD. The polysilicon is etched using the CDE method to remove the polysilicon deposited on the trench upper portion 12c and the semiconductor substrate 7 while leaving the second polysilicon 14 embedded in the trench middle portion 12b. As shown in FIG. 3D, the second polysilicon 14 is embedded inside the insulating film 13. The depth from the surface of the semiconductor substrate 7 to the upper end of the second polysilicon 14 is 100 to 400 nm.
[0053]
Next, polysilicon doped with n-type impurities at a higher concentration than the first and second polysilicon (11, 14) is deposited on the entire surface of the semiconductor substrate 7 and in the trench interior 12c. Then, a predetermined planarization process is performed to remove the polysilicon deposited on the semiconductor substrate 7 while leaving the third polysilicon 15 embedded in the trench upper portion 12c. As shown in FIG. 3D, the third polysilicon 15 is buried in the trench upper portion 12c.
[0054]
(E) Next, annealing is performed in a nitrogen atmosphere at 800 to 1000 ° C. to diffuse the n-type impurity added to the third polysilicon 15 into the p-well 9. As shown in FIG. 4A, an n-type dyeing diffusion layer 17 that is in contact with the side surface of the third polysilicon 15 and is exposed on the surface of the semiconductor substrate 7 is formed on the outer periphery of the third polysilicon 15. The
[0055]
Next, the upper portion of the third polysilicon 15 is selectively removed by using a wet etching method having an etching selection ratio larger than that of the semiconductor substrate 7 relative to the polysilicon, and the recess 26 shown in FIG. Form. Instead of the wet etching method described above, selective anisotropic etching of polysilicon may be performed using a mask having a window in a region where the recess 26 is to be formed.
[0056]
(F) Next, as shown in FIG. 4B, a resist 28 having a window is formed in a region where the STI 19 is to be formed, and RIE of the semiconductor substrate 7 is performed using this as a mask. A groove is formed in a region where the STI 19 is formed. After the etching is completed, the resist 28 is removed.
[0057]
(G) Next, a thick silicon oxide film (SiO 2) is formed on the entire surface of the semiconductor substrate 7 by CVD. ₂ Film) 29 is deposited. At this time, as shown in FIG. 4C, the recess 26 in the trench upper portion 12c and the trench in the region where the STI 19 are formed are formed in SiO 2. ₂ The membrane is embedded.
[0058]
(H) Next, by performing a planarization process such as CMP (Chemical Mechanical Polishing), the STI 19 and the trench cap 16 made of the oxide film 29 are simultaneously formed as shown in FIG. Form. Next, using the ion implantation method, n-type impurity ions are implanted into the entire surface of the semiconductor substrate 7 at a low speed, and a predetermined heat treatment is performed, thereby forming the SD diffusion layer 20 on the semiconductor substrate 7. The SD diffusion layer 20 is formed simultaneously with the source / drain regions of the MOSFET formed in the same semiconductor substrate 7.
[0059]
(I) Next, as shown in FIG. 5A, an interlayer insulating film 21 is deposited on the entire surface of the semiconductor substrate 7 by using the CVD method. A resist 30 having a window in a contact region where the metal wirings 22a and 22b are connected to the semiconductor substrate 7 is formed on the interlayer insulating film 21 by photolithography, and RIE of the interlayer insulating film 21 is performed using the resist 30 as a mask. . Thereafter, the resist 30 is removed.
[0060]
(N) Next, as shown in FIG. 5B, a resist 31 having a window having the same pattern as that of the metal wirings 22a and 22b is formed on the interlayer insulating film 21. Using this as a mask, RIE of the interlayer insulating film is performed to form a trench. A metal film 22 made of aluminum or the like is deposited on the entire surface of the semiconductor substrate 7 by sputtering. At this time, the metal film 22 is also embedded in the contact region and the trench for the metal wiring.
[0061]
Next, a planarization process such as CMP is performed to form metal wirings 22a and 22b. Finally, the trench capacitor 1 and the protection diode 3 shown in FIGS. 2A and 2B can be formed by forming the protective film 23 on the metal wirings 22a and 22b.
[0062]
As described above, the fuse circuit shown in FIG. 1 constitutes a Zener breakdown with respect to an overvoltage applied to the protective diode 3 immediately after the dielectric film is broken, but the information recorded in the fuse element 1 is stored. There is no Zener breakdown for the normal voltage applied to output. That is, the protective diode 3 serves as a filter against overvoltage. Therefore, there is no possibility that an overcurrent flows to the control circuit unit 2 arranged at the subsequent stage of the fuse element 51 and destroys the junction of the transistors 5 and 6. In addition, since it is not necessary to reduce the overvoltage in order to avoid the breakdown of the transistors 5 and 6, the dielectric film cannot be sufficiently destroyed, and writing of information into the fuse element 51 may be insufficient. It will disappear. Therefore, the resistance of the fuse element 1 after the breakdown can be sufficiently lowered by the overvoltage applied from the external power source 4, and the overcurrent is prevented from flowing to the control circuit unit 2 disposed at the subsequent stage of the fuse element 1. be able to.
[0063]
Further, as described with reference to FIGS. 2 to 5, a new manufacturing process is performed to form the fuse element 1 by forming the fuse element 1 substantially in the same structure as the trench capacitor in the memory cell. Therefore, the fuse element 1 can be formed simultaneously with the trench capacitor in the memory cell. Furthermore, by forming the protection diode 3 using the diffusion layers (17, 20) and the p-well 9 which are the constituent elements of the fuse element 1, no new element region is required to form the protection diode 3, The circuit area can be reduced and the degree of circuit integration can be improved. With respect to the memory, a plurality of fuse circuits are required because the replacement information of defective memory cells, trimming of device functions, and semiconductor memory device information are used as OTPROMs.
[0064]
Furthermore, the potential applied to the p-well 9 when the dielectric film 10 is broken is not a ground potential, but a negative potential of about −0.5 to −2.0 V is applied, so that the apparent protection diode 3 appears. Zener breakdown voltage can be lowered. Therefore, even if the junction breakdown voltage of the MOSFETs 5 and 6 in the control circuit unit 2 and the junction breakdown voltage of the protection diode 3 are equivalent, the protection diode 3 can be broken down (Zener breakdown) first. By intentionally lowering the Zener breakdown voltage of the protection diode 3, the degree of freedom in designing the MOSFETs 5 and 6 in the control circuit unit 2 is increased.
[0065]
(Other embodiments)
As described above, the present invention has been described by way of one embodiment. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples, and operational techniques will be apparent to those skilled in the art.
[0066]
In the embodiment, the “diffusion layer” of the claimed invention corresponds to both the dyeing diffusion layer 17 and the SD diffusion layer 20, but the present invention is not limited to this. Absent. The matter corresponding to the “diffusion layer” of the claimed invention may be configured by only one of the dyeing diffusion layer 17 and the SD diffusion layer 20. When constituted only by the diffusion layer 17, the Zener breakdown voltage of the PN junction 3 between the diffusion layer 17 and the p well 9 can be set independently from the junction voltage of the MOSFETs 5 and 6 of the memory cell, The degree of freedom in designing the MOSFET and the protection diode is improved. On the other hand, when only the SD diffusion layer 20 is used, the junction breakdown voltage of the MOSFETs 5 and 6 and the Zener breakdown breakdown voltage of the PN junction 3 may be equivalent, but as described above, a negative voltage is applied to the p well 9. Is applied, the apparent Zener breakdown withstand voltage of the PN junction 3 can be lowered.
[0067]
In the embodiment, the case where the capacitor having the trench structure is used as the fuse element 1 shown in FIG. 1 has been described. However, the present invention is not limited to this. Instead of the trench structure capacitor, a stack structure capacitor may be used.
[0068]
Thus, it should be understood that the present invention includes various embodiments and the like not described herein. Therefore, the present invention is limited only by the invention specifying matters according to the scope of claims reasonable from this disclosure.
[0069]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a semiconductor memory device that has no breakdown failure (conductivity failure) and that does not break a circuit connected to a fuse element, and a method for manufacturing the same.
[0070]
Specifically, by maintaining a high overvoltage at the time of dielectric film breakdown, the resistance of the fuse element after breakdown is sufficiently low, and an overcurrent that flows immediately after the dielectric film breakdown does not flow to the transistor connected to the fuse element. It is possible to provide a semiconductor memory device having a fuse circuit that can be manufactured and a method for manufacturing the same.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a fuse circuit included in a semiconductor memory device (DRAM) according to an embodiment of the present invention.
2A is a plan view schematically showing structures of a capacitor 1 and a protection diode 3 in the fuse circuit shown in FIG. 1, and FIG. 2B is a plan view of FIG. Sectional drawing along the AA 'cut surface of a) is shown.
3 (a) to 3 (d) are diagrams illustrating a method of manufacturing the trench capacitor 1 and the protection diode 3 according to the embodiment of the present invention shown in FIGS. 2 (a) and 2 (b). It is sectional drawing which shows the main processes (the 1).
4 (a) to 4 (d) are diagrams showing a method of manufacturing the trench capacitor 1 and the protection diode 3 according to the embodiment of the present invention shown in FIGS. 2 (a) and 2 (b). It is sectional drawing which shows the main processes (the 2).
5 (a) to 5 (c) are diagrams illustrating a method of manufacturing the trench capacitor 1 and the protection diode 3 according to the embodiment of the present invention illustrated in FIGS. 2 (a) and 2 (b). It is sectional drawing which shows the main processes (the 3).
6A is a plan view schematically showing a configuration of a conventional fuse element using a trench capacitor, and FIG. 6B is a cross-sectional view taken along line BB ′ of FIG. 6A. A cross-sectional view along the plane is shown.
7 (a) to 7 (c) are cross-sectional views showing main steps in the conventional method of manufacturing the fuse element shown in FIGS. 6 (a) and 6 (b). 1).
8 (a) and 8 (b) are cross-sectional views showing main steps in the conventional method of manufacturing the fuse element shown in FIGS. 6 (a) and 6 (b). 2).
9 is a circuit diagram showing a general fuse circuit when the trench capacitor shown in FIGS. 6 (a) and 6 (b) is used as a fuse element. FIG.
[Explanation of symbols]
1 Fuse element (capacitor)
2 Control circuit
3 Protection circuit (protection diode)
4 External power supply
5, 6 Transistor (MOSFET)
7 Semiconductor substrate
8 First conductivity type semiconductor layer (n-well)
9 Second conductivity type semiconductor layer (p-well)
10 Dielectric film
11 First conductor (first polysilicon)
12a Bottom of trench
12b Middle part of trench
12c Trench top
13 Insulating film
14 Second conductor (second polysilicon)
15 Third conductor (third polysilicon)
16 Trench cap
17 Dyeing diffusion layer
18 drawer area
19 STI
20 SD diffusion layer
21 Interlayer insulation film
22a, 22b Metal wiring
23 Protective film
24 trench
25, 28, 30, 31 resist
26 Recess
29 Oxide film

Claims (3)

It is composed of a pair of electrodes and a dielectric film sandwiched between the electrodes, and is composed of a trench-structure capacitor in which information is recorded by applying an overvoltage to one of the electrodes to destroy the dielectric film. and the fuse element,
A control circuit unit connected to the other electrode of the fuse element;
A Zener breakdown resistor connected to the other electrode of the fuse element in the previous stage of the control circuit unit and disposed in the opposite direction to the overcurrent flow through the fuse element immediately after breaking the dielectric film. A semiconductor memory device having a fuse circuit comprising: a protection circuit unit including a protection diode having a threshold voltage smaller than the overvoltage ;
A first conductivity type semiconductor layer disposed under the semiconductor substrate;
A second conductivity type semiconductor layer disposed on the semiconductor substrate;
A trench formed in the semiconductor substrate and reaching the first conductivity type semiconductor layer even if the bottom is shallow;
A first conductivity type diffusion layer disposed on the second conductivity type semiconductor layer adjacent to the trench;
A dielectric film disposed on a portion of the inner wall of the trench where the first conductive semiconductor layer is exposed;
A first conductor embedded inside the dielectric film;
An insulating film disposed on a portion of the inner wall of the trench where the second conductive semiconductor layer is exposed;
A second conductor embedded inside the insulating film;
A third conductor embedded in a portion where the diffusion layer of the inner wall of the trench is exposed;
Have
The fuse element includes at least the first conductive semiconductor layer, the dielectric film, and the first conductor,
The semiconductor memory device, wherein the protection diode includes at least the second conductive semiconductor layer and the diffusion layer . It is composed of a pair of electrodes and a dielectric film sandwiched between the electrodes,
Information is recorded by applying an overvoltage to one electrode to destroy the dielectric film.
A fuse element composed of a capacitor having a trench structure;
A control circuit unit connected to the other electrode of the fuse element;
A Zener breakdown resistor connected to the other electrode of the fuse element in the previous stage of the control circuit unit and disposed in the opposite direction to the overcurrent flow through the fuse element immediately after breaking the dielectric film. A protection circuit unit comprising a protection diode having a threshold voltage smaller than the overvoltage;
A method of manufacturing a semiconductor memory device having a fuse circuit comprising:
A first step of forming a first conductive type semiconductor layer and a second conductive type semiconductor layer on a lower part and an upper part of a semiconductor substrate,
A second step of forming a trench reaching the first conductivity type semiconductor layer even if the bottom is shallow, inside the semiconductor substrate;
A third step of forming a dielectric film on the exposed portion of the first conductivity type semiconductor layer of the inner wall of the trench;
A fourth step of embedding a first conductor inside the dielectric film;
A fifth step of forming an insulating film at a lower portion of the portion of the trench inner wall where the second conductive semiconductor layer is exposed;
A sixth step of embedding a second conductor inside the insulating film;
A seventh step of burying a third conductor in an upper portion of the portion where the second conductive type semiconductor layer is exposed on the inner wall of the trench;
Said third contact with the side surfaces of the conductor, and at least have a eighth step of forming a diffusion layer of the first conductivity type exposed at the surface of the semiconductor substrate,
At least the first conductive semiconductor layer, the dielectric film and the first conductor constitute the fuse element;
A method of manufacturing a semiconductor memory device, comprising: forming the protective diode from at least the second conductive semiconductor layer and the diffusion layer . The third conductor embedded in the seventh step is doped with a first conductivity type impurity having a higher concentration than the first and second conductors,
The eighth step is a step of performing a predetermined heat treatment to diffuse a first conductivity type impurity added to the third conductor into the second conductivity type semiconductor layer. 3. A method for manufacturing a semiconductor memory device according to 2 .

Images