JP4051818B2 - Radio equipment using CDMA transmission system - Google Patents

Description

受信側で、総和信号が正しく受信できるものとすれば、受信した総和信号に拡散符号列を乗じて、対応するセグメントの１次変調信号の値が、次に示すように求まる。
【００１３】
すなわち、第０のＷａｌｓｈ符号列に対応する値は、総和信号（０、１、２）と第０のＷａｌｓｈ符号列の内積で次のように与えられる。

となる。従って、総和信号（０、１、２）・第０のＷａｌｓｈ符号列との内積を符号長３２で正規化すれば、値ａが正しく受信され、値ｂと値ｃは完全に抑圧され混信することなく正しく受信できることが明らかになる。
【００１４】
同様に、第１のＷａｌｓｈ符号列に対応する値は、総和信号（０、１、２）と第１のＷａｌｓｈ符号列の内積で与えられ、その値は３２ｂとなり、第２のＷａｌｓｈ符号列に対応する値は、総和信号（０、１、２）と第２のＷａｌｓｈ符号列の内積で与えられ、その値は３２ｃとなる。従って、総和信号（０、１、２）と第１のＷａｌｓｈ符号列の内積を符号長３２で正規化すれば、値ｂが正しく受信され、総和信号（０、１、２）と第２のＷａｌｓｈ符号列の内積を符号長３２で正規化すれば、値ｃが正しく受信される。
【００１５】
このように、拡散符号列が互いに直交する限り、拡散符号列の数だけ多元接続でき、かつ拡散符号列が一致する場合だけ通信することができる。
なお、図１５におけるシンボル区間１のセグメント０における１次変調波は、０〜１の正なる値であり、セグメント１における１次変調波は、０〜−１の負なる値であるので、同図における対応するシンボル区間１のセグメント０のチップ値の符号は負、正の交番に、セグメント１のチップ値の符号は正、負の交番に変化する。
【００１６】
拡散信号のチップレートは、符号長が３２の場合には、３２ｋｓｐｓ・４セグメント・３２チップ／セグメント＝４．０９６Ｍチップ／秒となる（以降、チップ／秒をｃｐｓと記述する）。
全ての拡散信号は、各チップ区間において同期して変化するので、チップ値の総和をチップ区間における信号値とする総和信号は、チップ区間内では一定値を示す波形となる。従って、３２チャネルを同時通信する２Ｍｂｐｓの最大情報速度の場合でも、１チャネルの６４ｋｂｐｓの最小情報速度で伝送している場合でも、伝送情報速度には関係なく、チップレートは常に一定の４．０９６Ｍｃｐｓとなる。
【００１７】
このようにして、情報信号ならびに必要な制御信号に対応する複数個の拡散信号を、図１０に示すように、拡散符号発生回路（ＣＧ）１３０〜１３０ｎから出力される互いに直交する拡散符号列を用いて、拡散回路（ＳＳ）１２０〜１２ｎで生成し、次いで複数個の拡散符号の総和を総和回路（ＳＵＭ）１４０で求め、求めた総和信号を必要に応じて送信回路（ＴＸ）において周波数変換と電力増幅して、ＣＤＭＡ信号として送信する。
【００１８】
なお、ＣＤＭＡ信号の矩形波を正確に伝送するためには、チップレートの数倍の周波数帯が必要になるが、図１０に示すように、帯域制限回路（ＢＰＦ）１４１の機能としてバンドパスフィルタ操作が実施され、チップレート程度に周波数帯域幅が制限される。
ここで、上記のように送信回路（ＴＸ）から送信された電波が、理想的な電波伝播路を経て通信されることは、一般的に、ほとんどない。自動車電話や携帯電話等の移動通信では、送信機自体が移動するのでドップラーシフトが生じ、キャリア周波数が偏移する。あるいは、複数の電波伝播路を経て受信されることにより、受信波の位相や振幅が時間とともに変化するフェーディング現象が生じたりする。
【００１９】
そこで、受信側において、ＣＤＭＡ受信機は、受信、同期検波、受信制御、復調、逆拡散、位相補正、判断等の主要回路で構成される。
図１６において、受信制御回路（ＣＮＴ）２０４は、受信信号から受信機の制御に必要な各種制御信号を検出し、ならびに受信に必要な複数個の逆拡散符号列を出力する。同期検出回路（ＳＹＮＣ）２０３は、受信信号から、キャリア再生波、チップ同期信号、セグメント同期信号、ならびにシンボル同期信号等を出力する。
【００２０】
復調回路（ｄｅＭＯＤ）２０１は、図１７に示す構成を有している。同図において、受信回路（ＲＸ）２００と接続される入力端子２０１０に印加される受信波は、乗算器２０１１、２０１２に入力される。ここで、復調回路（ｄｅＭＯＤ）２０１は、同期検波方式を一般に用いており、キャリア再生波２０２と受信波との積を乗算器２０１１で求め、続いてキャリア周期毎にアキュムレータ２０１４で累積したキャリア周期毎の内積を求め、求めた内積をラッチレジスタ（ＲＥＧ）２０１６で取り込み、キャリア周期期間だけ保持し、ラッチレジスタ（ＲＥＧ）２０１６で保持した値を１次変調波の復調信号の同相成分ｉ（ｔ）としてキャリア周期毎に出力する。同時に、復調回路（ｄｅＭＯＤ）２０１は、キャリア再生波２０２を移相器２０１３で９０度移相した直交キャリア信号と受信波との積を乗算器２０１２で求め、続いてキャリア周期毎にアキュムレータ２０１５で累積してキャリア周期毎の内積を求め、求めた内積をラッチレジスタ（ＲＥＧ）２０１７で取り込み、キャリア周期期間だけ保持し、ラッチレジスタ（ＲＥＧ）２０１７で保持した値を１次変調波の復調信号の直交成分ｑ（ｔ）としてキャリア周期毎に出力する。アキュムレータ２０１４、２０１５に入力される信号Ｒは、制御端子２０１８からキャリア周期毎に入力される累積リセット信号であり、この累積リセット信号Ｒの前縁で、アキュムレータ２０１６、２０１７は入力値を保持する。
【００２１】
復調回路（ｄｅＭＯＤ）２０１からの復調信号の同相成分ｉ（ｔ）、直交成分ｑ（ｔ）は、図１６に示すように、ｎ＋１個の逆拡散回路（ｄｅＳＳ）２１０〜２１ｎに入力される。図１８に、この拡散回路（ｄｅＳＳ）２１０〜２１ｎの１つの構成例を示す。
入力端子２１００、２１０１に復調信号の同相成分ｉ（ｔ）、復調信号の直交成分ｑ（ｔ）がそれぞれ入力される。乗算器２１０２、２１０３は、チップ同期信号に従い、それぞれ復調信号の同相成分ｉ（ｔ）、復調信号の直交成分ｑ（ｔ）と、端子２２ｉから入力される第ｉ番の逆拡散符号列との積を求め、セグメント同期信号に従い積の累積をセグメント毎に求める。
【００２２】
ここで、ｉはｉ番目のチャネルであることを示す、また、第ｉ番の逆拡散符号列とは、送信側で用いた第ｉ番の拡散符号列に対応する逆拡散符号列をいい、Ｗａｌｓｈ関数を用いる場合には逆拡散符号列と拡散符号列は互いに等しくなっている。なお、図１６に示すように、逆拡散回路２０１〜２０ｎのそれぞれの端子２２０〜２２ｎには、対応する逆拡散符号列が入力される。
【００２３】
続いて、図１８において、乗算器２１０２、２１０３の出力は、アキュムレータ２０１４、２０１５で累積される。アキュムレータ２１０４、２１０５には、端子２１１０から累積リセット信号Ｒがセグメント毎に入力される。アキュムレータ２１０４、２１０５の出力は、それぞれ符号長で正規化され、ラッチレジスタ（ＲＥＧ）２１０６、２１０７でセグメント区間保持される逆拡散信号の同相成分Ｉ_i ' （ｔ）ならびに逆拡散信号の直交成分Ｑ_i ' （ｔ）として出力端子２１０８、２１０９から出力される。
【００２４】
なお、拡散符号列は互いに直交しているので、逆拡散符号列が送信の拡散符号列に一致する場合には、逆拡散回路２１０〜２１ｎの出力は、有限な値を出力し、正しく受信できる。逆拡散符号列が送信の拡散符号列に一致しない場合には、逆拡散回路２１０〜２１ｎの出力は、常にゼロとなり、受信信号を結果的に出力しない。
【００２５】
同時多元接続のｎ個の情報チャネルに関する逆拡散信号の同相成分Ｉ_i ' （ｔ）と逆拡散信号の直交成分Ｑ_i ' （ｔ）は、逆拡散回路２１１〜２１ｎからそれぞれ出力される。また、これらｎチャネルに共通なパイロット信号に関する逆拡散信号の同相成分Ｉ₀ ' （ｔ）ならびに逆拡散信号の直交成分Ｑ₀ ' （ｔ）は、逆拡散回路２１０から出力される。
【００２６】
これらの逆拡散信号は、それぞれ伝播中に、位相差や振幅ひずみ、遅延などの撹乱を受ける。既知の値、例えば、”０”の位相情報の１次変調を拡散したパイロット拡散信号を送信し、受信側で検知する位相差と既知の値との誤差を測定することで伝播中に生じた撹乱の位相誤差を概略知ることができる。従って、図１６に示すように、ｎチャネルの情報に対して、既知なる値を伝送するパイロット信号を１チャネル付加して、伝播中の撹乱を概略補正するパイロット方式が用いられることが多い。
【００２７】
このため、ｎ情報チャネルに対して１パイロットチャネルを付加する場合について説明するが、１情報チャネルに１パイロットチャネルを付加する場合も、あるいは各拡散信号における１次変調波の同相成分を情報に、直交成分をパイロット信号に割り当てる場合も同様である。
図１６において、逆拡散回路（ｄｅＳＳ）２１１〜２１ｎの各出力ならびに逆拡散回路（ｄｅＳＳ）の出力は、位相補正回路（ＣＭＰ）２３１〜２３ｎに導かれる。図１９に、この位相補正回路（ＣＭＰ）２３１〜２３ｎの１つの構成を示す。
【００２８】
入力端子２３００と２３０１に、逆拡散回路（ｄｅＳＳ）２１ｉから情報チャネルｉの同相成分Ｉ_i ' （ｔ）と逆拡散信号の直交成分Ｑ_i ' （ｔ）が、それぞれ入力される。また、入力端子２３０２と２３０３に、逆拡散回路２１０からパイロットチャネルの同相成分Ｉ₀ ' （ｔ）と直交成分Ｑ₀ ' （ｔ）が、それぞれ入力される。続いて、情報チャネルｉの同相成分Ｉ_i ' （ｔ）は乗算器２３１０と２３１１に、情報チャネルｉの直交成分Ｑ_i ' （ｔ）は乗算器２３１２と２３１３に入力され、パイロットチャネルの同相成分Ｉ₀ ' （ｔ）は乗算器２３１０と２３１２に、パイロットチャネルの直交成分Ｑ₀ ' （ｔ）は乗算器２３１３と２３１１に入力される。加算器２３２０は、乗算器２３１０と２３１３の出力の和を位相補正信号の同相成分Ｉ_i （ｔ）として端子２３４０に出力する。さらに、加算器２３２１は、乗算器２３１２の出力と乗算器２３１１の出力の差を位相補正信号の直交成分Ｑ_i （ｔ）として端子２３４１に出力する。
【００２９】
位相補正回路（ＣＭＰ）２３１〜２３ｎの出力は、図１６に示すように、判断回路（ＤＥＣ）２４１〜２４ｎに導かれる。判断回路（ＤＥＣ）２４１〜２４ｎは、位相補正信号の同相成分Ｉ_i （ｔ）、直交成分Ｑ_i （ｔ）から位相角を求めるマッピングを行い、このマッピングで得られた位相角により象限判定を行って情報シンボルとしての受信シンボルＳ_i （ｔ）を端子２５１〜２５ｎに出力する。
【００３０】
【発明が解決しようとする課題】
従来のＣＤＭＡ伝送方式において、１次変調波のＰＳＫ波に、Ｗａｌｓｈ符号列などの拡散符号列を乗じ、スペクトラムを拡散した拡散信号を生成する。チップ１〜チップ３における拡散符号列の時間応答波形を示す図２において、破線は従来の拡散符号列波形の１例を示している。チップ区間１ならびにチップ区間２では符号値１を、チップ区間３では符号値−１を、チップ区間４では符号値１の場合を示しているが、他の場合も同様である。チップ区間１とチップ区間２のように隣接するチップ区間で拡散符号値が互いに等しい場合には、隣接するチップ区間での拡散信号の波形に不連続性は生じない。
【００３１】
一方、チップ区間２とチップ区間３の間、あるいはチップ区間３とチップ区間４の間などのように、拡散符号値が互いに異なる場合には、チップ区間端で激しい波形の変化が拡散信号に現れる。
全てのチップ区間でチップ区間端まで符号値を保持した場合には、図２の破線で示すような激しい波形の変動がチップ区間端で生じ、拡散信号の周波数帯域幅が極端に増大する。その結果、通信品質が劣化するという問題がある。
【００３２】
そこで、本発明は、チップ区間端における拡散符号列波形の激しい変動を排除して、周波数帯域幅の増大を防止し、通信品質を向上させることを目的とする。
【００３３】
【課題を解決するための手段】
上記目的を達成するため、本発明では、例えば、図２の実線の波形で示すように、拡散符号値が隣接チップ区間で異なる場合に遷移区間で連続的に変化させ、遷移区間での拡散符号値の急激な変動を排除するようにしている。
ここで、遷移区間とは、各チップ区間端近傍に隣接チップ区間に跨って設置した区間をいう。例えば、図２の場合、チップ区間１とチップ区間２の間が遷移区間２、チップ区間２とチップ区間３との間が遷移区間３、チップ区間３とチップ区間４の間が遷移区間４となる。なお、全ての遷移区間は同じ時間長Ｒとしている。
【００３４】
このように、拡散符号値が隣接チップ区間で異なる場合に遷移区間での拡散符号値の急激な変動を排除することにより、チップ区間端における拡散符号列波形の激しい変動を排除して、周波数帯域幅の増大を防止することができる。
しかしながら、チップ区間端において拡散符号列波形を変化させ歪ませると、伝播すべき情報位相が変化してしまい、従来のＣＤＭＡ方式の受信機の構成のままでは、通信品質が劣化してしまうという問題が生じる。
【００３５】
そこで、本発明では、復調の際に、全てのチップ区間でチップ区間端まで受信信号を使用するのではなく、チップ中心付近の歪みの少ない区間の受信信号を有効領域とし、復調に使用する復調区間とすることにより、遷移区間周辺の不安定な値を除去し、安定な復調動作を行うことができるようにしている。すなわち、本発明の特徴は、特許請求の範囲に記載した通りのものであって、請求項１に記載の発明では、情報に対応してキャリア信号を位相変調して、１次変調波を生成する手段と、拡散符号の値が隣接チップ区間で異なる場合にチップ区間の端部領域の遷移区間で拡散符号の値を連続的に変化させ、拡散符号の値の急激な変動が排除された拡散符号列を発生する手段と、この手段によって発生された拡散符号列を前記１次変調波に乗じてスペクトラム拡散した拡散信号を生成し、その生成された拡散信号を送信する手段と、受信信号の中から、少なくとも前記拡散符号の値の急激な変動が排除された遷移区間を除いた復調区間の受信信号を選択する手段と、この手段によって選択された受信信号に対し逆拡散符号列を用いて逆拡散を行い情報を復元する手段とを備え、前記受信信号を選択する手段は、前記逆拡散符号列に基づき逆拡散符号の値が隣接するチップ区間で異なる場合にのみ、前記受信信号の中から前記復調区間の受信信号を選択するものであるＣＤＭＡ伝送方式を用いた無線機を特徴としている。
【００３６】
このように、受信信号の中から、少なくとも拡散符号の値の急激な変動が排除された遷移区間を除いた復調区間の受信信号を選択し、この選択された受信信号を用いて逆拡散を行っているから、送信側においてチップ区間端における拡散符号列を急激な変動を排除するように変化させても、安定した復調動作を行うことができる。
【００３７】
なお、受信信号を選択する手段としては、請求項２に記載の発明のように、受信信号を復調する復調手段と、逆拡散を行う手段との間にあって、復調手段によって復調された受信信号の中から復調区間の受信信号を選択するようにすることができる。
【００３９】
【発明の実施の形態】
以下、本発明を図に示す実施形態について説明する。
この実施形態における送信機は、図１に示すように、拡散符号発生回路（ＣＧ）１３０〜１３ｎと拡散回路（ＳＳ）１２０〜１２ｎの間に拡散符号列波形連続化回路（ＣＯＤＥ−ＣＳ）１５０〜１５ｎが挿入された構成となっている。なお、この送信機において、拡散符号列波形連続化回路（ＣＯＤＥ−ＣＳ）１５０〜１５ｎ以外の構成は、図１０に示すものと同様である。この拡散符号列波形連続化回路（ＣＯＤＥ−ＣＳ）１５０〜１５ｎを設けることにより、図２に示すように、拡散符号値が隣接チップ区間で異なる場合にのみ、遷移区間で拡散符号値を緩やかに変化させることができる。
【００４０】
図３に、拡散符号列波形連続化回路（ＣＯＤＥ−ＣＳ）１５０〜１５ｎの１つの構成を示す。図において、入力端子３００には、対応する拡散符号発生回路（ＣＧ）１３ｉからの拡散符号列が入力され、そのまま加算器３０１に入力される。出力端子３０６の出力は、クロック端子（ＣＬＫ）３０７に印加されるクロック信号の前縁で、ラッチレジスタ（ＲＥＧ）３０５に取り込まれ保持される。加算器３０１は、入力端子３００に入力される拡散符号値とラッチレジスタ（ＲＥＧ）３０５に保持されている値との差を出力する。この加算器３０１の出力値は、スムーサ（ＳＭＯ）３０３から出力される値と乗算器３０２において掛け算される。この乗算器３０２の出力は、加算器３０４において、ラッチレジスタ３０５の出力値と加算され、その加算値が出力端子３０６から出力される。
【００４１】
ここで、スムーサ（ＳＭＯ）３０３は、図４に示すように、出力（ｔ）が各遷移区間において０から１まで連続的に変化する値、例えば数式１で表わされる値を出力する。スムーサ出力（ｔ）は、チップ区間τに関して周期的に値を出力するので、ＲＯＭに１チップ区間分の出力値を格納しておき、その出力値を順次読み出すことにより、図４に示す値を周期的に出力することができる。
【００４２】
【数１】

【００４３】
次に、上記した拡散符号列波形連続化回路（ＣＯＤＥ−ＣＳ）の動作を説明する。その動作は、チップ区間に対して周期的であるので、時刻ｔ＝Ｒ／２から時刻ｔ＝２τ＋Ｒ／２までについて説明するが、他のチップ区間も同様である。
遷移区間の後縁ｔ＝Ｒ／２で、クロック端子（ＣＬＫ）３０７にクロックが印加され、かつ次のチップ区間の拡散符号値が確定するものとする。図２に示すように、時刻ｔ＝Ｒ／２において、出力端子３０６の出力が１になっているので、ラッチレジスタ（ＲＥＧ）３０５には１が取り込まれ保持される。かつ、入力端子３００にはチップ区間２の拡散符号値１が印加される。ラッチレジスタ（ＲＥＧ）３０５の出力と入力端子３００の入力が等しいので、加算器３０１の出力は０となる。従って、スムーサ（ＳＭＯ）３０３の出力値に係わりなく乗算器３０２の出力は、遷移区間２の全域において０となり、加算器３０４の出力は１のまま変化せず、出力端子３０５には値１が継続して出力される。さらに、遷移区間２の後縁ｔ＝τ＋Ｒ／２において、ラッチレジスタ（ＲＥＧ）３０５は、出力値１を取り込んで保持し、入力端子３００には次のチップ区間３の拡散符号値−１が印加される。
【００４４】
このため、加算器３０１の出力は−２となるが、スムーサ（ＳＭＯ）３０３は遷移区間３の前縁まで出力は０であるので、乗算器３０２は値０を継続して出力する。しかし、出力端子３０６には、乗算器３０４とラッチレジスタ（ＲＥＧ）３０５の和が出力されるので、ラッチレジスタ３０５に保持されている値１が、遷移区間３の前縁まで継続して出力される。遷移区間３において、スムーサ３０３の出力は前縁で値０から立ち上がり、終縁で値１まで連続して増大する。従って、乗算器３０２の出力は０〜−２に変化する。これにより、乗算器３０４の出力とラッチレジスタ３０５の保持値との和は、１〜−１に変化しながら出力端子３０６に現れる。このため、遷移区間３の拡散符号値は、図２に示すように滑らかに変化する波形に整形される。さらに、遷移区間３の終縁で、出力端子の値−１がラッチレジスタ３０５に取り込まれ、次の動作に移行し、上記と同様な動作が行われる。
【００４５】
このように拡散符号列波形連続化回路（ＣＯＤＥ−ＣＳ）１５０〜１５ｎを設けることにより、拡散符号値が隣接チップ区間で異なる場合に遷移区間で拡散符号値を緩やかに変化させ、チップ区間端における拡散符号列波形の激しい変動を排除して、周波数帯域幅の増大を防止することができる。しかしながら、チップ区間端における拡散符号列波形を歪ませると、伝播すべき情報位相が変化してしまい、従来のＣＤＭＡ方式の受信機の構成のままでは、通信品質が劣化してしまう。
【００４６】
また、所定の帯域幅で通信を行うために、送信波の周波数帯域を帯域制限回路（ＢＰＦ）１４１により帯域制限しているが、その場合、上記のように位相を連続化させると、遷移区間における歪んだ波形が、前後の区間に干渉として影響を与え、通信品質を劣化させてしまう。すなわち、帯域制限回路（ＢＰＦ）１４１として、図６に示すように、ｋ個の遅延器１４０１〜１４０ｋと、これらの遅延器１４０１〜１４０ｋによって遅延された信号にタップ係数Ｗ₁ 〜Ｗ_k を乗じる乗算器１４１１〜１４１ｋと、乗算器１４１１〜１４１ｋからの信号を総和する総和回路（ＳＵＭ）１４２０からなるトランスバーサルフィルタを用いた場合、遷移区間において歪んだ波形に対応する信号がこのフィルタに入力されると、フィルタの出力は、遷移区間の前後の区間においてその影響を受けることになり、出力される所望の周波数帯域に対して異なる周波数成分が混入してしまい、このことが通信品質を劣化させる。
【００４７】
そこで、この実施形態における受信機においては、図６に示すように、各チップ区間における遷移区間を除いた区間内で復調区間を設定し、この復調区間における受信信号値を用いて逆拡散を行うようにしている。
このため、受信機においては、図７に示すように、復調回路（ｄｅＭＯＤ）２０１と逆拡散回路（ｄｅＳＳ）２１０〜２１ｎの間に、選択回路（スイッチ回路）２５１、２５２を設け、タイミング制御回路２５３からタイミング信号が出力されているときにのみ、復調回路２０１からの復調信号の同相成分ｉ（ｔ）、復調信号の直交成分ｑ（ｔ）を、逆拡散回路（ｄｅＳＳ）２１０〜２１ｎに出力するようにしている。なお、この受信機において、選択回路２５１、２５２、タイミング制御回路２５３を設けた点以外は、図１６に示すものと同様である。
【００４８】
ここで、タイミング制御回路２５３は、チップ毎に出力される信号、例えばチップ同期信号に基づき、各チップ区間内の復調区間において上記したタイミング信号を出力する。この復調区間は、チップ中心付近の歪みの少ない区間に設定され、その開始タイミングはＲ／２以後、終了タイミングはτ−Ｒ／２以前となっている。この場合、例えば、この受信機のシステムクロックによるサンプリングにて復調期間を設定するときには、図８に示すように、チップ区間のサンプル数がｎで復調区間のサンプル数がｍのとき、サンプル数がｍ／２になるとタイミング信号を出力し、ｎ−ｍ／２−１になるとタイミング信号の出力を停止するようにすれば、上記した復調区間においてのみタイミング信号を出力させることができる。なお、サンプル数がｍ／２になるまで、およびサンプル数がｎ−ｍ／２−１を超えてｎ−１になるまでは、受信信号値を用いない破棄区間となっている。
【００４９】
また、復調回路２０１の出力をＡ／Ｄ変換器にてＡ／Ｄ変換し、その変換値に基づいて逆拡散を行うように構成されている場合には、Ａ／Ｄ変換のタイミングで上記したサンプリングを行うようにしてもよい。
さらに、逆拡散符号値が隣接チップ区間と同じ場合は、不連続点が存在しないため、チップ区間の全てにおいて上記したタイミング信号を出力させるようにしてもよい。この場合、図９に示すように、上記した選択回路２５１、２５２、タイミング制御回路２５３と同構成の選択回路２１１２、２１１３、タイミング制御回路２１１１を逆拡散回路（ｄｅＳＳ）２１０〜２１ｎのそれぞれに設け、その逆拡散回路（ｄｅＳＳ）における逆拡散符号列を基に、タイミング制御回路２１１１が、逆拡散符号値が隣接チップ区間と同じあるか否かを判定して、逆拡散符号値が隣接チップ区間と異なる場合のみ上記したタイミング信号を出力するようにすればよい。このようにすることにより、逆拡散符号値が隣接チップ区間と同じ場合に、遷移区間における復調信号の同相成分ｉ（ｔ）、直交成分ｑ（ｔ）も逆拡散処理に用いることができるので、復調の精度を向上させることができる。
【００５０】
従って、この実施形態によれば、送信機側にて、拡散符号値が隣接チップ区間で異なる場合に遷移区間で拡散符号値を緩やかに変化させ、チップ区間端における拡散符号列波形の激しい変動を排除して、周波数帯域幅の増大を防止するとともに、受信機側にて、各チップ区間内の復調期間における受信信号値を用いて逆拡散を行うようにしているから、遷移区間での波形の歪みに影響されずに、精度よく復調を行うことができ、通信品質を向上させることができる。
【００５１】
また、上記した実施形態で示した各回路は、それぞれの機能を実現する手段として把握されるものである。
なお、上記した通信は、移動局と基地局との間で行われるものであるため、移動局、基地局とも、上記した送信機および受信機を備えている。従って、移動局を携帯電話のような無線機とした場合には、その無線機に上記した送信機および受信機が備えられる。
【図面の簡単な説明】
【図１】本発明の一実施形態に係るＣＤＭＡ送信機の構成を示す図である。
【図２】チップ区間１〜４における拡散符号列波形を示す図である。
【図３】拡散符号列波形連続化回路（ＣＯＤＥ−ＣＳ）の構成を示す図である。
【図４】スムーサ（ＳＭＯ）の出力特性を示す図である。
【図５】帯域制限回路（ＢＰＦ）の構成を示す図である。
【図６】各チップ区間における遷移区間と復調区間を説明するための図である。
【図７】本発明の一実施形態に係るＣＤＭＡ受信機において、復調回路（ｄｅＭＯＤ）と逆拡散回路の間に、選択回路とタイミング制御回路を設けた構成を示す図である。
【図８】サンプル数に基づいて復調期間を設定する場合の説明図である。
【図９】逆拡散回路（ｄｅＳＳ）に、選択回路とタイミング制御回路を設けた構成を示す図である。
【図１０】従来のＣＤＭＡ送信機の構成を示す図である。
【図１１】図１０に示すＣＤＭＡ送信機の１次変調波の、シンボル０ならびにシンボル１区間における波形を示す図である。
【図１２】ＱＰＳＫのビット配置（ビットコンステレーション）例を示す図である。
【図１３】オフセットＱＰＳＫのビット配置（ビットコンステレーション）例を示す図である。
【図１４】１次変調波のシンボル区間におけるセグメント構成例を示す図である。
【図１５】セグメント区間におけるチップ構成例を示す図である。
【図１６】従来のＣＤＭＡ受信機の構成例を示す図である。
【図１７】図１６に示すＣＤＭＡ受信機中の復調回路（ｄｅＭＯＤ）の構成例を示す図である。
【図１８】図１６に示すＣＤＭＡ受信機中の逆拡散回路（ｄｅＳＳ）の構成例を示す図である。
【図１９】図１６に示すＣＤＭＡ受信機中の位相補正回路（ＣＭＰ）の構成例を示す図である。
【符号の説明】
１００〜１０ｎ…情報入力端子、
１１０〜１１ｎ…位相変調回路（ＭＯＤ）、
１２０〜１２ｎ…拡散回路（ＳＳ）、
１３０〜１３ｎ…拡散符号発生回路（ＣＧ）、
１４０…総和回路（ＳＵＭ）、
１４１…帯域制限回路（ＢＰＦ）、
１４２…送信回路（ＴＸ）、
１５１〜１５ｎ…拡散符号列波形連続化回路（ＣＯＤＥ−ＣＳ）、
２０１…復調回路（ｄｅＭＯＤ）、
２０２…キャリア再生波、
２０３…同期検出回路（ＳＹＮＣ）、
２０４…受信制御回路（ＣＮＴ）、
２１０〜２１ｎ…逆拡散回路（ｄｅＳＳ）、
２３１〜２３ｎ…位相補正回路（ＣＭＰ）、
２４１〜２４ｎ…判断回路（ＤＥＣ）、
２５１〜２５ｎ…出力端子、
２５３、２１１１…タイミング制御回路、
２５１、２５２、２１１２、２１１３…選択回路。[0001]
BACKGROUND OF THE INVENTION
CDMA (Code Division Multiple Access) transmission system The It relates to the radio used.
[0002]
[Prior art]
In recent years, those using a CDMA transmission method have been put into practical use in the field of mobile communications such as automobile phones and mobile phones.
FIG. 10 shows a schematic configuration of a general CDMA transmitter. In the figure, known values used for pilot signals from an input terminal 100 and information values from n information input terminals 101 to 10n are input to corresponding phase modulation circuits (MOD) 110 and 111 to 11n, respectively. The number n of input information means the number of communications for simultaneous multiple access.
[0003]
Each phase modulation circuit phase-modulates the carrier signal in accordance with the input information, and generates n + 1 primary modulation waves corresponding to the signals from the input terminals 100 to 10n.
The spreading circuits (SS) 120 to 12n respectively calculate the product of the corresponding primary modulation wave and the spreading code sequence applied from the spreading code generation circuits (CG) 130 to 13n, and the time period of the spreading code sequence (chip). (Period), and the obtained product is output as a spreading code. Note that the spread code sequences generated by the spread code generation circuits (CG) 130 to 13n are orthogonal to each other. Spreading code generation circuits (CG) 130 to 13n repeatedly generate spreading code sequences corresponding to each row of the Walsh function having a code length N of n + 1 or more within the number of segments within one symbol period.
[0004]
The n + 1 spread signals and various control signals are then summed in a summation circuit (SUM) 140. The output of the summing circuit (SUM) 140 is band-limited by a band-limiting circuit (BPF) 141, and is frequency-converted and amplified by a transmission as necessary in a transmission circuit (TX) 142 before being transmitted.
Here, the operation of the phase modulation circuits (MOD) 110 to 11n in FIG. 10 will be described in detail below. Each of the phase modulation circuits (MOD) 110 to 11n divides the carrier signal at a fixed time T as in the primary modulation wave and symbol structure shown in FIG. 11, and the phase of each period is represented by the bits of QPSK shown in FIG. According to the arrangement or the bit arrangement of the offset QPSK shown in FIG. 13, the phase of the carrier signal is modulated so as to correspond to the symbol values 00, 01, 10 and 11 transmitted in one period on a one-to-one basis, Generate.
[0005]
Here, the primary modulation wave is a generic term for phase-modulated signals such as QPSK and offset QPSK. Further, when QPSK is used as the primary modulation wave as described above, the phase of the QPSK wave takes four values of 0, 90, 180, 270 degrees (or 0, ± 90, 180 degrees). When the offset QPSK is used, the phase information of the QPSK wave assumes four values of 45, 135, 225, and 315 degrees (or ± 45 and ± 135 degrees). The phase difference is a remainder value of 360 degrees, and the phases of the QPSK and the offset QPSK wave are set so as to divide the entire phase space to the maximum. For example, the reference phase is 0 degrees for QPSK and 45 degrees for offset QPSK. If so, all phases are 90 degrees apart from each other. If the four types of phases of the primary modulation wave are associated with states 00, 01, 10, and 11, it is possible to correspond to a dibit in which the transmission bit sequence is grouped by two bits, and two bits can be transmitted in one symbol.
[0006]
On the other hand, the symbol period T is an amount defined by the reciprocal of the symbol rate. When the symbol rate is 32 k symbols / second (hereinafter, symbols / second is described as sps), T = 31.25 μsec. Become. Therefore, when the symbol rate is 32 ksps, the transmission speed of QPSK is 64 kbit / second (hereinafter, bit / second is described as bps).
[0007]
Next, the operation of the diffusion circuits (SS) 120 to 120n in FIG. 10 will be described. As described above, in order to express each of the four phases of QPSK or offset QPSK, each of the four types of waveforms different from each other by 90 degrees is required as the carrier waveform in the symbol period T. To describe the waveform, a minimum of 4 samples per symbol period is required. Here, the number of samples per symbol period is assumed to be four.
[0008]
Now, as shown in FIG. 14, each symbol period of the primary modulation wave is divided into four segment sections from segment 0 to segment 3 in equal time sections. Here, the segment means a period from the first code to the last code in a single spreading code sequence in each symbol period. Further, as shown in FIG. 15, each segment section is divided into a number of chip sections equal to the number of codes of the spread code string. The chip value is given by the product of the primary modulation wave and the spread code value in each chip section. Since the primary modulation wave is a time function, the time resolution of the chip value is the chip period τ. However, in CDMA transmission, since a spreading operation and a spreading operation on the receiving side, which will be described later, are performed, the time resolution of information to be transmitted is a segment period τN. Here, N is the code length.
[0009]
The waveform of the spread signal shown in FIG. 15 shows the case where the first code string of the Walsh function having the code length 32 is used as the spread code string. It is not always necessary to use the Walsh function as the spreading code string, but it is necessary that they are orthogonal to each other. Here, when the inner product of the code strings becomes zero, the code strings are said to be orthogonal. Hereinafter, the 32 Walsh code string as the code length will be described.
[0010]
First, the orthogonality will be described using the 0th to second Walsh code sequences as an example.
The 0th to 2nd Walsh code strings are given as follows.
0th code string: (-1, -1, -1, -1, ..., -1, -1, -1, -1)
First code string: (-1, 1, -1, 1, ..., -1, 1, -1, 1)
Second code string: (-1, -1, 1, 1, ..., -1, -1, 1, 1)
Inner product (0, 1) of the 0th and first Walsh code strings, inner product (1, 2) of the first and second Walsh code strings, and inner product (0, 2) of the 0th and second Walsh code strings Can be calculated as follows: That is,
Inner product (0, 1) = 1−1 + 1−1 +... + 1-1 + 1−1 = 0
Inner product (1,2) = 1-1-1 + 1 +... + 1-1-1 + 1 = 0
Inner product (0, 2) = 1 + 1-1-1 +... + 1 + 1-1-1 = 0
It becomes. Since these inner products are all 0, it becomes clear that the code sequences of the Walsh function are orthogonal to each other.
[0011]
On the other hand, the inner product of the Walsh code string confidence can be calculated as follows. That is,
Inner product (0, 0) = 1 + 1 + 1 + 1 +... + 1 + 1 + 1 + 1 = 32
Inner product (1, 1) = 1 + 1 + 1 + 1 +... + 1 + 1 + 1 + 1 = 32
Inner product (2, 2) = 1 + 1 + 1 + 1 +... + 1 + 1 + 1 + 1 = 32
Thus, the inner product of all code strings itself normalized by the code length 32 is always unit 1. This means that when the Walsh code sequence is used as the code sequence, the same Walsh code sequence can be used as the spreading code sequence and the despreading code sequence.
[0012]
Now, a case is assumed where, in a certain segment period, three pieces of information are multiplexed and transmitted using the above-described zeroth to second Walsh code strings. Assuming that the value a is transmitted using the 0th Walsh code string, the value b is transmitted using the first Walsh code string, and the value c is transmitted using the third Walsh code string, the summation circuit ( If the information (sum signal (0, 1, 2)) input to the (SUM) 140 is described in correspondence with the chip, it is as follows.

If the receiving side can correctly receive the sum signal, the received sum signal is multiplied by the spreading code string, and the value of the primary modulation signal of the corresponding segment is obtained as follows.
[0013]
That is, the value corresponding to the 0th Walsh code sequence is given as follows by the inner product of the sum signal (0, 1, 2) and the 0th Walsh code sequence.

It becomes. Therefore, if the inner product of the sum signal (0, 1, 2) and the 0th Walsh code string is normalized by the code length 32, the value a is correctly received, and the values b and c are completely suppressed and interfered. It becomes clear that it can receive correctly without.
[0014]
Similarly, the value corresponding to the first Walsh code string is given by the inner product of the sum signal (0, 1, 2) and the first Walsh code string, and its value is 32b, and the second Walsh code string has The corresponding value is given by the inner product of the sum signal (0, 1, 2) and the second Walsh code string, and its value is 32c. Therefore, if the inner product of the sum signal (0, 1, 2) and the first Walsh code string is normalized by the code length 32, the value b is correctly received, and the sum signal (0, 1, 2) and the second signal are received. If the inner product of the Walsh code string is normalized by the code length 32, the value c is correctly received.
[0015]
In this way, as long as the spreading code sequences are orthogonal to each other, multiple connections can be made as many as the number of spreading code sequences, and communication can be performed only when the spreading code sequences match.
Note that the primary modulation wave in segment 0 in symbol interval 1 in FIG. 15 has a positive value of 0 to 1, and the primary modulation wave in segment 1 has a negative value of 0 to −1. In the figure, the sign of the chip value of segment 0 in the corresponding symbol section 1 changes to negative and positive alternation, and the sign of the chip value of segment 1 changes to positive and negative alternation.
[0016]
When the code length is 32, the chip rate of the spread signal is 32 ksps · 4 segments · 32 chips / segment = 4.096 Mchips / second (hereinafter, chips / second is described as cps).
Since all spread signals change synchronously in each chip section, the sum signal having the sum of chip values as the signal value in the chip section has a waveform showing a constant value in the chip section. Therefore, regardless of the transmission information rate, the chip rate is always constant 4.096 Mcps, regardless of the transmission information rate, even when the maximum information rate is 2 Mbps for simultaneous communication of 32 channels or when the transmission is performed at the minimum information rate of 64 kbps for one channel. It becomes.
[0017]
In this way, a plurality of spread signals corresponding to the information signal and the necessary control signal are converted into orthogonal spread code sequences output from the spread code generation circuits (CG) 130 to 130n as shown in FIG. Using the spread circuit (SS) 120 to 12n, the sum of a plurality of spread codes is obtained by a sum circuit (SUM) 140, and the obtained sum signal is frequency-converted in the transmission circuit (TX) as necessary. The power is amplified and transmitted as a CDMA signal.
[0018]
In order to accurately transmit a rectangular wave of a CDMA signal, a frequency band several times the chip rate is required. As shown in FIG. 10, a bandpass filter (BPF) 141 functions as a bandpass filter. The operation is performed and the frequency bandwidth is limited to the chip rate.
Here, the radio waves transmitted from the transmission circuit (TX) as described above are generally hardly communicated via an ideal radio wave propagation path. In mobile communications such as car phones and mobile phones, the transmitter itself moves, so a Doppler shift occurs and the carrier frequency shifts. Or the fading phenomenon which the phase and amplitude of a received wave change with time occurs by receiving via a plurality of radio wave propagation paths.
[0019]
Therefore, on the receiving side, the CDMA receiver is composed of main circuits such as reception, synchronous detection, reception control, demodulation, despreading, phase correction, and determination.
In FIG. 16, a reception control circuit (CNT) 204 detects various control signals necessary for control of the receiver from the received signal, and outputs a plurality of despread code sequences necessary for reception. A synchronization detection circuit (SYNC) 203 outputs a carrier reproduction wave, a chip synchronization signal, a segment synchronization signal, a symbol synchronization signal, and the like from the received signal.
[0020]
The demodulation circuit (deMOD) 201 has the configuration shown in FIG. In the figure, a received wave applied to an input terminal 2010 connected to a receiving circuit (RX) 200 is input to multipliers 2011 and 2012. Here, the demodulating circuit (deMOD) 201 generally uses a synchronous detection method. The product of the carrier reproduction wave 202 and the received wave is obtained by the multiplier 2011, and then the carrier period accumulated by the accumulator 2014 for each carrier period. Each inner product is obtained, the obtained inner product is fetched by the latch register (REG) 2016, held for the carrier cycle period, and the value held by the latch register (REG) 2016 is the in-phase component i (t of the demodulated signal of the primary modulation wave ) For each carrier cycle. At the same time, the demodulation circuit (deMOD) 201 obtains the product of the orthogonal carrier signal obtained by shifting the carrier reproduction wave 202 by 90 degrees by the phase shifter 2013 and the received wave by the multiplier 2012, and then by the accumulator 2015 for each carrier period. The accumulated inner product for each carrier cycle is obtained, the obtained inner product is fetched by the latch register (REG) 2017, held for the carrier cycle period, and the value held by the latch register (REG) 2017 is used as the demodulated signal of the primary modulation wave. An orthogonal component q (t) is output for each carrier period. A signal R input to the accumulators 2014 and 2015 is a cumulative reset signal input from the control terminal 2018 for each carrier cycle. At the leading edge of the cumulative reset signal R, the accumulators 2016 and 2017 hold input values.
[0021]
The in-phase component i (t) and the quadrature component q (t) of the demodulated signal from the demodulating circuit (deMOD) 201 are input to n + 1 despreading circuits (deSS) 210 to 21n as shown in FIG. FIG. 18 shows one configuration example of the diffusion circuits (deSS) 210 to 21n.
In-phase component i (t) of the demodulated signal and quadrature component q (t) of the demodulated signal are input to input terminals 2100 and 2101, respectively. Multipliers 2102 and 2103 are respectively in-phase component i (t) of the demodulated signal, quadrature component q (t) of the demodulated signal, and the i-th despread code string input from terminal 22i in accordance with the chip synchronization signal. The product is obtained, and the accumulation of products is obtained for each segment according to the segment synchronization signal.
[0022]
Here, i indicates the i-th channel, and the i-th despread code sequence is a despread code sequence corresponding to the i-th spread code sequence used on the transmission side, When the Walsh function is used, the despread code sequence and the spread code sequence are equal to each other. In addition, as shown in FIG. 16, a corresponding despreading code string is input to each terminal 220-22n of the despreading circuits 201-20n.
[0023]
Subsequently, in FIG. 18, the outputs of the multipliers 2102 and 2103 are accumulated in the accumulators 2014 and 2015. The accumulators 2104 and 2105 receive the accumulated reset signal R from the terminal 2110 for each segment. The outputs of the accumulators 2104 and 2105 are normalized by the code length, respectively, and the in-phase component I of the despread signal held in the segment section by the latch registers (REG) 2106 and 2107 is obtained. _i '(T) and quadrature component Q of the despread signal _i 'Output from the output terminals 2108 and 2109 as (t).
[0024]
Since the spreading code sequences are orthogonal to each other, when the despreading code sequence matches the transmission spreading code sequence, the outputs of the despreading circuits 210 to 21n output finite values and can be received correctly. . When the despread code string does not match the transmission spread code string, the outputs of the despreading circuits 210 to 21n are always zero, and the reception signal is not output as a result.
[0025]
In-phase component I of the despread signal for n information channels of simultaneous multiple access _i '(T) and quadrature component Q of despread signal _i '(T) is output from each of the despreading circuits 211 to 21n. Further, the in-phase component I of the despread signal related to the pilot signal common to these n channels ₀ '(T) and quadrature component Q of the despread signal ₀ '(T) is output from the despreading circuit 210.
[0026]
These despread signals are each subjected to disturbance such as phase difference, amplitude distortion, and delay during propagation. It occurred during propagation by transmitting a pilot spread signal in which the primary modulation of a known value, for example, phase information of “0” was spread, and measuring the error between the phase difference detected on the receiving side and the known value The disturbance phase error can be known roughly. Therefore, as shown in FIG. 16, a pilot scheme that roughly corrects disturbance during propagation by adding one channel of a pilot signal that transmits a known value to n-channel information is often used.
[0027]
For this reason, a case where one pilot channel is added to n information channels will be described. However, when one pilot channel is added to one information channel, or in-phase components of the primary modulation wave in each spread signal are used as information. The same applies when assigning orthogonal components to pilot signals.
In FIG. 16, the outputs of the despreading circuits (deSS) 211 to 21n and the output of the despreading circuit (deSS) are guided to the phase correction circuits (CMP) 231 to 23n. FIG. 19 shows one configuration of the phase correction circuits (CMP) 231 to 23n.
[0028]
The in-phase component I of the information channel i from the despreading circuit (deSS) 21i is connected to the input terminals 2300 and 2301. _i '(T) and quadrature component Q of despread signal _i '(T) is input respectively. In addition, the input terminals 2302 and 2303 are connected to the in-phase component I of the pilot channel from the despreading circuit 210. ₀ '(T) and orthogonal component Q ₀ '(T) is input respectively. Subsequently, the in-phase component I of the information channel i _i '(T) sends to the multipliers 2310 and 2311 the orthogonal component Q of the information channel i. _i '(T) is input to multipliers 2312 and 2313 and the in-phase component I of the pilot channel ₀ '(T) is sent to the multipliers 2310 and 2312 and the orthogonal component Q of the pilot channel. ₀ '(T) is input to the multipliers 2313 and 2311. The adder 2320 converts the sum of the outputs of the multipliers 2310 and 2313 into the in-phase component I of the phase correction signal. _i Output to the terminal 2340 as (t). Further, the adder 2321 calculates the difference between the output of the multiplier 2312 and the output of the multiplier 2311 and the orthogonal component Q of the phase correction signal. _i Output to the terminal 2341 as (t).
[0029]
The outputs of the phase correction circuits (CMP) 231 to 23n are guided to determination circuits (DEC) 241 to 24n as shown in FIG. The decision circuits (DEC) 241 to 24n are in-phase components I of the phase correction signal. _i (T), orthogonal component Q _i Mapping for obtaining the phase angle from (t) is performed, and quadrant determination is performed based on the phase angle obtained by this mapping, and the received symbol S as the information symbol _i (T) is output to the terminals 251 to 25n.
[0030]
[Problems to be solved by the invention]
In a conventional CDMA transmission system, a spread signal having a spread spectrum is generated by multiplying a PSK wave of a primary modulation wave by a spread code string such as a Walsh code string. In FIG. 2 showing the time response waveform of the spreading code sequence in chip 1 to chip 3, the broken line shows an example of a conventional spreading code sequence waveform. In the chip section 1 and the chip section 2, the code value 1 is shown, in the chip section 3, the code value -1 is shown, and in the chip section 4, the code value 1 is shown, but the other cases are the same. When the spread code values are equal in adjacent chip sections such as chip section 1 and chip section 2, discontinuity does not occur in the waveform of the spread signal in the adjacent chip sections.
[0031]
On the other hand, when the spread code values are different from each other, such as between the chip section 2 and the chip section 3 or between the chip section 3 and the chip section 4, a severe waveform change appears in the spread signal at the end of the chip section. .
When the code value is held up to the end of the chip section in all the chip sections, a severe waveform variation as shown by the broken line in FIG. 2 occurs at the end of the chip section, and the frequency bandwidth of the spread signal is extremely increased. As a result, there is a problem that communication quality deteriorates.
[0032]
Therefore, an object of the present invention is to eliminate a drastic fluctuation of a spread code string waveform at the end of a chip section, prevent an increase in frequency bandwidth, and improve communication quality.
[0033]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, for example, as shown by the solid line waveform in FIG. 2, when the spreading code value is different in the adjacent chip section, it is continuously changed in the transition section, and the spreading code in the transition section is changed. We try to eliminate sudden fluctuations in value.
Here, the transition section refers to a section installed across adjacent chip sections in the vicinity of each chip section end. For example, in the case of FIG. 2, the transition section 2 is between the chip section 1 and the chip section 2, the transition section 3 is between the chip section 2 and the chip section 3, and the transition section 4 is between the chip section 3 and the chip section 4. Become. All transition sections have the same time length R.
[0034]
In this way, when the spread code value is different in the adjacent chip section, by eliminating the rapid fluctuation of the spread code value in the transition section, it is possible to eliminate the intense fluctuation of the spread code string waveform at the end of the chip section, An increase in width can be prevented.
However, if the spread code string waveform is changed and distorted at the end of the chip section, the information phase to be propagated changes, and the communication quality deteriorates with the conventional CDMA receiver configuration. Occurs.
[0035]
Therefore, in the present invention, at the time of demodulation, the received signal is not used up to the end of the chip section in all chip sections, but the received signal in the section with less distortion near the center of the chip is used as an effective area and demodulated for demodulation. By setting the interval, an unstable value around the transition interval is removed, and a stable demodulation operation can be performed. That is, the features of the present invention are as described in the claims. In the invention described in claim 1, Means for phase-modulating the carrier signal corresponding to the information to generate a primary modulated wave, and when the value of the spreading code is different in the adjacent chip section, the value of the spreading code is changed in the transition section of the end area of the chip section. Means for continuously changing and generating a spread code string from which sudden fluctuations in the value of the spread code are eliminated; and a spread signal obtained by multiplying the primary modulation wave by the spread code string generated by this means and performing spectrum spread And means for transmitting the generated spread signal, and means for selecting a received signal in a demodulation section excluding a transition section in which at least a sudden change in the value of the spreading code is excluded from the received signal And means for despreading the received signal selected by this means using a despread code sequence to restore information, wherein the means for selecting the received signal is despread based on the despread code sequence Sign value Only if the different adjacent chip section, radios using CDMA transmission scheme and selects a reception signal of the demodulation section from the received signal It is characterized by.
[0036]
In this way, a received signal in a demodulation section excluding a transition section in which at least a sudden change in the spread code value is excluded is selected from the received signals, and despreading is performed using the selected received signal. Therefore, stable demodulation operation can be performed even if the spreading code sequence at the end of the chip section is changed on the transmission side so as to eliminate sudden fluctuations.
[0037]
Na As means for selecting the received signal, the claims 2 As in the invention described in, the received signal in the demodulation section is selected from the received signal demodulated by the demodulating means between the demodulating means for demodulating the received signal and the means for performing despreading Can do.
[0039]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments shown in the drawings will be described below.
As shown in FIG. 1, the transmitter according to this embodiment includes a spreading code string waveform continuation circuit (CODE-CS) 150 between spreading code generation circuits (CG) 130 to 13n and spreading circuits (SS) 120 to 12n. ˜15n is inserted. In this transmitter, the configuration other than the spread code string waveform continuation circuits (CODE-CS) 150 to 15n is the same as that shown in FIG. By providing the spreading code string waveform continuation circuits (CODE-CS) 150 to 15n, as shown in FIG. 2, the spreading code value is gently reduced in the transition section only when the spreading code value is different in the adjacent chip section. Can be changed.
[0040]
FIG. 3 shows one configuration of spreading code string waveform continuation circuits (CODE-CS) 150 to 15n. In the figure, a spread code string from a corresponding spread code generation circuit (CG) 13 i is inputted to an input terminal 300 and inputted to an adder 301 as it is. The output of the output terminal 306 is captured and held in the latch register (REG) 305 at the leading edge of the clock signal applied to the clock terminal (CLK) 307. The adder 301 outputs the difference between the spread code value input to the input terminal 300 and the value held in the latch register (REG) 305. The output value of the adder 301 is multiplied by the value output from the smoother (SMO) 303 by the multiplier 302. The output of the multiplier 302 is added to the output value of the latch register 305 in the adder 304, and the added value is output from the output terminal 306.
[0041]
Here, as shown in FIG. 4, the smoother (SMO) 303 outputs a value in which the output (t) continuously changes from 0 to 1 in each transition section, for example, a value represented by Equation 1. Since the smoother output (t) periodically outputs a value with respect to the chip interval τ, the output values for one chip interval are stored in the ROM, and the output values are sequentially read out to obtain the values shown in FIG. It can be output periodically.
[0042]
[Expression 1]

[0043]
Next, the operation of the spread code string waveform continuation circuit (CODE-CS) will be described. Since the operation is periodic with respect to the chip interval, description will be made from time t = R / 2 to time t = 2τ + R / 2, but the same applies to other chip intervals.
It is assumed that a clock is applied to the clock terminal (CLK) 307 at the trailing edge t = R / 2 of the transition section, and the spreading code value of the next chip section is determined. As shown in FIG. 2, since the output of the output terminal 306 is 1 at time t = R / 2, 1 is captured and held in the latch register (REG) 305. In addition, the spreading code value 1 of the chip section 2 is applied to the input terminal 300. Since the output of the latch register (REG) 305 and the input of the input terminal 300 are equal, the output of the adder 301 becomes zero. Therefore, regardless of the output value of the smoother (SMO) 303, the output of the multiplier 302 becomes 0 throughout the transition interval 2, the output of the adder 304 remains 1 and the output terminal 305 has a value of 1. Output continuously. Further, at the trailing edge t = τ + R / 2 of the transition section 2, the latch register (REG) 305 captures and holds the output value 1, and the spreading code value −1 of the next chip section 3 is applied to the input terminal 300. Is done.
[0044]
For this reason, the output of the adder 301 becomes −2, but since the output of the smoother (SMO) 303 is 0 until the leading edge of the transition section 3, the multiplier 302 continuously outputs the value 0. However, since the sum of the multiplier 304 and the latch register (REG) 305 is output to the output terminal 306, the value 1 held in the latch register 305 is continuously output to the leading edge of the transition section 3. The In the transition section 3, the output of the smoother 303 rises from the value 0 at the leading edge and continuously increases to the value 1 at the trailing edge. Therefore, the output of the multiplier 302 changes from 0 to -2. As a result, the sum of the output of the multiplier 304 and the value held in the latch register 305 appears at the output terminal 306 while changing from 1 to -1. For this reason, the spreading code value of the transition section 3 is shaped into a smoothly changing waveform as shown in FIG. Further, at the end of the transition section 3, the value −1 of the output terminal is taken into the latch register 305, the next operation is performed, and the same operation as described above is performed.
[0045]
By providing the spread code string waveform continuation circuits (CODE-CS) 150 to 15n in this way, when the spread code value is different in the adjacent chip section, the spread code value is gradually changed in the transition section, and the chip section end is changed. Excessive fluctuations in the spread code string waveform can be eliminated to prevent an increase in the frequency bandwidth. However, if the spread code string waveform at the end of the chip section is distorted, the information phase to be propagated changes, and the communication quality deteriorates with the conventional CDMA receiver configuration.
[0046]
Further, in order to perform communication with a predetermined bandwidth, the frequency band of the transmission wave is band-limited by the band-limiting circuit (BPF) 141. In this case, if the phase is made continuous as described above, the transition section The distorted waveform in FIG. 5 affects the preceding and following sections as interference, and degrades the communication quality. That is, as shown in FIG. 6, the band limiting circuit (BPF) 141 includes k delay units 1401 to 140k and tap coefficients W to the signals delayed by these delay units 1401 to 140k. ₁ ~ W _k When a transversal filter including a multiplier 1411 to 141k that multiplies and a summation circuit (SUM) 1420 that sums signals from the multipliers 1411 to 141k is used, a signal corresponding to a waveform distorted in the transition section is transmitted to this filter. When input, the output of the filter is affected by the sections before and after the transition section, and different frequency components are mixed in the desired frequency band to be output, which reduces the communication quality. Deteriorate.
[0047]
Therefore, in the receiver in this embodiment, as shown in FIG. 6, the demodulation section is set within the section excluding the transition section in each chip section, and despreading is performed using the received signal value in this demodulation section. I am doing so.
For this reason, in the receiver, as shown in FIG. 7, selection circuits (switch circuits) 251 and 252 are provided between the demodulation circuit (deMOD) 201 and the despreading circuits (deSS) 210 to 21n, and the timing control circuit Only when the timing signal is output from 253, the in-phase component i (t) of the demodulated signal from the demodulating circuit 201 and the quadrature component q (t) of the demodulated signal are output to the despreading circuits (deSS) 210 to 21n. Like to do. This receiver is the same as that shown in FIG. 16 except that selection circuits 251 and 252 and a timing control circuit 253 are provided.
[0048]
Here, the timing control circuit 253 outputs the timing signal described above in the demodulation section within each chip section based on a signal output for each chip, for example, a chip synchronization signal. This demodulation section is set to a section with little distortion near the center of the chip, the start timing is after R / 2, and the end timing is before τ-R / 2. In this case, for example, when the demodulation period is set by sampling with the system clock of the receiver, as shown in FIG. 8, when the number of samples in the chip section is n and the number of samples in the demodulation section is m, the number of samples is If the timing signal is output at m / 2 and the output of the timing signal is stopped at nm / 2-1, the timing signal can be output only in the demodulation section. Note that the received signal value is not used until the number of samples reaches m / 2, and until the number of samples exceeds n−m / 2-1 and reaches n−1.
[0049]
Further, when the output of the demodulating circuit 201 is A / D converted by the A / D converter and despreading is performed based on the converted value, the timing described above is used at the timing of the A / D conversion. Sampling may be performed.
Further, when the despread code value is the same as that of the adjacent chip section, there is no discontinuity point, so the timing signal described above may be output in all of the chip sections. In this case, as shown in FIG. 9, the selection circuits 2112 and 2113 and the timing control circuit 2111 having the same configuration as the selection circuits 251 and 252 and the timing control circuit 253 are provided in the despreading circuits (deSS) 210 to 21n, respectively. Based on the despread code string in the despread circuit (deSS), the timing control circuit 2111 determines whether the despread code value is the same as the adjacent chip section, and the despread code value is the adjacent chip section. The timing signal may be output only when different from the above. In this way, when the despread code value is the same as the adjacent chip section, the in-phase component i (t) and quadrature component q (t) of the demodulated signal in the transition section can also be used for the despreading process. Demodulation accuracy can be improved.
[0050]
Therefore, according to this embodiment, when the spread code value is different in the adjacent chip section, the transmitter side gradually changes the spread code value in the transition section, and the spread code string waveform at the end of the chip section is severely changed. In addition to preventing an increase in frequency bandwidth, the receiver side performs despreading using the received signal value in the demodulation period in each chip section, so the waveform in the transition section Demodulation can be performed accurately without being affected by distortion, and communication quality can be improved.
[0051]
Each circuit shown in the above-described embodiment is grasped as a means for realizing each function.
Since the above-described communication is performed between the mobile station and the base station, both the mobile station and the base station are provided with the above-described transmitter and receiver. Therefore, when the mobile station is a wireless device such as a mobile phone, the wireless device is equipped with the transmitter and receiver described above.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration of a CDMA transmitter according to an embodiment of the present invention.
FIG. 2 is a diagram showing a spread code string waveform in chip sections 1 to 4;
FIG. 3 is a diagram showing a configuration of a spread code string waveform continuation circuit (CODE-CS).
FIG. 4 is a diagram illustrating output characteristics of a smoother (SMO).
FIG. 5 is a diagram illustrating a configuration of a band limiting circuit (BPF).
FIG. 6 is a diagram for explaining a transition section and a demodulation section in each chip section.
FIG. 7 is a diagram showing a configuration in which a selection circuit and a timing control circuit are provided between a demodulation circuit (deMOD) and a despreading circuit in a CDMA receiver according to an embodiment of the present invention.
FIG. 8 is an explanatory diagram when a demodulation period is set based on the number of samples.
FIG. 9 is a diagram illustrating a configuration in which a selection circuit and a timing control circuit are provided in a despreading circuit (deSS).
FIG. 10 is a diagram illustrating a configuration of a conventional CDMA transmitter.
11 is a diagram showing waveforms in the symbol 0 and symbol 1 sections of the primary modulation wave of the CDMA transmitter shown in FIG. 10;
FIG. 12 is a diagram illustrating an example of bit arrangement (bit constellation) of QPSK.
FIG. 13 is a diagram illustrating an example of bit arrangement (bit constellation) of offset QPSK.
FIG. 14 is a diagram illustrating a segment configuration example in a symbol section of a primary modulation wave.
FIG. 15 is a diagram illustrating a chip configuration example in a segment section;
FIG. 16 is a diagram illustrating a configuration example of a conventional CDMA receiver.
FIG. 17 is a diagram illustrating a configuration example of a demodulation circuit (deMOD) in the CDMA receiver illustrated in FIG. 16;
18 is a diagram illustrating a configuration example of a despreading circuit (deSS) in the CDMA receiver illustrated in FIG. 16;
FIG. 19 is a diagram illustrating a configuration example of a phase correction circuit (CMP) in the CDMA receiver illustrated in FIG. 16;
[Explanation of symbols]
100 to 10n ... information input terminal,
110 to 11n: phase modulation circuit (MOD),
120-12n ... diffusion circuit (SS),
130 to 13n: Spreading code generation circuit (CG),
140: Sum circuit (SUM),
141: Band limiting circuit (BPF),
142 ... transmission circuit (TX),
151 to 15n: Spreading code string waveform continuation circuit (CODE-CS),
201 ... demodulator circuit (deMOD),
202 ... Carrier regeneration wave,
203 ... Synchronization detection circuit (SYNC),
204: Reception control circuit (CNT),
210 to 21n: despreading circuit (deSS),
231 to 23n: phase correction circuit (CMP),
241 to 24n: determination circuit (DEC),
251 to 25n: output terminals,
253, 2111 ... timing control circuit,
251, 252, 2112, 2113... Selection circuit.

Claims (2)

Means for phase-modulating the carrier signal corresponding to the information to generate a primary modulated wave;
When the spreading code value is different in adjacent chip sections, the spreading code value is continuously changed in the transition section of the end area of the chip section, and a spreading code string is generated in which sudden fluctuations in the spreading code value are eliminated. Means to
Means for multiplying the primary modulation wave by the spread code string generated by the means to generate a spread spectrum signal, and transmitting the generated spread signal;
Means for selecting a received signal in a demodulation section excluding a transition section in which at least a sudden change in the value of the spreading code is excluded from the received signal;
Means for despreading the received signal selected by this means using a despread code sequence and restoring information ;
The means for selecting the received signal selects the received signal in the demodulation section from the received signal only when the value of the despread code is different between adjacent chip sections based on the despread code sequence. A wireless device using a CDMA transmission system. Means for receiving and demodulating the transmitted spread signal, wherein the means for selecting the received signal selects the received signal in the demodulation section from the demodulated received signal; A radio using the CDMA transmission system according to claim 1 .

Images