JP4050250B2 - Nonvolatile semiconductor memory device - Google Patents

Description

 The present invention relates to a nonvolatile semiconductor memory device using a NAND type EEPROM among electrically rewritable nonvolatile semiconductor memory elements (EEPROM).

 Magnetic disk devices are currently widely used as secondary storage devices for computers, but in recent years, electrically rewritable nonvolatile semiconductor memories (EEPROMs) are more reliable in terms of mechanical strength, lower power consumption, It has been used for applications such as replacing magnetic disks by taking advantage of its portability and high-speed access.

However, since there is a functional difference between the magnetic disk device and the EEPROM, in order to replace the conventional magnetic disk device as it is, control for filling this is necessary.

 As one type of EEPROM, a NAND type EEPROM capable of high integration is known. In this method, a plurality of memory cells are connected in series by sharing their sources and drains with adjacent ones, and connected to a bit line. A memory cell usually has a FETMOS structure in which a charge storage layer and a control gate are stacked. The memory cell array is integrated in a p-type well formed on a p-type substrate or an n-type substrate. The drain side of the NAND cell is connected to the bit line through the selection gate, and the source side is also connected to the source line (reference potential wiring through the selection gate (FIG. 12). The control gate of the memory cell is connected to the row. Normally, a set of memory cells connected to the same word line is called one page, and a set of pages sandwiched between a set of drain side and source side select gates is a 1 NAND block. Alternatively, it is simply referred to as one block (FIG. 13) Usually, one block is the smallest unit that can be independently erased.

 The operation of the NAND type EEPROM is as follows. Data is erased simultaneously for the memory cells in one NAND block. That is, all control gates of the selected NAND block are set to the reference potential VSS, and a high voltage VPP (for example, 20 V) is applied to the p-type well and the n-type substrate. As a result, electrons are emitted from the floating gate to the substrate in all the memory cells, and the threshold value is shifted in the negative direction. Normally, this state is defined as “1” state. Chip erase is performed by setting all NAND blocks to a selected state.

 Data write operation is performed in order from the memory cell farthest from the bit line. A high voltage VPP (for example, 20 V) is applied to the selected control gate in the NAND block, and an intermediate potential VM (for example, 10 V) is applied to the other non-selected gates. Further, VSS or VM is given to the bit line according to data. When VSS is applied to the bit line ("0" write), the potential is transmitted to the selected memory cell, and electrons are injected into the floating gate. As a result, the threshold value of the selected memory cell is shifted in the positive direction. Normally, this state is defined as a “0” state. Electron injection does not occur in the memory cell in which VM is applied to the bit line ("1" write), and therefore the threshold value remains unchanged and remains negative. The data read operation is performed by setting the control gate of the selected memory cell in the NAND block as VSS and setting the other control gate and selection gate as VCC and detecting whether or not a current flows in the selected memory cell.

 In the NAND type EEPROM, it is necessary to write data sequentially from a page close to the source line to a page on the drain side. The necessity will be described below with reference to FIG. In “1” writing, the intermediate potential VM (about 10 V) is transferred to the drain of the selected memory cell, and the erased state (that is, a negative threshold) is maintained without causing electron injection. FIG. 14 shows the state when the control gate 1 is in the selected state (VPP). Therefore, the control gate 2 is not selected and VM is given. Also, VM ("1" write) is given to the drain. FIG. 14A is a diagram when writing is performed from the source side, and FIG. 14B is a diagram when writing is performed from the drain side. In the case of FIG. 14A, since the drain side cell Ma2 has a negative threshold value, the drain potential VM is reliably transferred to the source side cell Ma1. However, in the case of FIG. 14B, assuming that the drain side cell Mb2 has already been written with "0" and has a positive threshold value (for example, 3.5 V), "1" is written to the source side cell Mb1. At this time, only a voltage obtained by subtracting the threshold voltage of the cell Mb2 from the VM is transferred to the cell Mb1. Therefore, in the cell Mb1, the potential difference between the control gate and the substrate becomes large, and erroneous writing may occur. As described above, means for sequentially writing from the source side is important in terms of preventing erroneous writing.

 In the conventional magnetic disk apparatus, the unit of access such as data reading and writing is a sector. A track formed on the circumference of the medium is divided into several tens of sectors, and numbers (addresses) are sequentially assigned to the sectors in accordance with the rotation direction. Assuming that there are 50 sectors in one track, an access such as writing four sectors of data from the fifth sector in the first access and writing four sectors of data from the first sector in the second access is normally performed. Is called. On the other hand, the access unit of the NAND type EEPROM is a page. Taking a 4M bit NAND type EEPROM as an example, one page is composed of 512 bytes, and one block is composed of eight pages. Therefore, in an application in which a magnetic disk device is replaced with a NAND type EEPROM, conversion is easy if one sector of the disk is mapped to one page of the NAND type EEPROM. However, as in the case of the magnetic disk, if access is performed such that four pages are written from the fifth page from the source side in one block and then four pages are written from the first page, erroneous writing occurs as described above. there is a possibility.

 One way to avoid this is to erase the block from the 5th page, which was written first, to the buffer once in the second access, and then erase this block. The procedure is to write data.

However, this operation wastes a limited number of times the EEPROM is rewritten. Another method is to make the access unit of the NAND type EEPROM a block of erase units. In this case, in order to rewrite a part of the data of the block as described above, the already written data in the block is once read into the buffer, and the data to be rewritten is overwritten on the buffer. The procedure of erasing the block and writing 8 pages of data from the first page is performed.

 As described above, in the NAND type EEPROM, data access is performed in units of pages corresponding to the sectors of the magnetic disk. However, when random data is written in units of pages as in the magnetic disk, the order of writing in the block is determined. There was a problem that there was a possibility that would be out of the rules and miswritten. In order to avoid this, if the data previously written in the buffer is sucked up and the block is erased, the rewriting is performed, which increases the number of rewrites and shortens the lifetime of the chip. When an access unit is blocked, data is written to all pages in the block at once. At this time, the data to be written is transferred from the buffer to the NAND-type EEPROM, but not all the data in the buffer is valid. In other words, when writing to a block and the writing is the first writing to the block, or when invalidating the data written to the block, there is no need to read the data in the block prior to rewriting. . Therefore, at this time, if there is data to be written to only some pages, the data for the remaining pages is invalid. Normally, no data is set in the invalid portion, so the “erased” data from the previous use of the buffer remains and is written as it is. In the conventional magnetic disk apparatus, there is no difference in writing time when writing "1" as data and when writing "0". However, in the case of a NAND type EEPROM, as described above, all data is “1” in the erased state, and electrons are injected only when data of “0” is written. In addition, since the time required for the electron injection is not constant for each bit, the process proceeds while verifying whether “0” is normally written. Therefore, if all the data in the page is “1”, the writing is completed instantaneously. Furthermore, since no electron injection occurs, stress on the oxide film is reduced. As described above, in consideration of the characteristics of the NAND-type EEPROM, if all invalid data portions are set to “1”, when this is spread over one page, it is possible to avoid wasting time for writing the page. However, since the conventional input / output system was for a magnetic disk having no such characteristics, no consideration was given to this point.

 The present invention has been made in view of the above-described problems, and prevents an increase in the number of times of writing due to a reversal of the order of writing and an increase in the number of times of writing due to rewriting, and prevents unnecessary stress on the insulating film of the memory cell. An object of the present invention is to provide a non-volatile semiconductor memory device capable of improving the life of a chip and minimizing the time required for writing.

 In order to achieve the above object, embodiments of the present invention are characterized in that (a) a nonvolatile semiconductor memory device connected to a host and records data, and (b) comprises a plurality of pages. NAND type EEPROM having a memory cell array divided into blocks, and (c) information for specifying a physical block that is stored in the NAND type EEPROM and to which data should be written corresponding to a logical page designated by the host; The gist of the invention is a nonvolatile semiconductor memory device including a management table including a pointer used for sequentially writing data from a physical page on the most source side in a block to a NAND type EEPROM.

 First, when writing data to the memory means, writing is always performed from a rule relating to the order of writing, that is, from the page on the source side in the block, regardless of the order of access to the page from the host system or the like. This shortens the life of the chip by increasing the number of times of writing by erasing data written on the drain side or the like after erasing the data written on the drain side or the like and then rewriting the data. Is avoided.

 Second, when data is written to the block, the data in the area where no valid data exists in the buffer is initialized so as to be the same as the data in the erased state. Thus, writing of a page filled only with invalid data is completed in the shortest time, and unnecessary stress is not applied to the insulating film of the memory cell, so that the life of the chip is avoided.

(First embodiment)
FIG. 1 is a block diagram showing the overall configuration of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. In the figure, reference numeral 1 denotes a NAND type EEPROM module as a memory means, which is composed of a memory cell array divided into blocks each composed of a plurality of pages. The EEPROM module 1 is connected to a host system (not shown) via a host interface 3 connected by data lines.

 A multiplexer 10 and a data buffer 11 are provided on the data line. In the host interface 3, a data register 4, an address register 5, a count register 6, a command register 7, a stator register 8, and an error register 9 are provided. Reference numeral 12 is a control logic, 13 is an ECC (error correction code) generator / checker, 14 is an address generator, 15 is a CPU having a function as a control means, 16 is a working RAM into which a page management table and the like described later are read, and 17 Control program ROM. The control program ROM 17 stores a series of control programs for writing data.

 The memory device according to the present embodiment uses a page management table for allocating and managing page positions in the block for data recorded in the EEPROM module 1 which is a nonvolatile memory area. This table is recorded in the EEPROM module 1 together with other user data, but is automatically read into the working RAM 16 when the apparatus is activated. The contents of this table are updated each time data is written to the EEPROM module 1, and this updated table is written back to the EEPROM module 1 each time or when the use of the apparatus is finished. I will do it.

 FIG. 2 manages the correspondence between the page address (logical page) and the physical position (physical page) in the block, and the physical position of the next page to be used in accordance with the rules regarding the writing order of the EEPROM module 1 2 is an example of a page management table 20 as a management means for pointing to the page. The page management table 20 is divided into n areas as shown in FIG. 2A, and each area 18 corresponds to each block of the EEPROM module 1. Here, for the sake of simplicity, assuming that the number of NAND-type EEPROMs constituting the memory device is one 4M-bit EEPROM, n, that is, the number of blocks is 128. These areas 18 are further composed of one pointer 21 serving as a point means and a flag area 22 having the number of pages (= 8) as shown in FIG. The pointer 21 is for sequentially writing to the pages in the block from the source side, and indicates the most source side page that has not yet been written. If this value exceeds the number of pages per block (In this example, 9) indicates that writing cannot be performed unless block erasing is performed. The logical page flag 22 is set to “0” when the logical page is not yet written, and when it is written, the physical position where the logical page is actually written is set to what number from the source side. It shall indicate whether it was a page.

 An outline of the operation when data is recorded will be described using a specific example. If nothing has been written in a certain block, the contents of the pointers and flags in the area 18 of the page management table 20 corresponding to the certain block are as shown in FIG. At this time, it is assumed that three pages of data are written from the fifth logical page of this block. First, since the value of the pointer 21 is 1, the content of the fifth logical page is written to the physical page on the most source side, the value of the flag 22 of the fifth logical page is updated to 1, and the value of the pointer 21 Is also incremented to indicate the second page from the source side. This operation is further repeated for two pages and updated as shown in FIG. Next, when writing five pages from the first logical page to the same block, the pointer 21 points to the fourth physical page, so five pages are written from here, and the table is shown in FIG. Update as shown in c). As a result, the pointer 21 becomes 9, so that the next writing to this block requires a process of saving data that cannot be rewritten to the buffer and then erasing the block and writing it back with new data. For example, if data for two pages is rewritten from the first logical page in the state of FIG. 3C, the contents of the third logical page to the seventh logical page that are not rewritten are sucked into the buffer, and block erasure is performed. The pointer 21 is also initialized to 1. Thereafter, the data for 7 pages in the buffer is written to the block. FIG. 3D shows the contents of the updated table in this case. Even if the content of the pointer is not 9, even when the number of pages to be written is larger than the number of remaining pages (for example, a write request for 6 pages from the third logical page in the state of FIG. 3B). ), It is necessary to perform the same processing. When data is read, the correspondence between the page address in the block and the physical position is obtained from the page management table 20 and necessary data is accessed.

 Next, the operation of this apparatus will be described using a flowchart. The host system sets an access start address in the address register 5 in the host interface 3 of FIG. 1, sets the sector length of data to be accessed in the count register 6, and finally sets an instruction such as read / write in the command register 7. . When an access instruction is written in the command register 7 of the host interface 3, the CPU 15 in the controller reads the instruction in the command register 7 and executes a series of control programs for command execution stored in the control program ROM 17. In the following description, for the sake of simplicity, it is assumed that the sector length designated by the host system and the page length in the EEPROM module 1 match.

 FIG. 4 is a flowchart showing a procedure for reading data from the EEPROM module 1. First, the CPU 15 in FIG. 1 determines the physical address of the EEPROM module 1 to be read with reference to the start address set in the host interface 3 and the address conversion table in the page management table 20 (step 101). . Next, data is read from the EEPROM module 1 to the data buffer 11 (step 102). Next, error processing and data transfer from the data buffer 11 to the host system, which will be described in detail later, are performed (steps 103 to 105).

 FIG. 5 is a flowchart showing a procedure for reading data from the EEPROM module to the data buffer. The CPU 15 accesses the EEPROM module 1 through the multiplexer 10 to set the read mode, and sets the data buffer 11 to the read mode (steps 201 and 202). The physical address of the EEPROM module 1 to be read is set in the address generator 14 (step 203). Then, an area in which the read data is to be stored is determined in the data buffer 11, and the head address is set as a write address to the data buffer 10 (step 204). Thereafter, the control logic 12 is instructed to execute a predetermined sequence for reading data.

 The control logic 12 sets the multiplexer 10 so that the read data from the EEPROM module 1 flows to the data buffer 11, and reads the data for one sector while incrementing the contents of the address generator 14 (step 205). Further, the ECC generator / checker 13 is controlled so as to detect an error by using these data and the ECC code read accompanying therewith. When data for one sector is read, the CPU 15 checks the ECC generator / checker 13 to check for data errors (step 206). If no error is detected, or if correction is possible even if detected, data is transferred from the data buffer 11 to the host system. If an uncorrectable error is detected, data transfer to the host system is not performed, and the CPU 15 assigns a code indicating that an error has occurred in the status register 8 in the host interface 3 to the error register 9. Is set to a code indicating the content of the error, the host system is notified that the execution of the instruction has been terminated abnormally, and the process is terminated (steps 207 to 210).

 FIG. 6 is a flowchart showing a procedure for transferring data from the data buffer to the host system. The CPU 15 sets the start address of the area where the data read out in the data buffer 11 is stored as a read address from the buffer (steps 301 and 302), and the control logic 12 stores data for one sector in the host system. Command to transfer. The control logic 12 controls the data buffer 11 and the host interface 3 to transfer one sector of data to the host system (step 303). When this is completed, the address register 5 is advanced by one sector, and the count register 6 1 is subtracted and the CPU 15 is notified that the transfer has been completed. As long as there is data to be transferred to the host system, the CPU 15 repeats this control. When all of the read data has been transferred, the CPU 15 sets a code indicating that there is no error in the status register 8 in the host interface 3, notifies the host system that the execution of the instruction has ended, and ends the processing. .

 7 and 8 are flowcharts showing a procedure for writing data into the EEPROM module 1. The CPU 15 determines the block on the EEPROM module 1 to which the host system is to write from the start address set in the host interface 3 (step 401). If the number of unused pages in the block of the EEPROM module 1 indicated by the host system is less than the number of pages to be written and the request from the host system does not rewrite all of the data in this block, rewrite in the block Data that cannot be read is read into the data buffer (steps 402 to 404). The procedure for reading data from the EEPROM to the data buffer 11 has been described with reference to the flowchart of FIG. The processing of FIG. 5 is repeated until all of the data in the block that is not overwritten is read into the buffer. Unless the number of unused pages in the block is equal to or greater than the number of pages to be written, block erasure is performed thereafter (step 405). Next, a write data transfer from the host system to the data buffer 11, a data write process from the data buffer 11 to the EEPROM module 1 and an error process, etc., which will be described in detail later, are executed. Initialization is performed (steps 406 to 411).

 FIG. 9 shows a procedure for transferring write data from the host system to the data buffer. The CPU 15 sets the data buffer 11 to the write mode (step 501), and sets an address on the data buffer 11 in which data transferred from the host system is stored as a write address to the buffer (step 502). Thereafter, the control logic 12 is instructed to transfer data for one sector from the host system. The control logic 12 controls the data buffer 11 and the host interface 3 to receive data for one sector from the host system, and when this is completed, notifies the CPU 15 that the transfer has been completed (step 503). The process of FIG. 9 is continued as long as data to be transferred from the host system remains and data for the block to be written to the EEPROM module 1 in the data buffer 11 is insufficient. When the transfer from the host system is completed, the CPU 15 refers to the pointer of the page management table of the block corresponding to the start address set in the host interface 3 and 1 stored in the data buffer 11 as described above. The page position of the corresponding block on the EEPROM module 1 where the data for the page is to be written is determined, and writing is performed.

 FIG. 10 is a flowchart showing a procedure for writing one page of data in the data buffer to the EEPROM module. The CPU 15 initializes the EEPROM module 1 and the data buffer 11 if necessary (steps 601 and 602), and then sets the head address of the page to be written in the address generator 14 (step 603). Sets the start address of the data to be written as the read address of the buffer (step 604). Then, a command is sent to the control logic 12 to execute a predetermined sequence for writing data. The control logic 12 sets the multiplexer 10 so that the write data from the data buffer 11 flows to the EEPROM module 1, and writes the data while incrementing the contents of the address generator 14 (step 605). Further, the ECC generator / checker 13 is controlled to generate an ECC code from these data, and this code is recorded together with the data (step 606). The process of FIG. 10 is continued while incrementing the pointer of the page management table until a write error occurs or data to be written to the block is finished. If data writing cannot be performed normally, necessary error processing is performed, and writing is performed again (steps 607 and 608). When writing is completed normally, the contents of the page management table are updated. When all the data requested by the host system has been recorded, or when the process is interrupted because recovery from an error is impossible, the CPU 15 sets a predetermined code in the status register 8 in the host interface 3 and stores it in the host system. Notify that the execution of the instruction is complete.

 In this embodiment, the EEPROM module is controlled by a controller operable in parallel with the host system via the host interface. However, the EEPROM module is controlled directly by the CPU of the host system. You may take it.

(Second Embodiment)
FIG. 11 is a block diagram showing a nonvolatile semiconductor memory device according to the second embodiment of the present invention. The CPU 15 accesses the EEPROM module 1 through the interface 25. In accessing, a buffer 30 provided in a part of the RAM 26 is used. If the EEPROM module 1 is composed of a 4 Mbit NAND type EEPROM, one block is 4 kbytes, so the size of the buffer 30, that is, the input / output unit is 4 kbytes. A portion corresponding to 31 to 38 in the buffer 30 is a portion corresponding to a page in the block of the NAND type EEPROM, but this device does not handle it as independent data.

 First, consider a case where a part of data in a certain block 2 in the EEPROM module 1 is rewritten. Since the data of the portion of block 2 that cannot be rewritten must be left, it must be read in advance. However, in this apparatus, since the access unit is one block, all the data of block 2 is transferred to the buffer 30. Next, data is rewritten on the buffer 30, and at the same time, the block 2 of the EEPROM module 1 is erased. Then, the contents of the buffer 30 are written for one block in order from the page on the source side.

 Next, consider the case where the contents of block 2 are invalidated and only data for three pages is written. In this case, since the data of block 2 is discarded, there is no need to read it in advance. Block 2 is immediately erased. If it is assumed that data for three pages is written at the positions of pages 31 to 33, the CPU 15 first sets data in this portion. At this time, the data when the EEPROM module is accessed before this access remains in the buffers 34 to 38 in the buffer 30 as they are. Therefore, if the data in the buffer 30 is written to the block 2 as it is, the contents of the pages 34 to 38 containing the originally meaningless data are verified and written as they are, and wasted time is wasted. Therefore, prior to writing to the block 2, the CPU 15 sets “1”, which is data at the time of erasing the EEPROM module, in the buffers 34 to 38 in the buffer 30. As described above, in the present embodiment, when data is written, initialization is performed so that all the data in the area where no valid data exists in the buffer 30 is the same as the data in the erased state. And unnecessary stress on the oxide film of the NAND type EEPROM is avoided.

 In the present embodiment, the EEPROM module 1 is directly controlled by the CPU 15 on the bus 27 via the interface 25. However, the EEPROM module 1 is interposed between the interface 25 and the EEPROM module 1 in parallel with the CPU 15. It may take the form of being controlled by an operable controller. In addition, the present embodiment can be variously modified and used without departing from the gist thereof.

1 is a block diagram showing a nonvolatile semiconductor memory device according to a first embodiment of the present invention. It is a figure which shows the structure of the page management table in 1st Embodiment. It is a figure for demonstrating operation of the said page management table. 3 is a flowchart for explaining a process of reading data from an EEPROM module in the first embodiment. 4 is a flowchart for explaining a process of reading data from the EEPROM module to the data buffer in the first embodiment. 4 is a flowchart for explaining read data transfer processing from the data buffer to the host system in the first embodiment. 4 is a flowchart for explaining a process of writing data to the EEPROM module in the first embodiment. 4 is a flowchart for explaining a process of writing data to the EEPROM module in the first embodiment. 4 is a flowchart for explaining a write data transfer process from the host system to the data buffer in the first embodiment. 4 is a flowchart for explaining a process of writing data in a data buffer to an EEPROM module in the first embodiment. It is a block diagram which shows the non-volatile semiconductor memory device which concerns on 2nd Embodiment of this invention. It is an equivalent circuit diagram showing one NAND cell of the EEPROM. It is an equivalent circuit diagram showing a memory cell array of EEPROM. It is a figure for demonstrating the write-in operation | movement of NAND type EEPROM.

Explanation of symbols

1 EEPROM module (memory means)
2 ... Block 3 ... Host interface 4 ... Data register 5 ... Address register 6 ... Count register 7 ... Command register 8 ... Status register 9 ... Error register 10 ... Multiplexer DESCRIPTION OF SYMBOLS 11 ... Data buffer 12 ... Control logic 13 ... ECC generator / checker 14 ... Address generator 15 ... CPU (control means)
16 ... Working RAM
17 ... Control program ROM
18 ... Area (block)
20 ... Page management table 21 as management means ... Point means pointer (point means)
22 ... Flag (area)
25 ... Interface 26 ... RAM
27 ... bus 30 ... buffers 31, 32, 33, 34, 35, 36, 37, 38 ... pages 101-105, 201-210, 301-303, 401-411, 501-503, 601-608 ... Steps

Claims (2)

A non-volatile semiconductor memory device connected to a host for recording data,
A NAND type EEPROM having a memory cell array divided into blocks composed of a plurality of pages;
Information for specifying a physical block to be written corresponding to a logical page specified by the host and stored in the NAND type EEPROM, and the most source side in the block with respect to the NAND type EEPROM A non-volatile semiconductor memory device comprising: a management table including a pointer used for sequentially writing data from the physical page.   2. The nonvolatile semiconductor memory device according to claim 1, wherein data supplied from the host and an ECC code corresponding to the data are written in the NAND type EEPROM.

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