JP4045011B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device technology, and more particularly to a technology effective when applied to a semiconductor memory device such as a flash EEPROM (flash memory) having a memory array in which bit lines have a hierarchical structure.
[0002]
[Prior art]
For example, as a technique studied by the present inventors, in a DINOR (DIvided bit line NOR) type as an example of a flash memory having a memory array in which bit lines have a hierarchical structure, an X decoder for selecting a word line, a main bit line In addition to the Y decoder for selecting a sub-bit line, a select gate decoder for selecting a sub-bit line is required. Since the output line of the select gate decoder runs in parallel with the word line, the X decoder and the select gate decoder are connected to the memory array. In general, a technique for arranging them in the same direction is known.
[0003]
As a technology relating to such a semiconductor memory device such as a flash memory, for example, a technology described in “Advanced Electronics I-9 Ultra LSI Memory” P23 to P28 issued on November 5, 1994, published by Bafukan Co., Ltd. Is mentioned.
[0004]
[Problems to be solved by the invention]
In the flash memory as described above, for example, as shown in FIG. 10, the X decoder XD and the select gate decoder SD are in the same direction with respect to the memory cell block BLK of the memory array MA, that is, on both sides of the memory array MA. Therefore, the power supply wiring for the decoder and the signal wiring L are arranged on both sides of the memory array MA, resulting in an increase in layout area. In addition, since the parasitic capacitance increases, the power consumption can be increased.
[0005]
Accordingly, an object of the present invention is to devise the arrangement of the X decoder and the select gate decoder with respect to the memory array in which the bit lines have a hierarchical structure, thereby preventing an increase in layout area and further suppressing an increase in power consumption. A semiconductor storage device such as a memory is provided.
[0006]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0007]
[Means for Solving the Problems]
Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
[0008]
That is, a semiconductor memory device of the present invention includes a memory array having bit lines in a hierarchical structure, an X decoder for selecting a word line of the memory array, a Y decoder for selecting a main bit line, and a select gate for selecting a sub bit line. In the configuration having the decoder, the X decoder and the select gate decoder are arranged on the same side with respect to the memory array.
[0009]
In this configuration, an X decoder is disposed near the memory array, and a select gate decoder is disposed outside the memory array. Further, the output line of the select gate decoder is disposed where the regularity of the arrangement of the X decoder is lost due to the select gate. It is supplied to the memory array through the decoders.
[0010]
Further, an address buffer and a predecoder are arranged outside the select gate decoder, and a signal line area for sharing a signal line is provided between the X decoder and the select gate decoder.
[0011]
The drive circuit for the source line and well feed line of the memory array is arranged at the same place as the select gate decoder, and the source line and well feed line are separated from the memory cell block of the memory array, and the regularity of the X decoder is At the point where it disappears, it is supplied to the memory array through the X decoder.
[0012]
In particular, the present invention is applied to a semiconductor memory device having a memory array in which bit lines of a DINOR type or the like have a hierarchical structure such as a flash memory.
[0013]
Therefore, according to the semiconductor memory device, for example, the array size of a DINOR type flash memory can be reduced. As a result, the cost can be reduced and the yield can be improved by reducing the chip size. Further, power consumption can be reduced by reducing the wiring length.
[0014]
This is because by disposing the X decoder and the select gate decoder on the same side with respect to the memory array, there is no power supply wiring or signal wiring between the decoders, and the chip size is reduced. This increases the number of chips acquired per wafer and improves the yield, thereby reducing the cost. Further, since the parasitic capacitance of the signal wiring is reduced, power consumption can be reduced.
[0015]
In particular, it is effective for DINOR type flash memories, and can be applied to DRAMs, SRAMs, FRAMs, etc., in which bit lines have a hierarchical structure, and can be applied to embedded products.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the same members are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.
[0017]
(Embodiment 1)
1 is a block diagram showing a semiconductor memory device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing an outline of a memory array and its peripheral circuits in the semiconductor memory device of the present embodiment. FIG. 4 (a) and 4 (b) are plan views and cross-sectional views showing the relationship between the memory cell block and the well layer, and FIGS. 5 (a) and 5 (b) show the structure of the memory cell. FIG. 6 is a characteristic diagram showing a multi-valued memory cell, and FIG. 7 is a block diagram showing another example of dividing the memory cell block.
[0018]
First, the configuration of the semiconductor memory device of this embodiment will be described with reference to FIG.
[0019]
The semiconductor memory device of the present embodiment is a DINOR type flash memory, for example, and includes a memory array MA composed of a plurality of memory cells having bit lines in a hierarchical structure, and an X decoder XD for selecting a word line of the memory array MA. A Y decoder YD for selecting a main bit line, a select gate decoder SD for selecting a sub bit line, a Y gate YG, a sense amplifier SA, a write control circuit WC, an X predecoder XPD, a Y predecoder YPD, an address buffer AB, It has a general configuration such as an I / O buffer I / OB, a power supply circuit PC, and a control circuit CC, and is formed on one semiconductor chip by a known semiconductor manufacturing technique.
[0020]
The memory array MA is divided into two memory cell blocks BLK0 and BLK2 as shown in FIGS. 2 and 3, for example, and the memory cells MC have a DINOR type connection in which the bit lines have a hierarchical structure. In particular, in the present embodiment, an X decoder XD is arranged on the same side (left side in FIG. 2) with respect to each memory cell block BLK of the memory array MA, and a select gate decoder SD is arranged outside the source line SL. The drive circuit for the well feed line WELL is also arranged in the select gate decoder SD on the same side. Further, the select gate line SG passes between the X decoders XD when the regularity of the X decoder XD is lost by the select gate, and the source line SL and the well power supply line WELL are separated by the memory cell block BLK. They are arranged between the X decoders XD where the regularity of the X decoder XD is lost.
[0021]
Each memory cell block BLK of the memory array MA is divided into two in units of a predetermined number of word lines W which are the outputs of the X decoder XD. Further, a connection method is adopted in which one main bit line MBL connected to the selection MOS transistor of the Y gate YG is shared by two sub bit lines SBL arranged one on each side. The memory cell MC connected to one of the sub bit lines SBL is selected via the selection MOS transistor of the select gate by the output of the select gate decoder SD. The main bit line MBL is selected by controlling the selection MOS transistor of the Y gate YG by a column selection signal which is an output of the Y decoder YD.
[0022]
In this memory array MA, the main bit line MBL is arranged across the divided memory cell blocks BLK. Each memory cell block BLK is supplied with a source line SL and a well power supply line WELL from a select gate decoder SD. These word lines W, main bit lines MBL, sub-bit lines SBL, source lines SL, and well power supply lines WELL are arranged such that the word line direction is the first metal wiring layer, bit line in order to loosen the wiring pitch in the bit line direction, for example. Although the direction is formed in the second metal wiring layer, this may be reversed.
[0023]
In one memory cell block BLK0, the memory cell MC connected between the word lines W00 to W0m and the sub bit lines SBL00 and SBL01 arranged on both sides of the main bit line MBL0 is connected to the word line by the X decoder XD00. W00 to W0m are selected, the main bit line MBL0 is selected by the Y decoder YD, one sub-bit line SBL01 is selected via the select gate line SG00 by the select gate decoder SD00, and the other select gate line SG01 is selected. Thus, the other sub-bit line SBL00 is selected. As a result, the read operation, the write operation, and the erase operation of all the memory cells MC connected to the arbitrarily selected word lines W00 to W0m and the sub bit lines SBL00 and SBL01 via the main bit line MBL0 are performed.
[0024]
During the read operation, any word line W00 to W0m is selected by the X decoder XD00, the main bit line MBL0 is selected by the Y decoder YD, and the sub bit lines SBL00 and SBL01 are selected by the select gate decoder SD. Designate memory cell MC. The data of the memory cell MC is read to the I / O line I / O, amplified by the sense amplifier SA, and then output from the I / O buffer I / OB. The write operation is performed by designating an arbitrary memory cell MC by selecting the word lines W00 to W0m, the main bit line MBL0, and the sub bit lines SBL00 and SBL01, and from the write control circuit WC through the I / O line I / O. Data can be written to the MC. The same applies to the other memory cell block BLK1, and the blocks related to the word lines W10 to W1m and the main bit line MBL1.
[0025]
In this memory array MA, for example, as shown in FIG. 4, a block well layer 11 is separated for each memory cell block BLK on a substrate 10, and this isolation region is a substrate isolation well layer 12. Lines are connected. As shown in FIG. 4B showing this cross section, each memory cell block BLK of the memory array MA is formed in each block well layer 11 on the separated substrate 10. The gap formed between the block well layers 11 becomes a region where regularity is lost, and the source line SL and the well power supply line WELL are passed as the substrate isolation well layer 12.
[0026]
Each memory cell MC of the memory array MA includes a source region 13 formed of an N-type diffusion layer and a P-type block well layer 11 on a substrate 10 made of single-crystal P-type silicon, for example, as shown in FIG. A drain region 14 is formed, and a tunnel insulating film 15, a floating gate 16, an interlayer insulating film 17, and a control gate 18 are sequentially stacked on the main surface, and one flash erasing type nonvolatile memory cell MC is formed by one transistor. It is configured. The gate electrode, the source electrode, and the drain electrode are assigned to the memory cell MC so as to be drawn from the control gate 18, the source region 13, and the drain region 14, respectively.
[0027]
For example, at the time of erasing, as shown in FIG. 5A, a positive high voltage (+ 12V) is applied to the control gate 18, a negative high voltage (-11V) is applied to the block well layer 11 and the source region 13, respectively. The region 14 is biased by floating, and electrons are injected into the floating gate 16. This increases the threshold value of the memory cell MC. At the time of writing, as shown in FIG. 5 (b), a negative high voltage (-11V) is applied to the control gate 18 and a positive voltage (+ 8V) is applied to the drain region 14, and the block well layer 11 has 0V and source. The region 13 is biased by floating and emits electrons from the floating gate 16. As a result, the threshold value of the memory cell MC is lowered. At the time of reading, 1-bit data is output for each memory cell MC of “1” corresponding to the high threshold voltage and “0” corresponding to the low threshold voltage.
[0028]
Further, this memory cell MC can be a multi-value storage memory cell MC of 2 bits or more per memory cell MC. For example, as shown in FIG. 6, when storing 4 bits as 4 values, the threshold value at the time of erasing is set as the reference voltage EV, and the threshold value at the time of writing is set as the reference voltages P1, P2 and P3. When reading, the threshold voltage is “11” of level 0 when the threshold voltage is lower than the reference voltage R1 at the time of reading, “10” of level 1 when the threshold voltage is higher than the reference voltage R1 and lower than the reference voltage R2, and the reference voltage is higher than the reference voltage R2. When the voltage is less than R3, data of level 2 is output, and when the voltage is higher than the reference voltage R3, data of level 3 is output. As described above, by setting the threshold values at the time of erasing and writing at a plurality of levels, a multi-value memory cell can be obtained.
[0029]
As described above, in the DINOR type flash memory, the select gate line SG is arranged in parallel with the word line W, and the select gate line SG needs to be selectively driven. Further, it is necessary to selectively drive the source line SL and the well power supply line WELL as described in the operation of the flash memory of FIG. In the conventional DINOR type flash memory, as shown in FIG. 10, the X decoder XD and the select gate decoder SD are arranged on both sides of the memory array MA, so that the power supply wiring and the signal wiring are arranged over both decoders. As a result, the layout area increases and the chip size increases.
[0030]
Therefore, in the embodiment of the present invention, as shown in FIG. 2, the X decoder XD and the select gate decoder SD are arranged on the same side with respect to the memory array MA, and the select gate line SG is the regularity of the X decoder XD. By eliminating the gap between the X decoders XD, the wiring can be passed without increasing the layout area. Further, the drive circuits for the source line SL and the well feed line WELL are also arranged on the same side, and the regularity of the X decoder XD is lost in the isolation region of the memory cell block BLK for the source line SL and the well feed line WELL. Therefore, the increase in layout area can be further suppressed by passing between the X decoders XD.
[0031]
Therefore, according to the semiconductor memory device of the present embodiment, by arranging the X decoder XD and the select gate decoder SD on the same side with respect to the memory array MA, there is no power supply wiring and signal wiring between the decoders, and the layout Since the increase in area can be suppressed, the chip size can be reduced. As a result, the number of chips acquired per wafer is increased and the yield is improved, so that the cost can be reduced. Further, since the parasitic capacitance of the signal wiring is reduced by reducing the wiring length, power consumption can be reduced. Furthermore, by arranging the drive circuits for the source line SL and the well power supply line WELL on the same side, an increase in layout area can be further suppressed.
[0032]
In the present embodiment, two sub bit lines SBL are arranged on each side of the main bit line MBL, but four or six sub bit lines SBL may be arranged. In this case, the number of selection MOS transistors of the sub bit line SBL increases. Accordingly, the gap between the X decoders XD is widened, the select gate decoder SD can be arranged between the X decoders XD, and the layout area can be further reduced. Further, drive circuits for the source line SL and the well power supply line WELL can also be arranged between the X decoders XD.
[0033]
Further, the memory array MA can be divided into four memory cell blocks BLK0 to BLK3 as shown in FIG. 7, for example, or in addition to the two memory cell blocks BLK. Also in this case, the main bit line MBL is arranged across all the memory cell blocks BLK divided into the memory cell blocks BLK.
[0034]
(Embodiment 2)
FIG. 8 is a block diagram schematically showing a memory array and its peripheral circuits in the semiconductor memory device according to the second embodiment of the present invention.
[0035]
The semiconductor memory device according to the present embodiment is a DINOR type flash memory as in the first embodiment, and includes a memory array MA, an X decoder XD, a Y decoder YD, a select gate decoder SD, a Y gate YG, and a sense amplifier SA. , A write control circuit WC, an X predecoder XPD, a Y predecoder YPD, an address buffer AB, an I / O buffer I / OB, a power supply circuit PC, a control circuit CC, and the like. The difference from the first embodiment is as follows. In addition to the X decoder XD and the select gate decoder SD, the arrangement of the address buffer AB and the X predecoder XPD is also considered.
[0036]
That is, in the present embodiment, as shown in FIG. 8, the X decoder XD, select gate decoder SD, address buffer AB, and X predecoder XPD are connected to the same side of the memory array MA, that is, to each memory cell block BLK. An X decoder XD on the same side, a select gate decoder SD on the outside, and an address buffer AB and an X predecoder XPD on the outside are arranged. From the address buffer AB, an X predecoder XPD and an X decoder XD, and a select gate decoder Since the wiring length of the signal wiring to the memory array MA via the SD can be reduced, it is effective for increasing the access speed and reducing the chip size.
[0037]
Therefore, according to the semiconductor memory device of the present embodiment, in addition to the X decoder XD and the select gate decoder SD, the address buffer AB and the X predecoder XPD are arranged on the same side with respect to the memory array MA. Since the chip size can be reduced, the number of chips acquired per wafer is increased and the yield is improved, so the cost can be reduced and the parasitic capacitance of the signal wiring is reduced by reducing the wiring length. The power can be reduced, and the access speed can be increased.
[0038]
(Embodiment 3)
FIG. 9 is a block diagram showing an outline of the memory array and its peripheral circuit in the semiconductor memory device according to the third embodiment of the present invention.
[0039]
The semiconductor memory device of the present embodiment is a DINOR type flash memory as in the first and second embodiments, and includes a memory array MA, X decoder XD, Y decoder YD, select gate decoder SD, Y gate YG, sense It comprises an amplifier SA, a write control circuit WC, an X predecoder XPD, a Y predecoder YPD, an address buffer AB, an I / O buffer I / OB, a power supply circuit PC, a control circuit CC, and the like. The difference is that the arrangement of signal lines between the X decoder XD and the select gate decoder SD is also taken into consideration.
[0040]
That is, in the present embodiment, as shown in FIG. 9, a signal line region ADD is provided between the X decoder XD and the select gate decoder SD, and some signals are generated by both the X decoder XD and the select gate decoder SD. The line can be shared, which is effective in reducing the parasitic capacitance of the signal line.
[0041]
Therefore, according to the semiconductor memory device of the present embodiment, X decoder XD, select gate decoder SD, address buffer AB and X predecoder XPD are arranged on the same side with respect to memory array MA, and X decoder XD and select gate are arranged. By providing the signal line region ADD with the decoder SD, the chip size can be reduced, so that the number of chips acquired per wafer is increased and the yield is improved, so that the cost can be reduced and further. Since the parasitic capacitance of the signal wiring is reduced by reducing the wiring length, power consumption can be reduced.
[0042]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
[0043]
For example, in the above embodiment, the DINOR type flash memory has been described. However, the present invention is not limited to this, and a flash memory of an AND type, a part of the NOR type, or a DRAM in which bit lines have a hierarchical structure. It can be widely applied to other semiconductor memory devices such as SRAM and FRAM, and embedded products.
[0044]
【The invention's effect】
Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
[0045]
(1) The X decoder and the select gate decoder are arranged on the same side of the memory array, the X decoder is arranged near the memory array, and the select gate decoder is arranged outside the memory array. Since the signal wiring is eliminated, the chip size can be reduced.
[0046]
(2). Since the chip size is reduced by (1), the number of chips acquired per wafer is increased and the yield is improved, so that the cost can be reduced.
[0047]
(3) The output line of the select gate decoder is supplied to the memory array through the space between the X decoders when the regular arrangement of the X decoder is lost by the select gate. Since the parasitic capacitance of the signal wiring is reduced, power consumption can be reduced.
[0048]
(4) Since the address buffer and predecoder are arranged outside the select gate decoder, the wiring length of the signal wiring can be reduced, so that the access speed can be increased and the chip size can be reduced.
[0049]
(5) Since a signal line area for sharing a signal line is provided between the X decoder and the select gate decoder, a part of the signal line can be shared, so that the parasitic capacitance of the signal line can be reduced. Reduction is possible.
[0050]
(6). The drive circuit of the source line and well feed line of the memory array is arranged at the same place as the select gate decoder, and the source line and well feed line are separated from the memory cell block of the memory array, and the rules of the X decoder Since the parasitic capacity of the signal wiring is reduced by reducing the wiring length, the power consumption can be reduced by supplying the memory array through the X decoder at a place where the characteristics are lost.
[0051]
(7) According to the above (1) to (6), in a semiconductor memory device such as a flash memory having a memory array in which bit lines such as DINOR type have a hierarchical structure, an X decoder, a select gate decoder, an address buffer for the memory array By devising the arrangement of the predecoder and the like, it is possible to prevent an increase in layout area, reduce costs, improve yield, and reduce power consumption.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a semiconductor memory device according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram schematically showing a memory array and its peripheral circuits in the semiconductor memory device according to the first embodiment of the present invention.
FIG. 3 is a circuit diagram showing in detail a memory array in the semiconductor memory device according to the first embodiment of the present invention;
4A and 4B are a plan view and a cross-sectional view showing the relationship between a memory cell block and a well layer in the semiconductor memory device according to the first embodiment of the present invention.
5A and 5B are cross-sectional views showing the structure of a memory cell and a bias state at the time of erasing and writing in the semiconductor memory device according to the first embodiment of the present invention.
FIG. 6 is a characteristic diagram showing a multilevel memory cell in the semiconductor memory device according to the first embodiment of the present invention;
FIG. 7 is a block diagram showing another example of dividing the memory cell block in the semiconductor memory device according to the first embodiment of the present invention;
FIG. 8 is a block diagram showing an outline of a memory array and its peripheral circuit in a semiconductor memory device according to a second embodiment of the present invention;
FIG. 9 is a block diagram showing an outline of a memory array and its peripheral circuit in a semiconductor memory device according to a third embodiment of the present invention;
FIG. 10 is a block diagram showing an outline of a memory array and its peripheral circuits in a semiconductor memory device as a premise of the present invention.
[Explanation of symbols]
MA memory array XD X decoder YD Y decoder SD select gate decoder YG Y gate SA sense amplifier WC write control circuit XPD X predecoder YPD Y predecoder AB address buffer I / OB I / O buffer PC power supply circuit CC control circuit BLK memory cell Block MC Memory cell W Word line MBL Main bit line SBL Sub bit line SG Select gate line SL Source line WELL Well power supply line I / O I / O line ADD Signal line region 10 Substrate 11 Block well layer 12 Substrate isolation well layer 13 Source region 14 Drain region 15 Tunnel insulating film 16 Floating gate 17 Interlayer insulating film 18 Control gate

Claims (7)

A semiconductor memory device having a memory array having bit lines in a hierarchical structure, an X decoder for selecting word lines of the memory array, a Y decoder for selecting main bit lines, and a select gate decoder for selecting sub bit lines. ,
The X decoder and the select gate decoder are arranged on the same side with respect to the memory array, wherein the X-decoder as close to the memory array is arranged, it is arranged the select gate decoder on the outside Rutotomoni,
A first connection point where the first sub-bit line and the second sub-bit line are arranged substantially in parallel with the main bit line, and the first sub-bit line and the main bit line are connected to each other. A semiconductor memory device , wherein a sub-bit line and a second connection point to which the main bit line is connected are provided so that currents flowing through the sub-bit lines are opposed to each other . The semiconductor memory device according to claim 1,
The output line of the select gate decoder is supplied to the memory array through the X decoder when the regularity of the arrangement of the X decoder is lost by the select gate. . The semiconductor memory device according to claim 1,
A semiconductor memory device, wherein an address buffer and an X predecoder are arranged outside the select gate decoder. The semiconductor memory device according to claim 1,
A semiconductor memory device, wherein a signal line region for sharing a signal line is provided between the X decoder and the select gate decoder. A semiconductor memory device having a memory array having bit lines in a hierarchical structure, an X decoder for selecting word lines of the memory array, a Y decoder for selecting main bit lines, and a select gate decoder for selecting sub bit lines. ,
The X decoder and the select gate decoder are disposed on the same side of the memory array and the X decoder is disposed on a side closer to the memory array ;
A first sub-bit line and a second sub-bit line are arranged substantially in parallel on the main bit line, and a connection point between the first sub-bit line and the main bit line is between the second sub-bit line and the main bit line. A semiconductor memory device, wherein the semiconductor memory device is disposed so as to face a connection point via a word line commonly connected to memory cells connected to each sub bit line . 6. The semiconductor memory device according to claim 5, wherein
Source line and U E le feeder lines of the memory array, the second memory cell blocks that is connected to the first memory block and the second X-decoder connected to the first X-decoder of the memory array A semiconductor memory device, wherein the memory array is supplied to the memory array. The semiconductor storage device according to claim 1, wherein
The semiconductor memory device is a flash EEPROM.

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