JP4043459B2 - Signal transmission system, receiver circuit of the signal transmission system, and semiconductor memory device to which the signal transmission system is applied - Google Patents

Description

  The present invention relates to a signal transmission system, a receiver circuit of the signal transmission system, and a semiconductor memory device to which the signal transmission system is applied, and in particular, transmission of signals between LSI chips or a plurality of signals in one LSI chip. The present invention relates to a signal transmission system that transmits signals between elements and constituent circuits, a receiver circuit of the signal transmission system, and a semiconductor memory device to which the signal transmission system is applied.

  In recent years, signal transmission between LSI (Large Scale Integration Circuits), for example, signal transmission between DRAM (Dynamic Random Access Memory) and a processor, or signal transmission between each component circuit in one semiconductor integrated circuit (chip) Is required to be performed at high speed.

  Traditionally, the performance of DRAMs and processors has greatly improved over time. That is, while the processor has been greatly improved in performance in terms of high speed, the DRAM has been greatly improved in performance mainly in terms of increased capacity. However, the increase in operation speed in DRAM is not as great as the increase in capacity. As a result, the speed gap between the DRAM and the processor becomes large, and in recent years, this speed gap has become an obstacle to improving the performance of computers. is there. Further, not only signal transmission between these chips but also signal transmission speed between elements and constituent circuits in one LSI chip (semiconductor integrated circuit) with the increase in size of the chip is a significant limitation on chip performance. It has become a factor.

  By the way, as a signal transmission method between a processor and a DRAM (DRAM module), those which are expected to spread in the past several years include SSTL (Series-Stub Terminated Logic), Rambus channel, and other small amplitudes. Signal standards are known.

  In SSTL and Rambus channels (or similar small-amplitude signal systems), the termination of the signal transmission path (transmission line) is terminated with a resistance close to the characteristic impedance of the line, thereby suppressing reflection at the termination and enabling high-speed signal transmission. It is possible. Further, by setting the signal to have a small amplitude, the power for charging and discharging the transmission line is reduced, and low power transmission is possible even at high speed operation.

FIG. 1 is a block diagram schematically showing an example of a conventional signal transmission system, and shows an example of a bus system to which SSTL is applied. In FIG. 1, reference numeral 101 is a driver circuit, 102 is a signal transmission line, 103 and 104 are termination resistors (R _T ), 151 to 153 are stub resistors (Rs), 161 is a processor (controller), and 162 and 163 Indicates a DRAM module. Reference sign _VTT indicates an intermediate potential (power supply line) between the power supply voltage Vcc and the ground voltage Vss.

As shown in FIG. 1, in the conventional bus system, for example, termination resistors 103 and 104 are provided at both ends (termination) of the transmission line, respectively, and are connected to a power supply line _VTT having an intermediate potential. The processor 161 and the DRAM modules 162 and 163 are connected to the transmission line 102 via stub resistors 151, 152, and 153 provided in the middle of the transmission line 102, respectively.

Here, the characteristic impedance of the transmission line 102 is about 50 ohms, and the resistance values of the termination resistors 103 and 104 are set to about 50 ohms, which is the same as the characteristic impedance Z _{0 of} the line. That is, the terminating resistors 103 and 104 provide a total resistance of 25 ohms at both ends, and the driver circuit drives this resistor to generate a signal voltage. Note that the output impedance of the driver circuit 101 is set to be small in order to have a large driving capability, that is, the transistors constituting the driver circuit 101 are configured by transistors having a large size.

  Specifically, for example, when considering a bus system to which SSTL is applied, since the signal amplitude needs to be at least 400 mV, the driver circuit needs to pass a current of about 16 mA. It is necessary to pass a double current of about 32 mA.

As described above, for example, in a bus system (signal transmission system) to which SSTL is applied, high-speed signal transmission is possible by a matching termination (termination resistor R _T ) and a stub resistor (Rs), and power consumption is also small amplitude signal. Is smaller than the conventional one. However, in the future, it is required to further increase the signal transmission band between the DRAM and the processor, and in spite of this, the power consumption of the entire device is required to be the same or lower than the present level. The signal transmission method is required. That is, for example, consuming 32 mA of current per bit is an unacceptable value in the future when the bus width increases to 64 bits or 128 bits.

  An object of the present invention is to provide a signal transmission system capable of high-speed operation with much lower power consumption in view of the problems of the above-described technology.

According to the present invention (fifth aspect of the present invention), there is provided a signal transmission system for performing signal transmission between a plurality of circuit blocks via a signal transmission path, the signal transmission system comprising a receiver circuit, The receiver circuit includes a first switch provided in a reference potential line, a first capacitor connected to the first switch, a second switch provided in the signal transmission path, and a first terminal connected to the first capacitor. A second capacitor having a second end connected to the second switch, a third switch, an input connected to the first capacitor and the second capacitor, and the input and the output being A logic determination unit connected via the third switch, wherein the signal transmission path is in a first state in which the first switch is off, the second switch is on, and the third switch is off. The first signal state of It judged by part, held in the second state where the first switch and the second switch ON becomes the third switch is turned on off, on the capacity of the first signal state of the signal transmission path to the first and, thereafter, the first and the third switch switches the second switch is turned on off in the third state becomes off, enter the second signal state of the signal transmission path capacity to the second , signal transmission system, characterized by determining the second signal state by the logic determination unit Ru provided.

  According to the present invention, there is provided a semiconductor memory device comprising the complementary bus amplifier as a data bus amplifier, the complementary bus driver as a sense amplifier, and the complementary bus as a data bus. The data bus amplifier removes the intersymbol interference component in the data transmitted from the sense amplifier via the data bus, thereby continuously performing the data bus without performing precharge of the data bus at the time of data transfer. A semiconductor memory device characterized in that reading is performed is provided.

According to the present invention, there is provided a receiver circuit connected to a signal transmission line, a first switch provided on a reference potential line, a first capacitor connected to the first switch, and the signal transmission line. A second switch provided on the second capacitor, a first terminal connected to the first capacitor, a second terminal connected to the second switch, a third switch, and an input connected to the first capacitor. A logic determination unit that is connected to the capacitor and the second capacitor, and whose input and output are connected via the third switch, wherein the first switch is off and the second switch is on In the first state in which the third switch is turned off, the first signal state of the signal transmission path is determined by the logic determination unit, the first switch is turned on, the second switch is turned off, and the third switch is turned on. in the second state becomes on, before Holding the first signal state of the signal transmission path capacity to the first, then the first and the third switch switches the second switch is turned on off in the third state turned off, the signal a second signal state of the transmission path to input to the capacitor to the second, receiver circuit of the second signal state and judging by the logic determination unit Ru provided.

  According to the signal transmission system of the present invention (the fifth aspect of the present invention), high-speed data transfer can be performed without precharging the data bus. In addition, since data can be sent with less change in the level of the bus due to data per bit, power consumption of the bus can also be reduced.

  Hereinafter, embodiments of a signal transmission system according to the present invention, a receiver circuit of the signal transmission system, and a semiconductor memory device to which the signal transmission system is applied will be described with reference to the drawings.

FIG. 2 is a block diagram showing the principle configuration of a signal transmission system (bus system) to which the first embodiment of the present invention is applied. In FIG. 2, reference numeral 1 is a driver circuit, 2 is a signal transmission line, 3 and 4 are termination resistors (R _T ), 51 to 53 are stub resistors (Rs), 61 is a processor (controller), and 62 and 63 are DRAMs. Modules 7 and 7 indicate damping resistance (R _D ). Reference sign _VTT indicates an intermediate potential (power supply line) between the power supply voltage Vcc and the ground voltage Vss.

As shown in FIG. 2, in the bus system according to the first embodiment of the present invention, for example, termination resistors 3 and 4 are provided at both ends (termination) of the transmission line, respectively, and the intermediate potential power supply line V _TT is provided. It is connected. Here, the resistance value R _T of the termination resistors 3 and 4 is set to be larger than the characteristic impedance Z ₀ of the transmission line 2 (R _T > Z ₀ ). Further, the output impedance of the driver circuit 1 is set to be large, that is, the transistor constituting the driver circuit 1 is composed of a small size transistor.

  The processor 61 and the DRAM modules 62 and 63 are connected to the transmission line 2 via stub resistors 61, 62, and 63 provided in the middle of the transmission line 2, respectively. Furthermore, a plurality of damping resistors 7 are inserted in the transmission line 2.

That is, in the bus system (signal transmission system) according to the first embodiment of the present invention, (1) the termination resistance _RT is made larger than the characteristic impedance Z ₀ of the transmission line, and (2) the output impedance of the driver circuit is increased. And / or (3) If necessary, one or a plurality of damping resistors _RD are inserted in series in the transmission line to reduce power consumption (low power). Here, when the termination resistance _RT is increased, the power consumed at the termination is reduced with the same signal amplitude, and when the output impedance of the driver circuit is increased, the signal current is reduced and the driver circuit is driven. This will also reduce power consumption. Instead of inserting the damping resistor R _D in series with the transmission line, the transmission line itself can be made of a substance having resistance.

  However, when the power is reduced as described above, the frequency characteristics of the transmission line are deteriorated, and the inherent response time in which the voltage signal on the transmission line responds becomes long. For this reason, the signal voltage does not reach the original full amplitude during the code length T, and a large intersymbol interference term is generated, and there is a possibility that the signal cannot be detected by a normal method.

  Therefore, in the second embodiment of the present invention, a means for predicting intersymbol interference from a past signal for a receiver (receiver circuit of a signal transmission system) is used, and the currently received signal is the predicted intersymbol interference. By subtracting from the voltage, the signal is configured to detect a partial response.

  FIG. 3 is a diagram showing the relationship between the code length and response time in a conventional general signal transmission system.

  As shown in FIG. 3, in a conventional general bus system (signal transmission system), for example, the signal is predetermined until the signal reaches its full amplitude due to multiple reflection of the signal on the transmission line (bus). Takes time. Here, the response time τ is defined as, for example, the time until the signal voltage reaches 90% of the full amplitude. In the conventional general bus system, the transmission (transmission) of the signal on the transmission line is ensured. In order to do this, the response time τ is set to be sufficiently shorter than the length of the transmitted code (one symbol) T, that is, the code length T is set sufficiently longer than the response time τ (T >> τ). ). Specifically, in a conventional general bus system, for example, the code length T is set to about 2 to 3 times the response time τ (T≈2 to 3τ). When the response time τ is long, signal transmission is performed. Cannot be accelerated.

  On the other hand, in the second embodiment of the present invention, the response time τ is equal to or longer than the code length (one period of data) T to be transmitted, that is, the code length T is the response of the signal transmission path. It is set to be equal to or shorter than the time τ (T ≦ τ: for example, T≈0.3τ), and a partial response indicated by the transmitted signal during the code length T is detected. . Therefore, in the second embodiment of the present invention, signal transmission can be performed at high speed.

  FIG. 4 is a diagram showing the relationship between the code length and the response time in the signal transmission system of the present invention.

As shown in FIG. 4, for example, the code data to be transmitted is data “0” in periods P _n−2, P _{n−1, Pn + 1} , and data “1” in periods P _{n and} P _{n + 2.} In the present invention, for example, the transmitted code length T is set shorter than the response time τ. Therefore, for example, a signal of data “1” in the period P _n is not detected in a state in which the signal voltage after the response time τ is sufficiently increased, but is a time during which the signal voltage is changing (rising). It is detected within the range of T. As is apparent from FIG. 4, the signal voltage changes (period P _n ) when the data “0” becomes continuous after the data “0” and the data becomes “1” → “0” → ”. This is different from the signal voltage change (period P _{n + 2} ) when it becomes 1 ″, but in the present invention, the influence of the data change up to the previous time is also applied to the continuous change of various data. Except for this, a change in signal voltage (data signal) in the transmission line (bus) is actually captured.

  As described above, in the second embodiment of the present invention, the transmitted code length T is set to be equal to or shorter than the response time τ of the signal transmission path (T ≦ τ), and the transmitted signal has a code length. By detecting a partial response shown during T, signal transmission speed is increased.

  Note that intersymbol interference prediction (removal of influence of past data change; partial response detector (PRD)) is a past received signal when the circuit response is linear, as will be described later. Can be realized by weighted addition (linear decision feedback; decision feedback equalizer (DFE)) or the like (see FIG. 12 and FIG. 13), and a non-linear code When there is inter-interference, the magnitude of the interference is recorded in advance in the memory, and the interference term can be predicted by reading the memory using the past received signal sequence as an address (FIGS. 14 and 15). reference).

  The prediction of the intersymbol interference can also be performed using an analog value of the signal voltage received one clock before. This method gives the best prediction when the signal voltage response is expressed in a first order lag system.

That is, in the first-order lag system, the signal voltage V (nT) is n = 0, ± 1, ± 2,.
V (nT) = xV _TT + (1−x) V ((n−1) T) + x (V _inf −V _TT ) (1)
It is expressed.
However, the fact that x = 1−exp (−T / τ) is used.

Here, τ is the time constant (response time) of the circuit, V _inf is the signal voltage (full amplitude) when data “1” or “0” is sent for a sufficient length, and V _TT is the reference voltage Show. The reference voltage V _TT is Vcc / 2 when a symmetrical CMOS driver is used.

  In the above equation (1), the first and second terms are terms indicating intersymbol interference, and the third term is a net signal term. That is, it can be understood from the equation (1) that the intersymbol interference is obtained by storing the signal voltage one clock before and taking the linear sum of the signal voltage one clock before and the fixed reference voltage. The linear sum of the analog voltage storage and the fixed voltage can be easily generated by a circuit using a capacitor described below.

  FIG. 5 is a diagram showing a configuration example of a receiver circuit in the signal transmission system according to the present invention, and FIG. 6 is a diagram for explaining the operation of the receiver circuit of FIG. Here, FIG. 5A is a block circuit diagram of a partial response detection circuit (receiver circuit), and FIG. 5B is a circuit diagram showing an example of an auto-zero comparator in the partial response detection circuit of FIG. It is. FIG. 6A is a diagram showing the timing of each signal used in the partial response detection circuit, and FIG. 6B is an example of a change in voltage (signal voltage) on the transmission line accompanying a change in data. FIG.

As shown in FIG. 5A, the partial response detection circuit 8 includes auto-zero comparators 81 and 82, a DLL (Delay Locked Loop) circuit 83, and a selection circuit (MUX) 84. The auto-zero comparators 81 and 82 are respectively supplied with a reference voltage V _TT (Vcc / 2), an input voltage (signal voltage) Vin, and control signals φ 1 and φ 2 that are outputs of the DLL circuit 83. The selection circuit 84 selects and outputs (data output) the output signal of the auto-zero comparator 81 or 82 at a predetermined timing.

As shown in FIG. 5B, the auto-zero comparator 81 (82) includes two capacitors 815 and 816, a CMOS inverter 818, and switches 811 to 814 and 817. Then, the switches 811 to 814 are controlled by the control signals φ 1 and φ 2 to control the voltage applied to the capacitors 815 and 816 (reference voltage V _TT or signal voltage Vin) and the connection of the capacitors 815 and 816. Yes. The switch 817 is provided in parallel with the inverter 818 and is controlled to be turned on / off by a control signal φ1. Here, as is apparent from FIG. 6A, the control signals φ1 and φ2 are signals that instantaneously become high level in synchronization with the falling and rising timings of the clock CLK. In addition, the switches 811 to 814 and 817 can be configured using a transfer gate composed of two transistors or one switching transistor.

That is, first, the auto-zero comparator 81 (82) stores the signal voltages V ((n−1) T) and V _TT in the capacitors 815 and 816 by the control signal φ1 (timing when the signal φ1 becomes high level). At this time, the input / output of the inverter 818 is connected to perform an auto-zero operation. By this auto-zero operation, the input node of the inverter 818 becomes Von (a voltage obtained when the input / output of the inverter is short-circuited, and a threshold voltage at which the output of the inverter is switched from “0” to “1”). As a result, the charges Q1 and Q2 stored in the capacitors 815 and 816 are defined as C1 and C2, respectively.
Q1 = (V ((n-1) T) -Von) C1
Q2 = (V _TT −Von) C2
It becomes.

Next, after the control signal φ1 becomes low level, capacitors 815 and 816 are connected in parallel by the control signal φ2 (timing at which the signal φ2 becomes high level) to connect the input V (nT) to the input node of the inverter 818. Lead. At this time, the voltage V at the input node of the inverter 818 is determined by the law of charge conservation.
V = V (nT)-(Q1 + Q2) / (C1 + C2)
= V (nT) - (1 -x) V ((n-1) T) -xV TT + Von)
= X (V _inf −V _TT ) + Von (2)
It becomes.

  The right side of the equation (2) is obtained by subtracting the intersymbol interference term from the equation (1) described above (that is, a net signal) and adding the voltage Von. Therefore, since the output of the inverter 818 is inverted depending on whether the net signal is positive or negative, only the net signal can be correctly determined. That is, as shown in FIG. 6B, even when the data changes, the analog value of the signal voltage received one clock before is used to eliminate the influence of the past data change and detect the data signal. Can be done accurately.

  Here, in the partial response detection circuit 8 of FIG. 5A, the output (OUTc) of the two auto-zero comparators 81 and 82 is selected by the selection circuit 84 because the input signal (Vin ) Is performed every 2T, the two auto zero comparators are interleaved to perform the determination process every 1T. The operation (processing) by the control signals φ1 and φ2 described above is reversed between one auto-zero comparator 81 and the other auto-zero comparator 82.

  FIG. 7 is a block circuit diagram showing a configuration example of a signal transmission system to which the present invention is applied, and FIG. 8 is a diagram showing simulation results of signal waveforms in each memory block in the signal transmission system of FIG.

7, reference numeral 201 is a driver circuit, 202 (221 to 226) is a signal transmission path, 250 to 254 are stub resistors (Rs), 261 to 264 are memories (DRAM modules), and 207 is a damping resistor (R). _D ). Here, the transmission lines 221 and 226 have a characteristic impedance of 70Ω and a length of 10 mm, and the transmission lines 222 to 225 have a characteristic impedance of 70Ω and a length of 12.5 mm. Further, the resistance values of the stub resistors 250 to 254 are each 25Ω, and the resistance value of the damping resistor 207 is 7Ω. Here, the characteristic impedance of the transmission lines 222 to 225 (215) is set to 70Ω, which is connected to various circuits (memory 261 to 264, etc.) to the transmission line. This is because the characteristic impedance is effectively about 50Ω due to the influence of parasitic capacitance and the like.

  The driver circuit 201 includes a P-channel MOS transistor 211, an N-channel MOS transistor 212, a capacitor 213, an inductor 214, and a transmission line 215. Here, the capacitance of the capacitor 213 is 4 pF, the inductance of the inductor 214 is 2.5 nH, and the transmission line 215 has a characteristic impedance of 70Ω and a length of 15 mm. The gate widths of the transistors 211 and 212 are set to be as small as several tens of μm (for example, the gate width of the transistor 211 is set to 60 μm and the gate width of the transistor 212 is set to 30 μm). As a result, it is possible to eliminate intersymbol interference using the above-described equation (1). In addition, by placing a resistor (damping resistor 207) in series with the transmission line, the vibration behavior of the signal voltage is eliminated, and more accurate intersymbol interference removal (estimation of intersymbol interference components) can be performed. .

  That is, as shown in FIG. 8, as a result of the simulation under the above conditions, the change in the signal voltage (data “1”) in the memory “2” (262) and the memory “4” (264) is expressed by the equation V = P0exp (-td) It can be seen that the approximation is sufficient.

Note that, as indicated by parentheses in FIG. 7, termination resistors 203 and 204 (R _T ) may be provided at both ends of the signal transmission path 202. Here, for example, the impedance of the transmission line is set to 70Ω, the termination resistance R _T is set to a range of ∞ ≧ R _T ≧ 200Ω, the damping resistor R _D is set to a range of 7Ω ≧ R _D > 0Ω, and The stub resistance Rs is preferably set to about 25Ω.

  As described above, according to the signal transmission system of the first embodiment of the present invention, the termination resistance is made larger than the characteristic impedance of the signal transmission path, the output resistance of the driver circuit is increased, or the signal transmission path is connected in series. By providing a damping resistor, signal power can be greatly reduced. Specifically, for example, according to circuit simulation, power consumption can be reduced to about 1/4 of SSTL. Furthermore, according to the receiver circuit of the signal transmission system according to the second aspect of the present invention, the intersymbol interference generated in the signal transmission system is predicted and removed from the past signal, so that it is accurate even in high-speed operation. Data can be received (transmitted).

FIG. 9 is a block diagram showing a first embodiment of the signal transmission system according to the first mode of the present invention. In FIG. 9, reference numeral 301 is a driver circuit, 302 (321 to 325) is a signal transmission line, 303 and 304 are termination resistors (R _T ), 351 to 354 are stub resistors (Rs), and 361 to 364 are memory modules ( DRAM module) and 310 indicates a processor or controller (DRAM controller).

Resistance of the terminating resistor 303 and 304 for connecting both ends of the transmission line 302 to the power supply line V _TT (termination) is, for example, a 200 [Omega, to be sufficiently larger than the characteristic impedance of the transmission line 302 (about 50 [Omega) Is set. Furthermore, each of the memory modules 361 to 364 is connected to the transmission line 302 via stub resistors 351 to 354, respectively. Here, the potential of the power supply line V _TT, for example, is set to an intermediate potential (Vcc / 2) between the power supply voltage Vcc and ground voltage Vss.

  The driver circuit 301 is configured as a CMOS inverter including a P-channel MOS transistor 311 and an N-channel MOS transistor 312. Here, the gate width of the transistor 311 is configured to be 60 μm, for example, and the gate width of the transistor 312 is configured to be 30 μm, for example. That is, the gate width of the driver transistor in the first embodiment of the first mode is, for example, about 1/7 to 1/8 of the gate width of the transistor in the conventional low output impedance type driver circuit. Yes. Thereby, the output impedance of the driver circuit is set large.

  According to the specific simulation result of the first example of the first mode, for example, even at a high transfer rate of 533 MHz, the power consumption per bit is about 12 mW, and the consumption per bit in SSTL. Compared with the electric power of 50 mW or more, the electric power is ¼ or less.

  FIG. 10 is a block diagram showing a second embodiment of the signal transmission system according to the first mode of the present invention.

In the second embodiment of the signal transmission system shown in FIG. 10, the termination resistors 303 and 304 in the first embodiment of FIG. 9 are removed, and a damping resistor 307 (R _D ) is provided between the transmission lines 321 to 325 (302). It is configured to be provided in series. Here, the damping resistance 307 inserted in series with the transmission line 302 has a value of about 70Ω as a whole. The damping resistor 307 allows the response of the signal transmission system to be approximated by a first-order lag system, and it is possible to receive an accurate signal by removing intersymbol interference by a receiving circuit using capacitive coupling.

  As a unique effect of the second embodiment of the first mode, since no terminating resistor is provided (because it is not released), the consumption of DC power is eliminated, and data “1” or “0” is almost always consumed. The power consumption of a signal that takes only one value is substantially zero.

  FIG. 11 is a block diagram showing a third embodiment of the signal transmission system according to the first mode of the present invention.

The third embodiment of the signal transmission system shown in FIG. 11 is the same as that of the first embodiment of FIG. 9 except that a damping resistor 307 (R _D ) is provided in series between the transmission lines 321 to 325 (302). It is a thing. Here, the damping resistor 307 inserted in series in the transmission line 302 has a value of about 30Ω as a whole, and the termination resistors 303 and 304 are set to about 300Ω.

  That is, in the third embodiment of the first mode, both a terminating resistance of about 300Ω and a damping resistance of about 30Ω in total are provided. As a result, the vibrational behavior of the waveform can be suppressed almost completely while suppressing the attenuation of the signal transmitted on the line, and the stability of signal transmission can be improved.

  FIG. 12 is a block circuit diagram showing a first embodiment of the receiver circuit of the signal transmission system according to the second mode of the present invention. In FIG. 12, reference numeral 41 is a differential amplifier, 42 is a determination circuit, 43 is a shift register, 44 is a resistor, and 45 is a resistor ladder circuit.

  In the first embodiment of the receiver circuit shown in FIG. 12, a predictor for predicting intersymbol interference is provided, and the output (reference voltage: Vref) of the predictor is supplied to the reference voltage side (−) of the differential amplifier 41. The signal voltage Vin is input to the signal input side. As a predictor, a so-called decision feedback system (Decision Feedback: Decision Feedback Equalizer (DFE)) is used to hold the past 4 bits of digital signals (d4 to d1) in the shift register 43 and a resistance ladder 45 (non-linear). An intersymbol interference term is generated via a weighted AD converter.

  That is, the shift register 43 holds the data d4 that is 4 bits before, the data d3 that is 3 bits before, and the data d2 that is 2 bits before, and the data d1 immediately before (1 bit before), and the previous bit The voltage is supplied to the reference voltage side of the differential amplifier 41 via resistors 454 to 451 having resistance values corresponding to the influence of (data before 4 bits to data immediately before). Here, the resistance value of the resistor 454 is set to be large because the influence of the data of 4 bits before is small, and the resistance value of the resistor 451 is set to be small because the influence of the immediately preceding data is large. ing.

  In the differential amplifier 41, the signal voltage Vin is differentially amplified by the reference voltage Vref, and the determination circuit 42 determines the output of the differential amplifier 41, thereby determining the transmitted data (signal voltage Vin). To do.

  According to the first embodiment of the receiver circuit shown in FIG. 12, by storing a sufficiently long sequence of past received signals, not only a first-order lag system but also prediction of correct intersymbol interference for various responses (past The data can be output accurately by removing the influence of the data change.

  FIG. 13 is a block circuit diagram showing a second embodiment of the receiver circuit of the signal transmission system according to the second mode of the present invention.

  In the second embodiment of the receiver circuit shown in FIG. 13, the resistor 44 and the resistor ladder circuit 45 in the first embodiment of the second mode described above are replaced with capacitive coupling by capacitors 44 'and 45'. That is, in the second example of the second mode, the non-linear weighted A / D converter is realized by capacitive coupling, which is consumed in comparison with the first example of the second mode using the resistor ladder described above. There is an advantage that electric power can be reduced. Note that switches 461 to 464 are connected to the capacitors 451 ′ to 454 ′ so as to select the data of 4 bits previous to the previous data held in the shift register 43 and the ground potential (Vss). It has become. Further, a switch 47 is connected to the reference voltage side (−) of the differential amplifier 41.

  In the receiver circuit of FIG. 13, first, at the time of initialization, the switches 461 to 464 are connected to the ground potential side and the switch 47 is turned on. Next, after the switch 47 is turned off, the switches 461 to 464 are switched to the output side of the shift register 43, and the data immediately before held in the shift register 43 to the data before 4 bits (d1 to d4) The voltage is applied to one end of each of the corresponding capacitors 451 ′ to 454 ′. Here, the other ends of the capacitors 451 ′ to 454 ′ are commonly connected to the reference voltage side of the differential amplifier 41. Note that the capacitance value of the capacitor 454 ′ corresponding to the 4-bit previous data is set small because the influence of the 4-bit previous data is small, and the capacitor 451 ′ is not affected by the immediately preceding data. Since it is large, its capacitance value is set large.

  FIG. 14 is a block circuit diagram showing a third embodiment of the receiver circuit of the signal transmission system according to the second mode of the present invention. In FIG. 14, reference numeral 48 indicates a memory, and 49 indicates a D / A converter.

  In the third embodiment of the receiver circuit shown in FIG. 14, the digital signals (d4 to d1) for the past 4 bits are held in the shift register 43, as in the first embodiment of the second mode described above, The contents of the memory 48 are read out using the digital signal sequence of the past received signals as an address. That is, the output corresponding to the signal held in the shift register 43 is read from the memory 48. The output of the memory 48 is supplied as a reference voltage Vref to the reference voltage side of the differential amplifier 41 via the D / A converter 49, and the signal voltage supplied to the signal input side (+) of the differential amplifier 41 is supplied. A differential amplification with Vin is performed, and the output of the differential amplifier 41 is determined by a determination circuit 42 to determine transmitted data (signal voltage Vin).

  Thus, according to the third embodiment shown in FIG. 14, for example, even when the intersymbol interference becomes nonlinear due to the influence of a transistor, a diode or the like, the value including this nonlinear element is stored in the memory 48. By storing the data, there is an advantage that a correct predicted value can be output (correct transmission data can be determined).

  FIG. 15 is a block circuit diagram showing a fourth embodiment of the receiver circuit of the signal transmission system according to the second mode of the present invention.

  The fourth embodiment of the receiver circuit shown in FIG. 15 basically uses the analog value of the signal voltage received one clock before in combination with the capacitor and switch shown in FIG. 13 is provided, and a decision feedback type predictor configuration using the capacitor of FIG. 13 is provided, and the intersymbol interference expressed by the above-mentioned equation (1) is input signal by the circuit combining the capacitor and the switch. Further, the error remaining by the decision feedback predictor is eliminated by using the reference side input of the differential amplifier. The fourth embodiment of the second mode has an advantage that the intersymbol interference removal can be performed with high accuracy with a small number of storage stages as compared with a normal decision feedback type predictor.

That is, in the receiver circuit of FIG. 15, first, the switch 511 is turned off, and the switches 512 and 513 are turned on, and the voltage difference between the voltage Vb and the signal voltage (Vin) is applied (accumulated) to the capacitor 514. ), and applies a difference voltage between the voltage Vb and the voltage V _TT against capacitor 515. At this time, the switches 561 to 564 are connected to the ground potential Vss. Here, the voltage Vb is a bias voltage for ensuring the operation of the differential amplifier 541. Further, by turning on the switch 545, the auto-zero operation of the differential amplifier 541 is also performed.

Next, the switches 512, 513, and 545 are turned off, the switch 511 is turned on, and the capacitors 514 and 515 are connected in parallel to lead to the signal input side (+) node of the differential amplifier 541. At this time, the switches 561 to 564 are controlled so as to select the past bit information held in the shift register 543 (the data before 4 bits to the bit data immediately before), thereby corresponding to the past bit information. As a result, the potential (Vref) of the node on the reference voltage side (−) of the differential amplifier 541 changes. Here, the capacitor 544 is provided in series between the reference voltage side and the voltage (power supply line) V _TT of the differential amplifier 541. Accordingly, as in FIG. 13 described above, for example, a predicted value of intersymbol interference based on the past 4 bits of data is applied to the differential amplifier 541 as the reference voltage Vref, and a signal on the signal input side is generated by the reference voltage Vref. Differential amplification is performed. The output of the differential amplifier 541 is determined by the determination circuit 542, and the transmitted data (signal voltage Vin) is determined.

  Here, the capacitance value of the capacitor 554 corresponding to the 4-bit previous data is set to be small, and the capacitance value of the capacitor 551 corresponding to the immediately previous bit data is set to be large as described above. It is the same as that. Note that the predictor for predicting intersymbol interference is not limited to the one configured by the capacitor and the switch, and the one using the resistance ladder of FIG. 12 or the one using the memory of FIG. Of course it can be used.

  16 is a circuit diagram showing an example of the auto-zero comparator in the receiver circuit of FIG. 5, and FIG. 17 is a circuit diagram showing another example of the auto-zero comparator in the receiver circuit of FIG.

  That is, the auto-zero comparator shown in FIG. 16 is obtained by configuring the switches 811 to 814 and 817 with N-channel MOS transistors in the circuit of FIG.

  In addition, the auto-zero comparator shown in FIG. 17 is configured such that switches 811 to 814 and 817 in the circuit of FIG. 5B are formed of transfer gates made of N-channel and P-channel MOS transistors. Here, in FIG. 17, inverters 810 and 820 are for generating inverted signals of control signals φ2 and φ1, respectively, whereby each transfer gate can be driven by a complementary signal.

  FIG. 18 is a circuit diagram showing still another example of the auto-zero comparator in the receiver circuit of FIG.

  The auto zero comparator shown in FIG. 18 is obtained by configuring the inverter 818 with a differential amplifier 8181 and an inverter 8182 (818 ') in the circuit of FIG. As shown in FIG. 18, the switch (transfer gate) 817 is provided between the signal input side of the differential amplifier 8181 and the output of the inverter 8182, and performs auto-zero processing. A reference voltage Vr is applied to the reference voltage side of the differential amplifier 8181. Further, the operational state of the differential amplifier 8181 is controlled by the enable signal CMe, and is activated and operated when the enable signal CMe is at a high level.

  19 to 24 are block diagrams each showing an example to which the signal transmission system of the present invention is applied.

  In FIG. 19, reference numeral 601 indicates a controller (memory controller or processor), and 602 indicates a memory (DRAM). The controller 601 is capable of outputting a plurality of control signals (clock signals: clocks) having different phases, a multi-phase DLL (Multi-phase Delay Locked Line: MP-DLL) 611, a partial response detector (PRD). 613, and driver circuits 612 and 614. The memory 602 includes an MP-DLL 621, a PRD 622, 623, and a driver circuit 624.

  The controller 601 and the memory 602 include a ni-bit unidirectional address signal line (signal transmission path; address bus) 615 and an nj-bit bidirectional data signal line (signal transmission path; data) from the controller side to the memory side. Bus) 616. Further, as described above, the driver circuits 612, 614, and 624 have a high output impedance, and the outputs of these driver circuits 612, 614, and 624 are subjected to partial response detection by the corresponding PRDs 622, 623, and 613, respectively. It has become. Here, the configurations and operations of the PRDs 622, 623, and 613 are as described in FIGS. 5, 6, and 12 to 15, for example, and the configurations of the signal transmission paths 615 and 616 are the same as those in FIG. As described with reference to FIGS. 20 to 24 below, the configuration of each signal transmission path (address bus and data bus), driver circuit, receiver circuit (PRD), and the like is the same as that described with reference to each of the above drawings. Can be applied.

  As is apparent from FIG. 19, in the controller 601, a control signal (clock) from the MP-DLL 611 subjected to synchronization control is supplied to each PRD 613 and driver circuits 612 and 614, and in the memory 602, synchronization is performed. A control signal from the controlled MP-DLL 621 is supplied to each PRD 622, 623 and driver circuit 624. In this application example, the clock CLK is supplied to each circuit block (controller and memory) through a normal signal line (for example, SSTL: Series-Stub Terminal Logic).

  In FIG. 20, reference numeral 603 denotes a controller (or one of processors or logic chip sets), 604a to 604d denote memories, and 651 and 652 denote logic chips. The controller 603 includes MP-DLL 631, PRD 632, 633, and driver circuits 634, 635, 636. The memories 604a to 604d have the same configuration. For example, the memory 604a includes an MP-DLL 641, PRDs 642 and 643, and a driver circuit 644. Further, the logic chip 651 includes a DLL 6511 and a driver circuit 6512, and the logic chip 652 includes a DLL 6521 and a PRD 6522.

  The controller 603 and the memories 604a to 604d are connected by a ni-bit unidirectional address bus 637 from the controller side to the memory side and an nj-bit bidirectional data bus 638. These buses 637 and 638 are configured as 1: 4 buses, but it goes without saying that the number of memories is not limited to four and can be variously modified.

  The controller 603 and the logic chip 651 include an np-bit unidirectional data signal line (data bus A) 653 from the logic chip 651 side to the controller 603 side, and an nq-bit single line from the controller 603 side to the logic chip 652 side. They are connected by a directional data signal line (data bus B) 654. That is, the signal transmission path (the signal transmission path of the present invention) in the signal transmission system of the present invention is applied to the unidirectional signal transmission paths 637, 653, 654 and the bidirectional signal transmission path 638.

  Further, the driver circuits 634, 635, 636, 644, 6512 have high output impedance, and the outputs of these driver circuits 634, 635, 636, 644, 6512 are respectively output by the corresponding PRD 6522, 642, 643, 633, 632 Partial response detection is performed. That is, the receiver circuit (the receiver circuit of the present invention) in the signal transmission system of the present invention is applied to PRD6522, 642, 643, 633, and 632. The driver circuit (driver circuit of the present invention) in the signal transmission system of the present invention is applied to the driver circuits 634, 635, 636, 644, and 6512.

  As is apparent from FIG. 20, in the controller 603, the control signal from the MP-DLL 631 subjected to synchronous control is supplied to each PRD 632, 633 and driver circuits 634 to 636, and the memory 604a (604a to 604d). , A control signal from the MP-DLL 641 is supplied to each of the PRDs 642 and 643 and the driver circuit 644. Further, in the logic chip 651, a control signal from the DLL 6511 is supplied to the driver circuit 6512, and in the logic chip 652, a control signal from the DLL 6521 is supplied to the PRD 6522.

  The signal transmission system shown in FIG. 21 is a modification of the signal transmission system of FIG. 20, and includes a processor (or graphic engine) 605 instead of the logic chips 651 and 652 in FIG. Reference numeral 603 'denotes a controller (or one of logic chips).

  The processor 605 includes an MP-DLL 6051, a PRD 6052, and driver circuits 6053 and 6054. As apparent from the comparison between FIG. 20 and FIG. 21, in this application example, the unidirectional data signal line 654 in FIG. 20 is configured as a bidirectional data signal line 654 ′, and correspondingly, the controller PRD 632 ′ is provided at 603 ′. That is, the signal transmission path of the present invention is applied to the unidirectional signal transmission paths 637 and 653 and the bidirectional signal transmission paths 638 and 654 ′, and the receiver circuit of the present invention is PRD6052, 642 and 643. , 633, 632, 632 ′, and the driver circuit of the present invention is applied to driver circuits 634, 635, 636, 644, 6053, 6054.

  The signal transmission system shown in FIG. 22 is a further modification of the signal transmission system shown in FIG. 21 and includes a logic chip 605 ′ as the processor 605. The present invention is applied to the signal transmission system shown in FIG. The signal transmission path 654 ′ is configured by a normal SSTL signal line.

  That is, the nq-bit bidirectional signal line connecting the logic chip 605 ′ and the controller 603 ″ is the SSTL signal line, and the driver circuits 6054 ′ and 634 ″ and the receivers 6052 ′ and 632 ″ are configured for SSTL. Therefore, the signal transmission path of the present invention is applied to the unidirectional signal transmission paths 637 and 653 and the bidirectional signal transmission path 638, and the receiver circuit of the present invention has PRDs 642, 643 and 643. 633, 632, and the driver circuit of the present invention is applied to driver circuits 635, 636, 644, 6053.

  In FIG. 23, reference numeral 606 denotes a controller (or processor), 607 denotes a memory, and 664 and 674 denote differential amplifiers. In the signal transmission system shown in FIG. 23, the supply of the clock CLK is such that the complementary signals CLK and / CLK are supplied to the DLLs 661 and 671 via the differential amplifiers 664 and 674, respectively.

  That is, the complementary clocks CLK and / CLK are supplied to the controller 606 and the memory 607, are differentially amplified by the differential amplifiers 664 and 674, respectively, and then supplied to the DLLs 661 and 671. The output (control signal) of the DLL 661 is supplied to the driver circuit 662 and the PRD 663, and the output of the DLL 671 is supplied to the driver circuit 672 and the PRD 673. Thus, in this application example, clock transmission is performed at high speed and with low power. The signal transmission path of the present invention is applied to the bidirectional signal transmission path 665, the receiver circuit of the present invention is applied to the PRD 663, 673, and the driver circuit of the present invention is the driver circuit 662, 672.

  24, reference numeral 608 indicates a controller (or processor), 609 indicates a memory, 684, 694 indicates a differential amplifier, and 685, 686, 695, 696 indicate driver circuits. In the signal transmission system shown in FIG. 24, the clock CLK is supplied by a normal signal line. Instead, complementary strobe signals ST-B, / ST-B and ST-A are sent from the DLLs 681 and 691 in accordance with the data output timing. , / ST-A is output. These complementary strobe signals ST-B and / ST-B and ST-A and / ST-A are received by the differential amplifiers 694 and 684 on the signal receiving side, and control the PRDs 692 and 682 via the DLLs 691 and 681. It is like that.

  As a result, in this application example, the delay similar to the delay due to the signal transmission path is canceled by the delay in the strobe signals ST-B, / ST-B and ST-A, / ST-A, and signal synchronization is performed strictly. It becomes possible. The signal transmission path of the present invention is applied to a bidirectional signal transmission path 687, the receiver circuit of the present invention is applied to PRDs 683, 693, and the driver circuit of the present invention is a driver circuit 682. 692.

  Hereinafter, a signal transmission system according to a third embodiment of the present invention will be described. Before that, a conventional signal transmission system and its problems will be described with reference to FIG.

  FIG. 25 is a block diagram schematically showing another example (Rambus channel) of a conventional signal transmission system. In FIG. 25, reference numerals 901 and 902 are termination resistors, 903 is a signal transmission path (bus), 904 is a termination resistor for a clock line, 905 is a clock generation source, and 906 is a clock line. Reference numeral 9-0 denotes a controller (DRAM controller), and 9-1 to 9-n denote devices (DRAM chips). The DRAM chips 9-1 to 9-n may be various constituent circuits provided in one chip or a DRAM module such as a DIMM (Dual Inline Memory Module) mounted with a plurality of DRAM chips. .

  As shown in FIG. 25, in the Rambus channel, the DRAM controller 9-0 and the plurality of DRAM chips 9-1, 9-2,... 9-n are connected by a common signal transmission path (bus). Yes.

  By the way, in order to transmit and receive high-speed signals, it is necessary to accurately match the timing of the signal sender and receiver. Therefore, in the Rambus channel, the clock CLK (CLKs, CLKr) is sent to the folded clock line 906, and the DRAM controller 9-0 extracts the clock from the vicinity of the folding point (P902). Then, the DRAM controller 9-0 determines the timing of signal capture and transmission in accordance with this clock.

  Further, when sending signals to the DRAM controller 9-0, each DRAM chip (DRAM module) 9-1 to 9-n takes out the clocks (CLKs) that are traveling toward the DRAM controller from the return clock line 906. In accordance with this, signal transmission timing is generated. Further, when receiving signals from the DRAM controller 9-0, each of the DRAM modules (DRAMs) 9-1 to 9-n extracts a clock (CLKr) directed from the DRAM controller and generates a reception timing.

  That is, when data is read from the DRAM chip and the signal is transmitted to the DRAM controller 9-0, the DRAM chip 9-1 specifically outputs the clock supplied from the clock generation source 905 and supplied via the clock line 906. CLKs is received at a point P912 on the clock line 906, and read data is transmitted to the DRAM controller 9-0 via points P911 and P901 on the signal transmission path 903. The DRAM chip 9-2 receives the clock CLKs at the point P922 on the clock line 906, and transmits the read data to the DRAM controller 9-0 via the points P921 and P901 on the signal transmission path 903. Further, the DRAM chip 9-n receives the clock CLKs at the point P9n2 on the clock line 906, and transmits the read data to the DRAM controller 9-0 via the points P9n1 and P901 on the signal transmission path 903.

  Here, the clock CLKs has a time shift (delay) corresponding to the distance between the point P912 and the point P902 on the clock line 906 between the DRAM chip 9-1 and the DRAM controller 9-0. The shift is canceled by a time shift (delay) corresponding to the distance between the point P911 and the point P901 on the signal transmission path 903 when a signal (read data) is transmitted from the DRAM chip 9-1 to the DRAM controller 9-0. Therefore, the DRAM controller 9-0 can take in an accurate (synchronized) signal.

  Similarly, in the DRAM chip 9-2, a time lag corresponding to the distance between the points P922 and P902 on the clock line 906 is a time corresponding to the distance between the points P921 and P901 on the signal transmission line 903. In the DRAM chip 9-n, the time lag corresponding to the distance between the point P9n2 and the point P902 on the clock line 906 is the distance between the point P9n1 and the point P901 on the signal transmission path 903. The DRAM controller 9-0 can take in an accurate signal by canceling out by a corresponding time lag.

  On the other hand, when the signal from the DRAM controller 9-0 is transmitted to the DRAM chip, the DRAM controller 9-0 receives the clock CLKr (CLKs) at the point P902 on the clock line 906, and receives the signal at the point on the signal transmission path 903. Transmit via P901. Specifically, when a signal (write data) is transmitted to the DRAM chip 9-1, the write data is shifted (delayed) by a time corresponding to the distance between the point P901 and the point P911 on the signal transmission path 903. However, since the clock CLKr transmitted to the DRAM chip 9-1 is also shifted by a time corresponding to the distance between the point P902 and the point P913 on the clock line 906, the shift of the signal (write data) is canceled out. In -1, it is possible to perform writing processing by fetching accurate (synchronized) writing data.

  Similarly, in the DRAM chip 9-2, the time lag of the write data corresponding to the distance between the points P901 and P921 on the signal transmission path 903 corresponds to the distance between the points P902 and P923 on the clock line 906. In the DRAM chip 9-n, the time lag of the write data corresponding to the distance between the point P901 and the point P9n1 on the signal transmission path 903 is point P902 on the clock line 906. And the time difference of the clock CLKr corresponding to the distance from the point P9n3, each DRAM chip can perform an accurate write process.

  As described above, in the signal transmission system (Rambus channel) shown in FIG. 25, when the clock line 906 and the signal transmission path 903 pass through exactly the same route and the electrical characteristics are exactly the same, both transmission and reception have the correct timing. Can be given. That is, the signal transmission system shown in FIG. 25 requires that the clock line 906 and the signal transmission path 903 pass through the same route with the same electrical characteristics.

  However, it is inevitable that the characteristics of the load are different between the clock line 906 and the signal transmission path (bus) 903. This is because the signal transmission path 903 is a latch circuit that operates in accordance with the reception timing and can perform high-sensitivity reception, whereas the clock line 906 cannot use a latch, so a differential amplifier or the like must be used. That is, since the load circuit is different between the latch circuit and the differential amplifier or the like, the electrical characteristics (for example, delay per unit distance) of the line are different between the clock and the signal. Even if the load characteristics are perfectly matched, it is impossible to trace the same route between the clock and the signal line by wiring on an actual board. Therefore, at higher frequencies, it becomes increasingly difficult to generate correct timing by the signal transmission system shown in FIG.

  Furthermore, not only in the signal transmission system shown in FIG. 25, in the current signal transmission system, when devices that transmit signals on the bus (signal transmission path) change one after another, a gap ( It was necessary to provide a time margin). That is, if signals overlap each other, they are received by mistake, so that such signals are prevented from overlapping. In order to eliminate or minimize this gap, it is necessary to define the transmission / reception timing very strictly, but this also becomes more difficult as the frequency increases.

  Therefore, the timing signal can be generated without requiring symmetry between the clock line and the signal line (signal transmission path: bus), and the gap when the transmission device is switched can be minimized. There is a demand for providing a signal transmission system.

  Next, the signal transmission system as the third mode of the present invention will be described in detail. First, the characteristics of the third mode of the present invention will be outlined.

  In the third embodiment of the present invention, a common timing is generated with an accuracy (for example, about 10 percent) sufficiently shorter than the maximum time for a signal to travel through the signal transmission path, and all elements (devices, LSI chips, etc.) are generated at this common timing. ) To work together. Here, the common timing is synthesized from the clocks respectively traveling in the opposite directions on the clock lines. Further, the receiving side is provided with a function for removing intersymbol interference (PRD and the like: see FIG. 4, FIG. 12, FIG. 13, FIG. 14, and FIG. 15), and is configured to operate all elements at a common timing. To do.

  The time for a signal to reach a receiving element (for example, a controller) from each element changes corresponding to the travel time of the signal. When the transmission element is switched, reception is performed at a common timing under this time difference, so that interference between codes increases. However, by using a means for removing intersymbol interference on the receiving side, all transmitting elements (devices, LSI chips, etc.) can be received at a common timing. Even when the timing is adjusted, by using the intersymbol interference removal (intersymbol interference component estimation) means (PRD), it is not necessary to perform a precise timing adjustment, so that a low-cost circuit can be used.

  That is, in the third embodiment of the present invention, a common reference time (hereinafter, referred to as a common time reference) for all devices (chip configuration circuit, DRAM chip, DRAM module, etc.) connected to the signal transmission path (bus). GMT (also referred to as Global Mean Time) is used, and reception is performed using the above-described reception method (the receiver circuit of the signal transmission system according to the second embodiment of the present invention) that eliminates intersymbol interference, and further, a driver As a circuit (driving circuit), a push-pull driver (a push-pull driver having a constant current or a large output resistance) is used. As a result, gapless transfer in read / write operations to different devices becomes possible, and the transmission characteristics of the data clock (clock line) running along the data line (transmission signal line) described above are the same as the data line. In addition, the control of the transmission clock (CLKs) and the reception clock (CLKr) (Rambus channel, Vernier, etc.) can be eliminated.

  FIG. 26 is a block diagram showing a principle configuration of a signal transmission system as a third mode of the present invention. In FIG. 26, reference numerals 701 and 702 are termination resistors, 703 is a signal transmission line (bus), 704 is a termination resistor for a clock line, 705 is a clock generation source, and 706 is a clock line. Reference numeral 7-0 denotes a controller (DRAM controller), and 7-1 to 7-n denote devices (DRAM chips). The DRAM chips 7-1 to 7-n may be various constituent circuits provided in one chip, or a DRAM module such as a DIMM mounted with a plurality of DRAM chips. May be an EPROM (Erasable and Programmable Read Only Memory), a flash EEPROM (Electrically Erasable and Programmable Read Only Memory), or the like. The controller (7-0) may be an ASIC (Application Specified Integrated Circuit), a graphic controller, or a microprocessor.

  FIG. 27 is a diagram (part 1) for explaining the operation of the signal transmission system of FIG.

  As shown in FIGS. 26 and 27, the common reference time (common timing) GMT of all the DRAM controllers 7-0 and DRAM chips 7-1 to 7-n connected to the signal transmission path 703 is the folded clock line 706. Generate using. That is, in the third embodiment of the present invention, the common timing GMT is used as an intermediate timing between the forward clock and the backward clock of the folded clock line 706 instead of using the transmission clock CLKs and the reception clock CLKr. Is generated.

  Specifically, in the DRAM chip 7-1, the forward clock CLK is taken in from the point P 712 on the clock line 706, the backward clock CLK is taken in from the point P 713 on the clock line 706, and the two clocks A common reference time GMT having an intermediate (intermediate phase) timing as a common timing is generated. Similarly, in the DRAM chip 7-2, the clock CLK on the forward path and the backward path is taken from the points P722 and P723 on the clock line 706, and the common reference time GMT having the intermediate timing as a common timing is generated. The DRAM chip 7-n takes in the forward and return clocks CLK from the points P7n2 and P7n3 on the clock line 706, and generates a common reference time GMT having the intermediate timing as a common timing. As a result, the common timing (common reference time GMT) for each cycle TT can be accurately obtained regardless of the position of the DRAM chip on the clock line 706.

  At this time, the forward (outward) path and the return (return) of the clock line 706 need to pass exactly the same path (route), but the transmission characteristic of the clock line 706 itself is the signal transmission path (data line) 703. The transmission characteristics may differ greatly. Further, the path through which the return clock line 706 passes may be different from the data line 703. In short, if an intermediate phase between the forward clock and the backward clock is selected, this becomes the common timing GMT. In order to uniquely determine the common reference time GMT, the length of the clock line 706 is limited. However, the actual clock CLK is divided by n (for example, divided by 4) to be four times as long (1/4). Frequency), the limit of the length of the clock line 706 can be increased n times (for example, 4 times), so that the common timing GMT can be distributed over a distance that is not a problem in practice. . In this case, the DRAM controller 7-0 and each of the DRAM chips 7-1 to 7-n are multiplied by n (for example, multiplied by 4) to restore the clock whose period is increased by n (for example, 4 times). A PLL circuit or a DLL circuit that performs a quadruple frequency) is provided.

  As described above, the common timing can be generated by using the folded clock line 706 to generate a signal having an intermediate phase between the forward and backward clocks. Does not have to be folded. For example, as will be described later, the forward and backward clocks can be run simultaneously on one clock line (corresponding to standing a standing wave on the clock line). On the standing wave when the length of the clock line is half the wavelength, a clock having the same phase can be obtained at any position. That is, the common timing can be distributed also by standing waves.

  Next, as a circuit for receiving a signal, a receiving circuit represented by the partial response detector (PRD) described above (refer to FIG. 4, FIG. 12, FIG. 13, FIG. 14, FIG. 15). Although it is used, the length L of the data line (bus) 703 is limited in order to use the PRD. Here, the condition that the time required for the wave to reciprocate (round trip time) is set to be equal to or less than the bit time T of the signal. This condition can actually be relaxed a little more.

  FIG. 28 is a diagram (part 2) for explaining the operation of the signal transmission system of FIG. 26. FIG. 28 (a) shows unit pulse signals transmitted by the DRAM chips 7-1 to 7-n. (B) shows waveforms when signals transmitted from the DRAM chips 7-1 to 7-n are received by the DRAM controller 7-0.

  As shown in FIG. 28 (b), intersymbol interference is removed on the receiving side (DRAM controller 7-0), and reception is performed at a common timing (received at t = TT). Any element (DRAM chip) If the upper limit of the delay from each element is determined so that the signal strength is sufficient, all elements can transmit and receive at a common timing. Here, each element transmits a new signal in synchronization with the start position of the bit time, and receives in synchronization with the end of the bit time. Further, the transmission timing and the reception timing may be slightly changed to optimize the signal strength, but the time reference is only the common timing TT.

  The driver circuit (drive circuit) is configured as a push-pull driver (a push-pull driver having a large constant current or output resistance). Note that a driver with a large output resistance means that the output impedance of the driver is larger than the characteristic impedance of the signal line, even if it is not a constant current driver. It is configured by appropriately reducing the size of.

  As a result, no matter which driver circuit (DRAM controller 7-0 or DRAM chips 7-1 to 7-n) tries to drive the bus 703 (and no driver circuit is driving the bus), The constant (more precisely, the response function) is constant regardless of time. That is, the system is a “linear time-invariant system”, and therefore the received signal is obtained by superimposing the unit pulse responses h (t).

Here, when h (t) is obtained for the worst condition, that is, when the round trip time is just the bit time T of the signal, h (nT) normalized by the final value of the step response is n = 0, 1, 2 ... 0,1-s ^** 2, (1-s ^** 2) S ^** 2, (1-s ^{**) S **} 4 ....

S is a voltage reflection coefficient at the line end, and it is assumed that both ends of the line are terminated with the same resistance. This is an exponential response when Exp (−T / τ) = s ^** 2.

Here, it can be seen that if S ^** 2 is set to about 0.5, the PRD can be received without any problem. This reflection coefficient is 5.8 times the characteristic impedance in terms of the value of the termination resistance R _T (701, 702). This is equivalent to a termination resistance of 290 ohms in a 50 ohm system. If a slightly smaller termination resistance is used, the intersymbol interference is reduced, and reception can be performed easily.

Next, assuming that the current value of the driver circuit is, for example, io = 3.5 mA, the final value of the step response is approximately 500 mV at io × R _T / 2, and therefore the magnitude of the net signal is 1− Multiply s ^** 2 to 250 mV. Thus, it can be seen that PRD can be received even under the worst conditions. Therefore, even if the chips (7-1 to 7-n) are switched, the amplitude of the transient voltage wave on the bus 703 is attenuated by s ^{** by} 2 every T. Interference can be removed and reception can be performed without any problem. That is, gapless transmission is possible.

  Since reception is possible under the worst conditions, all devices (chips) need only transmit or receive signals at the timing of the common reference time GMT. Therefore, there is no need for a PLL (Phase Locked Loop) or DLL that uses Vernier or matches the transmission clock and reception clock as in the Rambus channel.

  As described above, in the signal transmission system according to the third embodiment of the present invention, by removing the intersymbol interference by the receiving circuit, it becomes possible for all elements to use a common timing signal with a certain accuracy. Become. The certain accuracy mentioned here is derived from the fact that it allows a timing error that can eliminate intersymbol interference, and is sufficiently smaller than the time required for a signal to be transmitted (transmitted) on the signal line (for example, about 10 percent). It only needs time accuracy. In addition, in order to form a common timing signal, it is only necessary to have a clock that runs in both directions of the clock route (outward and backward), and there is no need to match the electrical characteristics and routes of the clock line and the signal line. There is an advantage that there is no restriction on the arrangement and form of the clock lines.

  Embodiments of the signal transmission system according to the third mode of the present invention will be described below in detail with reference to the drawings.

  FIG. 29 is a block diagram showing a first embodiment of the signal transmission system according to the third mode of the present invention. 29, reference numerals 701 and 702 are termination resistors, 703 is a signal transmission line (bus), 704 is a termination resistor for a clock line, 705 is a clock generation source, 706 is a clock line, and 770 to 774 are stub resistors. Is shown. Reference numeral 7-0 denotes a controller (DRAM controller), and 7-1 to 7-4 denote devices (DRAM chips).

  As described with reference to FIGS. 26 and 27, the DRAM controller 7-0 and the DRAM chips 7-1 to 7-4 take out round-trip clocks from the folded clock line 706, respectively, and output intermediate phase signals. By generating this, this is used as a common timing signal (common reference time GMT). The DRAM controller 7-0 and the DRAM chips 7-1 to 7-4 transmit and receive signals in accordance with a common timing signal (GMT). As the termination resistors 701 and 702, for example, 250 ohm resistors are used, and as the stub resistors 770 to 774, for example, 25 ohm resistors are used.

  As described above, according to the first embodiment of the signal transmission system of the third aspect of the present invention, the common timing signal (GMT) is intermediate between the forward clock and the backward clock of the folded clock line 706. Can be obtained as the timing. That is, a common timing signal having accurate common timing can be obtained regardless of the position of the DRAM chip on the clock line 706.

  FIG. 30 is a block diagram showing a modification of the signal transmission system of FIG. 29, and shows a multiprocessor system. In FIG. 30, reference numerals 7-1 to 7-4 indicate processor elements.

  As shown in FIG. 30, the third embodiment of the present invention is not limited to a signal transmission system using a bus (signal transmission path) 703 as shown in FIG. The present invention can also be applied to a processor system.

  FIG. 31 is a block diagram showing an example of a main part configuration of each device in the signal transmission system according to the third mode of the present invention. In FIG. 31, reference numeral 781 indicates a driver circuit (driving circuit), and 782 indicates a PRD (partial response detection circuit).

  As shown in FIG. 31, a DRAM chip 7-1 (each DRAM chip 7-2 to 7-4 or DRAM controller 7-0) is equipped with a PRD 782 for removing the influence of intersymbol interference, The reception of data is performed at a common timing TT by reducing the influence of intersymbol interference from the received waveform as shown in FIG. Thus, by using the PRD 782 using an auto-zero comparator (see FIGS. 5 and 16 to 18 etc.) as a receiving circuit, large intersymbol interference can be removed with a simple circuit.

  FIG. 32 is a block diagram showing another example of the main configuration of each device in the signal transmission system according to the third mode of the present invention. In FIG. 32, reference numeral 781 indicates a driver circuit, and 783 indicates an equalizer.

  As shown in FIG. 32, the DRAM chip 7-1 (each DRAM chip 7-2 to 7-4 or DRAM controller 7-0) includes an equalizer circuit 783 for minimizing the influence of intersymbol interference. Is installed. That is, in this configuration, an equalizer circuit 783 is used as a receiving circuit instead of the PRD 782 in FIG. 31, and the influence of intersymbol interference is reduced from the received waveform as shown in FIG. Data is received at timing TT.

  FIG. 33 is a block diagram showing a second embodiment of the signal transmission system according to the third mode of the present invention.

As shown in FIG. 33, in the second embodiment of the third mode, the length of the signal transmission path (signal line) 703 is set so that the signal can be reciprocated once or more on the signal line in the time of bit time T. It is supposed to be limited to. That is, a limit of 2L / v ₀ ≦ T is set, where v ₀ is the wave propagation speed on the signal line 703, L is the length of the signal line 703, and T is 1 bit time (1 bit length). . This makes it easy to keep the intersymbol interference small and allows all elements (DRAM controller and DRAM chip) to generate a common timing signal (GMT) by generating a signal having an intermediate phase between the reciprocating clock phases. Become.

  FIG. 34 is a block diagram showing a third embodiment of the signal transmission system according to the third mode of the present invention. In FIG. 34, reference numerals 701, 701 ′ and 702 are terminating resistors, 703 and 703 ′ are signal transmission paths (buses), 706 is a clock line, 7-0 is a controller (DRAM controller), and 7-1 to 7-n. 7-1 ',... Are devices (DRAM chips), and 708 is a buffer.

As shown in FIG. 34, in the third embodiment of the third mode, a buffer 708 is provided between signal transmission lines (signal lines) 703 and 703 ′. That is, for example, when the length of the signal line exceeds the above 2L / v ₀ ≦ T, the buffer 708 is appropriately provided.

  Here, the buffer 708 has a function of retransmitting a signal (a signal transmitted on the signal line 703) with a delay by an integral multiple of the 1-bit time T. Since the buffer delay is an integral multiple of T, the buffer and the elements (DRAM chip or the like) connected to the buffer can all be operated with the common timing signal so far. Naturally, signal transmission / reception of the buffer 708 is also performed based on the common timing.

  FIG. 35 is a block diagram showing a modification of the signal transmission system of FIG.

  As shown in FIG. 35, in this modification, in the third embodiment of FIG. 34, the buffer 708 is transmitted not only on the signal transmitted on the signal line 703 but also on the clock line 706 (706 ′). It is also provided for the clock. That is, the buffer 708 includes means for supplying a clock for other devices (DRAM chips 7-1 ', ...) connected to the buffer 708.

  This makes it possible to extend the distance for transmitting the signal by the buffer. However, if the distance of the clock distribution wiring becomes longer, simply generating a signal having the center phase of the reciprocating clock will generate a common clock. This is because it cannot be determined uniquely. Therefore, if the buffer 708 generates and sends a waveform delayed by the same phase as the waveform advanced by a certain phase from the common clock using DLL or PLL, the device (DRAM chip 7-1 ′,...) That has received this clock. Can have the same common timing as the buffer 708.

  FIG. 36 is a block diagram showing a fourth embodiment of the signal transmission system according to the third mode of the present invention. 36, reference numerals 780 to 78m denote buffers, 703 denotes a bus (signal line), and 7-1 to 7-n denote devices (DRAM chips).

  As shown in FIG. 36, in the fourth example of the third mode, each of the buffers 780 to 78m is connected to a plurality of sets of bus line groups 703, respectively. By using such buffers 780 to 78m, signals can be transmitted to and received from a large number of devices (DRAM chips) 7-1 to 7-n in a tree shape, and a large-scale system can be easily configured. it can. It goes without saying that various topologies such as a tree shape, a star shape, and a ring shape are possible as the topology of the signal line 703 using the buffers 780 to 78m.

  FIG. 37 is a circuit diagram showing an example of a driver circuit in the signal transmission system according to the third mode of the present invention. For example, the driver circuit (drive circuit) 781 in FIGS. 31 and 32 is shown.

  As shown in FIG. 37, the driver circuit for driving the signal line (signal transmission path 703) includes P-channel MOS transistors 7811 and 7812, N-channel MOS transistors 7815 and 7816, current sources 7813 and 7817, and a CMOS. Inverters 7814 and 7818 are provided. Here, the transistor 7812 is current-mirror connected to the transistor 7811, and the transistor 7816 is current-mirror connected to the transistor 7815. The driver circuit has a circuit system in which the constant current is switched by driving the source sides of the transistors 7812 and 7816 of the symmetrical current mirror type constant current driving circuit with the CMOS inverters 7814 and 7818, respectively. That is, the driver circuit 781 shown in FIG. 37 is configured as a constant current drive push-pull driver having symmetry.

  As a result, the output impedance of the driver circuit becomes high, and even if any driver circuit of each circuit block (DRAM chip or the like) is switched, the response function of the signal line system becomes constant, and the intersymbol interference removal rate is increased. Even more accurate signal transmission can be performed. Furthermore, even if an error occurs between the common timing signals generated in each block circuit and a period in which a plurality of driver circuits simultaneously drive signal lines occurs, a through current may flow if constant current driving is performed. There is an advantage that no problem occurs.

  FIG. 38 is a block diagram showing a fifth embodiment of the signal transmission system according to the third mode of the present invention. 38, reference numeral 711 is a common timing signal generation circuit, 712 is a variable delay circuit, 713 is a phase comparison circuit, 714 is a NAND gate, 715 is a driver circuit (real driver), and 716 is a dummy driver circuit (dummy). Driver). Here, the variable delay circuit 712 and the phase comparison circuit 713 constitute a DLL (Delay Locked Loop) circuit. The dummy driver 716 has the same configuration as the real driver 715 (having the same delay time), and the delay in the real driver 715 is removed by feeding back the output of the dummy driver 716 to the phase comparison circuit 713. It has become. Note that output data is supplied to one input of the NAND gate 714, and the output data is supplied to the real driver 715 in accordance with the output (timing signal) of the variable delay circuit 712.

  That is, in the fifth embodiment of the third mode, the clock transmitted to the clock line that has turned back and forth as described with reference to FIG. 27 is taken in, and the rising timings of the forward and backward clocks are taken. In addition to the common timing signal generation circuit 711 that generates the intermediate timing as a common timing, a phase comparison circuit 713, a variable delay circuit 712, and a dummy driver 716 for removing a delay in the driver circuit (real driver) 715 are further provided. It is supposed to be provided. Then, by controlling the delay amount of the variable delay circuit 712, the delay and delay variation in the real driver 715 are compensated, and more accurate signal transmission is performed. For example, the same adjustment using the DLL can be performed with respect to the input timing.

  FIG. 39 is a block diagram showing a sixth embodiment of the signal transmission system according to the third mode of the present invention.

  As shown in FIG. 39A, in the sixth embodiment of the third mode, the clock line 706 is configured as a single clock line, not a reciprocating clock line. A standing wave is generated in the clock line 706 by directly grounding one end of one clock line 706, that is, by removing the short-circuiting resistor 704 in FIG. 26 (FIG. 39B). )), And the standing wave is used as a common timing (GMT).

  Therefore, the sixth embodiment of the third mode uses the fact that when a standing wave is standing on the clock line 706, voltage oscillation of the same phase can be obtained in a region having a length half the wavelength. . In this method, the number of clock lines 706 is half that in the case of reciprocation, and the clock is reciprocated in one line. There is an advantage that accuracy is increased.

  FIG. 40 is a block diagram showing a seventh embodiment of the signal transmission system according to the third mode of the present invention. In FIG. 40A, reference numerals 761 and 762 indicate active terminators, and in FIG. 40B, reference numeral 7611 indicates a delay unit, and 7612 indicates a control power source unit.

  In the sixth embodiment shown in FIG. 39, the end of the clock line 706 is short-circuited. However, in the seventh embodiment of the third mode, an active terminator (active termination circuit) is connected to both ends of the clock line 706. ) 761 and 762 are provided for termination. Here, the active terminators 761 and 762 are controlled so that, for example, the reflected wave generated at the terminal end is the same as when the line is short-circuited at a position that is advanced by 1/16 of the wavelength from the terminal end. Yes. This active terminator 761 (762) includes, for example, a delay unit 7611 and a control power source unit 7612 as shown in FIG. 40B, monitors the voltage at the termination unit, and the delay unit 7611 This is realized by generating a current signal having a constant phase relationship with the voltage and feeding back to the terminal unit (control power supply unit 7612), and easily realized by using a known PLL circuit, DLL circuit, constant current drive circuit, or the like. be able to. According to the seventh embodiment of the third mode, a standing wave can be generated on the clock line 706 without matching the length of the clock line 706 to the clock frequency accurately. There is an advantage that the amplitude of the clock is also uniform.

  FIG. 41 is a circuit diagram showing an example of the common timing signal generation circuit (711) in the signal transmission system according to the third mode of the present invention. 41, reference numerals 7111 and 7112 are capacitors, 7113 and 7114 are P-channel MOS transistors, 7115 and 7116 are N-channel MOS transistors, 7117 are resistors, 7118 and 7119 are voltage sources, and 7120 is a current source. Show. A sine wave is used as the clock CLK transmitted through the clock line 706.

  When the common timing signal generation circuit 711 uses a sine wave as the clock CLK, the common timing signal generation circuit 711 illustrated in FIG. 41 uses a first sine wave (forward clock) s1 and a second sine wave (returning clock). The fact that a sine wave (common timing signal) s3 having a middle phase can be generated by taking the sum with the clock (s2) s2 is used. That is, two capacitors 7111 and 7112 are capacitively coupled to supply two clocks (s1, s2) to a differential amplification type comparator, thereby generating a common timing signal (s3). This method has an advantage that a circuit amount for generating a common timing signal can be reduced.

  FIG. 42 is a circuit diagram showing another example of the common timing signal generation circuit in the signal transmission system according to the third mode of the present invention. In this circuit as well, a sine wave is used as the clock CLK transmitted through the clock line 706.

  The common timing signal generation circuit 711 shown in FIG. 42 includes two comparators 720 and 730 and two inverters 740 and 750. Here, as a clock to be supplied to each comparator 720 (730), for example, a signal / s2 obtained by inverting the forward-side (forward) clock s1 and the backward-path (return) clock is used. The common timing signals s3 and / s3 having the following phases are generated.

  FIG. 43 is a circuit diagram showing an example of a comparator in the common timing signal generation circuit of FIG. As shown in FIG. 43, the comparator 720 (730) includes a plurality of P-channel MOS transistors 721, 722, 726 and a plurality of N-channel MOS transistors 723, 724, 725, 727.

  FIG. 44 is a circuit diagram showing still another example of the common timing signal generation circuit in the signal transmission system according to the third mode of the present invention.

  The common timing signal generation circuit shown in FIG. 44 is a conventionally known phase interpolator, which uses the phase interpolator to capture forward and backward clocks on the folded clock line, A common timing signal generation circuit 711 that generates an intermediate phase clock of the reciprocating clock can be configured.

  As shown in FIG. 44, the phase interpolator (common timing signal generation circuit) 711 includes a plurality of P-channel MOS transistors 771 to 784, a plurality of N-channel MOS transistors 785 to 791, capacitors 792 and 793, In addition, a comparator 794 is provided.

  By configuring the common timing signal generation circuit 711 using a phase interpolator as shown in FIG. 44, a rectangular wave driven by a normal CMOS driver can be used as a clock. There is an advantage that the common timing signal generation circuit can be configured with a circuit amount smaller than that of the DLL or PLL. Needless to say, various types of phase interpolators can be used in addition to those shown in FIG.

  FIG. 45 is a block diagram showing an eighth embodiment of the signal transmission system according to the third mode of the present invention. In FIG. 45, reference numerals 790 to 793 denote DLL circuits.

  As shown in FIG. 45, in the eighth embodiment of the third mode, the clock CLK ′ supplied to the clock line 706 has a period n times (for example, 4 times) the normal clock CLK. .

  That is, in the eighth embodiment of the third mode, a clock that can generate a common timing signal by generating a phase signal in the middle of a round-trip clock by lengthening the clock cycle (for example, four times). The upper limit of the length of the line 706 is increased. Here, in the method using the round-trip clock line (and the method using the standing wave clock), if the round-trip delay becomes longer than the clock cycle, an uncertainty of 180 degrees occurs in phase with the common timing. However, as in the eighth embodiment of the third mode, the length of occurrence of uncertainty can be increased by increasing the clock cycle.

  As shown in FIG. 45, in the DRAM controller 7-0 and each of the DRAM chips 7-1 to 7-3, the clock whose cycle is increased by n times (for example, 4 times) is returned to the original cycle (the cycle is changed). DLL circuits 790 to 793 that perform n multiplication (for example, multiplication by 4) for 1 / n, that is, frequency is multiplied by n are provided. A PLL circuit may be used as the DLL circuits 790 to 793.

  FIG. 46 is a diagram showing an example of a transmission path for clock distribution in the signal transmission system according to the third mode of the present invention. In FIG. 46, reference numeral 7061 indicates a shield, and 7062 indicates a clock pair line (twist line).

  As shown in FIG. 46, the transmission path (clock line 706) for distributing the clock CLK is transmitted by a differential pair (twist line 7062) crossed at constant intervals, and both sides are shielded by a ground level guard pattern. (7061). Such a clock line 706 obviously has a transmission characteristic different from that of the signal line, but in this method, the transmission characteristic of the signal line 703 and the clock line 706 may be different, so that no problem occurs. For this reason, there is an advantage that a sufficient shield can be applied to the clock line whose voltage constantly fluctuates, and noise caused by the clock can be reduced. It should be noted that since the transmission characteristics of the clock system and the signal system may be greatly different, it is needless to say that only the clock system can be configured to use a coaxial cable, an optical fiber, or the like.

  Thus, according to the signal transmission system according to the third aspect of the present invention, the degree of freedom of arrangement of the clock system and the signal system is high, and it is easy to minimize the gap when the elements are switched, A signal transmission system with low power consumption can be configured.

  Next, a signal transmission system according to the fourth embodiment of the present invention will be described in detail. First, the principle configuration of the fourth embodiment of the present invention will be described with reference to FIGS. 47 and 48. FIG. In the third embodiment described above, the forward and backward clocks are supplied to each DRAM chip and the like using the folded clock line (706). In the fourth embodiment, the forward and backward clocks are supplied. Clock wiring for clocks (forward and backward clock lines 1001 and 1002) and forward and backward clock generation circuits (forward and backward clock generation circuits 1100 and 1200) are used.

  FIG. 47 is a block diagram showing the principle configuration of the signal transmission system according to the fourth embodiment of the present invention, and FIG. 48 is a timing diagram for explaining the operation of the signal transmission system of FIG. In FIG. 47, reference numerals 10-1 to 10-n denote devices, for example, a DRAM chip (DRAM module) or a DRAM controller, 1100 is a forward clock generation circuit, and 1200 is a backward clock generation circuit. Show. FIG. 48 corresponds to FIG. 27 in the third embodiment of the present invention described above.

  As shown in FIG. 47, the signal transmission system according to the present invention includes a forward clock generation circuit 1100 (one or more sets) for generating a reciprocal clock for a set of signal lines (clock lines) 1001 and 1002. A backward clock generation circuit 1200 is provided. The devices 10-1 to 10-n that transmit and receive signals receive the forward clock φ1 from the forward clock generation circuit 1100 and the backward clock φ2 from the backward clock generation circuit 1200, and rise and rise of these clocks φ1 and φ2. An intermediate phase signal (common timing signal GMT: Global Mean Time) is generated by extracting the timing of the intermediate point of the fall.

  That is, as shown in FIG. 48, the device 10-1 has an intermediate phase between the forward clock φ1-1 transmitted via the clock line 1001 and the return clock φ2-1 transmitted via the clock line 1002. A common timing signal GMT is generated as a signal, and in the device 10-n, an intermediate phase between the forward clock φ1-n transmitted via the clock line 1001 and the return clock φ2-n transmitted via the clock line 1002 is obtained. The common timing signal GMT is generated as a signal having.

  Here, the backward clock generation circuit 1200 has a clock (unique phase) in which the timing of the intermediate point (intermediate phase) between the forward clock φ1 and the backward clock φ2 is uniquely extracted in each of the devices 10-1 to 10-n. φ2) needs to be generated. That is, the phase difference between the reciprocating clocks on the signal lines (clock lines) 1001 and 1002 (strictly, the phase difference between the forward and backward clocks φ1 and φ2 edges carrying the timing information) is predetermined. Is selected within the range (within ± 180 degrees at the maximum). Further, as will be described later, it is desirable that the backward clock generation circuit 1200 generates the backward clock φ2 so that the timing extraction at the intermediate point can be performed by a circuit as simple as possible.

  Then, according to the signal transmission system (signal transmission system) of the present invention, the common timing signal (GMT) with a certain accuracy can be obtained by removing intersymbol interference in each receiving circuit (devices 10-1 to 10-n). All elements can be used in common. Note that the above-mentioned constant accuracy is derived from allowing a timing error that can remove intersymbol interference, and is sufficiently smaller than the time required for a signal to be transmitted on a signal line (for example, 10 %) Time accuracy is sufficient. Further, in order to generate the common timing signal GMT, it is only necessary to have clock signals (1001, 1002) that run in both directions of the clock wiring route. As in the conventional signal transmission system shown in FIG. Since there is no need to match the electrical characteristics and routes of the line and the data line (signal transmission line), there are no restrictions on the arrangement and form of the clock line.

  Hereinafter, embodiments of the signal transmission system according to the fourth mode of the present invention will be described with reference to the drawings.

  FIG. 49 is a block diagram showing a first embodiment of the signal transmission system of the present invention. 49, reference numeral 10-0 is a chip such as a DRAM controller, 10-1 to 10-4 are chips such as a DRAM, 1100 is a forward clock generation circuit, and 1200 is a backward clock generation circuit. Reference numeral 1001 is a clock line for the forward clock φ1, 1002 is a clock line for the backward clock φ2, 1003 is a signal transmission path (a plurality of signal lines running in parallel: for example, 16 data lines), and , 1004 indicate clock lines for the reference clock clk.

  As shown in FIG. 49, the DRAM controller 10-0, the forward clock generation circuit 1100, and the backward clock generation circuit 1200 are connected to the reference clock (Free Running Clok from the terminals P1010, P1100, and P1200 of the clock line 1004 for the reference clock, respectively. : Free-running clock) clk, and the DRAM chips 10-1 to 10-4 receive the forward and backward clocks φ1 and φ2 via the forward and backward clock lines 1001 and 1002, respectively. By receiving φ2 and generating an intermediate phase signal, this is used as a common timing signal GMT (Global Mean Time). In FIG. 49, the reference clock clk is supplied to the DRAM controller 10-0 via the terminal P1010 of the clock line 1004 for the reference clock, but as with the DRAM chips 10-1 to 10-4, The DRAM controller 10-0 may be configured to generate the common timing signal GMT by receiving the forward clock φ1 and the backward clock φ2 and generating an intermediate phase signal.

  FIG. 50 is a block diagram showing an example of a common timing signal generation circuit 1300 applied to the signal transmission system of FIG. The common timing signal generation circuit 1300 is provided in each of the DRAM chips 10-1 to 10-4, for example. Reference symbol T indicates a clock cycle, and τ indicates a delay time (delay amount).

  As shown in FIG. 50, the common timing signal generation circuit 1300 receives a forward clock φ1 and provides a first variable delay circuit 1301 that gives a delay of + τ, and a second variable that receives a backward clock φ2 and gives a delay of −τ. The phase comparison circuit 1303 for comparing the phases of the output signals of the delay circuit 1302, the first and second variable delay circuits 1301 and 1302, and the comparison result of the phase comparison circuit 1303 (first and second variable The control circuit 1304 is configured to control the delay amounts (+ τ, −τ) of the first and second variable delay circuits 1301 and 1302 (so that the phase difference between the output signals of the delay circuits 1301 and 1302 becomes zero). ing. Here, as will be described later, the first and second variable delay circuits 1301 and 1302 are configured by a plurality of cascade-connected delay stages (delay units), and the control circuit 1304 causes a delay amount to a predetermined delay stage. Is to be given. The delay amount τ controlled by the control circuit 1304 is added to the clock cycle T in the first variable delay circuit 1301 (T + τ), and conversely, is subtracted from the clock cycle T in the second variable delay circuit 1302 (T− τ). The output signal (T + τ) of the first variable delay circuit 1302 is used as the common timing signal GMT.

As described above, the control circuit 1304 controls the delay amount τ so that the phase difference between the output signals of the first and second variable delay circuits 1301 and 1302 becomes zero (| τ | <T / 2). Here, if the output signal (GMT) of the first variable delay circuit 1301 is t1, and the output signal of the second variable delay circuit 1302 is t2,
t1 + (T + τ) = t2 + (T−τ)
From
τ = (t2−t1) / 2
Therefore,
t1 + (T + τ) = (t2 + t1) / 2 + T
Thus, intermediate timing can be obtained.

  FIG. 51 is a block diagram showing an example of the forward clock generation circuit 1100 applied to the signal transmission system of FIG.

  As shown in FIG. 51, the forward clock generation circuit 1100 that generates the forward clock φ1 can be configured by a driver 1101 that receives a reference clock (free running clock) clk supplied via a terminal P1100. .

  52 and 53 are block diagrams showing another example of the common timing signal generation circuit applied to the signal transmission system of FIG. 49, and FIG. 52 is a main DLL (Digital Locked Loop) portion of the common timing signal generation circuit 1300. 1300a, and FIG. 53 shows a sub DLL portion 1300b of the common timing signal generation circuit 1300.

  First, as shown in FIG. 52, the main DLL portion 1300a receives the forward clock φ1 (or the backward clock φ2), and phase-shifts the forward clock φ1 itself and the one delayed through the variable delay circuit 1305. Phase comparison is performed by the comparison circuit 1306, and control is performed via the control circuit 1307 so that the phase difference between the two signals is eliminated (that is, delayed by one period T). As a result, a delay T for one cycle of the clock (φ1, φ2) can be obtained.

  Further, by using the delay T (the number of delay stages corresponding to one period T) obtained by the main DLL portion 1300a of FIG. 52 described above, the time τ is added and subtracted by the sub DLL portion 1300b, respectively. The phase of the forward clock φ1 and the backward clock φ2 is adjusted.

  That is, as shown in FIG. 53, for the forward clock φ1, the first variable delay circuit 1301 adds a delay of τ to the delay T for one cycle (T + τ), and the return clock For φ2, the second variable delay circuit 1302 subtracts the delay of τ from the delay T for one cycle (T−τ). That is, similar to the common timing signal generation circuit 1300 of FIG. 50 described above, the phase comparison circuit 1303 outputs the output signal (T + τ) of the first variable delay circuit 1301 and the output signal (T−) of the second variable delay circuit 1302. The delay stage is selected via the control circuit 1304 so that the phase difference between these signals (T−τ, T + τ) becomes zero.

  FIG. 54 is a block diagram showing an example of a backward clock generation circuit 1200 applied to the signal transmission system of FIG.

  As shown in FIG. 54, the backward clock generation circuit 1200 that generates the backward clock φ2 receives the reference clock (free running clock) clk supplied via the terminal P1200, and gives a predetermined delay amount. A delay circuit 1201 can be used. Here, by setting the delay amount (delay time) given by the delay circuit 1201 to an appropriate value, for example, the phase difference between the round-trip clocks (φ1, φ2) on the clock line (1001, 1002) is ± 90 degrees. Within (preferably ± 45 degrees).

  FIG. 55 is a circuit diagram showing an example of a phase comparison circuit (phase comparison circuit 1303 in FIG. 50 and FIG. 48 (phase comparison circuit 1306 in FIG. 52)) applied to the common timing signal generation circuit of the signal transmission system in FIG. is there.

  As shown in FIG. 55, the phase comparison circuit 1303 includes, for example, two divide-by-2 units that halve the frequencies of the first and second input signals (T + τ, T-τ), and a plurality of P-channel types. It comprises a MOS transistor, a plurality of N-channel MOS transistors, a plurality of inverters, a plurality of NAND gates, and a plurality of NOR gates. Then, an output signal (/ DOWN, / UP) is output according to the phase difference between the first input signal φ1: T + τ and the second input signal φ2: T−τ, and a control circuit 1304 is described later. The delay time τ in the first and second variable delay circuits 1301 and 1302 is controlled via the first and second phase difference between the first and second input signals.

  56 is a block diagram showing an example of a control circuit (control circuit 1304 in FIG. 50 and FIG. 53 (control circuit 1307 in FIG. 52)) applied to the common timing signal generation circuit of the signal transmission system in FIG.

  As shown in FIG. 56, the control circuit 1304 includes, for example, an up / down counter (U / D counter) 1341, which receives a control signal (/ DOWN, / UP) from the phase comparison circuit 1303, and the U / D counter. The decoder 1342 is configured to receive the output signal 1341, and in response to the control signal (/ DOWN, / UP) from the phase comparison circuit 1303, the decoder 1342 performs a predetermined delay stage in the variable delay circuit of FIG. It comes to choose.

  57 shows a variable delay circuit (first and second variable delay circuits 1301 and 1302 in FIG. 50 and FIG. 53 (variable delay circuit 1305 in FIG. 52)) applied to the common timing signal generation circuit of the signal transmission system in FIG. ) Is a circuit diagram showing an example.

  As shown in FIG. 57, the first variable delay circuit 1301 (second variable delay circuit 1302) includes a plurality of delay stages (delay units) DU. Each delay unit DU includes an inverter and two NAND gates, and is connected to a delay line 1310 in common. The delay amount defined by any one delay unit DU selected by the decoder 1342 is given as the delay amount of the variable delay circuit. Of course, various known DLL circuit technologies can be applied to these configurations.

  FIG. 58 is a block diagram showing a second embodiment of the signal transmission system according to the fourth mode of the present invention.

  In the fourth embodiment of the present invention, the common timing signal GMT is generated by taking an intermediate timing of the round-trip clock signals (φ1, φ2). In order to uniquely generate the common timing signal GMT, The phase difference between the round trip clock signals needs to be within a certain limit. However, the phase difference between the reciprocating clock signals becomes difficult to keep the phase difference within a certain limit over the entire length of the clock line as the clock lines (1001, 1002) become longer. Therefore, in the second embodiment, the reciprocating clock lines (1011, 1021; 1012, 1022) are divided into lengths that allow the unique delivery of the common timing signal GMT, and the total length of the signal lines is long. The common timing signal GMT can be generated.

  That is, the second embodiment shown in FIG. 58 is different from the first embodiment shown in FIG. 49 in that a clock generation circuit and data buffers 1120, 1121, and 1122 are provided for each fixed distance, and each forward and backward clock is used. Forward and backward clocks φ11 and φ21; φ12 and φ22 are transmitted to the signal lines 1011 and 1021; 1012 and 1022, respectively, and data of sufficient amplitude is transmitted to the data lines 1031 and 1032. ing.

  Here, each clock generation circuit and the data buffers 1120, 1121, and 1122 generate a common timing signal GMT based on the clock sent from the previous block, and forward clocks for the next block from the common timing signal GMT. (And a return clock for the previous block).

  FIG. 59 is a block diagram showing a third embodiment of the signal transmission system according to the fourth mode of the present invention.

  In the third embodiment shown in FIG. 59, all the bus-connected data lines in FIG. 58 are connected in a point-to-point manner. In this case, clock generation circuits 1211, 1212, and 1213 for generating forward and backward clocks are provided for each of a plurality of devices (DRAM chips 10-11, 10-21, and 10-31), and other devices ( 10-1m, 10-2m, etc.), the common timing signal GMT is generated from the forward and backward clocks φ11, φ21; φ12, φ22 from the corresponding clock generation circuit to transmit and receive signals. The third embodiment is suitable for high-speed signal transmission because there is no reflection due to signal branching because the signal transmission is not in a bus format.

  FIG. 60 is a block diagram showing an example of the forward clock generation circuit applied to the signal transmission system as the fourth embodiment according to the fourth mode of the present invention. In FIG. 60, reference numeral 1102 denotes a driver, 1103 denotes a common timing signal generation circuit, 1104 denotes a phase comparison circuit, 1105 denotes a control circuit, and 1106 denotes a variable delay circuit.

  As shown in FIG. 60, in the fourth embodiment, the forward clock generation circuit 1100 is not composed of a simple driver 1101 as shown in FIG. 51, but a variable that receives a reference clock clk and gives a predetermined delay. The output signal of the delay circuit 1106 is output as the forward clock φ1 through the driver 1102, and the common timing signal generation circuit 1103 outputs the common timing signal (φ1) from the output signal (φ1) of the driver 1102 and the return clock φ2. (Intermediate phase signal) GMT is generated, the common timing signal and the reference clock clk are phase-compared by the phase comparison circuit 1104, and the delay amount (the number of delay stages) in the variable delay circuit 1106 is controlled via the control circuit 1105. It has become.

  That is, in the fourth embodiment, feedback is performed so that the common timing signal GMT coincides with the rising edge of the reference clock clk, and thereby the characteristics of the clock driver 1102 and the variable delay circuit 1106 vary in manufacturing or Even when the ambient temperature fluctuates, a stable phase return clock signal φ2 can be obtained, and a common timing signal GMT generated by a device (for example, a DRAM chip) on the signal line is a reference clock clk. It is comprised so that it may become the same timing. The reference clock clk is a clock signal supplied to a specific chip (for example, the DRAM controller 10-0).

  FIG. 61 is a block diagram showing an example of a backward clock generation circuit applied to the signal transmission system as the fifth embodiment according to the fourth mode of the present invention. 61, reference numeral 1231 is a variable delay circuit, 1232 is an operational amplifier, 1233 and 1234 are resistors and capacitors, 1235 is an inversion driver that inverts and outputs an input signal, 1236 is a phase comparison circuit, and 1237 is a control circuit. Is shown.

  As shown in FIG. 61, in the fifth embodiment, the return clock generation circuit 1200 is not configured by a simple delay circuit 1201 as shown in FIG. 54, but the return clock φ2 is received by the reference clock clk. As an output signal of the variable delay circuit 1231 giving a predetermined delay, the phase comparison circuit 1236 compares the output signal (φ2) of the variable delay circuit 1231 with the forward clock φ1 via the operational amplifier 1232 and the inverting driver 1235. It is supposed to be. Based on the phase comparison result, the delay amount (the number of delay stages) in the variable delay circuit 1231 is controlled via the control circuit 1237. Thus, the backward clock φ2 is output as a signal having a phase shifted (advanced) by 90 degrees from the phase of the forward clock φ1.

  As described above, according to the backward clock generating circuit 1200 of the fifth embodiment, the phase difference between the received forward clock φ1 and the backward clock φ2 is constant (the backward clock φ2 is 90% more than the forward clock φ1). Feedback control so that the characteristics of the clock driver (inversion driver 1235), variable delay circuit (1231), etc. fluctuate due to manufacturing variations, environmental temperature changes, etc. A return clock φ2 can be obtained. Here, the backward clock generation circuit 1200 configured using an analog circuit as shown in FIG. 61 is preferable because the circuit scale can be reduced when the variable range of the clock (φ2) is narrow.

  FIG. 62 is a block diagram showing another example of the backward clock generation circuit applied to the signal transmission system as the sixth embodiment according to the fourth mode of the present invention. In FIG. 62, reference numerals 1241 to 1244 denote variable delay circuits, 1245 denotes a phase comparison circuit, and 1246 denotes a control circuit. Here, the same delay amount is given to the four variable delay circuits 1241 to 1244 by the control circuit 1246.

  As shown in FIG. 62, in the sixth embodiment, the phase comparison circuit 1245 performs phase comparison between the forward clock φ1 and a signal obtained by delaying the forward clock φ1 by the four variable delay circuits 1241 to 1244, Since the same delay amount is given to the four variable delay circuits 1241 to 1244 by the control circuit 1246, the output clock of the third stage variable delay circuit 1243 is taken out as the return clock φ2, and thus the forward clock. A backward clock φ2 having a phase difference of 270 degrees (−90 degrees) with respect to φ1, that is, a phase advanced by 90 degrees from the forward clock φ1 is generated. As a result, it is possible to obtain a backward clock φ2 having a phase that does not depend on manufacturing variation of each circuit, temperature change, or the like. Here, the backward clock generation circuit 1200 configured using a DLL circuit as shown in FIG. 62 can cope with a case where the variable range of the clock (φ2) is wide.

  FIG. 63 is a diagram for explaining the operation (function) of the backward clock generation circuit 1200 applied to the signal transmission system as the seventh embodiment according to the fourth mode of the present invention. Here, the vertical axis θ represents the phase difference, and the horizontal axis x represents the position on the clock line (1001, 1002). Reference symbol L indicates the total length of the clock line.

  As shown in FIG. 63, in the seventh embodiment, any device (DRAM chip 10-1) in which the phase difference between the forward clock φ1 and the backward clock / φ2 (inverted signal of the clock φ2) is received. -10-n), it is ± 90 degrees or less. In other words, in this embodiment, the backward clock φ2 is inverted from the received forward clock φ1 with a phase advance sufficient to guarantee a phase delay in the clock line (1002). This function is realized, for example, by inverting the output of the feedback loop in the backward clock generation circuit shown in FIG.

  As described above, according to the seventh embodiment, since it is ensured that the phase difference between the reciprocating clock signals φ1 and φ2 is within a certain range, the common timing signal GMT is generated with high accuracy. Further, the influence of the common mode noise can be reduced by receiving the round-trip clock signals φ1 and φ2 by the differential receiving circuit.

  FIG. 64 is a block diagram showing still another example of the backward clock generation circuit applied to the signal transmission system as the eighth embodiment according to the fourth mode of the present invention.

  As shown in FIG. 64, in the eighth embodiment, the backward clock generation circuit 1200 includes an inversion driver 1205 that inverts and outputs an input signal (forward clock φ1).

  That is, for example, in the case of a short signal line in which the phase delay of the clock signal (φ1, φ2) in the clock receiving circuit, driver, clock line or the like does not become a problem, the backward clock generation circuit 1200 is connected by the inverting driver 1205. Thus, the circuit configuration of the backward clock generation circuit 1200 can be simplified.

  FIG. 65 is a block circuit diagram showing an example of a sine wave generating circuit applied to the signal transmission system as the ninth embodiment according to the fourth mode of the present invention. In the ninth embodiment, a sine wave (pseudo sine wave) is used as a clock, and a sine wave clock is generated from a pulsed (rectangular wave) clock (reference clock) clk by a sine wave generation circuit 1400. ing.

  As shown in FIG. 65, a sine wave generation circuit 1400 generates a triangular wave clock from a rectangular wave clock clk by a full amplitude CMOS circuit composed of P channel type MOS transistors 1401 and 1402 and N channel type MOS transistors 1403 and 1404. Further, a sine wave clock (pseudo sine wave clock) is generated by the non-linear amplifier 1405.

  In addition to the sine wave, a clock having a waveform such that a rising / falling time such as a triangular wave or a trapezoidal wave occupies a non-negligible ratio of the clock cycle may be used. Such a clock waveform (sinusoidal clock waveform) has an advantage that mutual interference with other signal lines can be reduced because there are fewer harmonic components than the rectangular wave clock waveform. Further, as shown in FIG. 67, there is an advantage that the common timing signal generation circuit 1300 provided in each device (DRAM chip or the like) can be configured by a differential comparator.

  FIG. 66 is a circuit diagram showing an example of the nonlinear amplifier 1405 in the sine wave generating circuit of FIG.

  As shown in FIG. 66, the nonlinear amplifier 1405 can be composed of P-channel MOS transistors 1451 to 1453 and N-channel MOS transistors 1454 to 146. Here, the size of each transistor is set to an appropriate size. For example, the gate lengths of the transistors 1451 and 1452 are about two times the gate lengths of the transistors 1454 and 1455, respectively. Are preferably larger than the gate lengths of the transistors 1451 and 1454, respectively. Note that the transistors 1453 and 1456 are defined according to the load to be driven, and are usually configured by large-sized transistors.

  FIG. 67 is a block diagram showing an example of a common timing signal generation circuit 1300 applied to the signal transmission system as the tenth embodiment according to the fourth mode of the present invention.

  As described above, for example, when a clock such as a sine wave is used, the common timing signal generation circuit 1300 provided in each device (DRAM chip or the like) 10 is connected to the forward and backward clocks φ1 and φ2 (/ φ2). A differential comparator 1308 as an input can be used.

That is, the reason that the common timing signal (intermediate timing) GMT can be generated by the differential comparator 1308 is that the forward clock φ1 and the inversion / φ2 of the backward clock are respectively φ1 = A · sin θ1, / φ2 = A · sin θ2. Then,
φ1- / φ2 = 2A · cos ((θ1-θ2) / 2) · sin ((θ1 + θ2) / 2)
And
If the value of (θ1−θ2) / 2 is within ± 90 degrees, it is possible to extract the common timing signal GMT (signal corresponding to the intermediate phase (θ1 + θ2) / 2) by comparing this signal. Recognize.

  FIG. 68 is a circuit diagram showing an example of the differential comparator 1308 in the common timing signal generation circuit of FIG.

  As shown in FIG. 68, the differential comparator 1308 is composed of P-channel MOS transistors 1380 and 1381 and N-channel MOS transistors 1385 to 1387, and the first differential amplification having N-type transistors 1385 and 1386 as inputs. , A P-channel MOS transistor 1382 to 1384 and N-channel MOS transistors 1388 and 1389, and a second differential amplification unit having P-type transistors 1383 and 1384 as inputs, and a buffer unit 1390. . Here, the buffer unit 1390 includes inverters 1391 to 1393 connected in cascade.

  As described above, the common timing signal generation circuit 1300 can be configured by the differential comparator 1308 having a simple circuit configuration without using a DLL circuit having a large circuit scale.

  FIG. 69 is a block diagram showing an example of a termination resistor in the signal transmission system as the eleventh embodiment according to the fourth mode of the present invention.

  In the eleventh embodiment, a sine wave is used as the waveform of the forward and backward clocks φ1 and φ2, and the end of the clock line 1001 that transmits the forward clock φ1 is connected to the characteristic impedance of the clock line (for example, 50 Terminated by a termination resistor 1501 having a resistance value (for example, 200 ohms) greater than ohms or 75 ohms, and similarly, the termination of the clock line 1002 that transmits the return clock φ2 is connected to the characteristic impedance of the clock line. It is terminated by a terminating resistor 1502 having a resistance value (for example, 200 ohms) greater than (for example, 50 ohms or 75 ohms).

  In the eleventh embodiment, the resistance values of the termination resistors 1501 and 1502 are made larger than the characteristic impedances of the clock lines 1001 and 1002, but the forward and backward clocks φ1 and φ2 are sinusoidal clocks. Even if the termination resistors 1501 and 1502 deviate greatly from the characteristic impedance, the clock waveform remains a sine wave. Further, the propagation characteristics of the waves (forward and backward clocks φ1, φ2) are different from the characteristics of the signal lines (clock lines 1001, 1002) due to the reflection of the line, but the intermediate timing of the round-trip clock (common) When extracting the timing signal GMT), no problem occurs. Then, by making the resistance values of the termination resistors 1501 and 1502 larger than the characteristic impedance of the clock lines 1001 and 1002, the power consumed by the termination resistors 1501 and 1502 (power consumption in the clock system) can be reduced. it can.

  FIG. 70 is a block diagram for explaining a forward clock supply method in a signal transmission system as a 12th embodiment according to the fourth mode of the present invention.

  In the twelfth embodiment, since the forward clock line is set to differential transmission (1001a, 1001b) and the complementary forward clocks φ1, / φ1 are transmitted, the backward signal generation circuit 1200 uses the forward clock as the forward clock. The return clock φ2 can be generated while reducing the influence of the mixed common mode noise. That is, the return signal generation circuit 1200 includes a differential comparator 1261 and a return clock generation unit 1262 (and a buffer 1263) to which complementary forward clocks φ1 and / φ1 are input.

  Here, the common timing signal generation circuit 1300 provided in each device (DRAM chip or the like) can be configured as a differential comparator 1308 for generating the common timing signal GMT described with reference to FIG. At this time, one of the complementary forward clocks φ1 and / φ1 (true signal φ1) and the backward clock φ2 are input to the differential comparator 1308. In this case as well, the influence of the common-mode noise can be reduced. It becomes possible.

  FIG. 71 is a block diagram showing a main part when the signal transmission system as the thirteenth embodiment according to the fourth mode of the present invention is applied to a printed circuit board.

  As shown in FIG. 71, in the thirteenth embodiment, a plurality of signal generation circuits (forward clock generation circuit 1100 and backward clock generation circuit 1200) 1270 are provided on a printed circuit board, and in each of these signal generation circuits 1270, The forward clock φ1 and the backward clock φ2 are generated using a reference clock (free running clock) clk running on the printed circuit board. That is, each signal generation circuit 1270 includes a variable delay circuit 1273 for a forward clock, a variable delay circuit 1272 for a backward clock, and a control circuit 1270. The reference clock clk is generated by the variable delay circuits 1273 and 1272. By delaying according to the control circuit 1270, the forward clock φ1 and the backward clock φ2 are generated, respectively.

  That is, as in the second embodiment shown in FIG. 58 described above, when the subsequent clock is sequentially generated from the previous clock (φ1, φ2), the jitter at the delay stage increases as the number of stages is increased. For example, with respect to a large number of signal generation circuits 1270 on the printed circuit board, the configuration as in the thirteenth embodiment shown in FIG. 71 can eliminate the accumulation of jitter.

  FIG. 72 is a block diagram showing a main part when the signal transmission system as the fourteenth embodiment according to the fourth mode of the present invention is applied to a semiconductor integrated circuit.

  As shown in FIG. 72, in the fourteenth embodiment, for example, in a semiconductor integrated circuit (semiconductor chip), signals (forward clock φ1 and return) supplied to a common timing signal generation circuit 1300 that generates a common timing signal GMT. Instead of using the output of the forward clock generation circuit (clock driver) 1100 as it is, the forward clock φ1 output via the pad 1281 is taken into the common timing signal generation circuit 1300 via the pad 1282. The common timing signal GMT is generated by compensating the phase difference of the clock (φ1) generated by the clock driver and the pad by comparing with the return clock φ2 supplied through the pad 1283. Here, the position (IP0) at which the forward clock φ1 output via the pad 1281 is taken in via the pad 1282 is output to the clock line (1001) via the pad 1281 and a predetermined external terminal (package terminal). The clock signal (φ1) thus obtained may be taken into the chip (circuit) again via another external terminal and the pad 1282, but an extra dedicated external terminal is required, so that the wire is not increased without increasing the number of external terminals. The clock signal may be captured by performing only bonding or the like.

  As described above, according to the signal transmission system of the fourth embodiment of the present invention, it is easy to improve the freedom of arrangement of the clock system and the signal system and minimize the gap when the elements are switched. In addition, a signal transmission system with low power consumption can be configured.

  Next, a fifth embodiment of the present invention will be described in detail. First, a conventional technique corresponding to the fifth embodiment of the present invention and problems in the conventional technique will be described with reference to the drawings.

  FIG. 73 is a block diagram schematically showing an example of a conventional semiconductor memory device corresponding to the fifth embodiment of the present invention. 73, reference numeral 2001 is a memory cell array, 2002 is a word decoder (word decoder string), 2003 is a sense amplifier (sense amplifier string), 2004 is a local data bus, 2005 is a global data bus, 2006 is a data bus amplifier, 2007 Indicates a local data bus precharge circuit, 2008 indicates a global data bus precharge circuit, 2009 indicates a local bus switch, and 2010 indicates a write amplifier.

  As shown in FIG. 73, a conventional semiconductor memory device (DRAM memory cell array unit) includes a plurality of memory arrays 2001, a word decoder (word decoder column) 2002, a sense amplifier (sense amplifier column) 2003, and a local data bus 2004. And a global data bus 2005 is provided. Further, the conventional semiconductor memory device pre-charges the data bus amplifier 2006 that amplifies data on the global data bus 2005 at the time of data read, the local data bus precharge circuit 2007 that precharges the local data bus 2004, and the global data bus 2005. A global data bus precharge circuit 2008, a local bus switch 2009 for controlling connection between the global data bus 2005 and the local data bus 2004, and a write amplifier 2010 for writing data to the memory cell.

  FIG. 74 is a circuit diagram showing an example of the sense amplifier 2003 in the semiconductor memory device of FIG.

  As shown in FIG. 74, the sense amplifier 2003 includes a latch-type sense amplifier (latch-type sense amplifier unit) 2031, a column transfer gate 2032, a column line short precharge circuit 2033, and a bit line transfer gate 2034. It is configured. Here, reference symbols BL and / BL indicate bit lines, and CL indicates a column selection line.

  75 is a circuit diagram showing an example of the data bus amplifier 2006 in the semiconductor memory device of FIG. 73. FIG. 76 is a data bus short precharge circuit (global data bus precharge circuit 2008) in the semiconductor memory device of FIG. It is a circuit diagram which shows an example of (local data bus precharge circuit 2007).

  As shown in FIGS. 75 and 76, the data bus amplifier 2006 and the global data bus precharge circuit 2008 (local data bus precharge circuit 2007) include a plurality of P-channel MOS transistors and N-channel MOS transistors, respectively. It is comprised by. Here, reference symbols DB and / DB denote data buses, PRE and / PRE denote precharge control signals, Vpr denotes a precharge reference voltage, and ES denotes an enable signal.

  FIG. 77 is a timing chart for explaining an example of a data read (burst read) sequence in the semiconductor memory device of FIG. Here, FIG. 77 shows a case where the output becomes a high level “H” when the data bus amplifier 2006 is disabled. Note that burst read is a method employed in, for example, synchronous DRAM (SDRAM), in which data of memory cells connected to one word line is read continuously.

  As shown in FIG. 77, in a burst read process of data in a conventional semiconductor memory device, for example, complementary data buses DB, / DB, complementary bit lines BL, / BL (BL0, / BL0 to BL3, / BL3 ), The bit lines BL, / BL and the data buses DB, / DB are first precharged to a predetermined level (precharge reference voltage Vpr). In particular, the complementary bit lines or the complementary data buses are , Precharge to the same potential as the pairing partner.

  Further, as shown in FIGS. 74 and 77, when data is read, when data appears on the bit line pair BL, / BL (BL0, / BL0 to BL3, / BL3), the bit having the same potential is thereby generated. A difference potential is generated in the line pair BL, / BL, and this difference potential is amplified to some extent by the sense amplifier 2003 (latch type sense amplifier unit 2031), and then the column transfer gate 2032 corresponding to the selected column address is opened. That is, by sequentially applying the column selection signals CL0 to CL3, the potentials of the bit line pairs BL0, / BL0 to BL3, / BL3 are precharged and the local data bus pair DB, / DB which is initially at the same potential. (2004). This difference potential is pre-charged via the local data bus switch 2009 and transferred to the global data bus pair DB, / DB (2005), which was initially at the same potential, and the global data bus amplifier (data bus amplifier 2006). ) And then output to the outside as read data (read data) through a buffer or other amplifier.

  When the next data is read, the system is initialized by precharging the local data bus (pair) 2004 and the global data bus (pair) 2005 while the sense amplifier 2003 is activated, and then the column transfer gate 2032. The difference potential is transmitted to the local data bus 2004 and the global data bus 2005, amplified by the global data bus amplifier 2006, and the read data is output to the outside in the same manner.

  Here, as shown in FIG. 77, the bus precharge in the operation of the memory (semiconductor memory device), that is, the initialization operation must be performed for each read data. However, when data is output in synchronization with the clock, these buses usually have a heavy capacity and take a long time to precharge. For example, about half of the clock period is the bus precharge time.

  In the fifth embodiment of the present invention, the above-described precharge time is eliminated and the data transfer rate is increased to twice or more. In other words, speeding up with the development of device process technology can take many years just by doubling the clock, but by removing the precharge time that was essentially indispensable with conventional methods. The purpose is to increase the data transfer rate.

  Therefore, in the fifth embodiment of the present invention, for example, by improving the signal transmission system (data bus driving method, global data bus amplifier method, etc.) in the semiconductor memory device, the read sequence of the semiconductor memory device is fundamentally improved. In other words, the data transfer rate is increased by removing the bus precharge time from the read cycle. Furthermore, in the conventional technique, the selection of each column transfer gate must be completely separated in time. However, according to the fifth aspect of the present invention, the selection of each column selection gate in terms of time. Can be overlapped. As a result, the data rate read from the memory can be dramatically increased by setting the precharge time to zero and overlapping the column selection gates.

  Therefore, the above-described PRD (Partial Response Detection) method is adopted for data transfer on the data bus. For PRD, H.Tamura et al., “Partial Response Detection Technique for Driver Power Reduction in High-Speed Memory-to-Processor Comunications”, which showed an interface method for speeding up data transmission between chips, Reference is made to 1997 IEEE International Solid-State Conference, ISSC97 / SESSION 20 / CLOCKING AND I / O / PAPER SA 20.7, pp342-343.

  Here, as described above, the PRD scheme means that when a signal exceeding a band is transmitted to a band-limited transmission path, the signal is disturbed by the intersymbol interference component of the signal. This is a method of reproducing a disturbed signal by removing the signal. This PRD method removes the intersymbol interference component and at the same time creates a reference level by itself in the process of removing the intersymbol interference component, so that data can be transmitted without precharging the transmission path as a hidden characteristic. It becomes possible. Therefore, the characteristic that data can be transferred without precharge is applied to the removal of the data bus precharge time from the data read cycle.

  In addition, when the PRD method is used, even if data of the previous cycle remains on the transmission line, if the next data arrives after the previous data reaches the receiving side, a certain amount of data overlaps. Is also allowed. That is, if this characteristic is used, when applied to a memory bus, a certain degree of overlap of column selection gates is allowed. In addition, the PRD method reduces the bus amplitude and can eliminate (but does not have to eliminate) precharge in principle, so that it is possible to reduce power consumption due to bus charge / discharge. . Further, the data rate can be increased by a circuit ingenuity by the PRD method, and it is not necessary to make a major change to the core portion (sense amplifier, memory cell array, word decoder, etc.) of the conventional memory.

  78 is a block diagram showing a first principle configuration of a signal transmission system according to the fifth mode of the present invention, and FIG. 79 is a waveform diagram for explaining the operation of the signal transmission system of FIG. FIG. 78 shows a signal transmission method using PRD that does not require precharging.

  In FIG. 78, reference numeral 2100 denotes a driver, 2200 denotes a floating bus (signal transmission path), and 2300 denotes a PRD bus amplifier (PRD data bus amplifier). Here, in the PRD method, there is no need to make the bus 2200 fully swing. Therefore, the driver 2100 may have a sufficiently small driving force. In the case of the first principle (first principle of the fifth mode), The waveform of the signal is as shown in FIG. In FIG. 79, reference symbol A indicates the waveform of the output signal of the driver 2100, B indicates the waveform of the input signal of the PRD bus amplifier 2300, and C indicates the waveform of the output signal of the PRD bus amplifier 2300.

  As shown in FIG. 79, since the driving force of the driver 2100 is reduced, the input waveform (B) of the PRD system bus amplifier 2300 is disturbed, but the PRD system bus amplifier 2300 is a PRD system. The reproduced output waveform (C) corresponds to the output waveform (A) of the driver 2100.

  That is, according to the first principle, the data output from the driver 2100 does not fully swing, and the signal on the receiving side (PRD bus amplifier 2300) does not necessarily have a certain threshold level. It can be seen that the data can be accurately reproduced by the PRD bus amplifier 2300 even if the level does not change such as high (High) or low (Low). In this first principle, since no precharge circuit is provided, the state before the data transmission (signal transmission) is in the state at the end of the previous data transmission. The level 2200 holds the state at the end of data transmission.

  80 is a block diagram showing a second principle configuration of the signal transmission system according to the fifth mode of the present invention, and FIG. 81 is a waveform diagram for explaining the operation of the signal transmission system of FIG. In the second principle shown in FIG. 80, a precharge circuit 2400 is added to the signal transmission system of the first principle shown in FIG.

  As described above, in the PRD method, it is not necessary to perform precharge. For example, when the bus 2200 is not moving, it is fixed at a certain level rather than being placed at a halfway level. May be preferred. Therefore, in the second principle, as shown in FIG. 81, when the bus 2200 is not moving, before starting to move or after moving, the bus 2200 is set to a certain level (precharge level). A precharge circuit 2400 is added.

  82 is a block diagram showing a third principle configuration of the signal transmission system according to the fifth mode of the present invention, and FIGS. 83 and 84 are waveform diagrams for explaining the operation of the signal transmission system of FIG. is there. In the third principle shown in FIG. 82, a load 2500 is further added to the signal transmission system of the second principle shown in FIG.

  In the third principle, for example, when the driving force of the driver 2100 output to the high level “H” and the low level “L” is asymmetric, or for some reason, the level of the bus 2200 gradually decreases during operation. In the case of shifting to the level “L” side or the high level “H” side, a load 2500 is provided for the purpose of suppressing the shift.

  FIG. 83 shows a waveform when the level of the bus 2200 (level B of the input signal of the PRD system bus amplifier 2300) is shifted to the low level “L” when the load 2500 is not provided, and FIG. Shows a waveform in which the shift is suppressed when the load 2500 is provided according to the third principle.

  Actually, when the PRD method is used, there is no problem in reading data even when the signal shifts toward a certain level and sticks to that level. However, as in the third principle, By adding the load 2500, it is possible to increase the operation margin of the PRD system bus amplifier 2300 when the level of the bus 2200 sticks to a certain level.

  FIG. 85 is a block diagram schematically showing an example of a semiconductor memory device to which the signal transmission system according to the fifth mode of the present invention is applied. 85, reference numeral 2001 is a memory cell array, 2002 is a word decoder (word decoder string), 2100 is a sense amplifier (sense amplifier string), 2201 is a local data bus, 2202 is a global data bus, and 2300 is a PRD data bus amplifier. 2401 is a local data bus precharge circuit, 2402 is a global data bus precharge circuit, 2009 is a local bus switch, 2010 is a write amplifier, and 2500 is a load.

  As shown in FIG. 85, the semiconductor memory device (DRAM memory cell array portion) to which the fifth embodiment of the present invention is applied includes a plurality of memory arrays 2001, a word decoder (word decoder string) 2002, a sense amplifier (sense amplifier). Column) 2100, a local data bus 2201, and a global data bus 2202. Further, the semiconductor memory device precharges the PRD data bus amplifier 2300 that amplifies the data on the global data bus 2202 when reading data, the local data bus precharge circuit 2401 that precharges the local data bus 2201, and the global data bus 2202. A global data bus precharge circuit 2402, a local bus switch 2009 for controlling connection between the global data bus 2202 and the local data bus 2201, a write amplifier 2010 for writing data to the memory cell, and a load 2500. .

  Here, local data bus 2201 and global data bus 2202 in FIG. 85 correspond to local data bus 2004 and global data bus 2005 in FIG. 73 described above, and local data bus precharge circuit 2401 and global data bus in FIG. The data bus precharge circuit 2402 corresponds to the local data bus precharge circuit 2007 and the global data bus precharge circuit 2008 in FIG. 73 described above. In the semiconductor memory device of FIG. 85, the data bus amplifier 2006 in FIG. 73 is configured as a PRD data bus amplifier 2300, and in the semiconductor memory device of FIG. 85, a load 2500 is provided on the global data bus 2202. Yes.

  85 and the principle of the fifth embodiment (FIGS. 78, 80, and 82) described above, the sense amplifier 2100 serves as a driver, the local data bus 2201 and the global data bus 2202 are buses, and global data A bus amplifier (PRD data bus amplifier) 2300 corresponds to the PRD bus amplifier. Here, in this specification (FIG. 85 and the like), the bus is divided into a local data bus and a global data bus. However, it is not essential that the bus is identified by another name. 85, a precharge circuit (local data bus / precharge circuit 2401 and global data bus / precharge circuit 2402) and a load 2500 are provided corresponding to the third principle of FIG. With the semiconductor memory device having such a configuration, it is possible to perform data reading without precharge during the above-described read cycle.

  FIG. 86 is a block diagram schematically showing the main part of the first embodiment of the signal transmission system according to the fifth mode of the present invention. The first principle configuration of FIG. 78 described above (providing a precharge circuit and a load) is shown. Is not supported).

  86, reference numeral 2100 is a driver (corresponding to the sense amplifier in FIG. 85), 2200 is a thimble end bus (signal transmission path), and 2300 is a PRD bus amplifier (corresponding to the PRD data bus amplifier in FIG. 85). ). In FIG. 86, reference symbol A indicates the waveform of the output signal of the driver 2100, B indicates the waveform of the input signal of the PRD bus amplifier 2300, and C indicates the waveform of the output signal of the PRD bus amplifier 2300.

  87 is a circuit diagram showing a configuration example of the driver and the bus amplifier in the signal transmission system of FIG. 86. FIGS. 87 (a) and 87 (b) show a circuit example of the driver 2100, and FIG. ) Shows a circuit example of the PRD bus amplifier 2300.

  As shown in FIG. 87 (a), the driver 2100 can be simply constituted by an inverter that inverts and amplifies input data (Din), but as shown in FIG. 87 (b), the driver 2100 is enabled. A circuit having a high impedance state (High-Z state) using a signal (/ EN) can also be configured.

  As shown in FIG. 87 (c), the PRD bus amplifier 2300 includes control signals (φ1, / φ1; φ2, / φ2; φ1 ′, / φ1 ′; φ1 ″, / φ1 ″; φ2 ′, / φ2 '; Φ2 ″, / φ2 ″), and a plurality of transfer gates, inverters, and capacitors (C1a, C2a; C1b, C2b) that are switching-controlled. That is, the PRD system bus amplifier 2300 in FIG. 87 (c) is a system that performs interleaving with a set of two, and includes PRD blocks 2300a and 2300b.

  88 is a diagram showing an example of a signal waveform for operating the bus amplifier of FIG. 87, and FIG. 89 is a diagram showing an example of a bus operation waveform in the signal transmission system of FIG.

  The PRD bus amplifier 2300 in FIG. 87 (c) is driven by a signal as shown in FIG. Here, the control signals φ1 ′, φ1 ″ and φ2 ′, φ2 ″ have substantially the same waveforms (slightly different timing) as the control signals φ1 and φ2, and are used as clocks to drive the PRD blocks 2300a and 2300b in an interleaved manner. The signals are output at synchronized alternate timings (rising and falling timings of the clock CLK). That is, while one PRD block (for example, 2300a) is performing calculation for removing (estimating) the intersymbol interference component for data at the next clock, the other PRD block (for example, 2300b) ) Receives data and outputs an output signal, which is alternately performed to reproduce data at high speed.

  In the operation waveform of the first example (first example of the fifth mode) shown in FIG. 89, the output signal (A) from the driver 2100, the signal (B) received by the PRD system bus amplifier 2300, and A signal (C) output from the PRD bus amplifier 2300 is shown, and specifically, an example of data transfer at 500 Mbps is shown. Thus, according to the first embodiment, it can be seen that the data can be accurately reproduced by the PRD bus amplifier 2300 without full swinging the data output from the driver 2100. In the first embodiment, since the data bus (2200) is not precharged, it is at an unspecified level when data is not transferred. Nevertheless, high-speed data transfer is possible. . In addition, since signal transmission can send data while reducing the amount of change in the bus level due to data per bit, the bus transmission can be substantially reduced, so that power consumption of the bus can also be reduced.

  FIG. 90 is a block diagram schematically showing a main part of the second embodiment of the signal transmission system according to the fifth mode of the present invention. A precharge circuit 2400 is further added to the first embodiment shown in FIG. This corresponds to the above-described second principle configuration (provided with a precharge circuit) in FIG.

  In the second embodiment shown in FIG. 90, precharge is performed by the precharge circuit 2400 when data is not transferred. Here, in the second embodiment, precharge is not performed during data transfer. However, if there is a time allowance for precharge time, data transfer is temporarily stopped and precharge circuit 2400 performs precharge. It can also be configured as follows. However, precharging every bit as in the prior art is not preferable in terms of data transfer efficiency.

  In the second embodiment, the data transfer starts from the precharge level and returns to the precharge level even after the transfer is completed. Therefore, the initial level of the bus 2200 is known, and there are design problems in other parts. Even in such a case, the problem can be easily analyzed. Even when the overall level of the bus 2200 gradually moves to a certain level, the level is returned to the precharge level when not at the time of data transfer, so that there is little sticking to that level. Here, the meaning of “less” means that if data reading is continued for a very long time, it may be stuck, and there is almost no problem in a normal reading operation. Even if the bus 2200 sticks to a certain level, it is possible to transfer data as in the first embodiment.

  FIG. 91 is a circuit diagram showing an example of a precharge circuit in the signal transmission system of FIG. The driver 2100 and the PRD bus amplifier 2300 can be the same as those in the first embodiment.

  As shown in FIG. 91, the precharge circuit 2500 is constituted by a transfer gate, and precharges the bus 2200 by applying a precharge level (Vpr) by the precharge control signals pre and / pre. Yes.

  FIG. 92 is a diagram showing an example of signal waveforms for operating the bus and the bus amplifier in the signal transmission system of FIG. Here, in the signal waveform diagram of FIG. 92, reference symbol (I) indicates a method for precharging the bus 2200 when data is not transmitted, and (II) is for precharging the bus 2200 only before and after data transmission. The method is shown. That is, FIG. 92 (I) shows a sequence in which precharging is continued when data is not transferred, and FIG. 92 (II) is that precharging is performed only before and after data transfer. The sequence which makes a floating state is shown.

  FIG. 93 is a diagram showing an example of bus operation waveforms in the signal transmission system of FIG. As shown in FIG. 93, according to the second embodiment, for example, the level of the bus 2200 is returned to the precharge level (Vpr) before and after data transfer.

  FIG. 94 is a block diagram schematically showing an essential part of a third embodiment of the signal transmission system according to the fifth mode of the present invention.

  As is apparent from the comparison between FIG. 94 and FIG. 86, the third embodiment is configured such that the single-ended bus 2200 in the first embodiment shown in FIG. 86 is configured as a complementary bus 2200 ′ (bus, / bus). A signal transmission system is configured by a driver 2100 ′ corresponding to the complementary bus 2200 ′ and a PRD system bus amplifier (PRD system complementary differential bus amplifier) 2300 ′.

  FIG. 95 is a diagram showing a configuration example of drivers and bus amplifiers in the signal transmission system of FIG. 94. FIGS. 95 (a) and 95 (b) show circuit examples of the driver 2100 ′, and FIG. ) Shows a circuit example of a PRD system bus amplifier (PRD system complementary differential bus amplifier) 2300 ′.

  As shown in FIG. 95 (a), the driver 2100 ′ can be simply constituted by a pair of inverters that invert and amplify the complementary data (Din, / Din) to be inputted. As shown in b), it can be configured as a circuit that generates complementary output signals A and / A from an input signal (positive logic input signal) Din.

  As shown in FIG. 95C, the PRD type complementary differential bus amplifier 2300 'includes first and second PRD amplifiers 2310 and 2320, and a latch type amplifier 2330. The first PRD amplifier 2310 receives the positive logic input signal B and supplies the output signal D to the latch amplifier 2330, and the second PRD amplifier 2320 receives and outputs the negative logic input signal / B. The signal E is supplied to the latch amplifier 2330.

  FIG. 96 is a circuit diagram showing an example of a PRD amplifier and a latch type amplifier in the bus amplifier (PRD type complementary differential bus amplifier) of FIG. 95 (c), and FIG. 96 (a) shows a PRD amplifier (first and first amplifiers). 2 PRD amplifiers 2310 and 2320), and FIG. 96B shows a circuit example of the latch-type amplifier 2330.

  As is apparent from a comparison between FIG. 96A and FIG. 87C, the first PRD amplifier 2310 (second PRD amplifier 2320) is a PRD bus for the single-ended bus of FIG. 87C. The configuration is the same as that of the amplifier 2300. Also, as shown in FIG. 96 (b), the latch-type amplifier 2330 receives the output signals D and E of the first and second PRD amplifiers 2310 and 2320 and outputs complementary output signals C and / C. It is like that. Thus, by making the data transmission system complementary, it becomes possible to reduce the influence of common mode noise and detect smaller signal changes. However, the circuit scale of the PRD type complementary differential bus amplifier 2300 'etc. becomes large.

  Note that the above-described circuits of the driver 2100 ′ and the PRD complementary differential bus amplifier 2300 ′ are merely examples, and it goes without saying that various other circuits can be applied as long as they can output complementary signals. Nor.

  FIG. 97 is a diagram showing an example of signal waveforms for operating the bus amplifier of FIG. 95, and FIG. 98 is a diagram showing an example of operation waveforms of the bus and bus amplifier in the signal transmission system of FIG.

  As shown in FIG. 97, control signals φ1, φ2 (φ1 ′, φ2 ′; φ1 ″, φ2 ″) are applied to clock CLK in order to interleave drive PRD blocks 2300a and 2300b, similarly to FIG. 88 described above. It is output at synchronized alternate timings.

  As shown in FIG. 98, in the third embodiment, the output signals (A, / A) of the driver 2100 ′ corresponding to the waveform in the first embodiment shown in FIG. The signals (B, / B) received by the system complementary differential bus amplifier 2300 ′ and the signals (C, / C) output by the PRD system complementary differential bus amplifier 2300 ′ are obtained. As described above, according to the third embodiment, it is understood that the data can be accurately reproduced by the PRD type complementary differential bus amplifier 2300 'without full swinging the data output from the driver 2100'.

  FIG. 99 is a block diagram schematically showing an essential part of a fourth embodiment of the signal transmission system according to the fifth mode of the present invention.

  In the fourth embodiment shown in FIG. 99, a precharge circuit 2400 ′ is added to the third embodiment shown in FIG. 94, and the PRD complementary differential bus amplifier 2300 ″ has a positive logic output. Only the signal (C) is output.

  FIG. 100 is a diagram showing a configuration example of a precharge circuit and a bus amplifier in the signal transmission system of FIG. 99, FIG. 100 (a) shows a circuit example of the precharge circuit 2400 ′, and FIG. A circuit example of a PRD type complementary differential bus amplifier 2300 "is shown.

  As shown in FIG. 100A, the precharge circuit 2500 ′ is composed of a plurality of transistors, and short-circuits the complementary buses bus and / bus (2200 ′) by the precharge control signals PRE and / PRE. A precharge level (Vpr) is applied.

  As shown in FIG. 100B, the PRD type complementary differential bus amplifier 2300 ″ includes first and second PRD amplifiers 2310 and 2320, and a current mirror type amplifier 2340. The first PRD amplifier 2310 receives the positive logic input signal B and supplies the output signal D to the current mirror type amplifier 2340, and the second PRD amplifier 2320 receives the negative logic input signal / B. The output signal E is supplied to the current mirror type amplifier 2340.

  101 is a circuit diagram showing an example of a PRD amplifier and a current mirror type amplifier in the bus amplifier (PRD type complementary differential bus amplifier) of FIG. 100, and FIG. 101 (a) shows a PRD amplifier (first and second amplifiers). A circuit example of the PRD amplifiers 2310 and 2320) is shown, and FIG. 101B shows a circuit example of the current mirror type amplifier 2340.

  As is clear from the comparison between FIG. 101A and FIG. 87C, the first PRD amplifier 2310 (second PRD amplifier 2320) is a PRD bus for the single-ended bus of FIG. 87C. The configuration is the same as that of the amplifier 2300. Further, as shown in FIG. 101 (b), the current mirror type amplifier 2340 receives the output signals D and E of the first and second PRD amplifiers 2310 and 2320, and outputs the output signal (positive logic signal) C. It is designed to output. Note that an enable signal en (/ en) is supplied to each control transistor of the current mirror type amplifier 2340.

  Thus, by using the complementary current mirror amplifier 2340, it is possible to reduce the influence of the common mode noise and detect a smaller signal change. However, the circuit scale of the current mirror type amplifier 2340 becomes large.

  FIG. 102 is a diagram showing an example of signal waveforms for operating the bus amplifier of FIG.

  As shown in FIG. 102, control signals φ1, φ2 (φ1 ′, φ2 ′; φ1 ″, φ2 ″) are supplied to clock CLK in order to interleave drive PRD blocks 2300a and 2300b, similarly to FIG. 88 described above. It is output at synchronized alternate timings. Further, the precharge control signal PRE is at a high level “H” (/ PRE is at a low level “L”) during a period other than when the bus 2200 ′ is moving (data is transferred), and the bus 2200 ′. Is precharged. The enable signal en supplied to the current mirror type amplifier 2340 becomes a high level “H” (/ en is a low level “L”) at the time of data transfer, and activates the current mirror type amplifier 2340 to generate data (C ) Is output.

  FIG. 103 is a diagram showing an example of operation waveforms of the bus and bus amplifier in the signal transmission system of FIG.

  As shown in FIG. 103, according to the fourth embodiment, the complementary signal (A, / A) output from the driver 2100 ′ is transmitted through the complementary bus 2200 ′, and the PRD type complementary type is transmitted. It can be seen that the differential bus amplifier 2300 ′ receives the complementary signals (B, / B) and outputs a signal (positive logic signal C). In the fourth embodiment, since the precharge circuit 2400 ′ is provided, the input signals (B, / B) of the PRD type complementary differential bus amplifier 2300 ′ before and after the data transfer are Level (precharge level Vpr).

  Here, the fourth embodiment (fourth embodiment of the fifth mode) consumes more power than the third embodiment described above, but can operate at a higher speed. In the third and fourth embodiments, the intersymbol interference component is once removed by the single-end type PRD buffer, and a certain amount of amplification is performed. Therefore, the input offset which is a complementary amplifier defect is It will not be a problem. The complementary input differential current mirror type amplifier is not limited to that shown in FIG. 101B, and various types of amplifiers can be used as long as the differential input can be amplified.

  FIG. 104 is a block diagram schematically showing an essential part of the fifth embodiment of the signal transmission system according to the fifth mode of the present invention, and the basic configuration corresponds to the above-described fourth embodiment. . That is, the fifth embodiment is characterized by the PRD type complementary differential bus amplifier 2300 ″.

  FIG. 105 is a block circuit diagram showing the main part of an example of the bus amplifier in the signal transmission system of FIG. 104, and shows a circuit example of the PRD type complementary differential bus amplifier 2300 ″.

  The PRD complementary differential bus amplifier 2300 ′ in the third and fourth embodiments described above is input to the complementary amplifier after the single-ended PRD bus amplifier, but in the fifth embodiment, The PRD type complementary differential bus amplifier 2300 ″ is a differential amplifier 2303 and an amplifier node for the input node of the differential amplifier 2303 after the PRD function portion 2301 composed of capacitors (capacitors C10a and C20a; C10b and C20b). The PRD type complementary differential bus amplifier 2300 "is also provided with a precharge circuit 2302. The two amplifiers (meaning having two main parts) are alternately switched to reproduce data at high speed. Perform amplification.

  Here, assuming that the values of the capacitors C10a and C10b are C10 and the values of the capacitors C20a and C20b are C20, the values C10 and C20 of these capacitors are expressed by the following formula: C10 / (C10 + C20) = (1 + exp (−T / If it is determined to satisfy τ)) / 2, the intersymbol interference can theoretically be completely eliminated. However, in the ideal state, it is sufficient to satisfy this equation. However, since a parasitic capacitance or the like actually enters, the capacitance ratio is set to a value close to satisfying this equation. Here, t represents a time constant of the bus 2200 ', and T represents a time at which data for 1 bit appears on the bus or a cycle for 1 bit.

  FIG. 106 is a waveform diagram showing the relationship between the bus time constant and the cycle of 1 bit. FIG. 106A shows the original waveform (data 1-1-0), and FIG. FIG. 106C is a diagram for explaining a time T at which 1-bit data appears on the bus 2200 ′, and FIG. 106C is a diagram showing a cycle (T) of 1 bit.

  When transmitting the original waveform (data 1-1-0) as shown in FIG. 106 (a), as shown in FIG. 106 (b), after each bit of data appears on the bus 2200 ′. A period in which a high impedance state (High-Z state) is set may be provided, or data may be transmitted in the entire period T of 1 bit as shown in FIG. That is, in both the waveforms of FIGS. 106B and 106C, the original data shown in FIG. 106A is accurately obtained by the PRD system bus amplifier (PRD system complementary differential bus amplifier 2300 ″). Can be detected.

  FIG. 107 is a diagram for explaining the operation of the bus amplifier of FIG.

  The PRD-type complementary differential bus amplifier 2300 ″ shown in FIG. 105 performs the operations shown in FIGS. 107 (a) and 107 (b) alternately by controlling the control signals φ1 and φ2.

  That is, when the control signal φ1 is at a high level “H” (/ φ1 is at a low level “L”) and the control signal φ2 is at a low level “L” (/ φ2 is at a high level “H”), FIG. As shown in FIG. 107B, when the intersymbol interference component estimation operation is performed and the control signal φ1 is at the low level “L” and the control signal φ2 is at the high level “H”, A signal determination operation is performed. Note that the amplifier precharge circuit 2302 precharges the input node of the differential amplifier 2303 during a period in which the intersymbol interference component estimation operation is performed.

  Here, in the bus amplifiers (PRD type complementary differential bus amplifier 2300 ′) in the third and fourth embodiments described above, the signal of the complementary bus 2200 ′ is received rather than receiving the complementary minute signal complementarily. Is received by the PRD method, and the subsequent differential voltage is amplified. Therefore, the sensitivity is improved to some extent as compared with the case of simple single-end, but intersymbol interference in the case of a complementary signal. It's just about removing the ingredients. In this case, malfunction may occur depending on the magnitude of the signal.

  On the other hand, in the fifth embodiment, the PRD complementary differential bus amplifier 2300 ″ is an original PRD bus amplifier for complementary signals, and ideally a code for a completely complementary signal. The interfering interference component can be estimated, and the sensitivity can be greatly improved as compared with the third and fourth embodiments. In other words, the operation margin can be greatly increased.

  FIG. 108 is a diagram showing another example of the bus amplifier in the signal transmission system of FIG. 104, FIG. 109 is a circuit diagram showing an example of a structural unit of the PRD amplifier in the bus amplifier of FIG. 108, and FIG. It is a circuit diagram which shows an example of the multiplexer in an amplifier.

  The bus amplifier (PRD type complementary differential bus amplifier 2300a) shown in FIG. 108 has the same configuration as the bus amplifier (PRD type complementary differential bus amplifier 2300 ") of FIG. 105. 2310a and 2320a and a multiplexer (MUX) 2330a The bus amplifier shown in Fig. 108 estimates intersymbol interference components with one PRD amplifier (first PRD amplifier 2310a), and The other PRD amplifier (second PRD amplifier 2320a) performs data determination, and at the next timing, one PRD amplifier (first PRD amplifier 2310a) performs data determination and the other PRD amplifier ( Interleaving in which the second PRD amplifier 2320a) estimates intersymbol interference components. Which enables high-speed data transfer by the operation.

  Here, in the PRD amplifier that is performing the intersymbol interference component estimation operation, the PRD amplifier is also precharged at the same time. This precharge time is performed behind the interleaved data read, and does not affect the data transfer cycle. The input node of the bus 2200 ′ and the bus amplifier (PRD system complementary differential bus amplifier 2300a: amplifier) includes a PRD capacitor, and the input node of the bus and the amplifier body is separated. The potential difference between the bus and the input node of the amplifier is not particularly limited in the PRD method, so the level of these input nodes when the amplifier starts operation by precharging is set to the best sensitivity of the complementary amplifier. can do. As a result, even if the same complementary amplifier is used for the main body, the sensitivity can be greatly increased.

  In the above circuit, a complementary transfer gate is used as a switch, but any other element having a switching function may be used. For example, only an NMOS transistor (NMOS transfer gate) or only a PMOS transfer gate may be used. But you can. Further, the differential amplifier 2303 in the fifth embodiment is configured as an NMOS gate receiver. However, whether to use the NMOS receiver or the PMOS receiver depends on the technology or the like. You can choose. Furthermore, in the fifth embodiment, a gate receiving latch is adopted for the differential amplifier 2303, but the differential amplifier is not limited to these. The differential amplifier 2303 used in the fifth embodiment can be stopped by the enable signals en and / en when data transfer is not performed.

  As shown in FIG. 109, the first PRD amplifier 2310a (second PRD amplifier 2320a) has the same configuration as the PRD-type complementary differential bus amplifier 2300 ″ shown in FIG. An amplifier precharge circuit 2302 and a differential amplifier 2303. The differential amplifier 2303 is configured as a gate-type latched differential amplifier. The circuit 2302 is precharge controlled by a control signal φ1 (/ φ1), and the operation of the differential amplifier 2303 is controlled by an enable signal en (/ en).

  As shown in FIG. 110, the MUX (multiplexer) 2330a receives the output signal (D) of the first PRD amplifier 2310a or the second signal according to the control signals φ1 ′ (/ φ1 ′) and φ2 ′ (/ φ2 ′). One of the output signals (E) of the PRD amplifier 2320a is selected and output as the output signal C of the bus amplifier (PRD type complementary differential bus amplifier 2300a). Here, the control signals φ 1 ′ (/ φ 1 ′) and φ 2 ′ (/ φ 2 ′) are signals similar to the control signals φ 1 (/ φ 1) and φ 2 (/ φ 2) (slightly different in timing).

  111 is a diagram showing an example of signal waveforms for operating the bus amplifier of FIG. 108, and FIG. 112 is a diagram showing an example of operation waveforms of the bus and bus amplifier in the signal transmission system of FIG.

  As shown in FIG. 111, one PRD amplifier (first PRD amplifier 2310a) estimates an intersymbol interference component using the control signals φ1 and φ2, and the other PRD amplifier (second PRD amplifier 2320a). Then, at the next timing, an interleave operation is performed in which one PRD amplifier performs data determination and the other PRD amplifier removes intersymbol interference components. The PRD amplifier that is performing the intersymbol interference component estimation operation also performs precharging at the same time.

  As shown in FIG. 112, according to the fifth embodiment, the complementary signal (A, / A) output from the driver 2100 ′ is transmitted via the complementary bus 2200 ′, and the PRD type complementary difference is transmitted. The dynamic bus amplifier 2300 ″ (2300a) receives complementary signals (B, / B) and outputs a signal (positive logic signal C).

  FIG. 113 is a diagram showing an example of a bus amplifier in the signal transmission system as the sixth example of the signal transmission system according to the fifth mode of the present invention. The sixth embodiment is also an example of a complementary bus, and the block diagram is the same as FIG. 108 described above.

  That is, as shown in FIG. 113, the bus amplifier (PRD type complementary differential bus amplifier 2300b) includes first and second PRD amplifiers 2310b and 2320b and a multiplexer (MUX) 2330b.

  FIG. 114 is a circuit diagram showing an example of a structural unit of PRD amplifiers (first and second PRD amplifiers 2310b and 2320b) in the bus amplifier of FIG.

  As is clear from comparison between FIG. 114 and FIG. 109, the PRD amplifier (2310b, 2320b) in the sixth embodiment is different from the PRD amplifier (2310a, 2320a) in the fifth embodiment shown in FIG. The configuration of the dynamic amplifier 2303a is different.

  As shown in FIG. 114, the differential amplifier 2303a of the sixth embodiment is provided with AND gates 2331 and 2332 with respect to the differential amplifier 2303 of FIG. That is, the differential amplifier 2303 in FIG. 109 supplies the enable signal en (/ en) directly to the gate of the control transistor, whereas the differential amplifier 2303a in the sixth embodiment shown in FIG. Then, the logic of the enable signal en and the control signal φ1 is taken by AND gates 2331 and 2332, and the switching of the control transistor is controlled by the output signals of these gates 2331 and 2332. As a result, the differential amplifier 2303a is switched on (activated) for only the minimum necessary period to reduce power consumption.

  Also in the sixth embodiment, the differential amplifier 2303a is configured as a gate receiving latch system as in the fifth embodiment. Here, the differential amplifier 2303a in the sixth embodiment is configured as an NMOS gate receiver, but whether it is an NMOS receiver or a PMOS receiver depends on the technology or the like and is optimal. Can be selected. The operation sequence is the same as that of the fifth embodiment shown in FIG.

  In FIG. 114, when the bus amplifier is precharged, the nodes N1a and N1b of the differential amplifier 2303a are precharged to a high level "H". Therefore, as in the sixth embodiment, the NMOS gate By adopting the receiving configuration, the operation speed of the amplifier can be improved. In the sixth embodiment, similarly to FIG. 108, one PRD amplifier (first PRD amplifier 2310b) estimates the intersymbol interference component and the other PRD amplifier (first PRD amplifier 2310b) using the control signals φ1 and φ2. The data is determined by the second PRD amplifier 2320b), and at the next timing, the data is determined by one PRD amplifier and the intersymbol interference component is estimated by the other PRD amplifier. High-speed data transfer.

  FIG. 115 is a circuit diagram showing another example of the structural unit of the PRD amplifier in the bus amplifier of FIG.

  115 is different from the differential amplifier (2303c) shown in FIG. 119 described later in that AND gates 2331 and 2332 are provided. That is, the differential amplifier 2303b in FIG. 115 takes the logic of the enable signal en and the control signal φ1 by the AND gates 2331 and 2332 and outputs the outputs of these gates 2331 and 2332, as in the differential amplifier 2303a in FIG. The switching of the control transistor is controlled by the signal. As a result, the differential amplifier 2303b is activated for a necessary minimum period to reduce power consumption.

  FIG. 116 is a circuit diagram showing an example of a multiplexer in the bus amplifier of FIG.

  As shown in FIG. 116, the MUX (multiplexer) 2330b receives the output signal (D) of the first PRD amplifier 2310b or the second signal according to the control signals φ1 ′ (/ φ1 ′) and φ2 ′ (/ φ2 ′). Either one of the output signals (E) of the PRD amplifier 2320b is selected, inverted by an inverter to match the logic, and output as the output signal C of the bus amplifier (PRD type complementary differential bus amplifier 2300b). It has become. Here, the MUX 2330b shown in FIG. 116 corresponds to the case where the PRD amplifier (differential amplifier 2303a) shown in FIG. 114 is used, and when the PRD amplifier (differential amplifier 2303b) shown in FIG. 115 is used. May use the MUX 2330a shown in FIG. It goes without saying that the logic of the signal can be changed and used in various ways as necessary.

  FIG. 117 is a diagram showing an example of operation waveforms of the bus and the bus amplifier in the sixth example of the signal transmission system according to the fifth mode of the present invention.

  As shown in FIG. 117, according to the sixth embodiment, the complementary signal (A, / A) output from the driver 2100 ′ is transmitted via the complementary bus 2200 ′, and the PRD type complementary type difference is transmitted. The dynamic bus amplifier 2300b receives complementary signals (B, / B) and outputs a signal (positive logic signal C). In FIG. 117, the output signal D of the first PRD amplifier 2310b and the output signal E of the second PRD amplifier 2320b are also shown.

  FIG. 118 is a diagram showing an example of a bus amplifier in a signal transmission system as a seventh embodiment of the signal transmission system according to the fifth mode of the present invention. The seventh embodiment is also an example of a complementary bus, and its block diagram is the same as that of FIGS. 108 and 113 described above.

  That is, as shown in FIG. 118, the bus amplifier (PRD type complementary differential bus amplifier 2300c) includes first and second PRD amplifiers 2310c and 2320c and a multiplexer (MUX) 2330c.

  FIG. 119 is a circuit diagram showing an example of a structural unit of the PRD amplifier in the bus amplifier of FIG.

  As described above, the differential amplifier 2303c in the PRD amplifier 2310c (2320c) of FIG. 119 corresponds to the differential amplifier 2303b shown in FIG. 115 excluding the AND gates 2331 and 2332.

  As shown in FIG. 119, in the seventh embodiment, the differential amplifier 2303c is configured as a current mirror amplifier. For example, the sensitivity is higher than that of a latch-type differential amplifier, and high-speed operation is possible. However, since the current mirror type amplifier often has a small dynamic range, it is preferable to optimize the input level to make the best use of the characteristics of the current mirror type differential amplifier 2303c. Therefore, although it is a complementary amplifier, for example, the sensitivity can be significantly increased as compared with the fifth embodiment. Note that the realization of high-speed data transfer by the interleave operation is the same as that in each of the embodiments described above.

  120 is a circuit diagram showing an example of a multiplexer in the bus amplifier of FIG.

  As shown in FIG. 120, the MUX (multiplexer) 2330c has the same configuration as the MUX 2330b shown in FIG. That is, the MUX 2330c generates an output signal (D) of the first PRD amplifier 2310c or an output signal (E) of the second PRD amplifier 2320c according to the control signals φ1 ′ (/ φ1 ′) and φ2 ′ (/ φ2 ′). Either one is selected and inverted by an inverter to match the logic and output as an output signal C of the bus amplifier (PRD type complementary differential bus amplifier 2300c).

  FIG. 121 is a diagram showing an example of signal waveforms for operating the bus amplifier of FIG. 118, and FIG. 122 is an operation of the bus and bus amplifier in the seventh embodiment of the signal transmission system according to the fifth mode of the present invention. It is a figure which shows an example of a waveform.

  As is apparent from a comparison between FIGS. 121 and 122 and FIGS. 111 and 112, the bus amplifier (PRD type complementary differential bus amplifier 2300c) and the signal transmission system in the seventh embodiment are the same as those in the fifth embodiment. The same operation as in the example will be performed.

  FIG. 123 is a diagram showing an example of a bus amplifier in the signal transmission system as the eighth embodiment of the signal transmission system according to the fifth mode of the present invention. The eighth embodiment is also an example of a complementary bus, and its block diagram is the same as that shown in FIG. 118 and the like.

  The eighth embodiment is intended to compensate for an input offset of a differential amplifier section that may cause a problem in the fifth to seventh embodiments, for example. That is, it is for compensating for the input offset of the differential amplifier of the eighth embodiment. That is, the differential amplifier 2303d of the eighth embodiment has a function of compensating for the input offset.

  124 is a circuit diagram showing an example of a structural unit of a PRD amplifier in the bus amplifier of FIG.

  As is clear from the comparison between FIG. 124 and FIG. 119, in the ninth embodiment, a precharge circuit 2302d is provided only for one input of the current mirror type differential amplifier 2303d, and the other input and output are controlled. The connection is made by a transfer gate that is switching-controlled by a signal φ1 (/ φ1).

  125 is a diagram for explaining the operation of the bus amplifier of FIG. 124. FIG. 125 (a) shows the intersymbol interference component estimation preparation operation and auto-zero operation, and FIG. 125 (b) shows the signal determination operation. Yes.

  First, as shown in FIG. 125A, at timing 1, the differential amplifier itself is electrically short-circuited with one input and output of the differential amplifier 2303d together with the estimation operation of the intersymbol interference component. The operation to remove the input offset is performed. At this time, the other input of the differential amplifier 2303d is simultaneously precharged to a level (Vpr) by which the differential amplifier becomes highly sensitive by the precharge circuit 2302d.

  Next, as shown in FIG. 125 (b), at timing 2, a data determination operation is performed. At this time, the short circuit between the input and output of the differential amplifier 2303d is cut off, and the precharge by the precharge circuit 2302d is also stopped.

  Thus, in the eighth embodiment, an input offset removal function (auto-zero function), which is a drawback of the complementary differential amplifier, is added. The PRD function part has the same configuration as that of the seventh embodiment, and unlike the third and fourth embodiments, it is possible to ideally completely remove the intersymbol interference component. Yes. That is, in the eighth embodiment, the input offset can be removed by the auto-zero function for the complementary amplifier. By removing this input offset, it is possible to detect, reproduce and amplify a further minute signal. become.

  By the way, normally, a complementary amplifier with an auto-zero function must be newly provided with a capacity for input offset compensation, but in the eighth embodiment, it is used for intersymbol interference component removal (intersymbol interference component estimation). Since the offset is also stored in the capacity, it is not necessary to newly provide a capacity for offset compensation, and the auto zero function can be added without causing an increase in area.

  In the eighth embodiment, two PRD amplifiers (bus amplifiers) 2310d and 2320d shown in FIG. 124 are interleaved to alternately reproduce and amplify signals, thereby transmitting signals at high speed.

  126 is a circuit diagram showing an example of the multiplexer (MUX) 2330d in the bus amplifier of FIG. 123, and has the same configuration as the MUX 2330c in the seventh embodiment shown in FIG.

  FIG. 127 is a diagram showing an example of signal waveforms for operating the bus amplifier of FIG. 123, and FIG. 128 is a bus and bus amplifier in the eighth embodiment of the signal transmission system according to the fifth mode of the present invention. It is a figure which shows an example of this operation | movement waveform.

  As shown in FIG. 127, in the eighth embodiment, the intersymbol interference component is estimated by one PRD amplifier (first PRD amplifier 2310d) using the control signals φ1 and φ2, and the other PRD amplifier ( The second PRD amplifier 2320d) performs data determination, and at the next timing, one PRD amplifier performs data determination and the other PRD amplifier performs intersymbol interference component estimation. High-speed data transfer. Further, as described above, the amplifier that is performing the intersymbol interference component estimation operation simultaneously performs input offset removal (auto-zero operation) and amplifier precharge (see the arrow position in FIG. 128). As described above, in the eighth embodiment, since the bus amplifier (PRD type complementary differential bus amplifier 2300d) is provided with the auto-zero function, it is possible to detect a further minute potential change.

  Here, since the auto-zero operation and the precharge operation are performed at the back of the interleaved data reading, the data transfer cycle is not affected (no extra time is required). As shown in FIG. 127, the enable signal en2 (/ en2) supplied to the second PRD amplifier 2320d is more than the enable signal en1 (/ en1) supplied to the first PRD amplifier 2310d. It is output at a timing delayed by one bit, and an unnecessary signal is prevented from being output from the MUX 2330d.

  Also in the eighth embodiment, the other configurations are the same as those in the above-described embodiments. That is, the input node of the bus and the bus amplifier (PRD type complementary differential bus amplifier 2300d) includes a capacitor for PRD, and the input node of the bus and the amplifier body is separated. Since the potential difference between the input nodes is not particularly limited in the PRD method, the level of these input nodes when the amplifier starts operation by precharging can be set to the best sensitivity of the complementary amplifier. . As a result, even if the same complementary amplifier is used for the main body, the sensitivity can be greatly increased.

  Further, in the above circuit, a complementary transfer gate is used as a switch, but any other element having a switch function may be used. For example, only an NMOS transistor (NMOS transfer gate) or a PMOS transfer gate may be used. Only the gate may be used. Further, the differential amplifier 2303d in the eighth embodiment is configured as an NMOS gate receiver, but whether to use the NMOS receiver or the PMOS receiver depends on the technology and the like. You can choose. The differential amplifier 2303d used in the eighth embodiment can be stopped by the enable signals en1, en2 (/ en1, / en2) when data transfer is not performed.

  FIG. 129 is a diagram showing an example of a bus amplifier 2300e in the signal transmission system as the ninth embodiment of the signal transmission system according to the fifth mode of the present invention, and FIG. 130 is a diagram of the PRD amplifier 2310e in the bus amplifier of FIG. It is a circuit diagram which shows an example of a structural unit. The ninth embodiment is also an example of a complementary bus. For example, unlike the eighth embodiment of FIG. 123, a PRD-type complementary differential bus amplifier 2300e is constituted by one PRD amplifier 2310e and a latch 2340e. It is. Here, the PRD amplifier 2310e shown in FIG. 130 has the same configuration as the PRD amplifier 2310d (2320d) shown in FIG. 124 described above.

  That is, in the ninth embodiment, the data transfer rate (transfer speed) is reduced by using one PRD amplifier 2310e without using two PRD amplifiers interleaved, but the area occupied by the bus amplifier is reduced. Is reduced (about half). Even in this case, bus precharge is unnecessary, and therefore data can be transferred at a higher speed than when the bus is precharged bit by bit. This is because the CR of the portion charged to remove the intersymbol interference of the amplifier is much smaller than the CR of the bus, so that the preparation time for removing the intersymbol interference can be shorter than the precharge time of the bus. Because.

  FIG. 131 is a circuit diagram showing an example of the latch 2340e in the bus amplifier 2300e of FIG.

  As shown in FIG. 131, the latch 2340e includes a first latch unit whose data fetch is controlled by the control signals φ1, / φ1, and a second latch whose data fetch is controlled by the control signals φ2, / φ2. However, you may comprise only one of the latch parts.

  132 is a diagram showing an example of signal waveforms for operating the bus amplifier of FIG. 129, and FIG. 133 is an operation of the bus and bus amplifier in the ninth embodiment of the signal transmission system according to the fifth mode of the present invention. It is a figure which shows an example of a waveform.

  The ninth embodiment is suitable when the transfer rate is not so high as to interleave using two PRD amplifiers, and it is preferable to reduce the area of the bus amplifier. Also in the ninth embodiment, a high-speed operation is possible as compared with the conventional system in which the bus is precharged bit by bit, and a complementary auto-zero function is provided, so that a complementary bus amplifier normally used is used. It is much more sensitive. Also, a PRD capacitor is included in the input node of the bus and the complementary amplifier body, the input node of the bus and the complementary amplifier body is separated, and the potential difference between the bus and the input node of the amplifier is Since there is no particular limitation, the level of these input nodes when the amplifier starts operation can be set to the best sensitivity of the complementary amplifier. Therefore, even if the same complementary amplifier is used for the main body, the sensitivity can be greatly increased.

  In other words, in the ninth embodiment, the area of the bus amplifier is reduced by eliminating interleaving in the bus amplifier of the eighth embodiment (the number of PRD amplifiers is one), but by using one PRD amplifier. The effect of reducing the area of the bus amplifier can be widely applied to various other bus amplifiers. Further, in the ninth embodiment, a complementary transfer gate is used as a switch, but any other element having a switch function may be used, for example, only an NMOS transistor (NMOS transfer gate), or Only a PMOS transfer gate may be used. Further, the differential amplifier 2303e in the ninth embodiment is configured as an NMOS gate receiver, but whether to use the NMOS receiver or the PMOS receiver depends on the technology or the like, and the optimum one is used. You can choose. The differential amplifier 2303e used in the ninth embodiment can be stopped by the enable signal en (/ en) when data transfer is not performed.

  FIG. 134 is a diagram showing an example of a bus amplifier in a signal transmission system as a tenth embodiment of the signal transmission system according to the fifth mode of the present invention, which is a pseudo PRD bus amplifier. However, the block diagram of FIG. 134 is the same as the block diagram of the eighth embodiment of FIG.

  That is, as shown in FIG. 134, the bus amplifier (PRD type complementary differential bus amplifier 2300f) includes first and second PRD amplifiers 2310f and 2320f and a multiplexer (MUX) 2330f.

  FIG. 135 is a circuit diagram showing an example (a) and another example (b) of the PRD amplifier structural unit in the bus amplifier of FIG. 134, and FIG. 136 is still another example of the PRD amplifier structural unit in the bus amplifier of FIG. It is a circuit diagram which shows the example of.

  The PRD amplifier 2310f (2320f) of the tenth embodiment includes an amplifier in the PRD function portion 2301 of the PRD amplifier 2310d of the eighth embodiment shown in FIG. 124, as shown in the PRD function portion 2301f in FIG. The capacity to be connected when the opposite bus is connected at the time of precharging is deleted. The precharge circuit 2302f and the differential amplifier 2303f are the same as in the eighth embodiment of FIG.

  The PRD amplifier 2310f ′ (2320f ′) shown in FIG. 135 (b) uses the PRD function part 2301f in FIG. 135 (a) as a logic gate (OR gate and OR gate) to which the control signals φ1, φ2 (/ φ1, / φ2) are supplied. And a PRD function portion 2301f ′ that performs switching using an AND gate.

  The PRD amplifier 2310f ″ (2320f ″) shown in FIG. 136 has a capacity (C30a, C30b) and a bus (B, / B) from the PRD amplifier shown in FIG. 135 (a) as shown in the PRD function portion 2301f ″ in FIG. In this case, if the bus time constant is small or the time for outputting data to the bus is smaller than the cycle per bit, the bus 106 (b) may be changed as described above. When the data bus has a stable level as described above, the capacity (C30a, C30b) is changed as shown in FIG. And the transfer gate for controlling the connection between the buses (B, / B).

  The PRD amplifier can be stopped by an enable signal en (/ en) except during data transfer.

  In the PRD method (pseudo PRD method) in the tenth embodiment, unlike the original PRD method, the current bit is “0” or “1” with respect to the previous bit value. This is a judgment. Therefore, the operation margin is smaller than that in the eighth embodiment. However, instead, the occupied area of the bus amplifier (PRD type complementary differential bus amplifier 2300f) can be reduced. The tenth embodiment also uses a complementary bus as in the fifth embodiment, for example, and the speed is increased by interleaving the two PRD amplifiers 2310f and 2320f. .

  FIG. 137 is a circuit diagram showing an example of the multiplexer 2330f in the bus amplifier of FIG.

  As shown in FIG. 137, the multiplexer (MUX) 2330f has the same configuration as the MUX 2330b of the sixth embodiment shown in FIG. 116, for example, and control signals φ1 ′, φ2 ′ (/ φ1 ′, / φ2 ′) Thus, the outputs of the PRD amplifiers 2310f and 2320f are alternately selected and output.

  Here, in the case of the PRD method, in order to eliminate intersymbol interference, a cycle for sampling the intersymbol interference component is required alternately with the present data sample. Therefore, interleaving is performed by combining two PRD amplifiers. By doing so, data transmission can be performed seamlessly. In the case of the first to fourth embodiments and the eighth to ninth embodiments according to the fifth aspect of the present invention, the auto-zeroing of the amplifier is simultaneously performed in the cycle for estimating the intersymbol interference component. The sensitivity is improved. Further, in the tenth embodiment, the pseudo-intersymbol interference component (corresponding to the data one bit before) is sampled by combining two PRD amplifiers, and the cycle in which the amplifier is set to auto-zero and this data sample are alternated. Is going to.

  FIG. 138 is a diagram showing an example of signal waveforms for operating the bus amplifier of FIG. 134. FIG. 139 is an operation of the bus and bus amplifier in the tenth embodiment of the signal transmission system according to the fifth mode of the present invention. It is a figure which shows an example of a waveform.

  Also in the tenth embodiment, the pseudo-intersymbol interference component (corresponding to the data one bit before) is sampled by two PRDs 2310f, and the precharge cycle of the amplifier and this data sample are alternately performed. This precharge time is performed behind the interleaved data read, and does not affect the data transfer cycle. Here, in the tenth embodiment, two PRD amplifiers are combined and interleaved to perform high-speed data transfer. However, as in the ninth embodiment, a single PRD amplifier is not used for interleaving. Needless to say, it can be configured as follows. In this case, the transfer rate is lowered, but the area occupied by the bus amplifier can be further reduced.

  As shown in FIG. 138, the enable signal en2 (/ en2) supplied to the second PRD amplifier 2320f is more effective than the enable signal en1 (/ en1) supplied to the first PRD amplifier 2310f. It is output at a timing delayed by one bit, and an unnecessary signal is prevented from being output from the MUX 2330f.

  FIG. 140 is a block diagram schematically showing an example of a semiconductor memory device as an eleventh embodiment to which the signal transmission system according to the fifth mode of the present invention is applied. In FIG. 140, reference numeral 2001 is a memory cell array, 2002 is a word decoder (word decoder string), 2100 is a sense amplifier (sense amplifier string), 2201 is a local data bus, 2202 is a global data bus, and 2300g is a PRD data bus amplifier. (PRD type complementary global data bus amplifier), 2401 is a local data bus precharge circuit, 2402 is a global data bus precharge circuit, 2009 is a local data bus switch, 2010 is a write amplifier, 2011 is a sense amplifier driver, Reference numeral 2012 denotes a column decoder (column decoder row).

  As shown in FIG. 140, the semiconductor memory device (DRAM memory cell array portion) as the eleventh embodiment includes a plurality of memory arrays 2001, a word decoder 2002, a sense amplifier 2100, a local data bus 2201, and global data. A bus 2202 is provided. In addition, the semiconductor memory device of the eleventh embodiment includes a PRD data bus amplifier 2300g that amplifies data on the global data bus 2202 when data is read, a local data bus precharge circuit 2401 that precharges the local data bus 2201, and a global A global data bus precharge circuit 2402 for precharging the data bus 2202, a local data bus switch 2009 for controlling connection between the global data bus 2202 and the local data bus 2201, and a write amplifier 2010 for writing data to the memory cell It has. Further, the semiconductor memory device according to the eleventh embodiment includes a column decoder 2012 for selecting a column transfer gate and a sense amplifier driver 2011 for driving the sense amplifier 2100, as will be described later. Here, the local data bus switch 2009 is configured as a complementary transfer gate of NMOS and PMOS, for example.

  141 is a diagram showing an example of a bus amplifier in the semiconductor memory device of FIG. Here, the local data bus 2201 and the global data bus 2202 in FIG. 140 correspond to the complementary bus 2200 ′ (B, / B) in FIG. 141.

  As shown in FIG. 141, the bus amplifier (PRD data bus amplifier 2300g) of the eleventh embodiment is configured as a complementary differential bus amplifier, and includes first and second PRD amplifiers 2310g and 2320g and a multiplexer. (MUX) 2330g is provided.

  142 is a circuit diagram showing an example of a structural unit of the PRD amplifier in the bus amplifier of FIG. 141, and FIG. 143 is a circuit diagram showing an example of a multiplexer in the bus amplifier of FIG.

  As is apparent from a comparison between FIG. 142 and FIG. 124 of the eighth embodiment, the PRD amplifiers (first and second PRD amplifiers 2310g and 2320g) in the eleventh embodiment are basically Although the configuration is the same as that of the PRD amplifier of the eighth embodiment, the source potential of the PMOS (P channel type MOS transistor) controlled by the enable signal en is not a high potential power supply voltage Vcc (Vii) but a predetermined potential. The potential is Vpr ′.

  As is clear from comparison between FIG. 143 and FIG. 126 of the eighth embodiment, the MUX 2330g in the eleventh embodiment has the same configuration as the MUX 2330d of the eighth embodiment, and the control signal φ1 One of the output signal D of the first PRD amplifier 2310g and the output signal E of the second PRD amplifier 2320g is selected by '(/ φ1') and φ2 '(/ φ2'), and the bus amplifier (PRD The signal is output as an output signal C of the system complementary differential bus amplifier 2300g). Here, the control signals φ 1 ′ (/ φ 1 ′) and φ 2 ′ (/ φ 2 ′) are signals similar to the control signals φ 1 (/ φ 1) and φ 2 (/ φ 2) (slightly different in timing).

  144 is a circuit diagram showing an example of a sense amplifier in the semiconductor memory device of FIG.

  The sense amplifier 2100 used in the semiconductor memory device (memory) of the eleventh embodiment is similar to the sense amplifier 2003 in the conventional semiconductor memory device (DRAM) shown in FIG. Sense amplifier (PMOS and NMOS complementary latch type sense amplifier unit) 2101, column transfer gate 2102 composed of NMOS for transferring the data amplified by the sense amplifier to the local data bus, for bit line short and precharge Bit line short precharge circuit 2103 and a bit line transfer gate 2104 made of NMOS for supporting the shared sense amplifier system. Here, reference symbols BL and / BL indicate bit lines, and CL indicates a column selection line.

  The column transfer gate 2102 is selected by the column decoder 2012 in FIG. 140, and the data of the selected sense amplifier 2100 is output to the data bus (2201, 2202: 2200 '). That is, except for the PRD system data bus amplifier 2300g, the basic configuration is the same as that of a normal DRAM, and it is clear that the present system can be applied to a similar DRAM although not specifically shown here. is there. For example, one case is when the data bus (2200 ') is not divided into a local data bus 2201 and a global data bus 2202.

  FIG. 145 is a diagram showing an example of operation waveforms of the bus and the bus amplifier in the semiconductor memory device of FIG. 140, and shows a read operation with a burst length of 8 (8-bit units: CL0 to CL7).

  As shown in FIG. 145, by sequentially outputting the column selection signals CL0 to CL7, the output of the MUX 2330g (data bus amplifier) in which the PRD amplifiers 2310g and 2320g are interleaved driven by the control signals φ1, φ2 (φ1 ′, φ2 ′). Read data is obtained as output C).

  In the eleventh embodiment, the data bus is precharged when there is no data on the data bus bus, / bus (2201, 2202: 2200 ′). For example, as in the first embodiment, Of course, it is possible to configure so that the bus is not precharged at all. In this case, the local data bus short precharge switch (2009), the global data bus short precharge switch, and the like are not required. In addition, it is possible to selectively perform precharge, and if it is known that the next read (read operation) will start immediately, no precharge is performed or a bus precharge command is supplied from the outside. Thus, it is possible to perform a precharge, or a specification of a selective operation in which the precharge is performed only before the write (write operation) and the operation of the write amplifier 2100 is performed smoothly.

  Further, since the bus amplifier 2300g (PRD amplifiers 2310g and 2320g) in the eleventh embodiment has an auto-zero function, it is possible to detect and amplify data even when a voltage change appearing on the data line is minute. Since the bus amplifier 2300g has a capacity inserted between the bus and the input of the current mirror amplifier (2303g) in the bus amplifier, the input of the amplifier is set to the place where the sensitivity of the current mirror amplifier is the largest. can do. As a result, it is possible to amplify a further minute potential change. If the bus is directly connected to the input, the bus potential becomes the input voltage, so that the amplifier cannot always be used where the sensitivity of the current mirror amplifier is large. In the eleventh embodiment, the bus amplifier corresponding to the eighth embodiment is used as the data bus amplifier (2300g). However, all of the buses and bus amplifier systems shown in the above-described embodiments (single-ended buses) are used. Can be replaced.

  FIG. 146 is a block diagram schematically showing an example of a semiconductor memory device as a twelfth embodiment to which the signal transmission system according to the fifth mode of the present invention is applied.

  The semiconductor memory device of the twelfth embodiment shown in FIG. 146 has the same configuration as the semiconductor memory device of the eleventh embodiment shown in FIG. 140 described above, but the configuration of the column decoder (column decoder array) 2120 is different. ing. The column decoder 2012 of the semiconductor memory device described above is not selected because of overlapping column transfer gates as in the case of a normal DRAM.

  That is, in a certain system bus, one arbitrary column transfer gate is turned on, data is transferred from the sense amplifier 2100 to the local data bus 2201 and the global data bus 2202, and amplified by the data bus amplifier 2300g. The Thereafter, the bus is precharged, but all column transfer gates must be closed before this time. This is because the precharge of the bus (2202) requires a predetermined time, and therefore the data of the sense amplifier 2100 is destroyed unless the column transfer gate is closed during the precharge time.

  However, when the PRD method is adopted, since the precharge period itself is eliminated, it is not necessary to provide a time for closing all the column transfer gates. In the PRD method, since the previous data and the next data can be overlapped originally, the next transfer gate is opened before the column transfer gate of the previous cycle is closed, and the next data is transferred to the data bus. Therefore, it is not necessary to make sure that the column transfer gate one bit before is closed. In the twelfth embodiment, the column decoder 2120 is configured by positively adopting the above.

  FIG. 147 is a block diagram showing a configuration example of the column decoder system in the semiconductor memory device of FIG. 146, and FIG. 148 is a diagram showing an example of operation waveforms of the bus and bus amplifier in the semiconductor memory device of FIG.

  In FIG. 147, reference numerals 2120a and 2120b indicate column decoders (A, B) of two systems (for even and odd numbers), 2121a and 2121b indicate column system predecoders (A, B) of two systems, Reference numerals 2122a and 2122b denote two systems of column selection line control pulse generation circuits (CL pulse generation circuits A and B). Reference numeral 2123 indicates a clock generation circuit (forming circuit).

  As shown in FIG. 147, the column decoder system (column decoder 2120) in the twelfth embodiment is driven by a clock signal (CLK, / CLK) of the second system or the like, for example, driven by a positive logic clock CLK. The first plurality of column decoders A (2120a) and the second plurality of column decoders B (2120b) driven by the inversion logic clock / CLK are interleaved by the column system predecoders 2121a and 2121b to obtain a column transfer gate. Is driven at high speed so that the front and rear column transfer gates overlap each other to some extent. Here, the column predecoder 2121a is supplied with the column address signal for even stages and the clock CLK, and the column predecoder 2121b is supplied with the column address signal for odd stages and the clock / CLK. In the example shown in FIG. 147, complementary clocks CLK and / CLK are directly supplied from the outside. For example, by providing a clock generation circuit 2123 using a PLL or the like as indicated by a broken line. Further, by generating more rigid clocks CLK and / CLK from the clock CLK ′ inside the chip, it becomes possible to operate at higher speed.

  In this way, overlapping the selection of the front and rear column transfer gates can increase the density of switching between these column transfer gates, and as a result, data transfer is faster than the time required to exclude the precharge time. Is possible. Even if the selection of column transfer gates is not designed to overlap, the PRD method is a method in which overlap is not essentially a problem, so there is a margin in the timing margin of the column transfer selection signal (CL). It becomes possible to design.

  As shown in FIG. 148, by sequentially outputting the column selection signals CL0 to CL7, outputs of the MUX 2330g (data bus amplifier) in which the PRD amplifiers 2310g and 2320g are interleaved driven by the control signals φ1 and φ2 (φ1 ′, φ2 ′). Read data is obtained as output C).

  In this twelfth embodiment, by increasing the time for opening the column transfer gate, the potential appearing on the data bus (2201, 2202) can be increased, and the operation margin can be increased. If the time for opening the column transfer gate is set to the same level as in the eleventh embodiment described above, the speed can be further increased.

  FIG. 149 is a block diagram schematically showing an example of a semiconductor memory device as a thirteenth embodiment to which the signal transmission system according to the fifth mode of the present invention is applied.

  The semiconductor memory device according to the thirteenth embodiment shown in FIG. 149 has substantially the same configuration as the semiconductor memory device according to the twelfth embodiment shown in FIG. 146 described above. A PMOS (P-channel MOS transistor) load 2413 is provided for the bus (2202). That is, a PMOS connected to the high potential power supply (Vcc) side is provided for the complementary buses bus and / bus (global data bus 2202). A predetermined load control signal V1L is supplied to each PMOS gate so that the load is turned on only when the data bus is used, for example.

  In the thirteenth embodiment, if nothing is done due to, for example, the characteristics of the NMOS of the column transfer gate and the low level drive capability in the sense amplifier 2100, the potential of the bus during the read is entirely This shows the case where the level is lowered to the low level (both complementary buses). That is, in the normal bus system, precharge is performed for each bit, so even if the bus potential is lowered to the low level as a whole, it is immediately returned to the precharge level (intermediate level). Since the bus precharge for each bit is not performed, for example, the bus potential is lowered to the low level as a whole. Of course, in the PRD method, for example, data can be reproduced even when the bus is stuck at a low level, but the operation margin is slightly reduced.

  150 is a diagram for explaining the difference in waveform of the data bus depending on the presence or absence of loading in the semiconductor memory device of FIG. 149. FIG. 150 (a) is a waveform diagram of the data bus (2202) when no load is provided. FIG. 150B shows a waveform diagram of the data bus when a load 2413 is provided.

  As is clear from the comparison between FIG. 150 (a) and FIG. 150 (b), when no load is provided (FIG. 150 (a)), the potential of the bus (global data bus 2202) is generally low. When the load 2413 is provided (FIG. 150 (b)), the overall level of the bus (global data bus 2202) is maintained at the intermediate level.

  Here, the size of the load 2413 is, for example, approximately the same size as the PMOS (P-channel MOS transistor) used in the latch (2101) in the sense amplifier 2100 (see FIG. 144). The increase is very small. Thus, by providing the load 2413, the operation margin of the bus amplifier 2300g (2300) can be increased.

  FIG. 151 is a diagram showing an example of loading in the semiconductor memory device of FIG. That is, the load 2413 can be applied with various configurations as shown in FIGS. 151A to 151I in addition to the PMOS as shown in FIG.

  In FIG. 151A, NMOSs connected to the high potential power supply (Vcc) side are provided for the complementary buses bus and / bus (global data bus 2202) as the load 2413, respectively. Is applied with a predetermined load voltage (high level voltage) V2L. FIG. 151 (b) shows the load 2413 provided with resistors connected to the high potential power supply for the buses bus and / bus. FIG. 151 (c) shows the resistances shown in FIG. A PMOS to which the enable signal / en is supplied is provided at the gate with respect to the potential power supply.

  In FIG. 151A, NMOSs connected to the high potential power supply (Vcc) side are provided for the complementary buses bus and / bus (global data bus 2202) as the load 2413, respectively. Is supplied with a predetermined load control signal (enable signal) V2L so that the load is turned on (connected) only when the data bus is used. FIG. 151 (b) shows the load 2413 provided with resistors connected to the high potential power supply for the buses bus and / bus. FIG. 151 (c) shows the resistances shown in FIG. A PMOS to which the enable signal / en is supplied is provided at the gate with respect to the potential power supply. That is, when PMOS or NMOS is used as the load 2413, the load can be turned on only when the data bus is used. However, when a resistor is used, switching control is performed as shown in FIG. 151 (c). A transistor (PMOS in the figure) may be provided.

  FIGS. 151 (d) to 151 (f) show a case where the potential of the bus generally rises to the high level during reading (both of the complementary buses) if nothing is done. In FIG. 151 (d), NMOSs connected to the low potential power supply (Vss) side are provided for the complementary buses bus and / bus as the load 2413, and a predetermined load is provided at the gate of each NMOS. The control signal (enable signal) V3L is supplied, and the load is turned on only when the data bus is used. FIG. 151 (e) shows the load 2413 provided with resistors connected to the low potential power supply for the buses bus and / bus. FIG. 151 (f) shows the NMOS in FIG. It has been replaced with. A predetermined load control signal (enable signal) V4L is supplied to the gate of each PMOS.

  FIGS. 151 (g) to 151 (i) show the case where the potential (Vtt) is other than the high potential power supply Vcc and the low potential power supply Vss. FIG. 151 (g) is complementary to the load 2413. The buses bus and / bus are respectively provided with PMOSs having a predetermined potential (Vtt), FIG. 151 (h) is provided with NMOSs, and FIG. 151 (i ) Is provided with transfer gates composed of PMOS and NMOS, respectively. V5L to V7L (/ V7L) indicate control signals (enable signals), respectively, and the load is turned on (connected) only when the data bus is used.

  152 to 154 are views showing examples of load mounting positions in the semiconductor memory device of the thirteenth embodiment to which the signal transmission system according to the fifth mode of the present invention is applied.

  That is, as shown in FIG. 149, the load (2413) as described above may be distributed in the global data bus 2202 in addition to being provided in the global data bus 2202 (see FIG. 152) or local. It may be provided on the data bus 2201 side (see FIG. 153) or may be provided on both the global data bus 2202 and the local data bus 2201 (see FIG. 154).

  FIG. 155 is a block diagram schematically showing an example of a semiconductor memory device as a 14th embodiment to which the signal transmission system according to the fifth mode of the present invention is applied. The fourteenth embodiment is basically the same as the thirteenth embodiment described above, but the load 2413 is a PMOS cross-couple to the bus.

  As shown in FIG. 155, when the load 2413 is configured as a PMOS cross couple with respect to the complementary buses bus and / bus, the movement amount in the high level direction of the complementary buses is the same as in the thirteenth embodiment. Larger than using a simple load. In the thirteenth embodiment (FIG. 149), the bus potential increases in the direction of the high potential (high level) at the same speed regardless of the high level and the low level. The data bus moving in the low potential (low level) direction is less moved in the high level direction. That is, the fourteenth embodiment not only prevents the data bus (2202) from sticking to a certain potential, but also has an amplifying action to compensate for the drive of the bus by the sense amplifier (2100). Therefore, the operation margin can be further increased.

  FIG. 156 is a diagram comparing the waveforms of the data buses when the loads according to the thirteenth and fourteenth embodiments to which the signal transmission system according to the fifth mode of the present invention is applied are provided.

  As is apparent from a comparison between the waveform of the thirteenth embodiment shown in FIG. 156 (a) and the waveform of the fourteenth embodiment shown in FIG. 156 (b), according to the fourteenth embodiment, the bus amplifier ( It can be seen that the operation margin of the PRD data bus amplifier 2300) can be further increased.

  In the example shown in FIG. 155, the load 2413 is provided with another PMOS in which the enable signal / en is supplied to the gate in order to turn off the load when the data bus is not used.

  FIG. 157 is a diagram showing a modification of the load applied to the semiconductor memory device of FIG.

  As shown in FIG. 157, in the fourteenth embodiment, for example, when the data bus is shifted to the high potential (high level) side, the load PMOS cross couple shown in FIG. What is necessary is just to comprise so that it may be set as an NMOS cross couple and it may be pulled to the low electric potential (low level) side. In the modification of FIG. 157, another NMOS to which the enable signal en is supplied to the gate is provided so that the load 2413 is turned off (cut off) when the data bus is not used.

  Also in the above fourteenth embodiment, as described with reference to FIGS. 152 to 154, the position where the load 2413 is provided can be one or a plurality distributed on the global data bus 2202, It can be provided on the data bus 2201 side, or can be provided on both the global data bus 2202 and the local data bus 2201.

  FIG. 158 is a block diagram schematically showing an example of a semiconductor memory device as a fifteenth embodiment to which the signal transmission system according to the fifth mode of the present invention is applied. The semiconductor memory device of the fifteenth embodiment is basically the same as the thirteenth embodiment of FIG. 149 or the fourteenth embodiment of FIG. 153, but the configuration of the sense amplifier 2100 is different. . That is, in the fifteenth embodiment, a direct sense amplifier (gate receiving sense amplifier) that amplifies the bit line level as it is and outputs it to the read data bus (RDB, / RDB) is applied as the sense amplifier 2100. .

  FIG. 159 is a circuit diagram showing an example of a sense amplifier applied to the semiconductor memory device of FIG. In FIG. 159, reference numeral 2103 denotes a bit line precharge circuit, 2104 denotes a bit line transfer gate, 2105 denotes a read control circuit (sense amplifier unit), 2106 denotes a write control circuit, and 2107 denotes a latch circuit. Reference symbol BTE is a bit line transfer enable signal, RDB and / RDB are read data buses, WDB and / WDB are write data buses, WE is a write enable signal, PLE and NLE are PMOS and NMOS latch enable signals, and Vpr is a bit. A line precharge level, PRE, indicates a bit line precharge signal.

  The sense amplifier shown in FIG. 159 is different from a normal latch type (for example, see FIG. 144), and the read control circuit 2105 directly outputs read data to the read data buses RDB and / RDB by receiving the gate. ing. By adopting this method, it is possible to further increase the data access time. Here, in terms of increasing the data access time, there is no difference from the normal gate receiving sense system, but the gate receiving sense is not a normal latch type sense amplifier (for example, the latch type sense amplifier unit in FIG. 144). By using the sense amplifier section (read control circuit 2105) of the system together with the PRD system bus, the access time can be further improved.

  Further, in the bus adopting the PRD method, as a worst case, the potential of the complementary bus is completely at the high level “H” and the low level “L”. At this time, the sense amplifier data and the bus data are reversed. In such a case, there is a risk that the data of the sense amplifier is inverted (data is destroyed) when the column transfer gate is open for a longer time than a certain time. Therefore, when a normal latch type sense amplifier is used, the time during which the column transfer gate can be opened is limited. However, it is possible to avoid even the latch type if the design is optimized. Therefore, when the gate receiving sense type sense amplifier (direct sense amplifier) is used as in the fifteenth embodiment, the data of the sense amplifier is not significantly affected by the potential of the data bus (RDB, / RDB). It is possible to dramatically increase not only the operation but also the operation and design margin. Examples of direct sense amplifiers include, for example, G. Kitsukawa et al., “A 23-ns 1-Mb BiCMOS DRAM”, IEEE Journal of Solid-State Circuits, Vol. 25, No. 5, October 1990. Referenced.

  FIG. 160 is a waveform diagram for explaining an example of the operation of the semiconductor memory device of FIG.

  The waveform diagram shown in FIG. 160 shows that the precharge level (Vpr) of the buses (RDB, / RDB) before and after data transfer is a high level “H” in a read operation with a burst length of 8 (8-bit units: CL0 to CL7). Vcc) is shown. That is, with respect to the precharge level of the bus, the higher the level, the greater the driving force for the bus of the sense amplifier receiving the NMOS gate. In this case, it is preferable to make the load smaller.

  161 is a waveform diagram for explaining another example of the operation of the semiconductor memory device of FIG.

  The waveform diagram shown in FIG. 161 shows a bus precharge level between a high level “H” and a low level “L” in a read operation with a burst length of 16 (16-bit units: CL0 to CL15). It shows the case where it is close. In this case, the load capability is higher than in the case of FIG.

  In the fifteenth embodiment, the NMOS gate receiving sense is adopted, but it goes without saying that it may be a PMOS gate receiving.

  FIG. 162 is a circuit diagram showing the main configuration of a semiconductor memory device as a 16th embodiment to which the signal transmission system according to the fifth mode of the present invention is applied.

  As shown in FIG. 162, in the sixteenth embodiment, the NMOS gate receiving sense amplifier section (reading control circuit 2105) in the fifteenth embodiment shown in FIG. 159 is replaced with a CMOS gate receiving sense amplifier section (reading control circuit). The circuit is configured as a circuit 2105 ′), and the other configuration is the same as that of the fifteenth embodiment. Note that when combined with the PRD method, the area occupied by the circuit increases, but it is preferable in terms of operation that the read control circuit 2105 'is formed of CMOS.

  FIG. 163 is a block diagram schematically showing an example of a semiconductor memory device as a 17th embodiment to which the signal transmission system according to the fifth mode of the present invention is applied.

  The seventeenth embodiment has basically the same configuration as that of the fourteenth embodiment shown in FIG. 155, but the bus is connected to the local data bus 2201 and the global data bus 2202 as in the fourteenth embodiment. A write amplifier 2010 and a bus amplifier (PRD data bus amplifier) 2300 are provided for each data bus 2200. A load 2413 and a data bus precharge circuit 2402 are also provided for each data bus 2002.

  That is, each PRD type data bus amplifier 2300 directly receives and amplifies data transferred from the transfer gate of the column. The PRD data bus amplifier 2300 is the same as that in the fourteenth embodiment.

  164 is a diagram illustrating an example of operation waveforms of the bus and the bus amplifier in the semiconductor memory device of FIG. 163. FIG. 165 is a diagram illustrating another example of operation waveforms of the bus and the bus amplifier in the semiconductor memory device of FIG. 163. is there.

  As shown in FIG. 164, in the seventeenth embodiment, the data bus 2200 is not formed so long as the local and global data buses (2201, 2202), that is, the length of the data bus 2200 is shortened. Therefore, the bus amplitude can be increased and the operation margin can be increased. This corresponds to the fact that, as shown in FIG. 165, if the column selection cycle is shortened and the bus amplitude level is set to the same level as in the fourteenth embodiment, further high-speed transfer becomes possible. .

  Here, the effect of the seventeenth embodiment described above is not because the buses are divided into the local data bus (2202) and the global data bus (2202) into one data bus 2200. It goes without saying that the same effect can be obtained even if the total data bus is shortened to reduce the time constant of the bus.

  By the way, in a semiconductor memory device, not only the PRD system but also data is output from a sense amplifier to a local data bus (there is no local data bus) and a global data bus, and this data is stored in a memory array (memory cell array). It reaches the data bus amplifier at the end and is amplified. If the unit of this memory array is large, there will be a difference in the distance from the sense amplifier to the bus amplifier. Therefore, in the time from when the column transfer gate opens until the data reaches the bus amplifier, the sense amplifier A difference will occur depending on the position up to. In particular, in the high-speed operation in which the difference in the arrival time of data on the data bus increases with respect to the data transfer rate, in the case of the PRD method, there is a risk of malfunction because the bus amplifier is moved by a clock. . Therefore, if the data skew deviation due to the position of the sense amplifier can be eliminated, the speed increase by the PRD method can be further increased to the high frequency side. Accordingly, the following eighteenth embodiment relates to the configuration and operation of a memory array (semiconductor memory device) that compensates for skew deviation.

  FIG. 166 is a block diagram schematically showing the main configuration of a semiconductor memory device as the 18th embodiment to which the signal transmission system according to the fifth mode of the invention is applied. In FIG. 166, reference numeral 2002a is a main word decoder, 2002b is a sub word decoder, 2100 is a sense amplifier row, 2201 is a local data bus pair, 2202 is a global data bus pair, and 2300 is a data bus amplifier (PRD type data bus amplifier). ).

  The semiconductor memory device shown in FIG. 166 shows a part of a 32 Mbit memory cell array (half a 16 Mbit block: 16 M block). This 16 M block is in the row direction (X direction: vertical direction). There are roughly 8 blocks (2M blocks). Here, each 2M block includes a memory cell array 2001, a sub word decoder column 2002b, a sense amplifier column 2100, a local data bus 2201, a global data bus 2202, and the like, and a bus amplifier 2300 is provided for each global data bus 2202. It has been. Here, each data bus (2201, 2202) is a PRD bus, and the data bus amplifier 2300 is also a PRD bus amplifier.

  167 is a diagram illustrating an example of a bus amplifier in the semiconductor memory device of FIG. 166, FIG. 168 is a circuit diagram illustrating an example of a structural unit of a PRD amplifier in the bus amplifier of FIG. 167, and FIG. 169 is a diagram of the bus amplifier of FIG. It is a circuit diagram which shows an example of a multiplexer. Here, FIGS. 167 to 169 correspond to FIGS. 141 to 143 of the eleventh embodiment described above.

  FIG. 170 is a block diagram showing a configuration example of a column decoder system in the semiconductor memory device according to the eighteenth embodiment to which the signal transmission system according to the fifth mode of the present invention is applied.

  In FIG. 170, reference numerals 2120a and 2120b indicate column decoders (A, B) of two systems (for even and odd addresses), and 2121a and 2121b indicate column system predecoders (A, B) of two systems. Reference numerals 2122a ′ and 2122b ′ denote two systems of column selection line control pulse generation circuits with delay adjustment function (CL pulse generation circuits A and B with delay adjustment function). Reference numeral 2123 indicates a clock generation circuit (forming circuit).

  As shown in FIG. 170, the column decoder system (column decoder 2120) in the eighteenth embodiment is driven by a clock signal (CLK, / CLK) of the second system, for example, driven by a positive logic clock CLK. The first plurality of column decoders A (2120a) and the second plurality of column decoders B (2120b) driven by the inversion logic clock / CLK are interleaved by the column system predecoders 2121a and 2121b to obtain a column transfer gate. Is driven at high speed so that the front and rear column transfer gates overlap each other to some extent. Here, the column predecoder 2121a is supplied with the column address signal for even stages and the clock CLK, and the column predecoder 2121b is supplied with the column address signal for odd stages and the clock / CLK.

  That is, a column address decode signal and a column pulse signal are supplied to the column decoders 2120a and 2120b, a column pulse (column selection line control pulse CL) is supplied after the address is determined, and column transfer is performed in synchronization with the column pulse. The gate operates. A clock (CLK) and a RAS row address (predecode address signal) are input to the CL pulse generation circuits 2122 a ′ and 2122 b ′ with a delay adjustment function. That is, the predecode address signal is an address (3 bits) signal for specifying any of the eight blocks of the row address. In this example, a pre-decode signal for 3 bits is input, but the present invention is not limited to this. In short, an address signal that can select a RAS block may be input.

  In the example shown in FIG. 170, complementary clocks CLK and / CLK are directly supplied from the outside. For example, by providing a clock generation circuit 2123 using a PLL or the like as indicated by a broken line. Further, by generating more rigid clocks CLK and / CLK from the clock CLK ′ inside the chip, it becomes possible to operate at higher speed.

  FIG. 171 is a diagram showing an example of the CL pulse generation circuit (CL pulse generation circuits 2122a 'and 2122b' with delay adjustment function) in FIG.

  As shown in FIG. 171, the CL pulse generation circuit 2122a ′ (2122b ′) with a delay adjustment function in the eighteenth embodiment determines the size of the capacitance provided on the source side of each NMOS according to the RAS predecode address. (C0> C1>...> C7), and a column pulse (column selection line control pulse CL) that rises faster as the distance from the data bus amplifier (2300) increases. . In other words, the CL pulse generation circuit 2122a ′ is arranged so that the column transfer gate rises earlier as the distance from the data bus amplifier increases. In other words, the array 2001 farther from the data bus amplifier 2300 and the sense amplifier 2100 to the data bus 2200 (2201, 2202). The column pulse CL is generated so that the timing at which data is transferred earlier.

  FIG. 172 is a diagram for explaining the operation of the CL pulse generation circuit 66 (CL pulse generation circuit with delay adjustment function) in FIG.

  Data (read data) reaches the data bus amplifier 2300 (2300g) through the local data bus 2201 and the global data bus 2202, but the time required for this is from an array (memory cell array 2001) far from the data bus amplifier 2300. The larger the data, the larger the data.

  Therefore, as shown in FIG. 172, the CL pulse generation circuit 2122a ′ (2122b ′) generates a column pulse CL that rises earlier as the distance from the data bus amplifier 2300 increases, so that the data output from any array can be obtained. The data bus amplifier 2300 is configured to reach the same time. That is, by controlling the rise time of the pulses in the CL pulse generation circuits 2122a ′, 2122b ′ with delay adjustment function so as to cancel the delay in the data bus + the delay of the signal line that drives the column transfer gate, The data arrival time in the data bus amplifier 2300 can always be the same timing, and the data confirmation can always be made constant. Since the PRD bus amplifier operates with a clock, it is possible to prevent malfunction of the amplifier at high speed operation by making the data always come at the same timing. That is, this method enables high-speed operation at a higher level of the PRD method memory bus.

  Of course, in this example, 32M blocks are divided into 8 blocks in the row direction, but the number of blocks is not limited to this, and the memory capacity is not limited to this. Furthermore, any method may be employed as long as the rise of the column pulse signal (CL) is advanced according to the distance from the data bus amplifier of the row block, or the rise of the column pulse signal is delayed as the block is closer to the data bus amplifier. In the above example, the length of the local data bus is set so as not to cause skew deviation on the local data bus.

  FIG. 173 is a diagram showing another example of the bus amplifier in the semiconductor memory device of FIG. 166, FIG. 174 is a circuit diagram showing an example of a unit of the PRD amplifier in the bus amplifier of FIG. 173, and FIG. 175 is the bus of FIG. It is a circuit diagram which shows an example of the latch in amplifier. Here, FIGS. 173 to 175 correspond to FIGS. 129 to 131 of the ninth embodiment described above.

  As described above, even when the above-described ninth embodiment is applied, although the transfer rate is lower than that of the bus amplifier shown in FIGS. 167 to 169 described above, high-speed data transfer is possible as compared with the conventional semiconductor memory device. is there. When the bus amplifier (PRD data bus amplifier 2300e) shown in FIGS. 173 to 175 is applied, the area occupied by the circuit can be reduced as compared with the bus amplifier (2300g) shown in FIGS. 167 to 169. There is a merit.

  FIG. 176 is a block diagram showing another configuration example of the column decoder system in the semiconductor memory device according to the eighteenth embodiment to which the signal transmission system according to the fifth mode of the present invention is applied.

  As is apparent from a comparison between FIG. 176 and FIG. 170, the column decoder system configuration example shown in FIG. 176 does not perform interleaving, and the column decoder 2120 is driven by a clock (positive logic clock CLK). It is like that. As described in the description of FIG. 170, a clock generation circuit 2123 using a PLL or the like as shown by a broken line in FIG. 176 is provided to generate a more rigid clock CLK from the clock CLK ′ inside the chip. You can also.

  FIG. 177 is a block diagram schematically showing a main configuration of a semiconductor memory device as a nineteenth embodiment to which the signal transmission system according to the fifth mode of the present invention is applied. FIG. 178 is a semiconductor memory device of FIG. It is a figure which shows an example of the CL pulse generation circuit applied to FIG. Here, FIGS. 177 and 178 correspond to FIGS. 166 and 171 showing the eighteenth embodiment described above.

  That is, as shown in FIG. 177, in the nineteenth embodiment, the 16M blocks of the memory cell array (array) are roughly divided into four blocks (4M blocks) in the row direction (X direction: vertical direction). There are other configurations similar to the eighteenth embodiment.

  However, as shown in FIG. 178, the control of the delay value in the CL pulse generation circuit (CL pulse generation circuits 2122a ′ and 2122b ′ with delay adjustment function) changes the size of the capacitor provided in the NMOS source. Instead, a column pulse (column selection line control pulse CL) that rises earlier as the distance from the data bus amplifier (2300) becomes longer depending on the number of delay stages (delay units including NAND gates and inverters) connected in cascade. Configured to generate. Needless to say, the configuration of the delay stage can be changed in various ways.

  As described above, in each example of the fifth mode of the present invention, the case where it is applied to a semiconductor memory device (DRAM) has been mainly described. However, the signal transmission system of the present invention is limited to the DRAM. Of course not.

  In the above, the signal transmission system according to the present invention is not limited to a bus system that connects a plurality of semiconductor chips (LSIs), and can be applied to signal lines between various circuit blocks.

It is a block diagram which shows an example of the conventional signal transmission system roughly. It is a block diagram which shows the principle structure of the signal transmission system with which this invention is applied. It is a figure which shows the relationship between the length of the code | cord | chord in a conventional general signal transmission system, and response time. It is a figure which shows the relationship between the length of the code | cord | chord in the signal transmission system of this invention, and response time. It is a figure which shows one structural example of the receiver circuit in the signal transmission system which concerns on this invention. It is a figure for demonstrating operation | movement of the receiver circuit of FIG. 1 is a block circuit diagram showing an embodiment of a signal transmission system to which the present invention is applied. It is a figure which shows the signal waveform in each memory block in the signal transmission system of FIG. It is a block diagram which shows 1st Example of the signal transmission system which concerns on the 1st form of this invention. It is a block diagram which shows 2nd Example of the signal transmission system which concerns on the 1st form of this invention. It is a block diagram which shows 3rd Example of the signal transmission system which concerns on the 1st form of this invention. It is a block circuit diagram which shows 1st Example of the receiver circuit of the signal transmission system which concerns on the 2nd form of this invention. It is a block circuit diagram which shows 2nd Example of the receiver circuit of the signal transmission system which concerns on the 2nd form of this invention. It is a block circuit diagram which shows 3rd Example of the receiver circuit of the signal transmission system which concerns on the 2nd form of this invention. It is a block circuit diagram which shows the 4th Example of the receiver circuit of the signal transmission system which concerns on the 2nd form of this invention. FIG. 6 is a circuit diagram illustrating an example of an auto-zero comparator in the receiver circuit of FIG. 5. FIG. 6 is a circuit diagram showing another example of an auto-zero comparator in the receiver circuit of FIG. 5. FIG. 6 is a circuit diagram showing still another example of an auto-zero comparator in the receiver circuit of FIG. 5. It is a block diagram which shows the 1st example with which the signal transmission system of this invention is applied. It is a block diagram which shows the 2nd example with which the signal transmission system of this invention is applied. It is a block diagram which shows the 3rd example to which the signal transmission system of this invention is applied. It is a block diagram which shows the 4th example with which the signal transmission system of this invention is applied. It is a block diagram which shows the 5th example with which the signal transmission system of this invention is applied. It is a block diagram which shows the 6th example to which the signal transmission system of this invention is applied. It is a block diagram which shows roughly the other example of the conventional signal transmission system. It is a block diagram which shows the principle structure of the signal transmission system as the 3rd form of this invention. FIG. 27 is a diagram (No. 1) for explaining the operation of the signal transmission system of FIG. 26; FIG. 27 is a diagram (No. 2) for explaining the operation of the signal transmission system of FIG. 26; It is a block diagram which shows 1st Example of the signal transmission system which concerns on the 3rd form of this invention. It is a block diagram which shows the modification of the signal transmission system of FIG. It is a block diagram which shows an example of a principal part structure of each device in the signal transmission system which concerns on the 3rd form of this invention. It is a block diagram which shows the other example of a principal part structure of each device in the signal transmission system which concerns on the 3rd form of this invention. It is a block diagram which shows 2nd Example of the signal transmission system which concerns on the 3rd form of this invention. It is a block diagram which shows 3rd Example of the signal transmission system which concerns on the 3rd form of this invention. It is a block diagram which shows the modification of the signal transmission system of FIG. It is a block diagram which shows 4th Example of the signal transmission system which concerns on the 3rd form of this invention. It is a circuit diagram which shows an example of the driver circuit in the signal transmission system which concerns on the 3rd form of this invention. It is a block diagram which shows 5th Example of the signal transmission system which concerns on the 3rd form of this invention. It is a block diagram which shows the 6th Example of the signal transmission system which concerns on the 3rd form of this invention. It is a block diagram which shows 7th Example of the signal transmission system which concerns on the 3rd form of this invention. It is a circuit diagram which shows an example of the common timing signal generation circuit in the signal transmission system which concerns on the 3rd form of this invention. It is a circuit diagram which shows the other example of the common timing signal generation circuit in the signal transmission system which concerns on the 3rd form of this invention. FIG. 43 is a circuit diagram illustrating an example of a comparator in the common timing signal generation circuit of FIG. 42. It is a circuit diagram which shows the further another example of the common timing signal generation circuit in the signal transmission system which concerns on the 3rd form of this invention. It is a block diagram which shows 8th Example of the signal transmission system which concerns on the 3rd form of this invention. It is a figure which shows an example of the transmission path for clock distribution in the signal transmission system which concerns on the 3rd form of this invention. It is a block diagram which shows the principle structure of the signal transmission system which concerns on the 4th form of this invention. 48 is a timing chart for explaining the operation of the signal transmission system of FIG. 47. FIG. It is a block diagram which shows 1st Example of the signal transmission system which concerns on the 4th form of this invention. FIG. 50 is a block diagram illustrating an example of a common timing signal generation circuit applied to the signal transmission system of FIG. 49. FIG. 50 is a block diagram showing an example of a forward clock generation circuit applied to the signal transmission system of FIG. 49. FIG. 50 is a block diagram (part 1) illustrating another example of a common timing signal generation circuit applied to the signal transmission system of FIG. 49; FIG. 50 is a block diagram (No. 2) showing another example of the common timing signal generation circuit applied to the signal transmission system of FIG. 49; FIG. 50 is a block diagram illustrating an example of a backward clock generation circuit applied to the signal transmission system of FIG. 49. FIG. 50 is a circuit diagram illustrating an example of a phase comparison circuit applied to a common timing signal generation circuit of the signal transmission system of FIG. 49. It is a block diagram which shows an example of the control circuit applied to the common timing signal generation circuit of the signal transmission system of FIG. FIG. 50 is a circuit diagram illustrating an example of a variable delay circuit applied to a common timing signal generation circuit of the signal transmission system of FIG. 49. It is a block diagram which shows 2nd Example of the signal transmission system which concerns on the 4th form of this invention. It is a block diagram which shows 3rd Example of the signal transmission system which concerns on the 4th form of this invention. It is a block diagram which shows an example of the forward clock generation circuit applied to the signal transmission system as 4th Example based on the 4th form of this invention. It is a block diagram which shows an example of the backward clock generation circuit applied to the signal transmission system as 5th Example based on the 4th form of this invention. It is a block diagram which shows the other example of the backward clock generation circuit applied to the signal transmission system as 6th Example which concerns on the 4th form of this invention. It is a figure for demonstrating operation | movement of the backward clock generation circuit applied to the signal transmission system as the 7th Example which concerns on the 4th form of this invention. It is a block diagram which shows the further another example of the backward clock generation circuit applied to the signal transmission system as the 8th Example which concerns on the 4th form of this invention. It is a block circuit diagram which shows an example of the sine wave generation circuit applied to the signal transmission system as 9th Example based on the 4th form of this invention. FIG. 66 is a circuit diagram illustrating an example of a nonlinear amplifier in the sine wave generation circuit of FIG. 65. It is a block diagram which shows an example of the common timing signal generation circuit applied to the signal transmission system as 10th Example which concerns on the 4th form of this invention. FIG. 68 is a circuit diagram illustrating an example of a differential comparator in the common timing signal generation circuit of FIG. 67. It is a block diagram which shows an example of the termination resistance in the signal transmission system as 11th Example based on the 4th form of this invention. It is a block diagram for demonstrating the supply system of the forward clock in the signal transmission system as 12th Example based on the 4th form of this invention. It is a block diagram which shows the principal part at the time of applying the signal transmission system as 13th Example based on the 4th form of this invention to a printed circuit board. It is a block diagram which shows the principal part at the time of applying the signal transmission system as 14th Example based on the 4th form of this invention to a semiconductor integrated circuit. It is a block diagram which shows typically an example of the conventional semiconductor memory device corresponding to the 5th form of this invention. FIG. 74 is a circuit diagram showing an example of a sense amplifier in the semiconductor memory device of FIG. 73. FIG. 74 is a circuit diagram showing an example of a data bus amplifier in the semiconductor memory device of FIG. 73. FIG. 74 is a circuit diagram showing an example of a data bus short precharge circuit in the semiconductor memory device of FIG. 73. FIG. 74 is a waveform diagram for explaining an example of a data read sequence in the semiconductor memory device of FIG. 73. It is a block diagram which shows the 1st principle structure of the signal transmission system which concerns on the 5th form of this invention. FIG. 79 is a waveform diagram for explaining the operation of the signal transmission system of FIG. 78; It is a block diagram which shows the 2nd principle structure of the signal transmission system which concerns on the 5th form of this invention. It is a wave form diagram for demonstrating operation | movement of the signal transmission system of FIG. It is a block diagram which shows the 3rd principle structure of the signal transmission system which concerns on the 5th form of this invention. FIG. 83 is a waveform diagram (part 1) for explaining the operation of the signal transmission system of FIG. 82; FIG. 83 is a waveform diagram (part 2) for describing the operation of the signal transmission system of FIG. 82; It is a block diagram which shows typically an example of the semiconductor memory device to which the signal transmission system which concerns on the 5th form of this invention is applied. It is a block diagram which shows typically the principal part of 1st Example of the signal transmission system which concerns on the 5th form of this invention. FIG. 87 is a circuit diagram showing a configuration example of a driver and a bus amplifier in the signal transmission system of FIG. 86. FIG. 88 is a diagram showing an example of signal waveforms for operating the bus amplifier of FIG. 87. FIG. 87 is a diagram showing an example of bus operation waveforms in the signal transmission system of FIG. 86. It is a block diagram which shows typically the principal part of 2nd Example of the signal transmission system which concerns on the 5th form of this invention. FIG. 91 is a circuit diagram showing an example of a precharge circuit in the signal transmission system of FIG. 90. FIG. 91 is a diagram illustrating an example of signal waveforms for operating a bus and a bus amplifier in the signal transmission system of FIG. 90. FIG. 91 is a diagram illustrating an example of bus operation waveforms in the signal transmission system of FIG. 90. It is a block diagram which shows typically the principal part of 3rd Example of the signal transmission system which concerns on the 5th form of this invention. FIG. 95 is a diagram illustrating a configuration example of a driver and a bus amplifier in the signal transmission system of FIG. 94. FIG. 96 is a circuit diagram showing an example of a PRD amplifier and a latch amplifier in the bus amplifier of FIG. 95. FIG. 96 is a diagram showing an example of signal waveforms for operating the bus amplifier of FIG. 95. FIG. 95 is a diagram illustrating an example of operation waveforms of a bus and a bus amplifier in the signal transmission system of FIG. 94. It is a block diagram which shows typically the principal part of 4th Example of the signal transmission system which concerns on the 5th form of this invention. FIG. 99 is a diagram illustrating a configuration example of a precharge circuit and a bus amplifier in the signal transmission system of FIG. 99. FIG. 100 is a circuit diagram illustrating an example of a PRD amplifier and a current mirror amplifier in the bus amplifier of FIG. 100. It is a figure which shows an example of the signal waveform for operating the bus amplifier of FIG. FIG. 100 is a diagram illustrating an example of operation waveforms of a bus and a bus amplifier in the signal transmission system of FIG. 99. It is a block diagram which shows typically the principal part of 5th Example of the signal transmission system which concerns on the 5th form of this invention. FIG. 105 is a block circuit diagram showing an example of a bus amplifier in the signal transmission system of FIG. 104. It is a wave form diagram which shows the relationship between the time constant of a bus | bath, and the period for 1 bit. FIG. 106 is a diagram for explaining the operation of the bus amplifier of FIG. 105. FIG. 103 is a diagram showing another example of the bus amplifier in the signal transmission system of FIG. 104. FIG. 109 is a circuit diagram showing an example of a structural unit of a PRD amplifier in the bus amplifier of FIG. 108. FIG. 109 is a circuit diagram showing an example of a multiplexer in the bus amplifier of FIG. 108. FIG. 109 is a diagram showing an example of signal waveforms for operating the bus amplifier of FIG. 108. FIG. 105 is a diagram showing an example of operation waveforms of a bus and a bus amplifier in the signal transmission system of FIG. 104. It is a figure which shows an example of the bus amplifier in the signal transmission system as a 6th Example of the signal transmission system which concerns on the 5th form of this invention. FIG. 114 is a circuit diagram illustrating an example of a structural unit of a PRD amplifier in the bus amplifier of FIG. 113. FIG. 114 is a circuit diagram illustrating another example of the structural unit of the PRD amplifier in the bus amplifier of FIG. 113. FIG. 114 is a circuit diagram illustrating an example of a multiplexer in the bus amplifier of FIG. 113. It is a figure which shows an example of the operation | movement waveform of the bus | bath and bus amplifier in 6th Example of the signal transmission system which concerns on the 5th form of this invention. It is a figure which shows an example of the bus amplifier in the signal transmission system as 7th Example of the signal transmission system which concerns on the 5th form of this invention. FIG. 119 is a circuit diagram illustrating an example of a structural unit of a PRD amplifier in the bus amplifier of FIG. 118. FIG. 120 is a circuit diagram showing an example of a multiplexer in the bus amplifier of FIG. 118. FIG. 119 is a diagram illustrating an example of a signal waveform for operating the bus amplifier in FIG. 118. It is a figure which shows an example of the operation | movement waveform of the bus | bath and bus amplifier in 7th Example of the signal transmission system which concerns on the 5th form of this invention. It is a figure which shows an example of the bus amplifier in the signal transmission system as an 8th Example of the signal transmission system which concerns on the 5th form of this invention. 124 is a circuit diagram showing an example of a structural unit of a PRD amplifier in the bus amplifier of FIG. 123. FIG. FIG. 123 is a diagram for explaining the operation of the bus amplifier of FIG. 124. 124 is a circuit diagram showing an example of a multiplexer in the bus amplifier of FIG. 123. FIG. 124 is a diagram showing an example of signal waveforms for operating the bus amplifier of FIG. 123. FIG. It is a figure which shows an example of the operation | movement waveform of the bus | bath and bus amplifier in 8th Example of the signal transmission system which concerns on the 5th form of this invention. It is a figure which shows an example of the bus amplifier in the signal transmission system as 9th Example of the signal transmission system which concerns on the 5th form of this invention. 129 is a circuit diagram illustrating an example of a structural unit of a PRD amplifier in the bus amplifier of FIG. 129. FIG. FIG. 129 is a circuit diagram illustrating an example of a latch in the bus amplifier of FIG. 129. 129 is a diagram illustrating an example of signal waveforms for operating the bus amplifier in FIG. 129; FIG. It is a figure which shows an example of the operation | movement waveform of the bus | bath and bus amplifier in 9th Example of the signal transmission system which concerns on the 5th form of this invention. It is a figure which shows an example of the bus amplifier in the signal transmission system as a 10th Example of the signal transmission system which concerns on the 5th form of this invention. FIG. 135 is a circuit diagram illustrating an example of a configuration unit of a PRD amplifier in the bus amplifier of FIG. 134 and another example. FIG. 135 is a circuit diagram showing still another example of a structural unit of a PRD amplifier in the bus amplifier of FIG. 134. It is a circuit diagram which shows an example of the multiplexer in the bus amplifier of FIG. It is a figure which shows an example of the signal waveform for operating the bus amplifier of FIG. It is a figure which shows an example of the operation | movement waveform of the bus | bath and bus amplifier in 10th Example of the signal transmission system which concerns on the 5th form of this invention. It is a block diagram which shows typically an example of the semiconductor memory device as 11th Example to which the signal transmission system which concerns on the 5th form of this invention is applied. FIG. 141 is a diagram showing an example of a bus amplifier in the semiconductor memory device of FIG. 140. FIG. 142 is a circuit diagram showing an example of a structural unit of a PRD amplifier in the bus amplifier of FIG. 141. FIG. 142 is a circuit diagram showing an example of a multiplexer in the bus amplifier of FIG. 141. FIG. 141 is a circuit diagram showing an example of a sense amplifier in the semiconductor memory device of FIG. 140. FIG. 141 is a diagram showing an example of operation waveforms of a bus and a bus amplifier in the semiconductor memory device of FIG. 140. It is a block diagram which shows typically an example of the semiconductor memory device as a 12th Example to which the signal transmission system which concerns on the 5th form of this invention is applied. FIG. 147 is a block diagram showing a configuration example of a column decoder system in the semiconductor memory device of FIG. 146. 146 is a diagram showing an example of operation waveforms of a bus and a bus amplifier in the semiconductor memory device of FIG. 146; FIG. It is a block diagram which shows typically an example of the semiconductor memory device as 13th Example to which the signal transmission system which concerns on the 5th form of this invention is applied. FIG. 145 is a diagram for describing a difference in waveform of a data bus depending on presence / absence of load in the semiconductor memory device of FIG. FIG. 146 is a diagram showing an example of loading in the semiconductor memory device of FIG. 149; It is a figure which shows an example of the attachment position of the load in the semiconductor memory device of 13th Example to which the signal transmission system which concerns on the 5th form of this invention is applied. It is a figure which shows the other example of the attachment position of the load in the semiconductor memory device of 13th Example to which the signal transmission system which concerns on the 5th form of this invention is applied. It is a figure which shows the further another example of the attachment position of the load in the semiconductor memory device of 13th Example to which the signal transmission system which concerns on the 5th form of this invention is applied. It is a block diagram which shows typically an example of the semiconductor memory device as 14th Example to which the signal transmission system which concerns on the 5th form of this invention is applied. It is a figure which compares and shows the waveform of the data bus at the time of providing the load by the 13th Example and 14th Example to which the signal transmission system which concerns on the 5th form of this invention is applied. FIG. 165 is a diagram showing a modification of the load applied to the semiconductor memory device of FIG. 155. It is a block diagram which shows typically an example of the semiconductor memory device as 15th Example to which the signal transmission system which concerns on the 5th form of this invention is applied. 158 is a circuit diagram illustrating an example of a sense amplifier applied to the semiconductor memory device in FIG. 158. FIG. FIG. 158 is a waveform diagram for describing an example of operation of the semiconductor memory device in FIG. 158. FIG. 158 is a waveform diagram for describing another example of the operation of the semiconductor memory device in FIG. 158. It is a circuit diagram which shows the principal part structure in the semiconductor memory device as a 16th Example to which the signal transmission system which concerns on the 5th form of this invention is applied. It is a block diagram which shows typically an example of the semiconductor memory device as a 17th Example to which the signal transmission system which concerns on the 5th form of this invention is applied. FIG. 167 is a diagram showing an example of operation waveforms of a bus and a bus amplifier in the semiconductor memory device of FIG. 163. FIG. 167 is a diagram showing another example of operation waveforms of a bus and a bus amplifier in the semiconductor memory device of FIG. 163. It is a block diagram which shows typically the principal part structure of the semiconductor memory device as 18th Example to which the signal transmission system which concerns on the 5th form of this invention is applied. 167 is a diagram illustrating an example of a bus amplifier in the semiconductor memory device in FIG. 166. FIG. 167 is a circuit diagram illustrating an example of a structural unit of a PRD amplifier in the bus amplifier of FIG. 167. FIG. 167 is a circuit diagram illustrating an example of a multiplexer in the bus amplifier of FIG. 167. FIG. It is a block diagram which shows one structural example of the column decoder system in the semiconductor memory device of 18th Example to which the signal transmission system which concerns on the 5th form of this invention is applied. FIG. 170 is a diagram showing an example of a CL pulse generation circuit in FIG. 170. FIG. 171 is a waveform diagram for explaining the operation of the CL pulse generation circuit of FIG. 167 is a diagram showing another example of the bus amplifier in the semiconductor memory device of FIG. 166. FIG. 174 is a circuit diagram illustrating an example of a structural unit of a PRD amplifier in the bus amplifier of FIG. 173; FIG. FIG. 174 is a circuit diagram illustrating an example of a latch in the bus amplifier of FIG. 173; It is a block diagram which shows the other structural example of the column decoder system in the semiconductor memory device of 18th Example to which the signal transmission system which concerns on the 5th form of this invention is applied. It is a block diagram which shows typically the principal part structure of the semiconductor memory device as a 19th Example to which the signal transmission system which concerns on the 5th form of this invention is applied. 178 is a diagram illustrating an example of a CL pulse generation circuit applied to the semiconductor memory device in FIG. 177. FIG.

Explanation of symbols

1, 201, 301 Driver circuit 2, 202, 302 Signal transmission path 3, 203, 303; 4, 204, 304 Termination resistance (R _T )
51-53, 250-254, 351-354 Stub resistance (R _S )
61,310 processor (controller)
62-63, 261-264, 361-364 Memory module 7,207,307 Damping resistance (R _D )
41,541 Differential amplifier 42,542 Determination circuit 43,543 Shift register 45 Resistance ladder circuit 451-454 Resistance 451'-454 ', 514,515,551-554 Capacitor 47,461-464,511-513,543 561-564 switch 48 memory 49 D / A converter 7-0 DRAM controller (controller: circuit block)
7-1-7-n DRAM chip (device: circuit block)
701, 702 Termination resistor 703 Signal transmission line (signal line)
704 Clock termination resistor 705 Clock generation source 706 Clock line 711 Common timing signal generation circuit 781 Driver circuit 782 PRD (Partial response detection circuit)
783 Equalizer 1100 Forward clock generation circuit 1200 Return clock generation circuit 1300 Common timing signal generation circuit 1301 First variable delay circuit 1302 Second variable delay circuit 1303 Phase comparison circuit 1304 Control circuit 2001 Memory cell array 2002 Word decoder (word decoder string) )
2003 Sense amplifier (sense amplifier array)
2010 Light amplifier 2100 Driver (sense amplifier)
2120 Column decoder (column decoder row)
2121 Column predecoder 2122 CL pulse generation circuit with delay adjustment function 2200 Bus (signal transmission path)
2201 Local data bus 2202 Global data bus 2209 Sense amplifier driver 2300 PRD system amplifier (PRD system data bus amplifier)
2301 PRD functional portion 2302 Amplifier precharge circuit 2303 Differential amplifier 2310 First PRD amplifier 2320 Second PRD amplifier 2330 Latch type amplifier 2340 Current mirror type amplifier 2400 Precharge circuit 2401 Local data bus precharge circuit 2402 Global data Bus precharge circuit 2413, 2500 Load

Claims (50)

A signal transmission system that performs signal transmission between a plurality of circuit blocks via a signal transmission path,
The signal transmission system includes a receiver circuit,
The receiver circuit is
A first switch provided on the reference potential line ;
A first capacitor connected to the first switch;
A second switch provided in the signal transmission path ;
A second capacitor having a first end connected to the first capacitor and a second end connected to the second switch;
A third switch;
A logic determination unit having an input connected to the first capacitor and the second capacitor, and the input and the output connected via the third switch,
In the first state in which the first switch is off, the second switch is on and the third switch is off, the first signal state of the signal transmission path is determined by the logic determination unit, and the first switch is in the second state where the second switch is turned on is the third switch is turned on off, the first signal state of the signal transmission line and held in the capacitor to the first, then the first switch is turned off in the second switch is in a third state in which the third switch is turned on is turned off, the second signal state of the signal transmission path to input to the capacitor to the second, the logic determines the second signal state The signal transmission system characterized by determining by a part.   The signal transmission system according to claim 1, wherein the signal transmission path has a single-ended configuration.   2. The signal transmission path according to claim 1, wherein the signal transmission path is configured as a complementary bus, and the signal transmission system includes a complementary bus amplifier having a complementary bus driver and the receiver circuit. Signal transmission system.   Further, the signal transmission system does not precharge the signal transmission path every bit during data transmission, and precharges the signal transmission path to a predetermined level potential except during the data transmission. 4. The signal transmission system according to claim 3, further comprising a precharge circuit.   The precharge circuit is configured to precharge the signal transmission path only for a predetermined period before and after data transmission, or to perform precharge of the signal transmission path in all periods other than data transmission. The signal transmission system according to claim 4.   5. The signal transmission system according to claim 4, wherein the precharge circuit arbitrarily precharges the signal transmission path from the outside. The second capacitor is coupled to a bus opposite to the bus to which the first capacitor is coupled to the same differential input unit during intersymbol interference component estimation operation, and is the same during data determination by volume the first attached to the differential input section is coupled to the bus to which they are attached claims 3-6, characterized in that is adapted to remove the intersymbol interference component of complement The signal transmission system according to claim 1. The value of the first capacitor is C10, the value of the second capacitor is C20, the time constant of the bus is τ, and the time when data for 1 bit appears on the bus or the cycle for 1 bit is T When
The value of the first and second capacitance, wherein: C10 / (C10 + C20) = (1 + exp (-T / τ)) according to claim 3-7, characterized in that it is a / 2 to satisfy almost The signal transmission system according to claim 1. Said complementary bus amplifier, signal transmission system according to any one of claims 3-7, characterized in that it comprises a differential amplifier of the latch type. The differential amplifier sets the output node of the differential amplifier to a high level when the transistor receiving data is an N-channel type except when reading data, or the differential amplifier when the transistor receiving data is a P-channel type. 10. The signal transmission system according to claim 9 , wherein the operation speed is improved by setting the output node of the amplifier to a low level. The differential amplifier is configured such that when a transistor receiving data is an N-channel type during an intersymbol interference component removal operation and a differential amplifier input node precharge operation other than during data transfer and during data read, 10. The signal transmission according to claim 9 , wherein the operation speed is improved by setting the output node to a high level or setting the output node of the differential amplifier to a low level when the transistor receiving the data is a P-channel type. system. Said complementary bus amplifier, signal transmission system according to any one of claims 3-7, characterized in that it comprises a current mirror type differential amplifier. The complementary bus amplifier, signal transmission system according to any one of claims 3-7, characterized in that the non-data transfer comprises a differential amplifier which is not operating. The signal transmission system according to any one of claims 3 to 13 , wherein the complementary bus amplifier is provided as a data bus amplifier, the complementary bus driver is provided as a sense amplifier, and the complementary bus is provided. A semiconductor memory device provided as a data bus, wherein the data bus amplifier removes an intersymbol interference component in data transmitted from the sense amplifier via the data bus, thereby precharging the data bus. A semiconductor memory device characterized in that data is continuously read without being transferred. 15. The semiconductor memory device according to claim 14 , wherein the semiconductor memory device is a dynamic random access memory. 16. The semiconductor memory device according to claim 14 , wherein the data bus has a hierarchical structure. The data bus includes a local data bus for transferring data from the sense amplifier via a selected column gate, and a global data bus for transferring data of the local data bus via a selected local data bus switch. The semiconductor memory device according to claim 14 , wherein the semiconductor memory device is a semiconductor memory device. The data bus amplifier reads data by interleaving the two amplifier units with intersymbol interference component removal function provided in parallel at the rising and falling timings of the clock or the rising timing of the complementary clock. The semiconductor memory device according to claim 14 , wherein the semiconductor memory device is a semiconductor memory device. The semiconductor memory device further includes a first column selection signal generating means including a column decoder and a column selection signal generating circuit for generating a column selection signal from a clock rising timing, and a clock falling timing or an inverted clock rising timing. And a second column selection signal generating means having a column selection signal generating circuit and a column selection signal generating circuit, and by interleaving the first and second column selection signal generating means 19. The semiconductor memory device according to claim 14, wherein a column selection signal is switched. 20. The semiconductor memory device according to claim 19 , wherein the first and second column selection signal generating units generate column selection signals by overlapping them. 21. The semiconductor memory device according to claim 14 , wherein the data bus amplifier is configured to read data by a single amplifier unit having an intersymbol interference component removal function. The amplifier unit with the intersymbol interference component removing function performs an estimation operation of the intersymbol interference component at the rising or falling timing of the clock, and performs a data determination operation at the falling or rising timing of the clock. The semiconductor memory device according to claim 21 , wherein The semiconductor memory device according to claim 14 , wherein the semiconductor memory device includes a load provided on the data bus. When the data bus gradually shifts to a low level when there is no load, the load is composed of a P-channel MOS transistor of a size that suppresses the shift of the data bus, and the complementary type Each data bus is driven to a high level via the P-channel MOS transistor, and the load operation is stopped by turning off the P-channel MOS transistor except during data transfer. 24. The semiconductor memory device according to claim 23 , wherein: When the data bus gradually shifts to a low level when there is no load, the load is composed of an N-channel MOS transistor of a size that suppresses the shift of the data bus, and the complementary bus Each data bus is driven to a high level via the N-channel MOS transistor, and the load operation is stopped by turning off the N-channel MOS transistor except during data transfer. 24. The semiconductor memory device according to claim 23 , wherein: When the data bus is gradually shifted to the low level when there is no load, the load is constituted by a resistor, the resistor is connected to a high level via a transistor, and other than during data transfer 24. The semiconductor memory device according to claim 23 , wherein the load is stopped by turning off the transistor. When the data bus gradually shifts to a low level when there is no load, the load is configured as a cross-couple of a P-channel MOS transistor, and the cross-coupled P-channel MOS transistor is controlled. Connected to a high level via a transistor, configured so that one bus to which high-level data is transferred is pulled higher than the other bus to which low-level data is transferred, and at the time of data transfer 24. The semiconductor memory device according to claim 23 , wherein the load operation is stopped by turning off the control transistor except for the above. When the data bus is gradually shifted to a higher level when there is no load, the load is constituted by an N-channel MOS transistor having a size sufficient to suppress the shift of the data bus, and the complementary type Each data bus is driven to a low level via the N-channel MOS transistor, and the load operation is stopped by turning off the N-channel MOS transistor except during data transfer. 24. The semiconductor memory device according to claim 23 , wherein: When the data bus is gradually shifted to a higher level when there is no load, the load is composed of a P-channel MOS transistor having a size that suppresses the shift of the data bus. Each data bus is driven to a low level via the P-channel MOS transistor, and the load operation is stopped by turning off the P-channel MOS transistor except during data transfer. 24. The semiconductor memory device according to claim 23 , wherein: When the data bus gradually shifts to a high level when there is no load, the load is configured by a resistor, the resistor is connected to a low level via a transistor, and other than during data transfer 24. The semiconductor memory device according to claim 23 , wherein the load operation is stopped by turning off the transistor. When the data bus gradually shifts to a high level when there is no load, the load is configured as a cross-couple of N-channel MOS transistors and the cross-coupled N-channel MOS transistors are controlled. Connected to a low level via a transistor, configured so that one bus to which low level data is transferred is pulled to a lower level than the other bus to which high level data is transferred, and at the time of data transfer 24. The semiconductor memory device according to claim 23 , wherein the load operation is stopped by turning off the control transistor except for the above. The load is provided only at one location on the global data bus, distributed at multiple locations on the global data bus, and only at the local data bus, or distributed at multiple locations on the global data bus and the local data bus. 32. The semiconductor memory device according to claim 23 , wherein: The semiconductor memory device according to claim 14 , wherein the sense amplifier is configured as a cross couple of CMOS transistors. The sense amplifier receives the difference potential of the bit line at the gate, transfers data to the data bus before the bit line is fully opened, and prevents the sense amplifier data from being inverted by the difference potential of the data bus. The semiconductor memory device according to claim 14 , wherein the semiconductor memory device is configured as described above. 35. The semiconductor memory device according to claim 34 , wherein the sense amplifier is configured as a P-channel or N-channel MOS transistor gate receiver amplifier or a CMOS transistor gate receiver amplifier. In the semiconductor memory device, the distance from the column selection signal generation circuit to the selected sense amplifier and the distance from the selected sense amplifier to the data bus amplifier via the data bus are selected. The time depending on the position of the sense amplifier from when the column selection signal is generated to when the sense amplifier is selected and the data is output and reaches the data bus amplifier, which is caused by the difference depending on the position of the sense amplifier in the memory cell array. 36. The compensation signal according to any one of claims 14 to 35 , wherein the control signal used in the data bus amplifier comes to a portion where the data reaching the data bus amplifier becomes valid by compensating for the deviation. The semiconductor memory device according to item. The semiconductor memory device generates the column selection signal at a later timing as the sense amplifier is closer to the column selection signal generation circuit and the data bus amplifier, and from the column selection signal generation circuit and the data bus amplifier. The column selection signal is generated at an earlier timing as the sense amplifier is farther away, and the timing at which data arrives at the data bus amplifier is made substantially constant regardless of the position of each sense amplifier. Item 37. The semiconductor memory device according to Item 36 . The semiconductor memory device is divided into a plurality of memory blocks crossing the length direction of the data bus directly connected to the data bus amplifier, and a block selection address for selecting the memory block is input to the column selection signal generation circuit, The delay amount in the column selection signal generation circuit is controlled by the block selection address so that the timing at which data arrives at the data bus amplifier is substantially constant regardless of the position of each sense amplifier. A semiconductor memory device according to claim 37 . The semiconductor memory device supplies a row-side block selection address to a column selection signal generation circuit, controls a delay amount in the column selection signal generation circuit based on the block selection address, and determines the generation timing of the column selection signal. 37. The semiconductor according to claim 36 , wherein an earlier timing is set for a block far from the bus amplifier, and a later timing is given for a block near the bus amplifier. Storage device. 40. The semiconductor memory according to claim 39 , wherein a delay amount in said column selection signal generating circuit is constituted by a transfer switch and an additional capacitor, and the value of said additional capacitor becomes larger as the block is closer to said bus amplifier. apparatus. The delay amount in the column selection signal generating circuit is configured by a delay line in which a plurality of delay stages are connected in cascade, and a block closer to the bus amplifier passes through more delay stages in the delay line. 40. The semiconductor memory device according to claim 39 . 42. The semiconductor memory device according to claim 41 , wherein each delay stage includes first and second NAND gates and an inverter. In the semiconductor memory device, a sense amplifier closer to the column selection signal generation circuit and the data bus amplifier generates a control signal used in the data bus amplifier earlier, and the column selection signal generation circuit and the data bus amplifier A part where the control signal used in the data bus amplifier is generated more slowly as the sense amplifier farther from the data bus amplifier, and the control signal used in the data bus amplifier reaches the data bus amplifier. 37. The semiconductor memory device according to claim 36 , wherein: A receiver circuit connected to the signal transmission path,
A first switch provided on the reference potential line ;
A first capacitor connected to the first switch;
A second switch provided in the signal transmission path ;
A second capacitor having a first end connected to the first capacitor and a second end connected to the second switch;
A third switch;
A logic determination unit having an input connected to the first capacitor and the second capacitor, and the input and the output connected via the third switch,
In the first state in which the first switch is off, the second switch is on and the third switch is off, the first signal state of the signal transmission path is determined by the logic determination unit, and the first switch is in the second state where the second switch is turned on is the third switch is turned on off, the first signal state of the signal transmission line and held in the capacitor to the first, then the first switch is turned off in the second switch is in a third state in which the third switch is turned on is turned off, the second signal state of the signal transmission path to input to the capacitor to the second, the logic determines the second signal state A receiver circuit characterized by being determined by a unit. The value of the first capacitor is C10, the value of the second capacitor is C20, the time constant of the bus is τ, and the time when data for 1 bit appears on the bus or the cycle for 1 bit is T When
45. The receiver circuit according to claim 44 , wherein the values of the first and second capacitors substantially satisfy the expression: C10 / (C10 + C20) = (1 + exp (−T / τ)) / 2. . 45. The receiver circuit according to claim 44 , wherein the differential amplifier is configured as a latch-type differential amplifier. The differential amplifier sets the output node of the differential amplifier to a high level when the transistor receiving data is an N-channel type except when reading data, or the differential amplifier when the transistor receiving data is a P-channel type. The receiver circuit according to any one of claims 44 to 46 , wherein an operation speed is improved by setting an output node of the amplifier to a low level. The differential amplifier is configured such that when a transistor receiving data is an N-channel type during an intersymbol interference component removal operation and a differential amplifier input node precharge operation other than during data transfer and during data read, an output node to a high level, or according to claim 44 to 46, characterized in that the transistor receiving said data is to improve the operating speed of the differential amplifier output node when the P-channel type as a low-level The receiver circuit according to any one of claims. The receiver circuit according to any one of claims 44 to 45 , wherein the differential amplifier is configured as a current mirror type differential amplifier. 47. The receiver circuit according to claim 44 , wherein the differential amplifier does not operate except during data transfer.

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