JP4039424B2 - Receiving device and display device - Google Patents

Description

  The present invention relates to a diversity receiver used for receiving broadcast or communication radio transmission signals, and a display device and an audio output device using the diversity receiver, and more particularly to a device that can be used even in a strong electric field.

  When receiving signals transmitted wirelessly using radio waves, not only direct waves that are received by directly propagating through the transmission path from the transmission side, but also indirect waves that are reflected by a reflective object in the transmission path, This directly interferes with the wave, resulting in multipath. The transmission characteristics under this multipath environment are inferior compared to the fixed reception particularly when performing mobile reception. In order to reduce the influence due to the fluctuation of the transmission characteristics and ensure good reception quality, a diversity method is adopted.

Conventional spatial diversity receivers compare the signal levels of signals received from multiple antennas, and switch between antennas based on the comparison results, and the signals received by multiple antennas. An addition method used by adding is known. As an example of the former, the configuration of a diversity receiver is disclosed in Japanese Patent Laid-Open No. 6-177805. As an example of the latter, Japanese Patent Laid-Open No. 2000-278243 discloses a diversity receiver.
JP-A-6-177805 JP 2000-278243 A

  As described above, the conventional diversity receiver assumes only when the signal level input to the receiving circuit is weak, that is, when the receiving side moves in an area where the electric field strength is weak. However, depending on the area where the receiving side moves, the electric field strength is strong and the signal level of the received signal may be too high. In other words, when the receiving side moves near the transmitting side that is transmitting radio waves for broadcasting or communication, the signal level of the received signal may exceed the upper limit of the allowable range for the input level of the receiving circuit. is there.

  In a receiving apparatus used for receiving a radio transmission signal for broadcasting or communication, particularly a receiving apparatus used for receiving a radio transmission signal for digital broadcasting or digital communication, an analog signal is provided before a demodulation circuit that demodulates the received signal. An A / D converter for converting to a digital signal is included. For example, when the received signal exceeds the upper limit of the input allowable range of the A / D converter, the A / D converter cannot sample the signal level accurately, and the reception performance of the receiving apparatus deteriorates. . Therefore, when the moving body moves in a region where the electric field strength is strong and the signal level of the received signal exceeds the upper limit of the input allowable range of the A / D converter, it is necessary to attenuate it.

The object of the present invention is to solve the above-mentioned problems and to efficiently adjust the signal level of the received signal even when the electric field strength is too strong as the signal level of the received signal exceeds the upper limit of the input allowable range of the A / D converter. An object of the present invention is to provide a receiving apparatus capable of performing the above.

In order to achieve the object of the present invention, in a receiving apparatus, for example, a plurality of receiving means for receiving a radio transmission signal, and at least one process of amplification, tuning, and frequency conversion is performed on the signal received by the receiving means. A plurality of signal processing means to perform, a level adjusting means for adjusting the signal level of the signal output from the signal processing means, and the level adjusting means are signals included in the plurality of signals output from the signal processing means. A phase adjusting unit that adjusts the phase of the signal having the second largest signal level and a signal having the second largest signal level, and a second signal whose phase is adjusted by the phase adjusting unit. Selection signal level adjusting means for attenuating the signal level of a signal having a large signal level, and the selection signal from the signal having the largest signal level Subtracting means for subtracting and outputting the signal having the second largest signal level adjusted by the bell adjusting means, and converting means for converting the signal output from the subtracting means from an analog signal to a digital signal, The level control means is configured to attenuate the signal having the highest signal level by the subtracting means when the electric field strength of the radio transmission signal received by the plurality of receiving means is equal to or greater than an input allowable range of the subtracting means. What is necessary is just to comprise so that the value which subtracted the signal of the 2nd largest signal level may become below the lower limit of the input allowable range of the said subtraction means.

As described above, according to the present invention, for example, even when the received signal exceeds the upper limit of the input allowable range of the A / D converter, the A / D converter accurately samples the signal level. Therefore, it is possible to prevent the reception performance of the receiving apparatus from being deteriorated.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a diversity receiver in the first and second embodiments according to the present invention. 10-1, 10-2 to 10-N are reception antennas, 20-1, 20-2 to 20-N are reception high frequency units, 30-1, 30-2 to 30-N are reception level detection circuits, and 40 is A level adjustment circuit 50 that adjusts the signal level of the output signal of the reception high-frequency units 20-1 and 20-2 to 20-N and outputs one signal, 50 is the reception high-frequency unit 20-1, 20-2 to 20-N And a selection circuit for selecting one signal from the output signal of the level adjustment circuit 40, 60 an adjustment signal level detection circuit for detecting the output signal level of the level adjustment circuit 40, 70 a control circuit, 80 a demodulation unit, 81 is an A / D converter and 82 is a demodulation circuit.

The diversity receiver is provided with a plurality of antennas 10-1 to 10-N that receive radio waves. The radio wave received by the antenna 10-1 is amplified, tuned, and frequency-converted by the reception high-frequency unit 20-1. The reception output amplified, tuned and frequency-converted by the reception high-frequency unit 20-1 is supplied to the reception level detection circuit 30-1 and to the level adjustment circuit 40 and the selection circuit 50. The other antennas 10-2 to 10-N perform the same operation as the antenna 10-1. Although not shown in FIG. 1, the detection output of the reception signal level detected by the reception level detection circuits 30-1 and 30-2 to 30 -N is supplied to the control circuit 70. The reception signal whose level is adjusted by the level adjustment circuit 40 is supplied to the selection circuit 50 and is also supplied to the adjustment signal level detection circuit 60. The detection output of the adjustment signal level detected by the adjustment signal level detector 60 is supplied to the control circuit 70. The control circuit 70 is a signal of a signal supplied to the A / D converter 81 based on the detection results of the reception level detection circuits 30-1, 30-2 to 30 -N and the detection result of the adjustment signal level detection circuit 60. The level adjustment circuit 40 and the selection circuit 50 are controlled so that the level is within the input allowable range. The output selected by the selection circuit 50 is supplied to the A / D converter 81 in the demodulator 80. The digital signal output converted from the analog signal to the digital signal by the A / D converter 81 is supplied to the demodulation circuit 82. The digital signal output is demodulated by the demodulation circuit 82 and becomes an output signal.

  Here, in the first embodiment, all of the detection outputs of the reception level detection circuits 30-1 and 30-2 to 30 -N are allowed to be input to the A / D converter 81 by the control circuit 70 of FIG. 1. When it is determined that the value exceeds the upper limit, the selection circuit 50 selects the output of the level adjustment circuit 40. When the control circuit 70 determines that at least one detection output of the reception level detection circuits 30-1 to 30-N is below the upper limit of the input allowable range of the A / D converter 81, the A / D converter The selection circuit 50 selects the output terminal having the highest signal level among the output signals of the reception high-frequency units 20-1 and 20-2 to 20 -N determined to be below the upper limit of the input allowable range of 81.

  The operation when the selection circuit 50 selects the output of the level adjustment circuit 40 in the configuration of the first embodiment will be described in detail below with reference to FIG. FIG. 2 shows an example of the configuration of the level adjustment circuit 40 in the first embodiment according to the present invention. 401 is a selection circuit, 402 is an inverter, 403 is an attenuator, and 404 is an adder. 2 are the outputs of the reception high-frequency units 20-1 and 20-2 to 20 -N, respectively, and are supplied to the selection circuit 401. The selection circuit 401 is controlled by the control circuit 70 of FIG. 1 based on the detection results of the reception level detection circuits 30-1, 30-2 to 30-N, and the signal having the largest signal level and the second largest signal among the input signals. Control is performed to select a signal at a signal level. The signal having the largest signal level selected by the selection circuit 401 is output as the selection signal 1 and supplied to the adder 404. The other signal selected by the selection circuit 401 is output as the selection signal 2 and supplied to the inverter 402. The inverter 402 inverts the phase of the input signal, and its output is supplied to the attenuator 403. The attenuation amount of the attenuator 403 is controlled based on the detection result of the adjustment signal level detection circuit 60 of FIG. 1 so that the output signal after the subtraction processing becomes a signal level within the input allowable range of the A / D converter 81. Controlled by circuit 70. The signal attenuated by the attenuator 403 is supplied to the adder 404. The adder 404 outputs a signal obtained by adding a signal obtained by inverting and attenuating the signal of the selection signal 2 to the selection signal 1, and the output is supplied to the selection circuit 50 as an output signal of the level adjustment circuit 40.

  Therefore, if the diversity receiver having the above configuration is used, the signal levels of the signals received by the respective antennas are compared, and it is determined that the signal levels of all these signals exceed the upper limit of the input allowable range of the A / D converter. In this case, a signal having a signal level lower than the upper limit of the input allowable range of the A / D converter is supplied by subtracting a signal obtained by attenuating the other received signal from one received signal based on the comparison result. Can do.

  Although the inverter 402 is used in FIG. 2, a phase shifter that adjusts the phase may be used.

  FIG. 3 is a block diagram showing the configuration of the level adjustment circuit of the diversity receiver according to the second embodiment of the present invention. In the configuration of the diversity receiver in the second embodiment, the configuration of the level adjustment circuit 40 of the diversity receiver in the first embodiment shown in FIG. 2 is replaced with the configuration shown in FIG. In the diversity receiver in the second embodiment, the operation difference from the first embodiment shown in FIG. 1 is that the control method of the control circuit 70 in FIG. 1 is different.

Hereinafter, the operation of the control circuit 70 of the diversity receiver in the second embodiment using the level adjustment circuit of FIG. 3 will be described. Here, in the second embodiment, all of the detection outputs of the reception level detection circuits 30-1 and 30-2 to 30-N are allowed to be input to the A / D converter 81 by the control circuit 70 of FIG. When it is determined that the value exceeds the upper limit, the selection circuit 50 selects the output of the level adjustment circuit 40. Further, when the control circuit 70 of FIG. 1 determines that at least one detection output of the reception level detection circuits 30-1 to 30-N is below the upper limit of the input allowable range of the A / D converter 81, the A / D The selection circuit 50 selects the output terminal having the highest signal level among the output signals of the reception high-frequency units 20-1, 20-2 to 20-N determined to be below the upper limit of the input allowable range of the D converter 81. Let Further, when the control circuit 70 in FIG. 1 determines that all of the detection outputs of the reception level detection circuits 30-1 and 30-2 to 30 -N are below the lower limit of the input allowable range of the A / D converter 81. The selection circuit 50 selects the output of the level adjustment circuit 40.

The operation when the selection circuit 50 selects the output of the level adjustment circuit 40 in the configuration of the second embodiment will be described in detail below with reference to FIG. In the level adjustment circuit of FIG. 3, 401 is a selection circuit, 403 is an attenuator, 404 is an adder, and 405 is a phase shifter. Inputs 1 and 2 to N in FIG. 3 are outputs of the reception high-frequency units 20-1 and 20-2 to 20 -N, respectively, and are supplied to the selection circuit 401. The selection circuit 401 is controlled by the control circuit 70 of FIG. 1 based on the detection results of the reception level detection circuits 30-1, 30-2 to 30-N, and the signal having the largest signal level and the second largest signal among the input signals. Control is performed to select a signal at a signal level. The signal having the largest signal level selected by the selection circuit 401 is output as the selection signal 1 and supplied to the adder 404. The other signal selected by the selection circuit 401 is output as the selection signal 2 and supplied to the phase shifter 405. The phase shifter 405 adjusts the phase of the input signal, and its output is supplied to the attenuator 403. The phase shift amount of the phase shifter 405 and the attenuation amount of the attenuator 403 are adjusted signal level detection circuit of FIG. 1 so that the output signal after the subtraction processing becomes a signal level within the input allowable range of the A / D converter 81. Based on the 60 detection results, control is performed by the control circuit 70. The signal attenuated by the attenuator 403 is supplied to the adder 404. The adder 404 outputs a signal obtained by adding a signal obtained by adjusting and attenuating the phase shift of the signal of the selection signal 2 to the selection signal 1, and the output is supplied to the selection circuit 50 as an output signal of the level adjustment circuit 40. Is done.

  That is, when it is determined by the control circuit 70 in FIG. 1 that all the detection outputs of the reception level detection circuits 30-1, 30-2 to 30-N exceed the upper limit of the input allowable range of the A / D converter 81. The level adjustment circuit operates as a subtracter, and all of the detection outputs of the reception level detection circuits 30-1, 30-2 to 30-N are allowed to be input to the A / D converter 81 by the control circuit 70 of FIG. If it is determined that the value falls below the lower limit, the level adjustment circuit operates as an adder.

  Therefore, if the diversity receiver having the above configuration is used, the signal levels of the signals received by the respective antennas are compared, and it is determined that the signal levels of all these signals exceed the upper limit of the input allowable range of the A / D converter. In this case, the upper limit of the input allowable range of the A / D converter is obtained by subtracting a signal obtained by attenuating the reception signal having the second largest reception level from the reception signal having the largest signal level based on the comparison result. A signal level of less than can be supplied. In addition, the signal levels of the signals received by each antenna are compared, and when it is determined that the signal levels of all these signals are below the lower limit of the input allowable range of the A / D converter, By adjusting the phase of the received signal having the second largest signal level to the received signal having the larger signal level and adding the attenuated signal, the signal level exceeding the lower limit of the input allowable range of the A / D converter A signal can be supplied.

  Note that the signal selected by the selection circuit 401 in the first and second embodiments according to the present invention is not limited to the above-mentioned conditions, and the level adjustment circuit shown in FIGS. It is also possible to select a signal whose signal level is within the input allowable range of the A / D converter 81.

  FIG. 4 is a block diagram showing the configuration of the diversity receiver in the third and fourth embodiments according to the present invention. 10-1, 10-2 to 10-N, 20-1, 20-2 to 20-N, 30-1, 30-2 to 30-N, 40, 60 and 80, 81, 82 are shown in FIG. Similarly, 71 is a control circuit.

  In the configuration of the third embodiment in FIG. 4, the difference from the configuration of the first embodiment shown in FIG. 1 is that the selection circuit 50 in FIG. 1 is omitted, and the signal input to the A / D converter 81 is All are supplied from the output of the level adjustment circuit 40, and the control circuit 70 in FIG. 1 is replaced with a control circuit 71 having a different control method. Here, the configuration of the level adjustment circuit 40 of FIG. 4 in the third embodiment is the same as the configuration of the level adjustment circuit 40 shown in FIG. The operations of the control circuit 71 and the level adjustment circuit 40 of the diversity receiver in the third embodiment when the level adjustment circuit of FIG. 2 is used will be described below with reference to FIGS.

Here, in the third embodiment, all of the detection outputs of the reception level detection circuits 30-1 and 30-2 to 30 -N are converted by the control circuit 71 of FIG. 4 into the A / D converter 8.
2 is determined based on the detection results of the reception level detection circuits 30-1 and 30-2 to 30-N, when it is determined that the upper limit of the input allowable range of 1 is exceeded. The control circuit 71 controls to select the signal having the largest signal level as the selection signal 1 and the signal having the second largest signal level as the selection signal 2. At this time, the attenuation amount of the attenuator 403 is based on the detection result of the adjustment signal level detection circuit 60 of FIG. 1 so that the output signal after the subtraction processing becomes a signal level within the input allowable range of the A / D converter 81. The level adjustment circuit 40 is controlled by the control circuit 70 and operates as a subtracter.

  Further, when the control circuit 70 of FIG. 1 determines that at least one detection output of the reception level detection circuits 30-1 and 30-2 to 30 -N is below the upper limit of the input allowable range of the A / D converter 81. 2 is the largest signal among the output signals of the reception high-frequency units 20-1, 20-2 to 20-N determined to be below the upper limit of the input allowable range of the A / D converter 81. The control circuit 71 controls to select an output terminal having a level as the selection signal 1 and an arbitrary output terminal as the selection signal 2.

  At this time, the amount of attenuation of the attenuator 403 is controlled by the control circuit 70 so as to be infinite, and the level adjustment circuit 40 operates as a selection circuit. Therefore, if the diversity receiver having the above configuration is used, the signal levels of the signals received by the respective antennas are compared, and it is determined that the signal levels of all these signals exceed the upper limit of the input allowable range of the A / D converter. In this case, a signal having a signal level lower than the upper limit of the input allowable range of the A / D converter is supplied by subtracting a signal obtained by attenuating the other received signal from one received signal based on the comparison result. Can do.

  In the configuration of the diversity receiver in the fourth embodiment, the configuration of the level adjustment circuit 40 of the diversity receiver in the third embodiment shown in FIG. 2 is replaced with the configuration shown in FIG. In the diversity receiver in the fourth embodiment, the operation difference from the third embodiment shown in FIG. 4 is that the control method of the control circuit 71 in FIG. 4 is different. The operations of the control circuit 71 and the level adjustment circuit 40 of the diversity receiver according to the fourth embodiment when the level adjustment circuit of FIG. 3 is used will be described below with reference to FIGS.

  Here, in the fourth embodiment, all of the detection outputs of the reception level detection circuits 30-1 and 30-2 to 30-N are allowed to be input to the A / D converter 81 by the control circuit 71 of FIG. 3 is determined based on the detection results of the reception level detection circuits 30-1, 30-2 to 30-N, the selection circuit 401 in FIG. The control circuit 71 controls to select the signal as the selection signal 1 and the signal having the second highest signal level as the selection signal 2. At this time, the attenuation amount of the attenuator 403 is based on the detection result of the adjustment signal level detection circuit 60 of FIG. 4 so that the output signal after the subtraction process becomes a signal level within the input allowable range of the A / D converter 81. The level adjustment circuit 40 is controlled by the control circuit 71 and operates as a subtracter.

  Further, when the control circuit 71 in FIG. 4 determines that at least one detection output of the reception level detection circuits 30-1 and 30-2 to 30 -N is below the upper limit of the input allowable range of the A / D converter 81. 3 is the largest signal among the output signals of the reception high-frequency units 20-1, 20-2 to 20-N determined to be below the upper limit of the input allowable range of the A / D converter 81. The control circuit 71 controls to select an output terminal having a level as the selection signal 1 and an arbitrary output terminal as the selection signal 2. At this time, the amount of attenuation of the attenuator 403 is controlled by the control circuit 71 so as to be infinite, and the level adjustment circuit 40 operates as a selection circuit.

Further, when the control circuit 71 in FIG. 4 determines that all of the detection outputs of the reception level detection circuits 30-1 and 30-2 to 30 -N are below the lower limit of the input allowable range of the A / D converter 81. 3 selects the signal having the highest signal level from the input signals as the selection signal 1 based on the detection results of the reception level detection circuits 30-1, 30-2 to 30-N. Is controlled by the control circuit 71 so as to select a signal having a larger signal level as the selection signal 2. At this time, the attenuation amount of the attenuator 403 is based on the detection result of the adjustment signal level detection circuit 60 of FIG. 1 so that the output signal after the addition processing becomes a signal level within the input allowable range of the A / D converter 81. The level adjustment circuit 40 is controlled by the control circuit 71 and operates as an adder.

  Therefore, if the diversity receiver having the above configuration is used, the signal levels of the signals received by the respective antennas are compared, and it is determined that the signal levels of all these signals exceed the upper limit of the input allowable range of the A / D converter. In this case, the upper limit of the input allowable range of the A / D converter is obtained by subtracting a signal obtained by attenuating the reception signal having the second largest reception level from the reception signal having the largest signal level based on the comparison result. A signal level of less than can be supplied.

  In addition, the signal levels of the signals received by each antenna are compared, and when it is determined that the signal levels of all these signals are below the lower limit of the input allowable range of the A / D converter, By adjusting the phase of the received signal having the second largest signal level to the received signal having the larger signal level and adding the attenuated signal, the signal level exceeding the lower limit of the input allowable range of the A / D converter A signal can be supplied.

  Note that the signal selected by the selection circuit 401 in the third and fourth embodiments according to the present invention is not limited to the above-described conditions, and the level adjustment circuit shown in FIGS. It is also possible to select a signal whose signal level is within the input allowable range of the A / D converter 81.

  In the first to fourth embodiments, the diversity receiver includes the adjustment signal level detection circuit 60. However, the control circuits 70 and 71 may include the reception level detection circuit without the configuration. Based on this detection result, the level adjustment circuit 40 can be controlled.

  In the first to fourth embodiments according to the present invention, the input stage in the demodulator is not limited to the A / D converter.

  Further, as the detection method of the level detection circuit, peak value detection, effective value detection, and average value detection are conceivable, but an appropriate detection method may be selected according to the quality of the line.

  In addition, as an application example using the above diversity receiver, a display device, an audio output device, and the like can be considered.

It is a block diagram which shows the structure of the diversity receiver in 1st and 2nd embodiment which concerns on this invention. It is a block diagram which shows the example of a structure of the level adjustment circuit used for the 1st and 3rd embodiment which concerns on this invention. It is a block diagram which shows the example of a structure of the level adjustment circuit used for 2nd and 4th embodiment which concerns on this invention. It is a block diagram which shows the structure of the diversity receiver in 3rd and 4th embodiment which concerns on this invention.

Explanation of symbols

10-1 to 10-N ... Antennas 20-1 to 20-N ... Reception high frequency units 30-1 to 30-N ... Receive level detection circuit 40 ... Level Adjustment circuit 50 ... selection circuit 60 ... adjustment signal level detection circuit 70, 71 ... control circuit 80 ... ... Demodulator 81 ... A / D converter 82 ... Demodulator circuit 401 ... Selector circuit 402 ... .... Inverter 403 ... ... Attenuator 404 ... ... Adder 405 ... ... Phase shifter

Claims (6)

A plurality of receiving means for receiving wireless transmission signals;
A plurality of signal processing means for performing at least one of amplification, tuning, and frequency conversion on the signal received by the receiving means;
Level adjusting means for adjusting the signal level of the signal output from the signal processing means;
Said level adjustment means, the most significant signal level of the signal and large signal level of the signal to the second is a signal included in a plurality of signals output from said signal processing means, a large signal level of the signal in the second the Phase adjusting means for adjusting the phase;
A selection signal level adjusting means for attenuating a signal level of the large signal level of the signal to the second adjusted phase by said phase adjusting means, said the most adjusted from a large signal level of the signal by the selection signal level adjusting means 2 A subtracting means for subtracting and outputting a signal having the second largest signal level ;
Conversion means for converting the signal output from the subtraction means from an analog signal to a digital signal ,
The level control means is attenuated from the signal of the highest signal level by the subtracting means when the electric field strength of the radio transmission signal received by the plurality of receiving means exceeds the input allowable range of the converting means . receiving apparatus characterized by a value obtained by subtracting the large signal level of the signal to the second prior SL is adjusted to be below the lower limit of the allowable input range of the conversion means.   2. The diversity receiver according to claim 1, wherein the phase adjusting unit is an inverter that inverts the phase of a signal. The receiving apparatus according to claim 1 or 2,
The selection signal level adjusting means is an attenuator for attenuating a signal level.   A display device comprising: the receiving device according to claim 1; and display means for displaying an image based on a signal output from the receiving device.   An audio output device comprising: the receiving device according to claim 1; and audio output means for outputting audio based on a signal output from the receiving device.   6. A data output device comprising: the receiving device according to claim 1; and data output means for outputting data based on a signal output from the receiving device.

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