JP4039238B2 - Analog / digital converter - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an oversampling analog / digital converter.
[0002]
[Prior art]
The analog / digital (hereinafter referred to as A / D) converter includes a quantizer that quantizes the amplitude of an analog input and a sampler that discretizes the time axis. A conventional A / D converter quantizes an analog signal at the moment of entering a clock by supplying a clock signal for sampling to the quantizer.
[0003]
Normally, an oversampling AD converter uses a 1-bit quantizer, and is configured to feed back and forth the output of the quantizer to increase or decrease a certain amount from the analog input signal. In this case, an analog signal is output as a pulse density modulated wave by sampling at a high frequency using a 1-bit quantizer. When performing the modulation, the clock signal is indispensable to hold the pulse output of the quantizer, so that the quantization and sampling must be performed simultaneously.
[0004]
[Problems to be solved by the invention]
In the oversampling A / D converter described above, how to increase the sampling frequency is the key to improving accuracy. However, this requires a mechanism to feed back the quantizer output and increase or decrease a certain amount from the analog input signal, and a mechanism to hold the quantizer output. It was difficult to raise.
[0005]
As an oversampling A / D converter, a quantizer using a Josephson junction has been proposed. In this A / D converter, the characteristic of the Josephson circuit is utilized, and feedback is automatically performed simultaneously with the output. However, since modulation (quantization) and sampling into a pulse density wave were performed by one Josephson junction, the sampling frequency could not be increased to a speed at which the high speed of the Josephson junction was fully exhibited.
[0006]
The present invention has been made in view of the above points, and a first object thereof is to improve accuracy in an oversampling A / D converter. A second object of the present invention is to allow the oversampling A / D converter using a Josephson junction as a quantizer to sufficiently exhibit the high speed of the Josephson junction.
[0007]
[Means for Solving the Problems]
In the present invention, in order to achieve the above-described object, quantization and sampling are performed separately.
[0008]
Specifically, according to the first aspect of the present invention, a Δ type or Σ-Δ type modulator that modulates an analog input signal into a pulse density modulated wave, and a sampling that samples the pulse density modulated wave using a clock signal. In a Δ-type or Σ-Δ type modulator , a quantizer that outputs a pulse when the analog input signal exceeds the threshold value regardless of the clock signal. The Σ-Δ modulator includes an integrator that integrates the analog input signal regardless of the clock signal , or a quantizer that outputs a pulse when the input from the resonator exceeds the threshold value. The sampler has a plurality of individual samplers to which a pulse density modulation wave is input simultaneously, and a clock signal supplied to these individual samplers is clocked between the individual samplers. Tsu is characterized in that the a delayed click signal shorter than the period of.
[0009]
According to the present invention, quantization and sampling can be performed separately, and sampling can be performed with high time resolution. Therefore, the accuracy of the oversampling A / D converter is improved. Can do.
[0010]
According to a second aspect of the present invention, there is provided an analog / digital device comprising: a Σ-Δ modulator that modulates an analog input signal into a pulse density modulated wave; and a sampler that samples a pulse density modulated wave using a clock signal. The Σ-Δ type modulator is an integrator or a resonator that integrates an analog input signal, and is connected to the integrator or the resonator, and is input from the integrator or the resonator regardless of the clock signal. And a quantizer using a Josephson junction that outputs a pulse when a threshold value is exceeded.
[0011]
According to this invention, quantization and sampling are performed separately, and in a quantizer using a Josephson junction, a pulse is output when the input exceeds the threshold value regardless of the clock signal. In the oversampling A / D converter, the high speed property of the Josephson junction can be sufficiently exhibited.
[0012]
According to a third aspect of the present invention, in the invention according to the second aspect, the sampler has a plurality of individual samplers to which a pulse density modulation wave is input simultaneously, and a clock supplied to these individual samplers. It is characterized in that the signal is delayed between the individual samplers by a time shorter than the period of the clock signal.
[0013]
According to the present invention, in the oversampling A / D converter using a Josephson junction as the quantizer, the accuracy can be improved.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a configuration of an oversampling A / D converter according to an embodiment of the present invention. The A / D converter includes an integrator 10, a quantizer 20, a frequency-voltage (current) converter 30, and a high time resolution sampler 40.
[0015]
In this configuration, the analog input signal is integrated by the integrator 10 and input to the quantizer 20. When the input from the integrator 10 exceeds the threshold value, the quantizer 20 outputs a return-to-zero pulse. The output of the quantizer 20 is converted into a voltage (or current) signal by the frequency-voltage (current) converter 30 and the analog input signal is reduced by the converted signal. Thus, by forming a loop for returning the output of the quantizer 20 to the input side and interposing the integrator 10 in the loop, the quantizer 20 performs noise shaping (that is, is in a flat state). A pulse density modulated wave (with noise shifted to the high frequency side) is output.
[0016]
Thus, a Σ-Δ type modulator is configured by the above-described configuration that modulates an analog input signal into a pulse density modulated wave. However, in the conventional Σ-Δ type modulator, a clock signal is input to the quantizer, and sampling is performed at the same time as quantization is performed by the clock signal. In the type modulator, the clock signal is not input to the quantizer 20, and the quantizer 20 outputs a pulse every time the input exceeds the threshold value due to the relationship between the input from the integrator 10 and the threshold value. . Therefore, a pulse density modulated wave is output from the Σ-Δ modulator regardless of the clock signal. This pulse density modulation wave represents an analog input signal by the density of impulse-shaped pulses, and information is represented by impulse time intervals. By reading this time interval with high accuracy, the performance of the A / D converter can be improved.
[0017]
The pulse density modulated wave output from the Σ-Δ modulator is sampled by the high time resolution sampler 40. As will be described in detail in a specific example to be described later, the high time resolution sampler 40 includes a plurality of individual samplers, and clock signals supplied to these individual samplers are individually sampled. It is assumed that the time resolution is effectively increased by delaying the clock signal by a time shorter than the period of the clock signal. The high time resolution sampler 40 outputs a multi-bit digital signal corresponding to the density of the pulse density modulated wave. Normally, a digital filter (low-pass filter) is connected after the high time resolution sampler 40.
[0018]
FIG. 2 shows a specific configuration of an A / D converter using a Josephson junction as the quantizer 20. In the configuration shown in FIG. 2, the integrator 10 includes a resistor 11 and a coil 12, and a quantizer 20 is connected to the integrator 10. The quantizer 20 is configured using a Josephson junction, and outputs a pulse when the input from the integrator 10 exceeds the threshold value regardless of the clock signal. In the case of the quantizer 20 using the Josephson junction, the current flowing from the integrator 10 to the quantizer 20 is decreased by a predetermined amount simultaneously with the output of the pulse. As the current decreases, feedback is applied, and as a result, a loop is formed in which the output of the quantizer 20 returns to the input side, as shown in FIG. Therefore, the integrator 10 and the quantizer 20 using a Josephson junction constitute a Σ-Δ modulator, and the analog input signal is modulated into a pulse density modulated wave.
[0019]
This pulse density modulated wave is sent to a plurality (four in the figure) of individual samplers (in this embodiment, D flip-flops: hereinafter referred to as DFFs) 41, 42, 43, 44 in the high time resolution sampler 40. Each is input simultaneously. In other words, the pulse density modulated waves are distributed in a tree shape and are simultaneously input to the first DFF 41, the second DFF 42, the third DFF 43, and the fourth DFF 44.
[0020]
The first to fourth DFFs 44 to 44 are supplied with first to fourth clock signals which are sampling signals. The first DFF 41 performs sampling in the sampling clock cycle (sampling cycle: T) by the first clock signal, and the subsequent second DFF 42, third DFF 43, and fourth DFF 44 sequentially sample clock cycles. Sampling is performed using the second clock signal, the third clock signal, and the fourth clock signal that are shifted by a shorter delay τ. That is, the second DFF 42 is sampled slower than the first DFF 41 by τ, the third DFF 43 is sampled by 2τ, and the fourth DFF 44 is sampled by 3τ. The relationship between this delay τ and the number of samplers N (N = 4 in this embodiment) is T = Nτ. In this case, the delay of each clock signal can be realized by using a wiring delay or the like. By making the sampling timing finer than the sampling period in this way, it is possible to examine the impulse time interval with higher time accuracy.
[0021]
The first to fourth DFFs 41 to 44 determine “1” when there is a pulse of a pulse density modulation wave within the sampling signal interval, and “0” when there is no pulse density modulation wave, and hold and output it. To do. Such a DFF is configured to internally store that a pulse has been input when a pulse is input, hold and output the stored state by a clock signal, and reset the internal storage. It can be realized by DFF using a Son junction. The outputs of the first to fourth DFFs 41 to 44 are added by the binary decoder 45 at the timing of the fourth clock signal and output as a multi-bit digital signal. That is, the number of outputs of each of the first to fourth DFFs 41 to 44 is counted and output every one sampling interval in the fourth DFF 44.
[0022]
FIG. 3 shows a state of sampling by the high time resolution sampler 40. As shown in the figure, the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are generated periodically with a delay τ.
[0023]
Here, when each pulse in the pulse density modulation wave is generated as shown in the figure, “1” is sequentially applied to the pulse a from the fourth DFF 44, the first DFF 41, the second DFF 42, and the third DFF 43. Although the binary decoder 45 performs addition at the timing of the fourth clock signal and outputs it, it outputs “1” at that timing and outputs “3” at the timing of the next fourth clock signal. To do. For the pulse b, “1” is sequentially output from the first DFF 41, the second DFF 42, the third DFF 43, and the fourth DFF 44, and the binary decoder 45 adds at the timing of the fourth clock signal. Go to output “4”. Therefore, when pulses a, b, c, d, e, and f are generated at time intervals as shown in the figure, the binary decoder 45 outputs “1”, “3”, “4”, “0”, Digital signals “2”, “2”, “4”, “3”, “2”, “3” are output in order.
[0024]
The numerical value of the output digital signal can indicate at which position the pulse is generated within the sampling signal interval (in this embodiment, the sampling interval in the fourth DFF 44). That is, as shown in FIG. 4, the larger the output numerical value, the more the pulse is generated at the position earlier in the sampling signal interval. On the other hand, when one DFF is used (for example, when only the first DFF 41 is used), it is determined that the pulse is “1” at any position within the sampling signal interval as shown in FIG. Is done. For this reason, when one DFF is used, a rounding error occurs, and the S / N ratio of the A / D converter is lowered. However, as in this embodiment, the quantizer 20 and the sampler 40 are used. When the sampling unit 40 performs sampling with the above-described high time resolution, high time accuracy is expressed as high amplitude accuracy. This is equivalent to converting the time accuracy into the amplitude direction of the digital output signal. In other words, although the sampling is performed at the same oversampling frequency as the conventional Σ-Δ modulator, the performance is equivalent to that using the multi-bit quantizer 20 instead of the 1-bit quantizer 20. Can be obtained.
[0025]
Note that, when the quantizer 20 is configured using a Josephson junction as in the above-described embodiment, quantization can be performed at high speed without using a clock signal. Even if sampling is performed using the clock signal, the speed can be increased. In other words, in the conventional oversampling A / D converter using the Josephson junction, the current of the clock signal and the input current are merged and added to one quantizer. The size of the analog input to be obtained has decreased, and the dynamic range (DR) of the original quantizer has not been fully extracted. On the other hand, when the clock signal is not supplied to the quantizer, the DR can be increased to the performance limit of the quantizer. In this case, if the frequency of the clock signal is increased as much as possible, rounding can be reduced even if the sampler is sampled by one clock signal. That is, high accuracy can be achieved.
[0026]
In the above-described embodiment, the A / D converter is configured using the Σ-Δ modulator. However, the A / D converter may be configured using the Δ modulator. The configuration in this case is shown in FIG. In this Δ-type modulator, the integrator 10 is located at the subsequent stage of the frequency-voltage (current) converter 30. Even in the case shown in FIG. 5, no clock signal is input to the quantizer 20, and the quantizer 20 causes the analog input signal to exceed the threshold value due to the relationship between the analog input signal and the threshold value. It is configured to output a pulse, and this is different from the conventional Δ-type modulator. Other configurations are the same as those of the embodiment shown in FIG.
[0027]
In the above-described embodiment, the Σ-Δ type modulator or the Δ type modulator is configured using the integrator 10, but the integrator 10 has a configuration other than that illustrated in FIG. A thing may be used. Further, a resonator may be used instead of the integrator 10. Specific examples of this resonator are shown in FIGS.
[0028]
The A / D converter shown in the above embodiment is a waveform analysis measurement and recording of a GHz RF signal that requires high-speed and high-accuracy reception and detection, an audio / video signal with a dynamic range exceeding 100 dB, and a signal that changes finely at high speed. It is useful and effective for digitizing analog signals.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration of an oversampling A / D converter configured using a Σ-Δ modulator.
FIG. 2 is a diagram showing a specific configuration of an A / D converter configured using a Josephson junction in the quantizer 20;
FIG. 3 is a timing chart showing a state of sampling by the high time resolution sampler 40;
FIG. 4 is a diagram for explaining the relationship between a pulse density modulated wave and the output of a high time resolution sampler 40;
FIG. 5 is a diagram showing a configuration of an oversampling A / D converter configured using a Δ-type modulator.
6 is a diagram showing a configuration of a resonator used in place of an integrator 10 in a Σ-Δ modulator or a Δ modulator. FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Integrator, 20 ... Quantizer, 30 ... Frequency-voltage (current) converter,
40 ... High time resolution sampler, 41-44 ... DFF as individual sampler,
45: Binary decoder.

Claims (3)

An analog / digital converter including a Δ type or Σ-Δ type modulator that modulates an analog input signal into a pulse density modulated wave, and a sampler that samples the pulse density modulated wave using a clock signal, ,
Wherein In the delta type modulator, said analog input signal regardless of the clock signal is configured to include a quantizer for outputting a pulse exceeds闘値, in the said sigma-delta type modulator, An integrator that integrates the analog input signal regardless of the clock signal or a quantizer that outputs a pulse when the input from the resonator exceeds a threshold value,
The sampler has a plurality of individual samplers to which the pulse density modulation wave is simultaneously input, and the clock signal supplied to the individual samplers is transmitted between the individual samplers. An analog / digital converter characterized by being delayed for a shorter time. An analog / digital converter including a Σ-Δ type modulator that modulates an analog input signal into a pulse density modulated wave, and a sampler that samples the pulse density modulated wave using a clock signal,
The Σ-Δ modulator is connected to an integrator or a resonator that integrates the analog input signal and the integrator or the resonator, and the input from the integrator or the resonator is not related to the clock signal. An analog / digital converter comprising: a quantizer using a Josephson junction that outputs a pulse when a value is exceeded.   The sampler has a plurality of individual samplers to which the pulse density modulation wave is simultaneously input, and the clock signal supplied to the individual samplers is transmitted between the individual samplers in the period of the clock signal. 3. The analog / digital converter according to claim 2, wherein the analog / digital converter is delayed for a shorter time.

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