JP4038663B2 - IC test system and minimum address selection method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an IC test apparatus for controlling an address search of fail data between storage devices (fail memories) storing a plurality of IC test results for redundancy.
[0002]
[Prior art]
A first module group for storing fail information, which is a measurement result in the IC test (16 fail memories 2 indicated by # 1 to # 16 in FIG. 1 and 16 buffer memories 3 indicated by # 1 to # 16 in FIG. 1). Measurement results of a plurality of devices under test (DUT) are stored.
Although the number of fail memories and buffer memories is 16 in FIG. 1, it is not necessarily required to be 16.
[0003]
In FIG. 1, the measurement result information of each DUT is divided and stored for each DUT on 16 cards per station.
The IC test apparatus is usually provided with two stations as the station, but it is not always necessary to have two stations.
Although not shown in FIG. 1, redundancy units are provided in the fail memories (# 1 to # 16) and the buffer memories (# 1 to # 16).
[0004]
The relationship between the fail memory 2 (# 1 to # 16) and the buffer memory 3 (# 1 to # 16) is such that the measurement results of a plurality of devices under test (DUT) measured by the tester unit are temporarily stored in the fail memory. By transferring the measurement result to the buffer memory for redundancy processing, it is possible to avoid occupying the fail memory all the time.
Note that the fail search for the redundancy process does not necessarily need to be performed on the buffer memory, and the fail search can be performed on the fail memory.
[0005]
When executing redundancy, there has conventionally been a system for searching for a fail or path corresponding to a minimum address in a fail search within a specific range address from a specified DUT group.
However, the function for executing the detection of the minimum address in the conventional fail search is that the search for each board (fail memory or buffer memory) is totaled by the second module having a configuration different from the first module. , Including the process of extracting the minimum address of the fail or pass in the fail search.
This process is conventionally executed by a second module (not shown) configured by hardware.
[0006]
[Problems to be solved by the invention]
Recently, in order to increase the speed of redundancy (fail DUT relief) processing and to meet the demand for the number of CPUs used for each user, the number of redundancy units has been increased (for example, 16 fail memories or 16 buffer memories). It is necessary to arrange one redundancy unit for eight, that is, two fail memories or buffer memories.
[0007]
As described above, when a plurality of redundancy units are provided, the second module, which is a hardware that performs the function of counting the minimum addresses detected in the fail search, is also divided into a plurality of units, which are separated by a separate control system. It becomes necessary to operate.
When the second module configured by hardware is divided into a plurality of parts and operated by different control systems, a plurality of DUT searches performed by a single integrated control system centered on the conventional tester unit 1 As a result of this, there arises a problem that the tabulation becomes impossible.
As a solution to the above problem, it is possible to cope with the problem by adding hardware. However, the cost problem and the physical volume of the IC memory test system main body also increase.
[0008]
An object (object) of the present invention is to provide an IC test system capable of executing a high-speed multiple DUT fail search at a low cost without increasing the size of an IC test apparatus by adding new hardware, and a fail ( It is to provide a method for selecting a (pass) address.
[0009]
[Means for Solving the Problems]
In order to solve the above-described problem, the measurement results of fail or path of a plurality of devices under measurement are stored in a plurality of fail memories or / and buffer memories under the control of the tester unit, and the plurality of fail memories or buffer memories are stored. In an IC test system that performs a fail search to detect the minimum address of a fail or path,
The plurality of redundancy units provided for the plurality of fail memories or buffer memories, and the tester unit, the fail search results from the fail memory or the buffer memory by the plurality of redundancy units are totalized, An IC test system is configured by minimum address selection means for selecting the minimum address of the fail addresses or pass addresses of a plurality of devices under measurement. (Claim 1)
[0010]
The plurality of redundancy units are configured to be centrally controlled by the tester unit. (Claim 2)
Further, the process of selecting the minimum address of the fail addresses or pass addresses of the plurality of devices under measurement by the totaling process of the fail search results from the fail memory or the buffer memory is executed by a software process by the tester unit. And (Claim 3)
[0011]
Also, the basic information of the specified device under measurement is read from the fail memory or buffer memory, and the flag area and information area corresponding to the fail memory or buffer memory to be subjected to the fail search are set in the tester unit. A step of outputting a fail search request for a plurality of devices to be measured to the fail memory card or the buffer memory, executing a fail search for the fail memory card or the buffer memory, and obtaining the search result The step of storing in the information area set in the tester unit and the step of selecting the minimum address by comparing the search results for each device under test stored in the buffer, Perform selection. (Claim 4)
[0012]
Further, in the flag area, when the device under measurement is not a fail search target, when fail search for all the devices under measurement has already been completed, and when the search results have already been acquired, A bit is set up. (Claim 5)
The minimum address is a fail address or a pass address between a plurality of devices under measurement, and the device under measurement having the minimum address is output as a final search result. (Claim 6)
[0013]
DETAILED DESCRIPTION OF THE INVENTION
The configuration of the apparatus according to the present invention will be described with reference to FIG.
In FIG. 1, reference numeral 1 denotes a tester unit that executes a test for a device under measurement.
Reference numeral 2 denotes a fail memory for storing the measurement result of the device under test by the tester unit, which is divided into 16 cards per station.
Although not shown in FIG. 1, there are a plurality of redundancy units (e.g., 8 units for 16 pieces of fail memory or buffer memory, that is, one unit for 2 units of fail memory or buffer memory). ) Is arranged.
[0014]
The IC test apparatus normally has two stations as the station, but it is not always necessary to have two stations, and the number of fail memories and buffer memories is 16 in FIG. It is not necessary to be the same as in the conventional case.
[0015]
Reference numeral 3 denotes a buffer memory, which is an auxiliary storage device for transferring the IC test result stored in the fail memory prior to redundancy processing or the like, and is divided into 16 cards per station.
Note that the fail search for the redundancy process does not necessarily have to be performed on the Bach memory, and the fail search can be directly performed on the fail memory.
[0016]
The tester unit 1 constituting the IC test system has a fail memory 2 or a buffer memory 3 which is a storage device in which an IC test result is stored by a fail search command requested by the uploaded device program prior to the redundancy process. Asks for a fail search.
[0017]
The fail memory 2 or the buffer memory 3 receives a request for fail search, searches for the minimum fail address or the minimum path address in each device under measurement, and transmits the search result to the tester unit 1.
[0018]
Corresponds to the minimum address in the specific range address in the specified device under test (DUT) group extracted from the first module group (fail memory (# 1 to # 16) / buffer memory (# 1 to # 16)) The fail or pass information is temporarily stored in a buffer in the tester unit.
Thereafter, a system that compares them and finally returns the address having the smallest value will be described with reference to FIG.
[0019]
First, the tester unit 1 reads the designated DUT basic information (IC test apparatus IP address, station number, total number, etc.) from the fail memory / buffer memory. (Step S1)
Next, the tester unit 1 creates a card (board with a fail memory or buffer memory) information flag and a card information buffer that require acquisition of search results. (Step S2)
Thereafter, a plurality of DUT fail search requests are output to each fail memory card (or buffer memory). (Step S3)
At this time, if it is not a search target, if the search has already been completed to the end, or if the search result has already been acquired, the card information flag bit created in step S2 is set.
Next, the search result for each card is stored with respect to the buffer having the card information flag set in the buffer created in step S2. (Step S4)
・ Compare search results for each stored card. (Step S5)
As a result of the comparison in step S5, the card having the smallest address is set as a value as the final search result. (Step S6)
[0020]
As described above, according to the configuration of the present invention, it is possible to compare the search results for each card at low cost and at high speed without increasing the size of the IC test apparatus, and to determine the card having the minimum address of fail or pass. By configuring the processing to be output as the final search result by software, the processing results of the redundancy units divided into a plurality (for example, 8) each operating independently are integrated and aggregated. Is possible.
[0021]
【The invention's effect】
In the first aspect of the present invention, the measurement results of the fail or path of a plurality of devices under measurement are stored in a plurality of fail memories or / and buffer memories under the control of the tester unit, and stored in the plurality of fail memories or buffer memories. In contrast, in an IC test system that performs a fail search to detect the minimum address of a fail or path,
The plurality of redundancy units provided for the plurality of fail memories or buffer memories, and the tester unit, the fail search results from the fail memory or the buffer memory by the plurality of redundancy units are totalized, Since the IC test system is configured by the minimum address selection means for selecting the minimum address of the fail address or pass address of a plurality of devices under measurement, the cost can be reduced without increasing the size of the IC test apparatus by adding new hardware. Thus, it is possible to realize a novel test result search control system of an IC test system that can execute a high-speed multiple DUT fail search.
[0022]
In the inventions according to claims 2 and 3, the plurality of redundancy units are controlled in an integrated manner by the tester unit, and the plurality of devices under measurement are collected by a totaling process of fail search results from the fail memory or the buffer memory. Since the process of selecting the minimum address of the fail address or pass address is executed by software processing by the tester unit, overall control can be realized by software corresponding to the addition of a plurality of redundancy units.
[0023]
According to a fourth aspect of the present invention, a step of reading basic information of a specified device under measurement from a fail memory or a buffer memory, and a flag area corresponding to the fail memory or buffer memory to be subjected to a fail search And a step of setting an information area in the tester unit, a step of outputting a fail search request for a plurality of devices to be measured to the fail memory card or the buffer memory, and a fail search for the fail memory card or the buffer memory. Executing and storing the search result in an information area set in the tester unit, comparing the search result for each device under measurement stored in the buffer, and selecting a minimum address; The smallest in IC test system New test result search control for an IC test system that can perform high-speed, multi-DUT fail search at low cost without increasing the size of the IC test device by adding new hardware. A system can be realized.
[0024]
Further, in the invention according to claim 5, in the flag area, when the device under measurement is not a fail search target, when a fail search for all the devices under measurement has already been completed, and search results have already been acquired. Since the configuration is such that the bit is set under conditions other than the case where it is already completed, a fail search for the device under measurement where the bit is set can be easily realized by software processing.
In the invention according to claim 6, the minimum address is a fail address or a pass address between a plurality of devices under measurement, and the device under measurement having the minimum address is output as a final search result. Therefore, the minimum address associated with the redundancy process can be easily selected.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an IC test system of the present invention.
FIG. 2 is a flowchart showing a procedure for selecting a minimum address in the IC test system of the present invention.
[Explanation of symbols]
1 Tester unit 2 Fail memory (# 1 to # 16)
3 Buffer memory (# 1 to # 16)

Claims (6)

By controlling the tester unit, the measurement results of fail or path of a plurality of devices under test are accumulated in a plurality of fail memories or / and buffer memories, and a fail search is executed for the plurality of fail memories or buffer memories. In an IC test system that detects the minimum address of a fail or path,
A plurality of redundancy units provided for the plurality of fail memories or buffer memories;
The tester unit includes a minimum address selecting means for summing up the fail search results from the fail memory or the buffer memory by the plurality of redundancy units and selecting the minimum address of the fail addresses or pass addresses of the plurality of devices under measurement. When,
An IC test system comprising: The IC test system according to claim 1, wherein the plurality of redundancy units are collectively controlled by the tester unit. The process of selecting the minimum addresses of the fail addresses or pass addresses of the plurality of devices under measurement by a totaling process of fail search results from the fail memory or the buffer memory is executed by a software process by the tester unit. The IC test system according to claim 1 or 2. Reading basic information of a specified device under test from fail memory or buffer memory;
Setting a flag area and an information area in the tester unit corresponding to the fail memory or buffer memory to be subjected to fail search;
Outputting a fail search request for a plurality of devices under measurement to the fail memory card or the buffer memory;
Performing a fail search on the fail memory card or buffer memory and storing the search result in an information area set in the tester unit;
Comparing the search results for each device under test stored in the buffer and selecting the smallest address;
A method for selecting a minimum address in an IC test system, comprising: Bits are set in the flag area under conditions other than when the device under measurement is not a fail search target, when a fail search has already been completed for all the devices under measurement, and when search results have already been acquired. 5. The method for selecting a minimum address in an IC test system according to claim 4, wherein: 6. The minimum address is a fail address or a pass address between a plurality of devices under measurement, and the device under measurement having the minimum address is output as a final search result. A method for selecting a minimum address in the described IC test system.

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