JP4034193B2

JP4034193B2 - Sampling pulse generator

Info

Publication number: JP4034193B2
Application number: JP2003004137A
Authority: JP
Inventors: 章弘川田; 隆博中島
Original assignee: Advantest Corp
Current assignee: Advantest Corp
Priority date: 2003-01-10
Filing date: 2003-01-10
Publication date: 2008-01-16
Anticipated expiration: 2023-01-10
Also published as: JP2004221724A

Description

【０００１】
【発明の属する技術分野】
この発明は、サンプリング装置のサンプリングタイミングを可変にする可変遅延手段を備えるサンプリングパルス発生装置に関する。特に、微小遅延可能な微小遅延手段と正負のサンプリングパルス供給手段を一体の回路構成で実現してより安価に構成できるサンプリングパルス発生装置の実現に関する。
【０００２】
【従来の技術】
【０００３】
【特許文献１】
特開平１０−１１２６３６号公報（第１図）
【０００４】
特開平１０−１１２６３６号公報では、共鳴トンネル・ダイオードを用いて極めて幅の狭い相反のパルスを発生させ、極めて広い周波数帯域を有する高速サンプリング回路の実現である。
【０００５】
本願の、図１は従来のサンプリング装置の原理構成図である。サンプリング装置は繰り返し発生する高周波の被測定信号Ｓ１を、所望のタイミング（位相）に順次変更しながら低速な周期で連続的にサンプリングしたサンプリング信号Ｓ２を出力するものである。この構成要素例としてはサンプリングヘッドＳＨと、パルサー回路１４と、微小遅延手段（位相シフト手段）２０とがある。ここで、外部から入力される基準クロックＲｃｌｋは被測定信号Ｓ１に同期した関係のクロックであり、且つ１／Ｎの低速なクロックと仮定する。
【０００６】
微小遅延手段（位相シフト手段）２０は基準クロックＲｃｌｋを受けて所望の位相量に微小遅延したサンプリングクロック２０ｃｌｋを出力する可変遅延手段である。可変とする遅延量（位相量）は被測定信号Ｓ１の少なくとも１サイクル時間が必要である。また、必要とされる遅延分解能（位相分解能）は被測定信号によっても異なるが、例えば５ｐＳ（ピコ秒）程度が要求される。
【０００７】
パルサー回路１４は、微小遅延手段２０からのサンプリングクロック２０ｃｌｋを受けて、鋭い狭パルスの正負のサンプリングパルスＳＰ＋、ＳＰ−に変換した後、サンプリングヘッドＳＨへ供給する。
【０００８】
サンプリングヘッドＳＨは、パルサー回路１４からの正負のサンプリングパルスＳＰ＋、ＳＰ−による一瞬のタイミングで、被測定信号Ｓ１のアナログ電圧をサンプリングしてホールドした結果のサンプリング信号Ｓ２を出力する。
【０００９】
【発明が解決しようとする課題】
上述説明したように、従来のサンプリング装置ではサンプリングヘッドＳＨへ所望に遅延した正負のサンプリングパルスを供給する為に、微小遅延が可能な微小遅延手段２０とパルサー回路１４とを備える構成で実現していた。
そこで、本発明が解決しようとする課題は、微小遅延可能な微小遅延手段と正負のサンプリングパルス供給手段を一体の回路構成で実現してより安価に構成できるサンプリングパルス発生装置を提供することである。
【００１０】
【課題を解決するための手段】
第１の解決手段を示す。ここで第２図（ａ）と第３図は、本発明に係る解決手段を示している。
上記課題を解決するために、サンプリング装置のサンプリングヘッドＳＨへ所定周期の正負の差動のサンプリングパルスを供給し、且つ前記サンプリングパルスのタイミングを連続的に可変可能な遅延手段を備えるサンプリングパルス発生装置であって、ステップリカバリ・ダイオード（ＳＲＤ）Ｄ１と、所定パルス幅生成手段と、電流方向スイッチング手段と、順方向電流量可変手段と、逆方向電流量可変手段とを備え、
上記ＳＲＤは流れる電流が順方向から逆方向に切替えて当該ダイオードの少数キャリアライフタイムτの直後において、アノードとカソードの両端から極性の異なる急峻な正インパルスＰ＋と負インパルスＰ−を発生するものであり、
前記所定パルス幅生成手段は上記ＳＲＤの両端で発生した正ステップパルスと負ステップパルスが伝送線路を進行波として各々伝搬させ、当該進行波が反射して戻ってくる反射波との合成波形に基づいて所定パルス幅のサンプリングパルスを生成するもの（例えば第２伝送線路Ｌ２と第３伝送線路Ｌ３とショート用コンデンサＣ１）であり、
上記電流方向スイッチング手段は外部からサンプリング用の基準クロックＲｃｌｋを受けて当該基準クロックのハイ／ローレベルに対応して上記ＳＲＤに流れる電流の方向を反転させるもの（例えば差動パルス駆動回路１１０とトランジスタＱ１、Ｑ２、Ｑ３、Ｑ４）であり、
上記順方向電流量可変手段は上記ＳＲＤに流れる順方向電流ＩFの電流量を外部から可変可能に制御するもの（例えばＤＡ変換器１２１とトランジスタＱ５と抵抗Ｒ１）であり、
上記逆方向電流量可変手段は上記ＳＲＤに流れる逆方向電流ＩRの電流量を外部から可変可能に制御するもの（例えばＤＡ変換器１２２とトランジスタＱ６と抵抗Ｒ２）である、ことを特徴とするサンプリングパルス発生装置である。
【００１１】
次に、第２の解決手段を示す。ここで第３図は、本発明に係る解決手段を示している。
上述所定パルス幅生成手段の一態様は、第１伝送線路Ｌ１と第２伝送線路Ｌ２と第３伝送線路Ｌ３と第４伝送線路Ｌ４と第１コンデンサ（ショート用コンデンサＣ１）とを備え、
上記電流方向スイッチング手段に基づいて２値の電圧レベルに切り替え制御する一方の第１電圧レベル切替端（トランジスタＱ２のコレクタ端）と他方の第２電圧レベル切替端（トランジスタＱ３のエミッタ端）との両端の間に対して第１伝送線路Ｌ１、第２伝送線路Ｌ２、ＳＲＤ、第３伝送線路Ｌ３、第４伝送線路Ｌ４の順番で直列接続し、
第１伝送線路Ｌ１と第２伝送線路Ｌ２の接続点と、第３伝送線路Ｌ３と第４伝送線路Ｌ４の接続点との間に、上記ステップパルスに対するインピーダンスが十分に低いショート状態に近い容量値の第１コンデンサ（ショート用コンデンサＣ１）を接続し、
上記第２伝送線路Ｌ２と第３伝送線路Ｌ３とは生成すべきパルス幅の時間に対して１／２程の伝搬遅延量を示す所定特性インピーダンスの伝送線路であり、
上記第１伝送線路Ｌ１と第４伝送線路Ｌ４とは上記ＳＲＤへ直流電流を供給でき、且つ第２伝送線路Ｌ２又は第３伝送線路Ｌ３でステップパルスを反射させるときの反射波形に影響を与えない程度にハイインピーダンスの伝送線路（又はパルス通過阻止用インダクタンス要素）である、ことを特徴とする上述サンプリングパルス発生装置がある。
【００１２】
次に、第３の解決手段を示す。ここで第３図は、本発明に係る解決手段を示している。
上述電流方向スイッチング手段の一態様は、差動パルス駆動回路１１０と第１トランジスタＱ１と第２トランジスタＱ２と第３トランジスタＱ３と第４トランジスタＱ４とを備え、
上記差動パルス駆動回路１１０は外部からサンプリング用の基準クロックＲｃｌｋを受けて、当該基準クロックがローレベルのときには上記第２トランジスタＱ２と第３トランジスタＱ３とを動作状態にバイアスする所定バイアス電圧を発生し、当該基準クロックがハイレベルのときには上記第１トランジスタＱ１と第４トランジスタＱ４とを動作状態にバイアスする所定バイアス電圧を発生するものであり、
上記第１トランジスタＱ１のエミッタ端と第２トランジスタＱ２のコレクタ端とが接続されて伝送線路を介してＳＲＤのカソード端へ接続し、
上記第３トランジスタＱ３のエミッタ端と第４トランジスタＱ４のコレクタ端とが接続されて伝送線路を介してＳＲＤのアノード端へ接続し、
上記第１トランジスタＱ１と第３トランジスタＱ３のコレクタ端は正電源＋Ｖへ接続し、
上記第２トランジスタＱ２のエミッタ端は上記順方向電流量可変手段に接続し、
上記第４トランジスタＱ４のエミッタ端は上記逆方向電流量可変手段に接続し、
第２トランジスタＱ２と第３トランジスタＱ３とは動作状態にバイアスされているときにＳＲＤに対して順方向電流ＩFが流れるように電流スイッチさせるものであり、
上記第１トランジスタＱ１と第４トランジスタＱ４とは動作状態にバイアスされているときにＳＲＤに対して逆方向電流ＩRが流れるように電流スイッチさせるものである、ことを特徴とする上述サンプリングパルス発生装置がある。
【００１３】
次に、第４の解決手段を示す。ここで第３図は、本発明に係る解決手段を示している。
上述順方向電流量可変手段の一態様は、第１ＤＡ変換器１２１と第５トランジスタＱ５と第１抵抗Ｒ１とを備え、
上記第１ＤＡ変換器１２１は外部からの第１制御データを受けて対応する直流電圧１２１ｓを発生するものであり、
上記第５トランジスタＱ５はベース端に上記直流電圧１２１ｓを受け、エミッタ端に第１抵抗を接続してコレクタ端から上記第１制御データに対応する順方向電流ＩFをシンクするものである、ことを特徴とする上述サンプリングパルス発生装置がある。
【００１４】
次に、第５の解決手段を示す。ここで第３図は、本発明に係る解決手段を示している。
上述逆方向電流量可変手段の一態様は、第２ＤＡ変換器１２２と第６トランジスタＱ６と第２抵抗Ｒ２とを備え、
上記第２ＤＡ変換器１２２は外部からの第２制御データを受けて対応する直流電圧１２２ｓを発生するものであり、
上記第６トランジスタＱ６はベース端に上記直流電圧１２２ｓを受け、エミッタ端に第２抵抗を接続してコレクタ端から上記第２制御データに対応する逆方向電流ＩRをシンクするものである、ことを特徴とする上述サンプリングパルス発生装置がある。
【００１５】
尚、本願発明手段は、所望により、上記解決手段における各要素手段を適宜組み合わせて、実用可能な他の構成手段としても良い。また、上記各要素に付与されている符号は、発明の実施の形態等に示されている符号に対応するものの、これに限定するものではなく、実用可能な他の均等物を適用した構成手段としても良い。
【００１６】
【発明の実施の形態】
以下に本発明を適用した実施の形態の一例を図面を参照しながら説明する。また、以下の実施の形態の説明内容によって特許請求の範囲を限定するものではないし、更に、実施の形態で説明されている要素や接続関係等が解決手段に必須であるとは限らない。更に、実施の形態で説明されている要素や接続関係等の形容／形態は、一例でありその形容／形態内容のみに限定するものではない。
【００１７】
本発明について、図２〜図４とを参照して以下に説明する。尚、従来構成に対応する要素は同一符号を付し、また必要がない限り同一符合の要素は説明を省略する。
【００１８】
図２は本発明のサンプリング装置の原理構成図である。この構成要素はサンプリングヘッドＳＨと、差動パルス発生／パルス遅延手段１００とを備える。
【００１９】
差動パルス発生／パルス遅延手段１００は微小遅延が可能な微小遅延手段と正負のサンプリングパルス供給手段を一体回路に構成したものである。図３は差動パルス発生／パルス遅延手段の具体的な構成例である。
【００２０】
図３の構成例に示す構成要素は差動パルス駆動回路１１０と、ＤＡ変換器１２１、１２２と、トランジスタＱ１〜Ｑ６と、抵抗Ｒ１、Ｒ２と、伝送線路Ｌ１〜Ｌ４と、ショート用コンデンサＣ１と、ステップリカバリ・ダイオードＤ１と、出力コンデンサＣ２、Ｃ３とを備える。
【００２１】
ステップリカバリ・ダイオード（ＳＲＤ）Ｄ１は、本回路構成により、対称的で急峻な正パルスＳＰ＋と負パルスＳＰ−とを発生させるものである。ここで、図２（ｂ）のＳＲＤが有する遅れ時間ｔsの関係式と、図４の遅れ時間ｔsの説明図について説明する。
遅れ時間ｔsとは順方向電流ＩFによってＳＲＤに蓄積された少数キャリアが消失するまでの時間である。図２（ｂ）に示す遅れ時間ｔsのパラメータとしては、順方向電流ＩFと逆方向電流ＩRと少数キャリアライフタイムτと順方向伝達時間ｔfとがあり、式１のような関係式となっている。特に、サンプリング装置に適用する場合、ｔf＞＞τの条件となる結果、遅れ時間ｔsはＩFとＩRによってほぼ決まることになる。
【００２２】
図４（ａ）はＳＲＤへパルスを印加する原理図であり、図４（ｂ）はＳＲＤに流れる電流と遅れ時間ｔsの関係を示す応答特性である。ＳＲＤに流れる電流量を変更することにより、遅れ時間ｔｓは図４Ｄ、Ｅ、Ｆの応答特性のように変化することが知られている。従って、ＳＲＤに流れる電流を外部から制御可能にすることにより、サンプリングパルスＳＰの発生タイミングを微調整することが可能となる。図３の構成例はその具体的な回路構成例である。また、遅れ時間ｔs経過後にＳＲＤは急激にＯＦＦする結果、ＳＲＤの両端には正負の急峻なステップ電圧が発生するので、従来のようなパルサー回路１４は不要である。
【００２３】
図３に戻り、差動パルス駆動回路１１０はトランジスタＱ１〜Ｑ４のＯＮ／ＯＦＦを制御するスイッチ信号の発生部であって、定常時はトランジスタＱ２、Ｑ３をＯＮ状態に制御して、ステップリカバリ・ダイオードＤ１に順方向電流ＩFを流している。次に、基準クロックＲｃｌｋが立ち上がり（若しくは立下がり）に変化したら、トランジスタＱ２、Ｑ３をＯＦＦ状態に制御し、トランジスタＱ１、Ｑ４をＯＮ状態に制御して、ステップリカバリ・ダイオードＤ１に逆方向電流ＩRを流すように切り替え制御する。これによれば、図３Ａの経路に示す順方向電流ＩFが流れた後において、図３Ｂの経路に示す逆方向電流ＩRが流れるが、この切替動作後、遅れ時間ｔsの後にＳＲＤの両端からサンプリングパルスＳＰ＋、ＳＰ−が発生する。
尚、ＯＮされるトランジスタは、完全に飽和状態に制御してしまうと、高速なスイッチ動作に支障となってくるので、能動状態を維持できる程度（例えばコレクタ電流＞ｈFE×ベース電流）のバイアス条件で当該トランジスタをＯＮ状態に制御することが望ましい。
【００２４】
トランジスタＱ１〜Ｑ４はステップリカバリ・ダイオードＤ１に流れる電流方向を切り替える為のスイッチであって、図３Ａの経路に示す順方向電流ＩFを流すときにはトランジスタＱ３、Ｑ２をＯＮ状態にする。逆に、図３Ｂの経路に示す逆方向電流ＩRを流すときにはトランジスタＱ１、Ｑ４をＯＮ状態にする。
【００２５】
次に、一方のＤＡ変換器１２１とトランジスタＱ５と抵抗Ｒ１とは第１の可変定電流源であって、ステップリカバリ・ダイオードＤ１に流す順方向電流ＩFを規定するものである。即ち、ＤＡ変換器１２１が外部からの制御データを受けてこれに対応した直流電圧１２１ｓをトランジスタＱ５のベース端へ供給する。前記電圧とエミッタ端に接続されている抵抗Ｒ１とによって決まる定電流をコレクタ端でシンクできる。このシンク電流ＩFsはステップリカバリ・ダイオードＤ１に流れる順方向電流ＩFとなる。
【００２６】
他方のＤＡ変換器１２２とトランジスタＱ６と抵抗Ｒ２とは第２の可変定電流源であって、ステップリカバリ・ダイオードＤ１に流す逆方向電流ＩRを規定するものである。即ち、ＤＡ変換器１２２が外部からの制御データを受けてこれに対応した直流電圧１２２ｓをトランジスタＱ６のベース端へ供給する。前記電圧とエミッタ端に接続されている抵抗Ｒ２とによって決まる定電流をコレクタ端でシンクできる。このシンク電流ＩRsはステップリカバリ・ダイオードＤ１に流れる逆方向電流ＩRとなる。
【００２７】
ここで、図４（ｃ）の遅延時間の特性例を説明する。図４Ａの試験条件は順方向電流ＩF＝１００〜２００ｍＡに変化させ、逆方向電流ＩR＝３００ｍＡ固定とした場合の遅延時間特性であり、図４Ｂの試験条件は順方向電流ＩF＝１７０ｍＡ固定とし、逆方向電流ＩR＝２５０〜３５０ｍＡに変化させた場合の遅延時間特性である。図の横軸はＩF／ＩRの比率であり、縦軸が遅延時間（ｎｓ）である。
第１に、図４Ａの試験条件では、順方向電流ＩFの変化に対して遅延時間は約５０ｐｓ／ｍＡの遅延変化を示している。第２に、図４Ｂの試験条件では、逆方向電流ＩRの変化に対して遅延時間は約１５ｐｓ／ｍＡの遅延変化を示している。
【００２８】
ここで１０ｂｉｔのＤＡ変換器１２１、１２２を使用したときの分解能について試算する。一方のＤＡ変換器１２１の順方向電流ＩFを０〜２５０ｍＡの範囲で変化できるとすると、電流設定値の分解能は約０．２４ｍＡとなる。したがって、遅延時間の分解能は３．６ｐｓとなる。他方のＤＡ変換器１２２の逆方向電流ＩRを０〜５００ｍＡの範囲で変化できるとすると、電流設定値の分解能は約０．４９ｍＡとなり、遅延時間の分解能は２５ｐｓとなる。この結果、１０ｂｉｔ程度の分解能を持つＤ／Ａ変換回路により２５ｐｓ、および４ｐｓ程度という２つの遅延時間分解能を持つサンプリングパルス発生回路を実現することができる。
【００２９】
上記のことから、粗い時間分解能で遅延時間を調整したい場合には、順方向電流ＩFを変化させるのが適当であり、逆に、細かい時間分解能で遅延時間を調整したい場合には、逆方向電流ＩRを変化させるのが適当であることが判る。尚、図４（ｃ）において、両者による遅延量の総合可変範囲は５ｎｓ程度が実現できる。従って、被測定信号の周波数は２００ＭＨｚ（１／５ｎｓ）以上であれば、外部に可変遅延手段を必要としない。これは大きな利点である。
尚、上記総合可変範囲が不足する場合には、例えば５ｎｓ単位に遅延量を可変にできる遅延手段を外部に備えて、入力される基準クロックＲｃｌｋを５ｎｓ単位に遅延させても良い。
【００３０】
図３に戻り、伝送線路Ｌ１〜Ｌ４は、伝搬遅延量を付与する例えば５０Ωの特性インピーダンスの遅延線路である。伝送線路Ｌ２、Ｌ３は発生するサンプリングパルスＳＰの要求パルス幅に対応し、ＳＲＤ逆バイアス時の端子間容量も入れた伝搬遅延量が、例えば５０ピコ秒となるよう適用する。伝送線路Ｌ１、Ｌ４は５０Ωのインピーダンスで伝送線路Ｌ２、Ｌ３を駆動する為の線路であり、例えば数百ピコ秒程度の伝搬遅延量を適用する。
【００３１】
ショート用コンデンサＣ１は、ＳＲＤ両端に生じたパルスが通過できる程度に低いインピーダンス値にするものである。これによれば、ＳＲＤの遅れ時間ｔs経過後にＯＮからＯＦＦに急峻に電流変化した瞬間に、ＳＲＤの両端子から発生する正負の両ステップ電圧は各々伝送線路Ｌ２、Ｌ３を進行波として伝搬してショート用コンデンサＣ１へ到達し、正負の両パルスは当該ショート用コンデンサＣ１を各々通過した後、各々の伝送線路Ｌ２、Ｌ３を反射波として伝搬してＳＲＤの端子に到達する。
この結果、ＳＲＤの両端子の電圧は、当該端子のステップ電圧と伝送線路Ｌ２、Ｌ３の遅延時間後に到達する逆電圧の反射波の合成によって、例えば５０＋５０＝１００ピコ秒のパルス幅のインパルスが生成される。生成された急峻な正のインパルスＰ＋と負のインパルスＰ−は出力コンデンサＣ２、Ｃ３を介してサンプリングパルスＳＰ＋、ＳＰ−としてサンプリングヘッドＳＨへ供給される。
【００３２】
【発明の効果】
本発明は、上述の説明内容からして、下記に記載される効果を奏する。
上述説明した図３の発明構成例及び図４（ｃ）の特性例によれば、一方の１０ｂｉｔのＤＡ変換器１２１による順方向電流ＩFの制御によって、例えば２５ｐｓ程度の遅延時間分解能の比較的粗い遅延時間の調整が可能であり、他方の１０ｂｉｔのＤＡ変換器１２２による逆方向電流ＩRの制御によって、例えば４ｐｓ程度の遅延時間分解能の比較的細かい遅延時間の調整が可能となる大きな利点が得られることとなる。
更に、両者による遅延量の総合可変範囲は５ｎｓ程度が実現できるからして、被測定信号の周波数は２００ＭＨｚ（１／５ｎｓ）以上に適用できる結果、外部に可変遅延手段を備えること無く所望の位相へ遅延させてサンプリングすることが実用的に可能である。従って、簡単で安価な回路構成で高分解能で実用的な可変遅延手段が実現できる大きな利点が得られる。
従って、本発明の技術的効果は大であり、産業上の経済効果も大である。
【図面の簡単な説明】
【図１】従来のサンプリング装置の原理構成図である。
【図２】本発明のサンプリング装置の原理構成図と、ＳＲＤが有する遅れ時間ｔsの関係式を説明する図である。
【図３】図２の差動パルス発生／パルス遅延手段の具体的な構成例である。
【図４】遅れ時間ｔsの説明図と、遅延時間の特性例である。
【符号の説明】
Ｃ１ショート用コンデンサ
Ｄ１ステップリカバリ・ダイオード（ＳＲＤ）
Ｌ１，Ｌ２，Ｌ３，Ｌ４伝送線路
Ｑ１，Ｑ２，Ｑ３，Ｑ４，Ｑ５，Ｑ６トランジスタ
Ｒ１，Ｒ２抵抗
Ｃ２，Ｃ３出力コンデンサ
１４パルサー回路
２０微小遅延手段（位相シフト手段）
１００差動パルス発生／パルス遅延手段
１１０差動パルス駆動回路
１２１，１２２ＤＡ変換器
ＩF 順方向電流
ＩR 逆方向電流
ＳＨサンプリングヘッド[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a sampling pulse generator provided with variable delay means for making the sampling timing of a sampling device variable. In particular, the present invention relates to the realization of a sampling pulse generator that can be constructed at a lower cost by realizing a minute delay means capable of minute delay and a positive and negative sampling pulse supply means with an integrated circuit configuration.
[0002]
[Prior art]
[0003]
[Patent Document 1]
JP-A-10-112636 (FIG. 1)
[0004]
Japanese Patent Application Laid-Open No. 10-112636 discloses the realization of a high-speed sampling circuit having a very wide frequency band by generating a very narrow reciprocal pulse using a resonant tunneling diode.
[0005]
FIG. 1 of the present application is a principle configuration diagram of a conventional sampling apparatus. The sampling device outputs a sampling signal S2 continuously sampled at a low-speed cycle while sequentially changing the high-frequency signal under test S1 that is repeatedly generated to a desired timing (phase). Examples of this component include a sampling head SH, a pulsar circuit 14, and a minute delay means (phase shift means) 20. Here, it is assumed that the reference clock Rclk input from the outside is a clock having a relationship synchronized with the signal S1 to be measured and is a low-speed clock of 1 / N.
[0006]
The minute delay means (phase shift means) 20 is a variable delay means that receives the reference clock Rclk and outputs a sampling clock 20clk that is slightly delayed to a desired phase amount. The variable delay amount (phase amount) requires at least one cycle time of the signal under measurement S1. Further, the required delay resolution (phase resolution) varies depending on the signal under measurement, but for example, about 5 pS (picosecond) is required.
[0007]
The pulsar circuit 14 receives the sampling clock 20clk from the minute delay means 20, converts it into positive and negative sampling pulses SP +, SP- of a sharp narrow pulse, and then supplies it to the sampling head SH.
[0008]
The sampling head SH outputs a sampling signal S2 as a result of sampling and holding the analog voltage of the signal under measurement S1 at a momentary timing by the positive and negative sampling pulses SP + and SP- from the pulsar circuit 14.
[0009]
[Problems to be solved by the invention]
As described above, the conventional sampling apparatus is realized with a configuration including the micro delay means 20 capable of performing micro delay and the pulsar circuit 14 in order to supply positive and negative sampling pulses delayed as desired to the sampling head SH. It was.
Therefore, the problem to be solved by the present invention is to provide a sampling pulse generator that can be constructed at a lower cost by realizing a minute delay means capable of minute delay and a positive and negative sampling pulse supply means with an integrated circuit configuration. .
[0010]
[Means for Solving the Problems]
A first solution will be described. Here, FIG. 2 (a) and FIG. 3 show the solution means according to the present invention.
In order to solve the above-mentioned problem, a sampling pulse generator comprising delay means capable of supplying positive and negative differential sampling pulses of a predetermined cycle to a sampling head SH of the sampling apparatus and continuously changing the timing of the sampling pulses. A step recovery diode (SRD) D1, a predetermined pulse width generation means, a current direction switching means, a forward current amount variable means, and a reverse current amount variable means;
The SRD generates steep positive impulses P + and negative impulses P− having different polarities from both ends of the anode and the cathode immediately after the minority carrier lifetime τ of the diode by switching the flowing current from the forward direction to the reverse direction. Yes,
The predetermined pulse width generation means is based on a combined waveform of a positive step pulse and a negative step pulse generated at both ends of the SRD as a traveling wave through the transmission line, and a reflected wave that reflects and returns the traveling wave. Generating a sampling pulse having a predetermined pulse width (for example, the second transmission line L2, the third transmission line L3, and the shorting capacitor C1),
The current direction switching means receives the sampling reference clock Rclk from the outside and inverts the direction of the current flowing through the SRD in accordance with the high / low level of the reference clock (for example, the differential pulse drive circuit 110 and the transistor Q1, Q2, Q3, Q4)
The forward current variable means controls the amount of forward current IF flowing through the SRD so as to be variable from the outside (for example, DA converter 121, transistor Q5, and resistor R1).
The reverse current variable means is a means for controlling the amount of reverse current IR flowing through the SRD so as to be variable from the outside (for example, a DA converter 122, a transistor Q6, and a resistor R2). It is a pulse generator.
[0011]
Next, a second solving means will be shown. FIG. 3 shows the solution means according to the present invention.
One aspect of the predetermined pulse width generating means includes a first transmission line L1, a second transmission line L2, a third transmission line L3, a fourth transmission line L4, and a first capacitor (shorting capacitor C1).
A first voltage level switching terminal (collector terminal of the transistor Q2) for switching control to a binary voltage level based on the current direction switching means and a second voltage level switching terminal (the emitter terminal of the transistor Q3) on the other side. The first transmission line L1, the second transmission line L2, the SRD, the third transmission line L3, and the fourth transmission line L4 are connected in series in order between the both ends.
Between the connection point of the first transmission line L1 and the second transmission line L2 and the connection point of the third transmission line L3 and the fourth transmission line L4, a capacitance value close to a short state in which the impedance to the step pulse is sufficiently low. The first capacitor (short capacitor C1)
The second transmission line L2 and the third transmission line L3 are transmission lines having a predetermined characteristic impedance indicating a propagation delay amount of about 1/2 with respect to the time of the pulse width to be generated,
The first transmission line L1 and the fourth transmission line L4 can supply a direct current to the SRD and do not affect the reflected waveform when the step pulse is reflected by the second transmission line L2 or the third transmission line L3. There is a sampling pulse generator described above, which is a transmission line (or an inductance element for preventing pulse passage) having a high impedance to an extent.
[0012]
Next, a third solving means will be shown. FIG. 3 shows the solution means according to the present invention.
One aspect of the current direction switching means includes a differential pulse drive circuit 110, a first transistor Q1, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4.
The differential pulse driving circuit 110 receives a sampling reference clock Rclk from the outside, and generates a predetermined bias voltage for biasing the second transistor Q2 and the third transistor Q3 to an operating state when the reference clock is at a low level. When the reference clock is at a high level, a predetermined bias voltage for biasing the first transistor Q1 and the fourth transistor Q4 to the operating state is generated.
The emitter end of the first transistor Q1 and the collector end of the second transistor Q2 are connected to each other and connected to the cathode end of the SRD via a transmission line;
The emitter end of the third transistor Q3 and the collector end of the fourth transistor Q4 are connected and connected to the anode end of the SRD via the transmission line,
The collector terminals of the first transistor Q1 and the third transistor Q3 are connected to a positive power source + V,
The emitter end of the second transistor Q2 is connected to the forward current variable means,
The emitter end of the fourth transistor Q4 is connected to the reverse current variable means.
The second transistor Q2 and the third transistor Q3 are for current switching so that the forward current IF flows to the SRD when biased to the operating state.
The sampling pulse generator as set forth above, wherein the first transistor Q1 and the fourth transistor Q4 are for switching current so that a reverse current IR flows with respect to the SRD when biased to an operating state. There is.
[0013]
Next, a fourth solving means will be shown. FIG. 3 shows the solution means according to the present invention.
One aspect of the forward current variable means includes the first DA converter 121, the fifth transistor Q5, and the first resistor R1,
The first DA converter 121 receives first control data from the outside and generates a corresponding DC voltage 121s.
The fifth transistor Q5 receives the DC voltage 121s at the base end, connects the first resistor to the emitter end, and sinks the forward current IF corresponding to the first control data from the collector end. There is the above-described sampling pulse generator characterized.
[0014]
Next, a fifth solving means will be shown. FIG. 3 shows the solution means according to the present invention.
One aspect of the reverse current variable means includes the second DA converter 122, the sixth transistor Q6, and the second resistor R2.
The second DA converter 122 receives the second control data from the outside and generates a corresponding DC voltage 122s.
The sixth transistor Q6 receives the DC voltage 122s at the base end, connects the second resistor to the emitter end, and sinks the reverse current IR corresponding to the second control data from the collector end. There is the above-described sampling pulse generator characterized.
[0015]
In addition, the invention means of the present application may be combined with each element means in the above-described solution means as appropriate to form other practical means that can be used as desired. Moreover, although the code | symbol provided to each said element respond | corresponds to the code | symbol shown by embodiment etc. of this invention, it is not limited to this, The structural means to which the other equivalent which is practical is applied It is also good.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
An example of an embodiment to which the present invention is applied will be described below with reference to the drawings. Further, the scope of the claims is not limited by the description of the following embodiment, and further, the elements and connection relationships described in the embodiment are not necessarily essential to the solution means. Further, the description / forms of the elements and connection relationships described in the embodiments are merely examples, and the present invention is not limited to the description / form contents.
[0017]
The present invention will be described below with reference to FIGS. In addition, the element corresponding to a conventional structure attaches | subjects the same code | symbol, and abbreviate | omits description of the element of the same code | symbol unless it is required.
[0018]
FIG. 2 is a principle configuration diagram of the sampling apparatus of the present invention. This component includes a sampling head SH and differential pulse generation / pulse delay means 100.
[0019]
The differential pulse generation / pulse delay means 100 comprises a minute delay means capable of minute delay and a positive and negative sampling pulse supply means in an integrated circuit. FIG. 3 shows a specific configuration example of the differential pulse generation / pulse delay means.
[0020]
3 include a differential pulse driving circuit 110, DA converters 121 and 122, transistors Q1 to Q6, resistors R1 and R2, transmission lines L1 to L4, and a shorting capacitor C1. , A step recovery diode D1 and output capacitors C2 and C3.
[0021]
The step recovery diode (SRD) D1 generates a symmetric and steep positive pulse SP + and a negative pulse SP− with this circuit configuration. Here, a relational expression of the delay time ts of the SRD of FIG. 2B and an explanatory diagram of the delay time ts of FIG. 4 will be described.
The delay time ts is the time until the minority carriers accumulated in the SRD disappear due to the forward current IF. As parameters of the delay time ts shown in FIG. 2B, there are a forward current IF, a reverse current IR, a minority carrier lifetime τ, and a forward transmission time tf. Yes. In particular, when applied to a sampling device, the condition of tf >> τ results in the delay time ts being substantially determined by IF and IR.
[0022]
FIG. 4A is a principle diagram for applying a pulse to the SRD, and FIG. 4B is a response characteristic showing the relationship between the current flowing through the SRD and the delay time ts. It is known that by changing the amount of current flowing in the SRD, the delay time ts changes like the response characteristics of FIGS. 4D, 4E, and 4F. Therefore, the generation timing of the sampling pulse SP can be finely adjusted by enabling the current flowing through the SRD to be controlled from the outside. The configuration example of FIG. 3 is a specific circuit configuration example. Further, as a result of the SRD turning off rapidly after the lapse of the delay time ts, positive and negative steep step voltages are generated at both ends of the SRD, so that the conventional pulsar circuit 14 is unnecessary.
[0023]
Returning to FIG. 3, the differential pulse drive circuit 110 is a switch signal generator that controls ON / OFF of the transistors Q1 to Q4. A forward current IF is passed through the diode D1. Next, when the reference clock Rclk changes to rising (or falling), the transistors Q2 and Q3 are controlled to be in the OFF state, the transistors Q1 and Q4 are controlled to be in the ON state, and the reverse current IR to the step recovery diode D1. Switch control to flow. According to this, after the forward current IF shown in the path of FIG. 3A flows, the reverse current IR shown in the path of FIG. 3B flows. After this switching operation, sampling is performed from both ends of the SRD after the delay time ts. Pulses SP + and SP- are generated.
It should be noted that if the transistor to be turned on is completely saturated, a high-speed switching operation is hindered. Therefore, the bias condition is such that the active state can be maintained (for example, collector current> hFE × base current). Thus, it is desirable to control the transistor to be in an ON state.
[0024]
The transistors Q1 to Q4 are switches for switching the direction of the current flowing through the step recovery diode D1, and when the forward current IF shown in the path of FIG. 3A flows, the transistors Q3 and Q2 are turned on. On the contrary, when the reverse current IR shown in the path of FIG. 3B is supplied, the transistors Q1 and Q4 are turned on.
[0025]
Next, one DA converter 121, the transistor Q5, and the resistor R1 are first variable constant current sources, and define the forward current IF that flows through the step recovery diode D1. That is, the DA converter 121 receives control data from the outside and supplies a corresponding DC voltage 121s to the base end of the transistor Q5. A constant current determined by the voltage and the resistor R1 connected to the emitter end can be sinked at the collector end. The sink current IFs becomes a forward current IF flowing through the step recovery diode D1.
[0026]
The other DA converter 122, transistor Q6, and resistor R2 are the second variable constant current source, and define the reverse current IR flowing through the step recovery diode D1. That is, the DA converter 122 receives control data from the outside and supplies a DC voltage 122s corresponding to the control data to the base terminal of the transistor Q6. A constant current determined by the voltage and the resistor R2 connected to the emitter end can be sinked at the collector end. The sink current IRs becomes a reverse current IR flowing through the step recovery diode D1.
[0027]
Here, a characteristic example of the delay time in FIG. 4C will be described. 4A is a delay time characteristic when the forward current IF is changed to 100 to 200 mA and the reverse current IR is fixed to 300 mA. The test condition of FIG. 4B is the forward current IF fixed to 170 mA. This is a delay time characteristic when the reverse current IR is changed to 250 to 350 mA. In the figure, the horizontal axis represents the ratio IF / IR, and the vertical axis represents the delay time (ns).
First, in the test condition of FIG. 4A, the delay time shows a delay change of about 50 ps / mA with respect to the change of the forward current IF. Second, in the test condition of FIG. 4B, the delay time shows a delay change of about 15 ps / mA with respect to the change of the reverse current IR.
[0028]
Here, a trial calculation is made for the resolution when the 10-bit DA converters 121 and 122 are used. If the forward current IF of one DA converter 121 can be changed in the range of 0 to 250 mA, the resolution of the current setting value is about 0.24 mA. Therefore, the resolution of the delay time is 3.6 ps. Assuming that the reverse current IR of the other DA converter 122 can be varied in the range of 0 to 500 mA, the resolution of the current set value is about 0.49 mA and the resolution of the delay time is 25 ps. As a result, a sampling pulse generation circuit having two delay time resolutions of about 25 ps and about 4 ps can be realized by a D / A conversion circuit having a resolution of about 10 bits.
[0029]
From the above, when adjusting the delay time with coarse time resolution, it is appropriate to change the forward current IF. Conversely, when adjusting the delay time with fine time resolution, the reverse current It can be seen that it is appropriate to change IR. In FIG. 4C, the total variable range of the delay amount due to both can be realized as about 5 ns. Therefore, if the frequency of the signal under measurement is 200 MHz (1/5 ns) or more, no external variable delay means is required. This is a great advantage.
When the total variable range is insufficient, for example, a delay unit capable of changing the delay amount in units of 5 ns may be provided outside, and the input reference clock Rclk may be delayed in units of 5 ns.
[0030]
Returning to FIG. 3, the transmission lines L <b> 1 to L <b> 4 are delay lines having a characteristic impedance of, for example, 50Ω, which impart a propagation delay amount. The transmission lines L2 and L3 are applied so that the propagation delay amount corresponding to the required pulse width of the generated sampling pulse SP and including the inter-terminal capacitance at the time of SRD reverse bias is, for example, 50 picoseconds. The transmission lines L1 and L4 are lines for driving the transmission lines L2 and L3 with an impedance of 50Ω. For example, a propagation delay amount of about several hundred picoseconds is applied.
[0031]
The shorting capacitor C1 has a low impedance value so that a pulse generated at both ends of the SRD can pass. According to this, at the moment when the current suddenly changes from ON to OFF after the lapse of the SRD delay time ts, both positive and negative step voltages generated from both terminals of the SRD propagate as traveling waves on the transmission lines L2 and L3, respectively. After reaching the shorting capacitor C1, both positive and negative pulses pass through the shorting capacitor C1, respectively, and then propagate as reflected waves on the transmission lines L2 and L3 to reach the terminal of the SRD.
As a result, the voltage of both terminals of the SRD generates an impulse having a pulse width of, for example, 50 + 50 = 100 picoseconds by combining the step voltage of the terminal and the reflected wave of the reverse voltage that arrives after the delay time of the transmission lines L2 and L3. Is done. The generated steep positive impulse P + and negative impulse P− are supplied to the sampling head SH as sampling pulses SP + and SP− through output capacitors C2 and C3.
[0032]
【The invention's effect】
The present invention has the following effects in view of the above description.
According to the above-described configuration example of FIG. 3 and the characteristic example of FIG. 4C, the delay current resolution of, for example, about 25 ps is relatively controlled by controlling the forward current IF by one 10-bit DA converter 121. Coarse delay time can be adjusted, and the control of the reverse current IR by the other 10-bit DA converter 122 provides a great advantage that a relatively fine delay time can be adjusted with a delay time resolution of about 4 ps, for example. Will be.
Further, since the total variable range of the delay amount by both can be realized as about 5 ns, the frequency of the signal under measurement can be applied to 200 MHz (1/5 ns) or more. As a result, a desired phase can be obtained without providing an external variable delay means. It is practically possible to sample with a delay. Therefore, a great advantage can be obtained that a practical variable delay means with high resolution can be realized with a simple and inexpensive circuit configuration.
Therefore, the technical effect of the present invention is great, and the industrial economic effect is also great.
[Brief description of the drawings]
FIG. 1 is a principle configuration diagram of a conventional sampling device.
FIG. 2 is a diagram illustrating a principle configuration of a sampling apparatus according to the present invention and a relational expression of a delay time ts possessed by an SRD.
3 is a specific configuration example of the differential pulse generation / pulse delay means of FIG.
FIG. 4 is an explanatory diagram of a delay time ts and an example of characteristics of the delay time.
[Explanation of symbols]
C1 Capacitor for short D1 Step recovery diode (SRD)
L1, L2, L3, L4 Transmission lines Q1, Q2, Q3, Q4, Q5, Q6 Transistors R1, R2 Resistors C2, C3 Output capacitor 14 Pulsar circuit 20 Minute delay means (phase shift means)
100 Differential Pulse Generation / Pulse Delay Unit 110 Differential Pulse Drive Circuits 121, 122 DA Converter IF Forward Current IR Reverse Current SH Sampling Head

Claims

A sampling pulse generator for supplying the sampling pulses of positive and negative differential to the sampling head SH of the sampling device,
Includes a step recovery diode (SRD), and a predetermined pulse width generating means, and a current direction switching means,
The SRD generates steep positive and negative impulses having different polarities from both ends of the anode and the cathode immediately after the flowing current is switched from the forward direction to the reverse direction.
The predetermined pulse width generating means, positive step pulse and a negative step pulse generated at both ends of the SRD causes respectively propagate as a traveling wave transmission line, the composite waveform of the reflected wave in which the traveling wave reflected back Based on this, a sampling pulse with a predetermined pulse width is generated,
The current direction switching means receives a reference clock for sampling from the outside and reverses the direction of the current flowing through the SRD corresponding to the high / low level of the reference clock.
It said current direction switching means, and a differential pulse drive circuit and the first transistor and the second transistor and the third transistor and a fourth transistor,
The differential pulse driving circuit receives a reference clock for sampling from the outside, and generates a predetermined bias voltage for biasing the second transistor and the third transistor to an operating state when the reference clock is at a low level. When a reference clock is at a high level, a predetermined bias voltage for biasing the first transistor and the fourth transistor to an operating state is generated.
The emitter end of the first transistor and the collector end of the second transistor are connected and connected to the cathode end of the SRD via the transmission line;
The emitter end of the third transistor and the collector end of the fourth transistor are connected and connected to the anode end of the SRD via the transmission line,
First transistor and the collector of the third transistor is connected to a positive power supply,
The emitter end of the second transistor conducts a forward current when the second transistor is biased to an operating state ,
The emitter end of the fourth transistor conducts a reverse current when the fourth transistor is biased to the operating state ,
The second transistor and the third transistor are for current switching so that a forward current IF flows to the SRD when biased to an operating state.
The first transistor and the fourth transistor are for current switching so that a reverse current IR flows to the SRD when biased to an operating state.
A sampling pulse generator characterized by that.

The predetermined pulse width generating means includes first transmission line and the second transmission line and the third transmission line and the fourth transmission line and a first capacitor,
A first transmission line and a second transmission between both ends of one first voltage level switching end and the other second voltage level switching end that are controlled to switch to a binary voltage level based on the current direction switching means. Line, SRD, third transmission line, fourth transmission line are connected in series in this order,
And a connection point of the first transmission line and the second transmission line, between a connection point of the third transmission line and the fourth transmission line, impedance for the step pulse is first capacitor sufficiently low capacitance value is connected,
The second transmission line and the third transmission line, a transmission line of predetermined characteristic impedance that indicates the propagation delay of a half degree relative to time of the pulse width to be generated,
The first transmission line and the fourth transmission line, high enough not to affect the reflected waveform when the reflecting step pulses can be supplied direct current to the SRD, and the second transmission line or the third transmission line The sampling pulse generator according to claim 1, wherein the sampling pulse generator is an impedance transmission line.

A sampling pulse generator for supplying the sampling pulses of positive and negative differential to the sampling head SH of the sampling device,
A step recovery diode (SRD), and a predetermined pulse width generating means, the current direction switching means, and a forward current quantity changing means comprises,
The SRD generates steep positive and negative impulses having different polarities from both ends of the anode and the cathode immediately after the flowing current is switched from the forward direction to the reverse direction.
The predetermined pulse width generating means, positive step pulse and a negative step pulse generated at both ends of the SRD causes respectively propagate as a traveling wave transmission line, the composite waveform of the reflected wave in which the traveling wave reflected back Based on this, a sampling pulse with a predetermined pulse width is generated,
The current direction switching means receives a reference clock for sampling from the outside and reverses the direction of the current flowing through the SRD corresponding to the high / low level of the reference clock.
The forward current amount varying means includes a first 1DA converter and the fifth transistor and a first resistor,
Said 1DA transducer, which generates a corresponding DC voltage by receiving the first control data from the outside,
The fifth transistor receives the DC voltage at a base end, connects a first resistor to an emitter end, and sinks a forward current IF corresponding to the first control data from a collector end. The sampling pulse generator according to claim 1.

The predetermined pulse width generating means includes first transmission line and the second transmission line and the third transmission line and the fourth transmission line and a first capacitor,
A first transmission line and a second transmission between both ends of one first voltage level switching end and the other second voltage level switching end that are controlled to switch to a binary voltage level based on the current direction switching means. Line connection, SRD, 3rd transmission line, 4th transmission line in order,
A first capacitor having a sufficiently low impedance with respect to the step pulse is connected between a connection point between the first transmission line and the second transmission line and a connection point between the third transmission line and the fourth transmission line;
The second transmission line and the third transmission line, a transmission line of predetermined characteristic impedance that indicates the propagation delay of a half degree relative to time of the pulse width to be generated,
The first transmission line and the fourth transmission line, high enough not to affect the reflected waveform when the reflecting step pulses can be supplied direct current to the SRD, and the second transmission line or the third transmission line 4. The sampling pulse generator according to claim 3 , wherein the sampling pulse generator is an impedance transmission line.

A sampling pulse generator for supplying the sampling pulses of positive and negative differential to the sampling head SH of the sampling device,
A step recovery diode (SRD), a predetermined pulse width generation means, a current direction switching means, and a reverse current amount variable means;
The SRD generates steep positive and negative impulses having different polarities from both ends of the anode and the cathode immediately after the flowing current is switched from the forward direction to the reverse direction.
The predetermined pulse width generating means, positive step pulse and a negative step pulse generated at both ends of the SRD causes respectively propagate as a traveling wave transmission line, the composite waveform of the reflected wave in which the traveling wave reflected back Based on this, a sampling pulse with a predetermined pulse width is generated,
The current direction switching means receives a reference clock for sampling from the outside and reverses the direction of the current flowing through the SRD corresponding to the high / low level of the reference clock.
It said reverse current amount varying means includes a first 2DA converter and sixth transistor and a second resistor,
The second DA converter receives the second control data from the outside and generates a corresponding DC voltage.
The sixth transistor receives the DC voltage at the base end, connects a second resistor to the emitter end, and sinks the reverse current IR corresponding to the second control data from the collector end. Sampling pulse generator.

The predetermined pulse width generating means includes first transmission line and the second transmission line and the third transmission line and the fourth transmission line and a first capacitor,
A first transmission line and a second transmission between both ends of one first voltage level switching end and the other second voltage level switching end that are controlled to switch to a binary voltage level based on the current direction switching means. Line, SRD, third transmission line, fourth transmission line are connected in series in this order,
And a connection point of the first transmission line and the second transmission line, between a connection point of the third transmission line and the fourth transmission line, impedance for the step pulse is first capacitor sufficiently low capacitance value is connected,
The second transmission line and the third transmission line, a transmission line of predetermined characteristic impedance that indicates the propagation delay of a half degree relative to time of the pulse width to be generated,
The first transmission line and the fourth transmission line, high enough not to affect the reflected waveform when the reflecting step pulses can be supplied direct current to the SRD, and the second transmission line or the third transmission line 6. The sampling pulse generator according to claim 5 , wherein the sampling pulse generator is an impedance transmission line.