JP4017149B2 - Processor with function for preventing unauthorized execution of programs - Google Patents

Description

【００７３】
このようなマイクロプログラムに従った認証手続は、外部プログラムからは全く見えない状態で実行される。本実施例に係る認証手続は、プロセッサ・チップ１００内部で完結されるので、プロセッサ１００外部からの監視は殆ど不可能なのである。
【００７４】
第２の実施の形態
本発明の第２の実施例は、図１に示したものと等価なハードウェア構成により具現される。但し、第１の実施例との相違点は、共通鍵ではなく公開鍵方式で暗号化する点にある。図４には、第２の実施例に係るプログラム保護動作をフローチャートにして示している。以下、図４を参照しながら説明する。
【００７５】
ソフトウェア供給業者は、保護対象たるソフトウェア・プログラムをレキシブル・ディスク又はＣＤ−ＲＯＭなどの記憶媒体に格納した形態で、市場に流通する。このソフトウェア・プログラムには、固有の識別情報すなわちソフトウェアＩＤ（通常はシリアルな番号で構成される）が付されている。ユーザは、フレキシブル・ディスク又はＣＤ−ＲＯＭなどの記憶媒体をソフトウェア供給業者から購入するという形態で、ソフトウェア・プログラムの限定的な使用権を取得する（記憶媒体の購入は、ソフトウェァの著作権や無制限な使用権を全く意味しない点に充分留意されたい）。そして、ユーザは、記憶媒体を所定のドライブ・ユニット８１／８２に装填して、ソフトウェア・プログラムをシステム２００のハード・ディスク８１上にインストールする。
【００７６】
このインストール作業には、プロセッサＩＤ１６を暗号化する手続（ステップＳ２００）と、暗号化したプロセッサＩＤ及びプロセッサ１００に内蔵された公開鍵をソフトウェア供給業者に送付する手続（ステップＳ２０２）を含んでいる。暗号化処理は、暗号化復号化ユニット１７が、ソフトウェア供給業者から与えられた公開鍵を用いて行われる。送付手続は、ソフトウェア供給業者に対するＫｅｙ（後述）の要求を意味する。なお、送付手続は、郵送に依る他、ＮＩＣ９０で接続された外部ネットワーク経由での伝送という形態で行ってもよい。
【００７７】
ソフトウェア供給業者は、受け取った暗号情報を、自分の秘密鍵を用いて復号化して、元のプロセッサＩＤを得る（ステップＳ２０４）。そして、このプロセッサＩＤと、業者自身が手元で管理しているソフトウェアＩＤとを一体化して、再びプロセッサ１００の公開鍵を用いて暗号化して、Ｋｅｙを生成する（ステップＳ２０６）。Ｋｅｙは、プロセッサＩＤとソフトウェアＩＤとを１つのコードとして同時に暗号化したものであり、各々に切り離すことはできない。Ｋｅｙは、ソフトウェアの使用不能状態を解く鍵としての性質を持ち、郵送あるいはネットワーク経由でユーザに返送される（ステップＳ２０８）。
【００７８】
このＫｅｙを取得した状態で、コンピュータ・システム２００上でソフトウェア・プログラムの実行が促されたとする。これは、例えばＯＳ（オペレーティング・システム）のような外部プログラムが"ＬＯＡＤ ＭＭＵ…"のような実行許可インストラクションを発行して、メモリ管理ユニット１５にプログラムＩＤとプログラムの格納番地／属性情報がセットすることにより、実現される。
【００７９】
本実施例の実行許可インストラクションに該当する処理手続は、図４の破線ブロックで囲まれている。実行許可は、メモリ管理ユニット１５への各変数のセット以外に所定の認証手続を含んでいる。
【００８０】
当該インストラクションが発行されると、プロセッサ１００は、受け取っているＫｅｙを復号化して、プロセッサＩＤとソフトウェアＩＤとを取得する（ステップＳ２１０）。復号化処理は、暗号化復号化ユニット１７が、プロセッサ１００自身に内蔵された秘密鍵を用いて行う。
【００８１】
次いで、プロセッサ１００は、復号化して得られたプロセッサＩＤとソフトウェアＩＤを、プロセッサ１００自身に内蔵されたプロセッサＩＤ、及び装填した記憶媒体から得られたソフトウェアＩＤの各々と比較する（ステップＳ２１２）。
【００８２】
この比較の結果、照合に失敗したならば、メモリ管理ユニット１５によるプログラムの実行は拒否される（ステップＳ２１４）。他方、照合が成功裡に終わったならば、メモリ管理ユニット１５によるプログラムの実行は肯定され（ステップＳ２１６）、プログラムが実行される（ステップＳ２１８）。
【００８３】
このような実行許可インストラクションの手続は、例えばマイクロコードＲＯＭ１４中で、上述のようなインストラクションの処理手続を記述することによって実現可能である。
【００８４】
ステップＳ２１０〜Ｓ２１６は、"Ｌｏａｄ ＭＭＵ …"という単一のインストラクションで実行される。該インストラクションを記述した疑似マイクロプログラム・コードを、以下に示しておく。
【００８５】
【数３】

【００８６】
このようなマイクロプログラムに従った認証手続は、外部プログラムからは全く見えない状態で実行される。本実施例に係る認証手続は、プロセッサ・チップ１００内部で完結されるので、プロセッサ１００外部からの監視は殆ど不可能なのである。
【００８７】
第３の実施の形態
本発明の第３の実施例は、プロセッサ１００が持つプロセッサＩＤを用いず、これに代わって時々刻々発生する乱数を用いるとともに、セキュリティ・デバイス９５との協働的動作によってプログラム保護を行う点で、上述の第１及び第２の実施例とは相違する。
【００８８】
図５には、本発明の第３の実施の形態に係るコンピュータ・システム２００及びプロセッサ１００のハードウェア構成を模式的に示している。以下、各部について説明する。
【００８９】
プロセッサ１００の外部ピンに直結したプロセッサ・バス１０１は、ブリッジ回路６０経由でシステム・バス７０に接続されている。ブリッジ回路６０は、プロセッサ・バス１０１とシステム・バス７０間の動作速度の相違を吸収するためのデータ・バッファや、メイン・メモリ５０へのアクセス動作を制御するためのメモリ・コントローラを含んでいる。
【００９０】
メイン・メモリ５０は、プロセッサ１００が実行するプログラム・コードや処理データを一時格納するための読み書き可能メモリであり、通常は、１以上のＤＲＡＭ（ダイナミックＲＡＭ）チップで構成される。メイン・メモリ５０上で展開されるメモリ空間は、メモリ管理ユニット１５によって管理される。
【００９１】
システム・バス７０には、ＰＣＩ（Peripheral Component Interconnect）バスやＩＳＡ（Industry Standard Architecture）バスが該当し、各種周辺装置が相互接続されている。周辺装置には、例えばキーボードやディスプレイなどのコンソール類（図示しない）、ハード・ディスク・ドライブ（ＨＤＤ）８１、フレキシブル・ディスク・ドライブ（ＦＤＤ）８２、ＣＤ−ＲＯＭドライブ８３などの外部記憶装置類、外部ネットワークと接続するためのネットワーク・インターフェース・カード（ＮＩＣ）９０、シリアル・ポート経由でシリアル・データの入出力を行うためのシリアルＩ／Ｏコントローラ９１などが含まれる。なお、バス７０上の動作は、ロジック・アナライザなどを用いて解析することができる。
【００９２】
本実施例では、シリアル・ポートにはセキュリティ・デバイス９５が外部接続されている。セキュリティ・デバイス９５は、保護対象たるソフトウェア・プログラムに付随する性質を持ち、ソフトウェアＩＤを格納する他、共通鍵又は公開鍵いずれかの方式による暗号化ユニットを含んでいる。セキュリティ・デバイス９５の動作については後述する。
【００９３】
ソフトウェア供給業者は、通常、フレキシブル・ディスクやＣＤ−ＲＯＭなどの記憶媒体の形態でソフトウェア・プログラムを配布する。各ユーザは、これら記憶媒体を所定のドライブ・ユニットに装填し、ＨＤＤ８１にコピーすることによって、ソフトウェア・プログラムをシステムにインストールすなわち利用可能な状態に置くようになっている。また、最近では、インターネットなどの外部ネットワーク経由でソフトウェア・プログラムが配布されることも多くなっている。
【００９４】
プロセッサ１００は、当業界においてＣＰＵ（Central Processing Unit）若しくはＭＰＵ（Micro Processing Unit）と呼ばれるものである。プロセッサ１００は、通常はマザー・ボード（図示しない）上に搭載される回路チップであり、各入出力装置（図示しない）を制御してデータの授受を行ったり、データを演算処理し、処理結果をメイン・メモリ５０上に記憶したりするなどのコンピュータ・システム（図示しない）の中枢機能を果たしている。
【００９５】
図５に示すように、本実施形態に係るプロセッサ１００は、バス・インターフェース１１と、デコーダ１２と、制御ユニット１３と、マイクロコードＲＯＭ１４と、メモリ管理ユニット１５と、暗号化復号化ユニット１７と、乱数発生ユニット１８とを含んでいる。
【００９６】
バス・インターフェース１１は、プロセッサ１００外部のコンポーネントとの間でインストラクションやデータを授受するためのユニットである。バス・インターフェース１１は、プロセッサ・バス１７と直結している。なお、プロセッサ・バス１７は、ブリッジ回路６０を経由してメイン・メモリ５０やシステム・バス７０と相互接続されている。
【００９７】
デコーダ１２は、バス・インターフェースで受け取ったインストラクションを解釈して、制御ユニット１３が理解できる形式に変換するためのユニットである。
【００９８】
制御ユニット１３は、インストラクションを実行する手順を整えるユニットである。実行するインストラクションは、ワイヤード・ロジック（配線論理）で実行するタイプと、マイクロ・プログラムで実行するタイプの２つに大別される。前者の場合は、インストラクションの実行制御に必要な論理を直線的に実装した順序回路が用いられる。また、後者の場合には、インストラクションはマイクロコード（又はピココード）と呼ばれるさらに細かいコードの集合（すなわちマイクロプログラム）で構成されており、該当するマイクロプログラムをマイクロコードＲＯＭ１４から読み出して実行することになる。なお、１つのプロセッサで利用できるインストラクション全体を「インストラクション・セット」と呼ぶ。
【００９９】
マイクロコードＲＯＭ１４は、インストラクションの実行に必要なマイクロードを格納した読み出し専用メモリである。言い換えれば、マイクロコードＲＯＭ１４は、各インストラクションの実行手順を定義した不揮発メモリである。例えば、"ＬＯＡＤ"、"ＳＴＯＲＥ"、"ＭＯＶＥ"などのインストラクションは、ある変数をプロセッサ１００内のレジスタ（図示しない）に書き込むためのインストラクションであるが、これらの動作の詳細をマイクロコードＲＯＭ１４内で記述することによって定義することができる。
【０１００】
メモリ管理ユニット（ＭＭＵ）１５は、プログラム・コードやデータをメイン・メモリ上に展開するなど、プロセッサ１００のメモリ空間を管理するためのユニットである。メモリ管理ユニット１５は、通常、仮想記憶機能とメモリ保護機能という２つの機能を提供している。仮想記憶機能とは、論理アドレスを物理アドレスに変換したり、物理アドレスに該当するブロック（ページ）がメイン・メモリ上に存在しないときに外部記憶装置との間でブロック（ページ）の入れ替え（すなわち「スワッピング」）を行う機能のことである。また、メモリ保護機能とは、１つのプログラムで生じた障害が他のプログラムに影響を及ぼさないようにする機能のことである。
【０１０１】
また、メモリ管理ユニット１５は、メモリ空間上に存在する各プログラムのアドレス情報や属性情報を管理するためのＭＭＵテーブルを備えている。ＭＭＵテーブルの構造や機能は図２を参照した上記説明と略同一なので、ここでは説明を省略する。
【０１０２】
あるプログラムをプロセッサ１００に実行させるためには、メモリ管理ユニット１５にプログラムＩＤとそのアドレス情報・属性情報を与える旨のプログラム・コードを制御ユニット１３に供給すればよい。一般には、"Ｌｏａｄ ＭＭＵ…"なるインストラクションによって、実質上、アプリケーションの実行が許可される。
【０１０３】
本実施例では、この"Ｌｏａｄ ＭＭＵ …"インストラクションは、マイクロプログラムという形態で実装され、メモリ管理ユニット１５への各変数セットの他に、所定の認証手続が含まれている。この認証手続は、マイクロプログラム中で記述されているので、プロセッサ１００の外部からは認証手続の存在自体が見えない。認証手続は、プロセッサ・チップ１００内部で完結的に実行されるので、この動作を外部から監視することは殆ど不可能である。したがって、"Ｌｏａｄ ＭＭＵ …"インストラクションを発行した外部プログラムからは全く見えない状態で、プロセッサ１００はこの認証手続を実行することができる。但し、認証手続の詳細は後述する。
【０１０４】
暗号化復号化ユニット１７は、所定のデータを暗号化したり、逆に暗号化されたデータを復号化するための演算ユニットである。例えば、プロセッサ１００が外部に出力する乱数のように秘匿性のあるデータは、暗号化復号化ユニット１７によって予め暗号化してから、バス・インターフェース１１経由でプロセッサ１００の外部に出力される。逆に、暗号化されたデータ（例えばソフトウェア供給者から渡されるＫｅｙ：後述）の復号化も行う。
【０１０５】
暗号化及び復号化の方式は、共通鍵、公開鍵のうちいずれの方式を採用してもよい。後者の公開鍵方式は、公開鍵と秘密鍵という一組の暗号鍵が用いられ、一方の鍵で暗号化したときには他方の鍵でしか復号化できない。例えば、第３者が公開鍵で暗号化したデータは秘密鍵を持つ本人しか復号化できないので、秘密情報を安全に送付することができる（周知）。
【０１０６】
乱数発生ユニット１８は、時々刻々乱数を発生するためのユニットであり、本実施例ではプロセッサＩＤの代わりに用いられる。乱数を用いるのは、固定値を用いたのでは、認証手続を複数回重ねて動作を監視することで見破られてしまう虞があるからである。
【０１０７】
なお、プロセッサ１００を構成するためには、図５に示した以外にも多くのユニット等が必要である。図５から省略されたユニットの例は、整数同士の算術演算と論理演算（ＡＮＤ，ＯＲ，ＮＯＴ）を担当するＡＬＵ（Arithmetic and Logic Unit）や、実数（浮動小数点等）演算を担当するＦＰＵ（Floating-Point Unit）、インストラクションの実行手順を直線的に実装した配線論理回路（ＰＬＡ：Programmable Logic Array）、入出力用のレジスタなどである。但し、これらは当業者には周知であり、また、本発明の要旨を構成するものではないので、本明細書中では省略している。また、図面の錯綜を回避するため、図中の各ハードウェア・ブロック間の接続も一部しか図示していない点を了承されたい。
【０１０８】
次いで、プロセッサ１００によるプログラム保護動作について、図６を参照しながら説明する。
【０１０９】
ソフトウェア供給業者は、保護対象たるソフトウェア・プログラムをフレキシブル・ディスク又はＣＤ−ＲＯＭなどの記憶媒体に格納した形態で、市場に流通する。このソフトウェア・プログラムには、固有の識別情報すなわちソフトウェアＩＤ（通常はシリアルな番号で構成される）が付されている。ユーザは、フレキシブル・ディスク又はＣＤ−ＲＯＭなどの記憶媒体をソフトウェア供給業者から購入するという形態で、ソフトウェア・プログラムの限定的な使用権を取得する（記憶媒体の購入は、ソフトウェァの著作権や無制限な使用権を全く意味しない点に充分留意されたい）。
【０１１０】
本実施例が、上記第１及び第２の実施例と相違するのは、ソフトウェア・プログラムを格納した記憶媒体と一緒にセキュリティ・デバイス９５が配布される点である。ユーザは、ソフトウェア・プログラムをハード・ディスク８１上にインストールするともに、セキュリティ・デバイス９５をシリアル・ポートに外部接続する（ステップＳ３００）。この実施例では、Ｋｅｙの要求は、ソフトウェア供給業者ではなくセキュリティ・デバイス９５に対して行われる（後述）。
【０１１１】
コンピュータ・システム２００上でソフトウェア・プログラムの実行が促されたとする。これは、例えばＯＳ（オペレーティング・システム）のような外部プログラムが"ＬＯＡＤ ＭＭＵ…"のような実行許可インストラクションを発行して、メモリ管理ユニット１５にプログラムＩＤとプログラムの格納番地／属性情報がセットすることにより、実現される。
【０１１２】
本実施例の実行許可インストラクションに該当する処理手続は、図６の破線ブロックで囲まれている。実行許可は、メモリ管理ユニット１５への各変数のセット以外に所定の認証手続を含んでいる。
【０１１３】
当該インストラクションが発行されると、プロセッサ１００は、まず、乱数発生ユニット１８が発生した乱数をセキュリティ・デバイス９５に送ることで、Ｋｅｙの要求を行う（ステップＳ３０２）。乱数の送付はシステム・バス７０経由で行われる。但し、乱数は時々刻々変化する性質を持ち、同じ乱数は一回しか使用しないので、バス７０の動作をスヌープされてセキュリティが破られる可能性は極めて低い。
【０１１４】
セキュリティ・デバイス９５は、受け取った乱数と、自身が格納するソフトウェアＩＤとを一体化して、共通鍵を用いて暗号化してＫｅｙを生成し、システム・バス７０経由でプロセッサ１００に送り返す（ステップＳ３０４）。
【０１１５】
プロセッサ１００は、共通鍵を用いてＫｅｙを復号化して、乱数とソフトウェアＩＤとに分解する（ステップＳ３０６）。復号化処理は、暗号化復号化ユニット１７を用いて行われる。
【０１１６】
次いで、プロセッサ１００は、復号化して得られた乱数とソフトウェアＩＤを、プロセッサ１００自身が保持する元の乱数、及び装填した記憶媒体から得られたソフトウェアＩＤの各々と比較する（ステップＳ３０８）。
【０１１７】
この比較の結果、照合に失敗したならば、メモリ管理ユニット１５によるプログラムの実行は拒否される（ステップＳ３１０）。他方、照合が成功裡に終わったならば、メモリ管理ユニット１５によるプログラムの実行は肯定され（ステップＳ３１２）、プログラムが実行される（ステップＳ３１４）。
【０１１８】
このような実行許可インストラクションの手続は、例えばマイクロコードＲＯＭ１４中で、上述のようなインストラクションの処理手続を記述することによって実現可能である。
【０１１９】
ステップＳ３０２〜Ｓ３１２は、"Ｌｏａｄ ＭＭＵ …"という単一のインストラクションで実行される。該インストラクションを記述した疑似マイクロプログラム・コードを、以下に示しておく。
【０１２０】
【数４】

【０１２１】
このようなマイクロプログラムに従った認証手続は、外部プログラムからは全く見えない状態で実行される。本実施例に係る認証手続は、プロセッサ・チップ１００内部で完結されるので、プロセッサ１００外部からの監視は殆ど不可能なのである。
【０１２２】
第４の実施の形態
本発明の第４の実施例は、図５に示したものと等価なハードウェア構成により具現される。但し、第３の実施例との相違点は、共通鍵ではなく公開鍵方式で暗号化する点にある。図７には、第４の実施例に係るプログラム保護動作をフローチャートにして示している。以下、図７を参照しながら説明する。
【０１２３】
ソフトウェア供給業者は、保護対象たるソフトウェア・プログラムをフレキシブル・ディスク又はＣＤ−ＲＯＭなどの記憶媒体に格納した形態で、市場に流通する。このソフトウェア・プログラムには、固有の識別情報すなわちソフトウェアＩＤ（通常はシリアルな番号で構成される）が付されている。ユーザは、フレキシブル・ディスク又はＣＤ−ＲＯＭなどの記憶媒体をソフトウェア供給業者から購入するという形態で、ソフトウェア・プログラムの限定的な使用権を取得する（記憶媒体の購入は、ソフトウェァの著作権や無制限な使用権を全く意味しない点に充分留意されたい）。
【０１２４】
本実施例では、ソフトウェア・プログラムを格納した記憶媒体と一緒にセキュリティ・デバイス９５に配布される。ユーザは、ソフトウェア・プログラムをハード・ディスク８１上にインストールするともに、セキュリティ・デバイス９５をシリアル・ポートに外部接続する（ステップＳ４００）。Ｋｅｙの要求は、ソフトウェア供給業者ではなくセキュリティ・デバイス９５に対して行われる（後述）。
【０１２５】
コンピュータ・システム２００上でソフトウェア・プログラムの実行が促されたとする。これは、例えばＯＳ（オペレーティング・システム）のような外部プログラムが"ＬＯＡＤ ＭＭＵ…"のような実行許可インストラクションを発行して、メモリ管理ユニット１５にプログラムＩＤとプログラムの格納番地／属性情報がセットすることにより、実現される。
【０１２６】
本実施例の実行許可インストラクションに該当する処理手続は、図７の破線ブロックで囲まれている。実行許可は、メモリ管理ユニット１５への各変数のセット以外に所定の認証手続を含んでいる。
【０１２７】
当該インストラクションが発行されると、プロセッサ１００は、まず、乱数発生ユニット１８が発生した乱数とプロセッサ１００の公開鍵をセキュリティ・デバイス９５に送ることで、Ｋｅｙの要求を行う（ステップＳ４０２）。乱数の送付はシステム・バス７０経由で行われる。但し、乱数は時々刻々変化する性質を持ち、同じ乱数は一回しか使用しないので、バス７０の動作をスヌープされてセキュリティが破られる可能性は極めて低い。
【０１２８】
セキュリティ・デバイス９５は、受け取った乱数と、自身が格納するソフトウェアＩＤとを一体化して、公開鍵を用いて暗号化してＫｅｙを生成し、システム・バス７０経由でプロセッサ１００に送り返す（ステップＳ４０４）。
【０１２９】
プロセッサ１００は、自身の秘密鍵を用いてＫｅｙを復号化して、乱数とソフトウェアＩＤとに分解する（ステップＳ４０６）。復号化処理は、暗号化復号化ユニット１７を用いて行われる。
【０１３０】
次いで、プロセッサ１００は、復号化して得られた乱数とソフトウェアＩＤを、プロセッサ１００自身が保持する元の乱数、及び装填した記憶媒体から得られたソフトウェアＩＤの各々と比較する（ステップＳ４０８）。
【０１３１】
この比較の結果、照合に失敗したならば、メモリ管理ユニット１５によるプログラムの実行は拒否される（ステップＳ４１０）。他方、照合が成功裡に終わったならば、メモリ管理ユニット１５によるプログラムの実行は肯定され（ステップＳ４１２）、プログラムが実行される（ステップＳ４１４）。
【０１３２】
このような実行許可インストラクションの手続は、例えばマイクロコードＲＯＭ１４中で、このようにインストラクションの処理手続を記述することによって実現可能である。
【０１３３】
ステップＳ４０２〜Ｓ４１２は、"Ｌｏａｄ ＭＭＵ …"という単一のインストラクションで実行される。該インストラクションを記述した疑似マイクロプログラム・コードを、以下に示しておく。
【０１３４】
【数５】

【０１３５】
このようなマイクロプログラムに従った認証手続は、外部プログラムからは全く見えない状態で実行される。本実施例に係る認証手続は、プロセッサ・チップ１００内部で完結されるので、プロセッサ１００外部からの監視は殆ど不可能なのである。
【０１３６】
追補
以上、特定の実施例を参照しながら、本発明について詳解してきた。しかしながら、本発明の要旨を逸脱しない範囲で当業者が該実施例の修正や代用を成し得ることは自明である。すなわち、例示という形態で本発明を開示してきたのであり、限定的に解釈されるべきではない。本発明の要旨を判断するためには、冒頭に記載した特許請求の範囲の欄を参酌すべきである。
【０１３７】
【発明の効果】
以上詳記したように、本発明によれば、コンピュータ・システムに提供されるソフトウェア・プログラムの不正な使用・実行を防止する優れた技術を提供することができる。
【０１３８】
また、本発明によれば、プログラムの不正実行防止機能を備えた優れたプロセッサ、プログラムの不正実行を防止するためにプロセッサが実行するインストラクション、及びプログラムの不正実行防止方法を提供することができる。
【０１３９】
また、本発明によれば、外部から監視・変更することができないプログラムの不正実行防止機能付き優れたプロセッサ、プロセッサが実行するインストラクション、及びプログラムの不正実行防止方法を提供することにある。
【０１４０】
また、本発明によれば、ソフトウェア供給者がソフトウェア・プログラムの使用権をただ１つのプロセッサにのみ許可することができる、優れたプログラムの不正実行防止方法を提供することができる。
【図面の簡単な説明】
【図１】図１は、本発明の第１の実施の形態に係るコンピュータ・システム及びプロセッサ１００のハードウェア構成を模式的に示した図である。
【図２】図２は、ＭＭＵテーブルの構造や機能を模式的に示した図である。
【図３】図３は、本発明の第１の実施の形態に係るプログラム保護動作を示したフローチャートである。
【図４】図４は、本発明の第２の実施の形態に係るプログラム保護動作を示したフローチャートである。
【図５】図５は、本発明の第３の実施の形態に係るコンピュータ・システム及びプロセッサ１００のハードウェア構成を模式的に示した図である。
【図６】図６は、本発明の第４の実施の形態に係るプログラム保護動作を示したフローチャートである。
【図７】図７は、本発明の第５の実施の形態に係るプログラム保護動作を示したフローチャートである。
【符号の説明】
１１…バス・インターフェース、１２…デコーダ、１３…制御ユニット、
１４…マイクロコードＲＯＭ、１５…メモリ管理ユニット（ＭＭＵ）、
１６…プロセッサＩＤ、１７…暗号化復号化ユニット、
５０…メイン・メモリ、６０…ブリッジ回路、７０…システム・バス、
８１…ハード・ディスク・ドライブ（ＨＤＤ）、
８２…フレキシブル・ディスク・ドライブ（ＦＤＤ）、
８３…ＣＤ−ＲＯＭドライブ、
９０…ネットワーク・インターフェース・カード（ＮＩＣ）、
９１…シリアルＩ／Ｏコントローラ、９５…セキュリティ・デバイス、
１００…プロセッサ、２００…コンピュータ・システム。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technique for preventing unauthorized use / execution of a software program provided to a computer system, and more particularly to a processor having a function for preventing unauthorized execution of a program.
[0002]
[Prior art]
Along with recent technological innovations, computer systems have become widespread not only in universities and research institutes but also in companies and general households. Computer systems include workstations, personal computers (PCs), etc. that are relatively inexpensive and can be purchased by general users, in addition to host / mainframe and office computers. In particular, the rapid spread of PCs is remarkable.
[0003]
Under such technological trends, various software running on a computer system has been developed and marketed, and the software industry has risen to rival or exceed the hardware industry. The software mentioned here includes an “OS (operating system)” for controlling the operation of the entire computer system, and an “application” for realizing functional operations suitable for the purpose and business of each user on the system. Is included. Application programs include various functions and applications such as word processors, spreadsheets, databases, and communications.
[0004]
Users generally purchase software that they want to install on their computer systems in the form of removable media such as flexible disks and CD-ROMs, and then use these media by loading them into appropriate drive units. Is. Recently, it has become possible to introduce a software program by transferring (downloading) desired software to its own local disk via an external network such as the Internet.
[0005]
However, the act of purchasing media storing software programs is only a limited use right of the software program, and the purchaser also obtained the copyright and the copy right of the software program. is not. Unrestricted or unauthorized copying of software programs is strictly prohibited by copyright law (well-known). (Note that it is reasonable to interpret the use of software programs downloaded via the network in a limited way.)
[0006]
From the standpoint of software vendors that provide software programs, the company earns profits by distributing program storage media for a fee, and is inherently enjoyed if unlimited and unauthorized copying acts are rampant. We cannot secure the profits we should have. Unauthorized use of software programs also diminishes the willingness to develop for those engaged in the software industry, which in turn may calm down the activities of the industry itself. For this reason, a protection technology for prohibiting (or preventing) unauthorized use or unauthorized copying of software programs has been developed.
[0007]
An example of protection is to encrypt a software program that is desired to prevent unauthorized use. In other words, software vendors distribute encrypted program storage media for a fee or free of charge, and give a key for decryption only to legitimate users, so that the program stored on the media can be stored. The use can be suitably limited.
[0008]
Here, the problem is how to provide the user with the key. For example, a software vendor can give a user a key by mail such as a letter, but in this case, unauthorized use of the key is very easy.
[0009]
Furthermore, as a technically advanced method, so-called “security device” can be used. In this case, the software vendor distributes and distributes the program storage medium with the security device attached. The security device includes identification information necessary for a predetermined authentication procedure, and is used by being connected to a serial port or a parallel port of a user's PC, for example. On the other hand, the programs stored on the media include some check points (ie, “authentication routines”) in addition to this routine for performing operations specific to the functions and uses of the program itself. Yes.
[0010]
An example of an authentication routine is that at each check point, a CPU (Central Processing Unit) that is executing a program accesses the security device to read identification information, and checks whether this matches the identification information of the program. Thus, the CPU is allowed to continue the program only when they match.
[0011]
Another example of the authentication routine is as follows. In other words, a code according to a certain rule is written into the security device by the CPU executing the program. The security device prepares identification information scrambled or encrypted using the received code. Furthermore, the CPU reads the scrambled or encrypted identification information, descrambles or decrypts it with the program, and collates it with the identification information owned by the program. Only when the verification is successful is the CPU allowed to continue the program. Since the CPU and the security device are connected via a bus outside the CPU chip, the authentication routine can be prevented from being decrypted by the bus snoop by performing scrambling and encryption.
[0012]
The two examples using these security devices are common in that authentication processing is performed by an instruction (instruction) to the CPU that is executing the program.
[0013]
By using a security device, the level of security could be improved considerably. Also, the right to use a software program could be limited to only one computer system with a security device attached. However, this method is not perfect. For example, if a logic analyzer (well-known) is used, bus transactions can be easily monitored, so that the authentication routine can be analyzed to find out the identity information and the identity of the encryption key.
[0014]
In order to further improve the security level, a measure is taken of sequentially changing the input value to the security device. However, ICE (InCircuitEmulator)^{/ * /}The software can be disassembled relatively easily using a device such as, and then the program can be altered to jump unconditionally to the access routine (ie, authentication routine) to the security device. is there.
[0015]
According to the inventor's consideration, in order to strengthen the protection of the software program, first of all, it is preferable to design the security operation to be indispensable for the program execution. In this sense, the above conventional example in which the program stored in the medium itself includes an authentication routine is suitable. Furthermore, this authentication routine must be in a form that cannot be accessed or changed from the outside. In the case of the above-described conventional example using a security device, the authentication routine is implemented in the form of system operation and does not appear in the appearance, but is technically readable (as described above). In short, it is hard to say that the protection of the program is perfect with the conventional protection method with external access.
[0016]
Annotation
The ICE is an apparatus that is usually used to support program and hardware development, and operates in exactly the same manner as the CPU by being inserted into a CPU socket instead of the CPU. Unlike the CPU, the ICE can read bus access and register values for each instruction. By using such an instruction trace function of ICE, an authentication routine can be found from a software program using an external device address as a trigger. Furthermore, if an illegal patch is applied to the program address, the program address can be tampered to continue without accessing the security device.
[0017]
[Problems to be solved by the invention]
An object of the present invention is to provide an excellent technique for preventing unauthorized use / execution of a software program provided to a computer system.
[0018]
It is a further object of the present invention to provide an excellent processor having a function for preventing illegal execution of programs, which cannot be monitored and changed from the outside.
[0019]
[Means for Solving the Problems]
The present invention has been made in consideration of the above-mentioned problems. The first aspect of the present invention incorporates a memory management unit having a function of managing a main memory and an instruction set for operating the memory. A processor with a function for preventing unauthorized execution of a program, wherein the instruction set includes an execution permission instruction that permits execution of a program code on the main memory, and the execution permission instruction is A processor with a function for preventing unauthorized execution of a program, including a predetermined authentication operation in addition to an operation for giving an identification number and address information / attribute information of a program to be executed to the memory management unit.
[0020]
Here, the predetermined authentication operation may include a comparison operation between identification information stored inside the processor and identification information supplied from outside the processor.
[0021]
The identification information used for authentication may be composed of a processor ID unique to the processor and a software ID unique to the software program.
[0022]
Alternatively, the identification information may be composed of a random number generated internally by the processor and a software ID unique to the software program.
[0023]
In addition, when the predetermined authentication operation is successfully completed, an operation of giving an identification number of the program to be executed and address information / attribute information to the memory management unit is permitted, but when the predetermined authentication operation fails, the operation is performed. The operation of giving the identification number of the program to be performed and the address information / attribute information to the memory management unit may be prohibited.
[0024]
The processor with an unauthorized execution preventing function according to the second aspect further includes an encryption means for encrypting the processor ID and outputting the encrypted processor ID to the outside via the bus interface, and the encrypted identification information via the bus interface. And decrypting means for retrieving the processor ID and the software ID from outside and decrypting the processor ID, and the predetermined authentication operation may include a comparison operation between the IDs.
[0025]
According to a second aspect of the present invention, there is provided a processor with a function for preventing unauthorized execution of a program, which executes a predetermined process while reading / writing a program code or data on a main memory. A bus interface that exchanges instructions and data with the outside of the processor, a decoder that decodes the received instructions, a built-in memory that stores procedures for one or more instructions, and a procedure for one or more instructions A logic circuit, a control unit that executes instructions according to a procedure stored in the built-in memory or a procedure implemented in the logic circuit, a processor ID unique to the processor, and a memory having a function of managing the main memory Including management unit One of the built-in memory and the logic circuit stores a procedure of an execution permission instruction that permits execution of a program code on the main memory, and the procedure of the execution permission instruction executes. A processor with a function for preventing unauthorized execution of a program, comprising: a predetermined authentication operation in addition to an operation for providing the memory management unit with identification information and address information / attribute information of a power program.
[0026]
The processor with an unauthorized execution preventing function according to the second aspect further includes an encryption means for encrypting the processor ID and outputting the encrypted processor ID to the outside via the bus interface, and the encrypted identification information via the bus interface. And decrypting means for retrieving the processor ID and the software ID from outside and decrypting the processor ID, and the predetermined authentication operation may include a comparison operation between the IDs.
[0027]
In addition, when the predetermined authentication operation is successfully completed, an operation of giving an identification number of the program to be executed and address information / attribute information to the memory management unit is permitted, but when the predetermined authentication operation fails, the operation is performed. The operation of giving the memory management unit the identification number of the program to be performed and the address information / attribute information may be prohibited.
[0028]
According to a third aspect of the present invention, there is provided a processor having a function for preventing unauthorized execution of a program, which executes a predetermined process while reading / writing a program code or data on a main memory. A bus interface that exchanges instructions and data with the outside of the processor, a decoder that decodes the received instructions, a built-in memory that stores procedures for one or more instructions, and a procedure for one or more instructions A logic circuit; a control unit that executes instructions according to a procedure stored in the built-in memory or a procedure implemented in the logic circuit; a random number generation unit; and a memory management unit having a function of managing the main memory. Including the internal memory or One of the logic circuits stores a procedure of an execution permission instruction for permitting execution of a program code on the main memory, and the procedure of the execution permission instruction is used to identify a program to be executed. A processor with a function for preventing unauthorized execution of a program, characterized by including a predetermined authentication operation in addition to an operation of giving information and address information / attribute information to the memory management unit.
[0029]
The processor with unauthorized execution prevention function according to the third aspect further includes random number output means for outputting a random number generated by the random number generation unit to the outside via the bus interface, and encrypted identification information as the bus The predetermined authentication operation may include a comparison operation between the random number and the software ID. The decryption unit receives the external value via the interface and decrypts the random number and the software ID.
[0030]
In addition, when the predetermined authentication operation is successfully completed, an operation of giving an identification number of the program to be executed and address information / attribute information to the memory management unit is permitted, but when the predetermined authentication operation fails, the operation is performed. The operation of giving the memory management unit the identification number of the program to be performed and the address information / attribute information may be prohibited.
[0031]
[Action]
The processor according to the present invention is of a type incorporating a memory management unit for managing code / data storage operations on the main memory, and as one of the instruction sets, a program program on the main memory. It includes an execution permission instruction that permits execution of code (application).
[0032]
This kind of execution permission instruction is generally described by a procedure (for example, "LOAD MMU ...") that sets the identification number of the program to be executed, the storage address of the program, and the attribute information of the program in the memory management unit. Included). Instruction procedures are defined by the microprogram.
[0033]
In the present invention, the execution permission instruction includes an authentication procedure for authenticating the right to use the program in addition to a procedure for setting predetermined data in the memory management unit. This authentication operation is performed, for example, by comparing the identification information held inside the processor with the identification information supplied from the outside of the processor (for example, the supplier of the software program). The execution of the software program is permitted only when the authentication process is successfully completed.
[0034]
The identification information used for the authentication procedure includes, for example, a processor ID unique to the processor (for example, given at the time of manufacture) and a software ID given to the software program. Alternatively, the identification information includes a random number that is generated from time to time by the processor and a software ID that is uniquely given to the software program.
[0035]
Since such an authentication operation is executed inside the processor, it is almost impossible to monitor and detect from the outside. In addition, since the authentication procedure is included in a microprogram that describes an instruction meaning permission to execute the program, the presence of the authentication procedure itself is hidden from the outside. Therefore, according to the present invention, prevention of unauthorized execution of a program can be greatly enhanced.
[0036]
Further, by using the processor ID inherent to the processor chip as the identification information used for the authentication process, the right to use a specific software program can be limited to a single processor. In this sense, it can be said that illegal execution of programs is strictly prohibited.
[0037]
Other objects, features, and advantages of the present invention will become apparent from a more detailed description based on embodiments of the present invention described later and the accompanying drawings.
[0038]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0039]
First embodiment
FIG. 1 schematically shows a hardware configuration of the computer system 200 and the processor 100 according to the first embodiment of the present invention. The computer system 200 includes a main memory 50 and various peripheral devices in addition to the processor 100 that performs core control of the system 200. Hereinafter, each part will be described.
[0040]
A processor bus 101 directly connected to an external pin of the processor 100 is connected to a system bus 70 via a bridge circuit 60. The bridge circuit 60 includes a data buffer for absorbing a difference in operation speed between the processor bus 101 and the system bus 70 and a memory controller for controlling an access operation to the main memory 50. .
[0041]
The main memory 50 is a readable / writable memory for temporarily storing program codes executed by the processor 100 and processing data, and is usually composed of one or more DRAM (dynamic RAM) chips. A memory space developed on the main memory 50 is managed by a memory management unit 15 (described later).
[0042]
The system bus 70 is a PCI (Peripheral Component Interconnect) bus or an ISA (Industry Standard Architecture) bus, and various peripheral devices are interconnected. Peripheral devices include, for example, consoles (not shown) such as a keyboard and a display, a hard disk drive (HDD) 81, a flexible disk drive (FDD) 82, a CD-ROM drive 83, and other external storage devices, A network interface card (NIC) 90 for connecting to an external network, a serial I / O controller 91 for inputting / outputting serial data via a serial port, and the like are included. The operation on the bus 70 can be analyzed using a logic analyzer or the like.
[0043]
Software suppliers usually distribute software programs to general users in the form of storage media such as flexible disks and CD-ROMs. Each user loads the storage medium into a predetermined drive unit and copies it to the HDD 81 to install the software program in the system 200, that is, to make it available for use. Recently, software programs are often distributed via an external network such as the Internet (well-known).
[0044]
The processor 100 is called CPU (Central Processing Unit) or MPU (Micro Processing Unit) in the industry. The processor 100 is a circuit chip that is usually mounted on a mother board (not shown), and controls each input / output device (not shown) to exchange data, perform arithmetic processing on data, and process results. Are stored in the main memory 50, and the central function of the computer system 200 is performed.
[0045]
As shown in FIG. 1, the processor 100 according to the present embodiment includes a bus interface 11, a decoder 12, a control unit 13, a microcode ROM 14, a memory management unit 15, a processor ID 16, and encryption / decryption. Unit 17 is included.
[0046]
The bus interface 11 is a unit for exchanging instructions and data with components outside the processor 100. The bus interface 11 is directly connected to the processor bus 101. The processor bus 101 is interconnected with the main memory 50 and the system bus 70 via the bridge circuit 60.
[0047]
The decoder 12 is a unit for interpreting instructions received via the bus interface 11 and converting the instructions into a format understandable by the control unit 13.
[0048]
The control unit 13 is a unit that prepares a procedure for executing instructions. Instructions to be executed are roughly classified into two types, that is, a type that is executed by wired logic and a type that is executed by a micro program. In the former case, a sequential circuit in which logic necessary for instruction execution control is linearly mounted is used. In the latter case, the instruction is composed of a finer set of codes (that is, microprograms) called microcode (or picocode), and the corresponding microprogram is read from the microcode ROM 14 and executed. . An entire instruction that can be used by one processor is referred to as an “instruction set”.
[0049]
The microcode ROM 14 is a read-only memory that stores microcode necessary for execution of instructions. In other words, the microcode ROM 14 is a non-volatile memory that defines the execution procedure of each instruction. For example, instructions such as “LOAD”, “STORE”, and “MOVE” are instructions for writing a variable to a register (not shown) in the processor 100. Details of these operations are stored in the microcode ROM 14. It can be defined by writing.
[0050]
The memory management unit (MMU) 15 is a unit for managing the memory space of the processor 100 such as developing program codes and data on the main memory 50. The memory management unit 15 normally provides two functions, a virtual storage function and a memory protection function. The virtual storage function means that a logical address is converted into a physical address, or when a block (page) corresponding to the physical address does not exist in the main memory, the block (page) is exchanged with the external storage device (that is, “Swapping”). The memory protection function is a function that prevents a failure that occurs in one program from affecting other programs.
[0051]
The memory management unit 15 includes an MMU table for managing address information and attribute information of each program existing in the memory space. FIG. 2 schematically illustrates the structure and function of the MMU table. Each entry in the MMU table includes fields for storing the address and flag of the corresponding program. The flag indicates program attribute information (for example, whether the program is in an execution format, read-only, or readable / writable).
[0052]
Each program on the memory space has a unique program ID. In order to cause the processor 100 to execute a certain program, a program code for giving the program ID and its address information / attribute information to the memory management unit 15 may be supplied to the control unit 13. The memory management unit 15 refers to its own MMU table and permits the execution of the corresponding program. The following expression describes pseudo code for permitting execution of a program.
[0053]
[Expression 1]
Mov R1, Program_ID
(Set the program ID in register R1)
Mov R2, Memory_Address_ & Flag
(Set the address and flag in register R2)
Load MMU, R1, R2
(Set the contents of registers R1 and R2 in the memory management unit)
Jmp Application
(Jump to the application)
[0054]
“Mov”, “Load”, and the like in the above code are instructions for the processor 100, which means setting a variable to a register. The detailed execution procedure of each instruction is defined in the form of either a wired program or a microprogram defined in the microcode ROM 14 (described above).
[0055]
The step “Load MMU...” In the pseudo code is an instruction for substantially permitting execution of the application. In this embodiment, the “Load MMU...” Instruction is implemented in the form of a microprogram, and includes a predetermined authentication procedure in addition to a variable set to the memory management unit 15.
[0056]
Since this authentication procedure is described in the microprogram, the existence of the authentication procedure itself cannot be seen from the outside of the processor 100. Since the authentication procedure is executed completely inside the processor chip 100, it is almost impossible to monitor this operation from the outside. Therefore, the processor 100 can execute this authentication procedure without being visible to the external program that issued the “Load MMU...” Instruction. However, details of the authentication procedure will be described later.
[0057]
The processor ID 16 is identification information unique to the processor 100 (usually composed of a serial number), and is uniquely assigned at the time of manufacture, for example. The entity of the processor ID 16 is numerical / character data written in a non-volatile memory (not shown), and is appropriately read out by the control unit 13.
[0058]
The encryption / decryption unit 17 is an arithmetic unit for encrypting predetermined data or conversely decrypting the encrypted data. For example, highly confidential data such as the processor ID 16 is encrypted in advance by the encryption / decryption unit 17 and then output to the outside of the processor 100 via the bus interface 11. On the contrary, the encrypted data (for example, Key delivered from the software supplier: described later) is also decrypted.
[0059]
Either the common key or the public key may be adopted as the encryption and decryption method. In the latter public key method, a pair of encryption keys, a public key and a secret key, is used. When encryption is performed with one key, decryption can be performed only with the other key. For example, since the data encrypted by the third party with the public key can be decrypted only by the person having the secret key, the secret information can be exchanged safely (well known).
[0060]
In order to configure the processor 100, many units other than those shown in FIG. 1 are required. Examples of units omitted from FIG. 1 include ALU (Arithmetic and Logic Unit) responsible for arithmetic and logical operations (AND, OR, NOT) between integers, and FPU (real number (floating point etc.)) responsible for arithmetic operations. Floating-Point Unit), a wiring logic circuit (PLA: Programmable Logic Array) in which instruction execution procedures are linearly mounted, and an input / output register. However, since these are well known to those skilled in the art and do not constitute the gist of the present invention, they are omitted in the present specification. Also, it should be noted that only a part of the connections between the hardware blocks in the figure is shown in order to avoid the confusion of the drawings.
[0061]
Next, the program protection operation by the processor 100 will be described with reference to FIG.
[0062]
A software supplier distributes the software program to be protected in the form of being stored in a storage medium such as a flexible disk or a CD-ROM. This software program is given unique identification information, that is, a software ID (usually composed of a serial number). The user obtains a limited use right of the software program in the form of purchasing a storage medium such as a flexible disk or a CD-ROM from a software supplier. Note that it does not imply any use rights at all). Then, the user loads a storage medium into a predetermined drive unit 81/82 and installs the software program on the hard disk 81 of the system 200.
[0063]
This installation operation includes a procedure for encrypting the processor ID 16 with a common key (step S100) and a procedure for sending the encrypted processor ID to the software supplier (step S102). The encryption process is performed using the encryption / decryption unit 17. The sending procedure means a Key (described later) request to the software supplier. Note that the sending procedure may be performed in a form of transmission via an external network connected by the NIC 90 in addition to the mail.
[0064]
The software supplier decrypts the received encryption information and obtains the original processor ID (step S104). Then, a key is generated by integrating the processor ID and the software ID managed by the trader himself and encrypting them with a common key (step S106). The key is obtained by simultaneously encrypting the processor ID and the software ID as one code and cannot be separated from each other. The key has a property as a key for solving the unusable state of the software, and is returned to the user by mail or via the network (step S108).
[0065]
Assume that execution of a software program is prompted on the computer system 200 in a state where the key is acquired. This is because, for example, an external program such as an OS (operating system) issues an execution permission instruction such as “LOAD MMU...”, And the program ID and the program storage address / attribute information are set in the memory management unit 15. This is realized.
[0066]
The processing procedure corresponding to the execution permission instruction of this embodiment is surrounded by a broken line block in FIG. The execution permission includes a predetermined authentication procedure in addition to the setting of each variable to the memory management unit 15.
[0067]
When the instruction is issued, the processor 100 first decrypts the received key and obtains a processor ID and a software ID (step S110). Decryption processing is performed using the encryption / decryption unit 17.
[0068]
Next, the processor 100 compares the processor ID and software ID obtained by decryption with each of the processor ID built in the processor 100 itself and the software ID obtained from the loaded storage medium (step S112).
[0069]
If the comparison fails as a result of the comparison, execution of the program by the memory management unit 15 is rejected (step S114). On the other hand, if the verification is successful, execution of the program by the memory management unit 15 is affirmed (step S116), and the program is executed (step S118).
[0070]
Such an execution permission instruction procedure can be realized by, for example, describing the instruction processing procedure as described above in the microcode ROM 14.
[0071]
Steps S110 to S116 are executed by a single instruction “Load MMU...”. The pseudo microprogram code describing the instructions is shown below.
[0072]
[Expression 2]

[0073]
The authentication procedure according to such a microprogram is executed in a state invisible to the external program. Since the authentication procedure according to the present embodiment is completed inside the processor chip 100, monitoring from outside the processor 100 is almost impossible.
[0074]
Second embodiment
The second embodiment of the present invention is implemented by a hardware configuration equivalent to that shown in FIG. However, the difference from the first embodiment is that encryption is performed using a public key method instead of a common key. FIG. 4 is a flowchart showing the program protection operation according to the second embodiment. Hereinafter, a description will be given with reference to FIG.
[0075]
The software supplier distributes the software program to be protected in the form of being stored in a storage medium such as a rewritable disc or a CD-ROM. This software program is given unique identification information, that is, a software ID (usually composed of a serial number). The user obtains a limited use right of the software program in the form of purchasing a storage medium such as a flexible disk or a CD-ROM from a software supplier. Note that it does not imply any use rights at all). Then, the user loads a storage medium into a predetermined drive unit 81/82 and installs the software program on the hard disk 81 of the system 200.
[0076]
This installation operation includes a procedure for encrypting the processor ID 16 (step S200) and a procedure for sending the encrypted processor ID and the public key built in the processor 100 to the software supplier (step S202). The encryption process is performed by the encryption / decryption unit 17 using the public key given by the software supplier. The sending procedure means a Key (described later) request to the software supplier. Note that the sending procedure may be performed in a form of transmission via an external network connected by the NIC 90 in addition to the mail.
[0077]
The software supplier obtains the original processor ID by decrypting the received encryption information using its own secret key (step S204). Then, the processor ID and the software ID managed by the supplier are integrated, and encrypted using the public key of the processor 100 again to generate a key (step S206). The key is obtained by simultaneously encrypting the processor ID and the software ID as one code and cannot be separated from each other. The key has a property as a key for solving the unusable state of the software, and is returned to the user by mail or via the network (step S208).
[0078]
Assume that execution of a software program is prompted on the computer system 200 in a state where the key is acquired. This is because, for example, an external program such as an OS (operating system) issues an execution permission instruction such as “LOAD MMU...”, And the program ID and the program storage address / attribute information are set in the memory management unit 15. This is realized.
[0079]
The processing procedure corresponding to the execution permission instruction of this embodiment is surrounded by a broken line block in FIG. The execution permission includes a predetermined authentication procedure in addition to the setting of each variable to the memory management unit 15.
[0080]
When the instruction is issued, the processor 100 decrypts the received key and obtains a processor ID and a software ID (step S210). The decryption process is performed by the encryption / decryption unit 17 using a secret key built in the processor 100 itself.
[0081]
Next, the processor 100 compares the processor ID and software ID obtained by decryption with each of the processor ID incorporated in the processor 100 itself and the software ID obtained from the loaded storage medium (step S212).
[0082]
If the comparison fails as a result of the comparison, execution of the program by the memory management unit 15 is rejected (step S214). On the other hand, if the verification is successful, execution of the program by the memory management unit 15 is affirmed (step S216), and the program is executed (step S218).
[0083]
Such an execution permission instruction procedure can be realized by, for example, describing the instruction processing procedure as described above in the microcode ROM 14.
[0084]
Steps S210 to S216 are executed by a single instruction “Load MMU...”. The pseudo microprogram code describing the instructions is shown below.
[0085]
[Equation 3]

[0086]
The authentication procedure according to such a microprogram is executed in a state invisible to the external program. Since the authentication procedure according to the present embodiment is completed inside the processor chip 100, monitoring from outside the processor 100 is almost impossible.
[0087]
Third embodiment
The third embodiment of the present invention does not use the processor ID of the processor 100, but instead uses a random number that is generated every moment, and protects the program by cooperative operation with the security device 95. This is different from the first and second embodiments described above.
[0088]
FIG. 5 schematically shows a hardware configuration of the computer system 200 and the processor 100 according to the third embodiment of the present invention. Hereinafter, each part will be described.
[0089]
A processor bus 101 directly connected to an external pin of the processor 100 is connected to a system bus 70 via a bridge circuit 60. The bridge circuit 60 includes a data buffer for absorbing a difference in operation speed between the processor bus 101 and the system bus 70 and a memory controller for controlling an access operation to the main memory 50. .
[0090]
The main memory 50 is a readable / writable memory for temporarily storing program codes executed by the processor 100 and processing data, and is usually composed of one or more DRAM (dynamic RAM) chips. The memory space developed on the main memory 50 is managed by the memory management unit 15.
[0091]
The system bus 70 is a PCI (Peripheral Component Interconnect) bus or an ISA (Industry Standard Architecture) bus, and various peripheral devices are interconnected. Peripheral devices include, for example, consoles (not shown) such as a keyboard and a display, a hard disk drive (HDD) 81, a flexible disk drive (FDD) 82, a CD-ROM drive 83, and other external storage devices, A network interface card (NIC) 90 for connecting to an external network, a serial I / O controller 91 for inputting / outputting serial data via a serial port, and the like are included. The operation on the bus 70 can be analyzed using a logic analyzer or the like.
[0092]
In this embodiment, a security device 95 is externally connected to the serial port. The security device 95 has a property attached to the software program to be protected, and stores a software ID, and includes an encryption unit using either a common key or a public key. The operation of the security device 95 will be described later.
[0093]
Software suppliers usually distribute software programs in the form of storage media such as flexible disks and CD-ROMs. Each user loads these storage media into a predetermined drive unit and copies them to the HDD 81, so that the software program is installed in the system, that is, can be used. Recently, software programs are often distributed via an external network such as the Internet.
[0094]
The processor 100 is called CPU (Central Processing Unit) or MPU (Micro Processing Unit) in the industry. The processor 100 is a circuit chip that is usually mounted on a mother board (not shown), and controls each input / output device (not shown) to exchange data, perform arithmetic processing on data, and process results. Is stored in the main memory 50 and performs a central function of a computer system (not shown).
[0095]
As shown in FIG. 5, the processor 100 according to the present embodiment includes a bus interface 11, a decoder 12, a control unit 13, a microcode ROM 14, a memory management unit 15, an encryption / decryption unit 17, And a random number generation unit 18.
[0096]
The bus interface 11 is a unit for exchanging instructions and data with components outside the processor 100. The bus interface 11 is directly connected to the processor bus 17. The processor bus 17 is interconnected with the main memory 50 and the system bus 70 via the bridge circuit 60.
[0097]
The decoder 12 is a unit for interpreting the instruction received by the bus interface and converting it into a format understandable by the control unit 13.
[0098]
The control unit 13 is a unit that prepares a procedure for executing instructions. Instructions to be executed are roughly classified into two types, that is, a type that is executed by wired logic and a type that is executed by a micro program. In the former case, a sequential circuit in which logic necessary for instruction execution control is linearly mounted is used. In the latter case, the instruction is composed of a finer set of codes (that is, microprograms) called microcode (or picocode), and the corresponding microprogram is read from the microcode ROM 14 and executed. . An entire instruction that can be used by one processor is referred to as an “instruction set”.
[0099]
The microcode ROM 14 is a read-only memory that stores microcode necessary for execution of instructions. In other words, the microcode ROM 14 is a non-volatile memory that defines the execution procedure of each instruction. For example, instructions such as “LOAD”, “STORE”, and “MOVE” are instructions for writing a variable to a register (not shown) in the processor 100. Details of these operations are stored in the microcode ROM 14. It can be defined by writing.
[0100]
The memory management unit (MMU) 15 is a unit for managing the memory space of the processor 100 such as developing program codes and data on the main memory. The memory management unit 15 normally provides two functions, a virtual storage function and a memory protection function. The virtual storage function means that a logical address is converted into a physical address, or when a block (page) corresponding to the physical address does not exist in the main memory, the block (page) is exchanged with the external storage device (that is, “Swapping”). The memory protection function is a function that prevents a failure that occurs in one program from affecting other programs.
[0101]
The memory management unit 15 includes an MMU table for managing address information and attribute information of each program existing in the memory space. The structure and function of the MMU table are substantially the same as those described above with reference to FIG.
[0102]
In order to cause the processor 100 to execute a certain program, a program code for giving the program ID and its address information / attribute information to the memory management unit 15 may be supplied to the control unit 13. In general, execution of an application is substantially permitted by the instruction “Load MMU...”.
[0103]
In this embodiment, this “Load MMU...” Instruction is implemented in the form of a microprogram, and includes a predetermined authentication procedure in addition to each variable set to the memory management unit 15. Since this authentication procedure is described in the microprogram, the existence of the authentication procedure itself cannot be seen from the outside of the processor 100. Since the authentication procedure is executed completely inside the processor chip 100, it is almost impossible to monitor this operation from the outside. Therefore, the processor 100 can execute this authentication procedure without being visible to the external program that issued the “Load MMU...” Instruction. However, details of the authentication procedure will be described later.
[0104]
The encryption / decryption unit 17 is an arithmetic unit for encrypting predetermined data or conversely decrypting the encrypted data. For example, confidential data such as random numbers output to the outside by the processor 100 is encrypted in advance by the encryption / decryption unit 17 and then output to the outside of the processor 100 via the bus interface 11. On the contrary, the encrypted data (for example, Key delivered from the software supplier: described later) is also decrypted.
[0105]
Either the common key or the public key may be adopted as the encryption and decryption method. In the latter public key method, a pair of encryption keys, a public key and a secret key, is used. When encryption is performed with one key, decryption can be performed only with the other key. For example, since the data encrypted by the third party with the public key can be decrypted only by the person having the secret key, the secret information can be sent safely (well known).
[0106]
The random number generation unit 18 is a unit for generating random numbers every moment, and is used in place of the processor ID in this embodiment. The reason for using a random number is that if a fixed value is used, it may be overlooked by monitoring the operation by overlapping the authentication procedure a plurality of times.
[0107]
In order to configure the processor 100, many units other than those shown in FIG. 5 are required. Examples of units omitted from FIG. 5 are ALU (Arithmetic and Logic Unit) responsible for arithmetic and logical operations (AND, OR, NOT) between integers, and FPU (real number (floating point etc.)) responsible for arithmetic operations. Floating-Point Unit), a wiring logic circuit (PLA: Programmable Logic Array) in which instruction execution procedures are linearly mounted, and an input / output register. However, since these are well known to those skilled in the art and do not constitute the gist of the present invention, they are omitted in the present specification. Also, it should be noted that only a part of the connections between the hardware blocks in the figure is shown in order to avoid the confusion of the drawings.
[0108]
Next, the program protection operation by the processor 100 will be described with reference to FIG.
[0109]
A software supplier distributes the software program to be protected in the form of being stored in a storage medium such as a flexible disk or a CD-ROM. This software program is given unique identification information, that is, a software ID (usually composed of a serial number). The user obtains a limited use right of the software program in the form of purchasing a storage medium such as a flexible disk or a CD-ROM from a software supplier. Note that it does not imply any use rights at all).
[0110]
This embodiment is different from the first and second embodiments in that the security device 95 is distributed together with a storage medium storing a software program. The user installs the software program on the hard disk 81 and connects the security device 95 externally to the serial port (step S300). In this embodiment, Key's request is made to the security device 95 rather than the software supplier (described below).
[0111]
Assume that execution of a software program is prompted on the computer system 200. This is because, for example, an external program such as an OS (operating system) issues an execution permission instruction such as “LOAD MMU...”, And the program ID and the program storage address / attribute information are set in the memory management unit 15. This is realized.
[0112]
The processing procedure corresponding to the execution permission instruction of the present embodiment is surrounded by a broken line block in FIG. The execution permission includes a predetermined authentication procedure in addition to the setting of each variable to the memory management unit 15.
[0113]
When the instruction is issued, the processor 100 first makes a Key request by sending the random number generated by the random number generation unit 18 to the security device 95 (step S302). The random number is sent via the system bus 70. However, random numbers have the property of changing from moment to moment, and the same random numbers are used only once. Therefore, the possibility that the security of the bus 70 is snooped and the security is broken is extremely low.
[0114]
The security device 95 integrates the received random number and the software ID stored in itself, generates a key by encrypting it using a common key, and sends it back to the processor 100 via the system bus 70 (step S304). .
[0115]
The processor 100 decrypts the key using the common key and decomposes it into a random number and a software ID (step S306). Decryption processing is performed using the encryption / decryption unit 17.
[0116]
Next, the processor 100 compares the decrypted random number and the software ID with the original random number held by the processor 100 itself and the software ID obtained from the loaded storage medium (step S308).
[0117]
If the comparison fails as a result of the comparison, execution of the program by the memory management unit 15 is rejected (step S310). On the other hand, if the verification is successful, execution of the program by the memory management unit 15 is affirmed (step S312), and the program is executed (step S314).
[0118]
Such an execution permission instruction procedure can be realized by, for example, describing the instruction processing procedure as described above in the microcode ROM 14.
[0119]
Steps S302 to S312 are executed by a single instruction "Load MMU ...". The pseudo microprogram code describing the instructions is shown below.
[0120]
[Expression 4]

[0121]
The authentication procedure according to such a microprogram is executed in a state invisible to the external program. Since the authentication procedure according to the present embodiment is completed inside the processor chip 100, monitoring from outside the processor 100 is almost impossible.
[0122]
Fourth embodiment
The fourth embodiment of the present invention is implemented by a hardware configuration equivalent to that shown in FIG. However, the difference from the third embodiment is that encryption is performed using a public key method instead of a common key. FIG. 7 is a flowchart showing the program protection operation according to the fourth embodiment. Hereinafter, a description will be given with reference to FIG.
[0123]
A software supplier distributes the software program to be protected in the form of being stored in a storage medium such as a flexible disk or a CD-ROM. This software program is given unique identification information, that is, a software ID (usually composed of a serial number). The user obtains a limited use right of the software program in the form of purchasing a storage medium such as a flexible disk or a CD-ROM from a software supplier. Note that it does not imply any use rights at all).
[0124]
In this embodiment, it is distributed to the security device 95 together with the storage medium storing the software program. The user installs the software program on the hard disk 81 and connects the security device 95 externally to the serial port (step S400). The Key request is made to the security device 95, not the software supplier (described later).
[0125]
Assume that execution of a software program is prompted on the computer system 200. This is because, for example, an external program such as an OS (operating system) issues an execution permission instruction such as “LOAD MMU...”, And the program ID and the program storage address / attribute information are set in the memory management unit 15. This is realized.
[0126]
The processing procedure corresponding to the execution permission instruction of this embodiment is surrounded by a broken line block in FIG. The execution permission includes a predetermined authentication procedure in addition to the setting of each variable to the memory management unit 15.
[0127]
When the instruction is issued, the processor 100 first sends a key request by sending the random number generated by the random number generation unit 18 and the public key of the processor 100 to the security device 95 (step S402). The random number is sent via the system bus 70. However, random numbers have the property of changing from moment to moment, and the same random numbers are used only once. Therefore, the possibility that the security of the bus 70 is snooped and the security is broken is extremely low.
[0128]
The security device 95 integrates the received random number and the software ID stored in the security device 95, encrypts it using the public key, generates a key, and sends it back to the processor 100 via the system bus 70 (step S404). .
[0129]
The processor 100 decrypts the key using its own secret key and decomposes it into a random number and a software ID (step S406). Decryption processing is performed using the encryption / decryption unit 17.
[0130]
Next, the processor 100 compares the decrypted random number and the software ID with the original random number held by the processor 100 itself and the software ID obtained from the loaded storage medium (step S408).
[0131]
If the comparison fails as a result of the comparison, execution of the program by the memory management unit 15 is rejected (step S410). On the other hand, if the verification is successful, the execution of the program by the memory management unit 15 is affirmed (step S412), and the program is executed (step S414).
[0132]
Such an execution-permitted instruction procedure can be realized, for example, by describing the instruction processing procedure in the microcode ROM 14.
[0133]
Steps S402 to S412 are executed by a single instruction "Load MMU ...". The pseudo microprogram code describing the instructions is shown below.
[0134]
[Equation 5]

[0135]
The authentication procedure according to such a microprogram is executed in a state invisible to the external program. Since the authentication procedure according to the present embodiment is completed inside the processor chip 100, monitoring from outside the processor 100 is almost impossible.
[0136]
Supplement
The present invention has been described in detail above with reference to specific embodiments. However, it is obvious that those skilled in the art can make modifications and substitutions of the embodiments without departing from the gist of the present invention. In other words, the present invention has been disclosed in the form of exemplification, and should not be interpreted in a limited manner. In order to determine the gist of the present invention, the claims section described at the beginning should be considered.
[0137]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to provide an excellent technique for preventing unauthorized use / execution of a software program provided to a computer system.
[0138]
Further, according to the present invention, it is possible to provide an excellent processor having a function for preventing unauthorized execution of a program, instructions executed by the processor to prevent unauthorized execution of a program, and a method for preventing unauthorized execution of a program.
[0139]
Another object of the present invention is to provide an excellent processor with a function for preventing unauthorized execution of a program that cannot be monitored or changed from the outside, an instruction executed by the processor, and a method for preventing unauthorized execution of a program.
[0140]
Further, according to the present invention, it is possible to provide an excellent method for preventing illegal execution of a program, in which a software supplier can grant the right to use a software program to only one processor.
[Brief description of the drawings]
FIG. 1 is a diagram schematically showing a hardware configuration of a computer system and a processor 100 according to a first embodiment of the present invention.
FIG. 2 is a diagram schematically showing the structure and function of an MMU table.
FIG. 3 is a flowchart showing a program protection operation according to the first embodiment of the present invention.
FIG. 4 is a flowchart showing a program protection operation according to a second embodiment of the present invention.
FIG. 5 is a diagram schematically illustrating a hardware configuration of a computer system and a processor 100 according to a third embodiment of the present invention.
FIG. 6 is a flowchart showing a program protection operation according to a fourth embodiment of the present invention.
FIG. 7 is a flowchart showing a program protection operation according to a fifth embodiment of the present invention.
[Explanation of symbols]
11 ... Bus interface, 12 ... Decoder, 13 ... Control unit,
14 ... Microcode ROM, 15 ... Memory management unit (MMU),
16 ... processor ID, 17 ... encryption / decryption unit,
50 ... Main memory, 60 ... Bridge circuit, 70 ... System bus,
81 ... a hard disk drive (HDD),
82 ... Flexible disk drive (FDD),
83 ... CD-ROM drive,
90 ... Network interface card (NIC),
91 ... Serial I / O controller, 95 ... Security device,
100: processor, 200: computer system.

Claims (4)

A processor with a function for preventing unauthorized execution of a program, having a built-in memory management unit having a function of managing a main memory and having an instruction set for operating itself,
The instruction set includes instructions that allow execution of program code on the main memory;
The execution of the program code includes a predetermined authentication operation in the processor, in addition to the operation of giving the software ID and address information / attribute information of the software program to be executed to the memory management unit,
The predetermined authentication operation is performed by comparing the processor ID unique to the processor stored in the processor with the processor ID of the encrypted data from the software supplier, and stored in the processor and external to the processor. Including a comparison between the software ID unique to the software program supplied from the software ID and the software ID of the encrypted data from the software supplier, whereby the predetermined authentication operation is completely invisible to the external program The processor, wherein the processor is executed in a state. It said processor encrypts a unique processor ID the processor, further comprising means for providing a processor ID, which is dark Goka the software provider, processor according to claim 1. Further comprising means for receiving the encrypted data including a processor ID and software ID from the software provider, processor according to any of claims 1-2. Encrypting the processor-specific processor ID, and further includes an encryption decrypting unit for decrypting the encrypted data from the software provider, processor according to any one of claims 1 to 3 .

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