JP4015510B2 - Interlayer insulating film for multilayer wiring of semiconductor integrated circuit and manufacturing method thereof - Google Patents

Interlayer insulating film for multilayer wiring of semiconductor integrated circuit and manufacturing method thereof Download PDF

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JP4015510B2
JP4015510B2 JP2002262304A JP2002262304A JP4015510B2 JP 4015510 B2 JP4015510 B2 JP 4015510B2 JP 2002262304 A JP2002262304 A JP 2002262304A JP 2002262304 A JP2002262304 A JP 2002262304A JP 4015510 B2 JP4015510 B2 JP 4015510B2
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insulating film
silicon
gas
multilayer wiring
interlayer insulating
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JP2004103752A (en
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直人 辻
文紀 尾崎
聡 高橋
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日本エー・エス・エム株式会社
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Priority to US10/657,416 priority patent/US7098129B2/en
Priority to EP03020250A priority patent/EP1396884A3/en
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    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
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    • H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
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    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
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    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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    • H01L21/7684—Smoothing; Planarisation

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体集積回路の多層配線用層間絶縁膜及びその製造方法に関し、特に、Cu多層配線に使用するためのポリッシングストッパ膜及びその製造方法に関する。
【０００２】
【従来技術】
半導体集積回路は、これまで高速化及び高機能化を目指し、微細化が進んできた。従来、半導体集積回路の多層配線材料としてAlが使用されてきたが、配線が微細かつ長距離になるにつれ、電流密度の増大で発生するエレクトロマイグレーションによる断線事故及びAlの抵抗率及び絶縁膜の誘電率に起因する信号遅延といった点が問題になってきた。
【０００３】
次世代の多層配線材料として注目されているのがCuである。Cuは断線事故に対して強く、抵抗もAlに比べて小さい。1997年に、IBMとMotorolaによって、デュアルダマシン(Dual-Damascene)と呼ばれる技術が開発された。従来は、Al膜をエッチングで凸状に加工して配線を形成し、その後層間を絶縁膜で埋め込んでいた。これに対してダマシン配線技術は、平坦な層間絶縁膜に配線パターンの溝をエッチングで形成し、全面にCu薄膜を堆積させた後、化学機械研磨（CMP）によって研磨し、溝部分にのみCuを残して配線とするものである（例えば、非特許文献１参照）。
【０００４】
【非特許文献１】
「次世代ULSIプロセス技術」株式会社リアライズ社、平成１２年２月２９日、ｐ.558−565
【０００５】
このダマシン配線技術では、低誘電率絶縁膜の適用が必須である。低誘電率絶縁膜として、スピンコート法による無機SOG膜、材料ガスとしてCxFyHzを用いたプラズマCVD法によるa-C:F膜、材料ガスとしてシリコン系炭化水素を用いたプラズマCVD法によるSixCyOz膜等が知られている。
【０００６】
【発明が解決しようとする課題】
ダマシン配線技術のCMP工程では、研磨布と研磨液（スラリー）を用いて研磨を行うが、絶縁膜の機械的強度が低いとCu配線部分より絶縁膜部分が凹んでしまうディッシングと呼ばれる問題が生じる。これは、研磨レートの異なる材料が同一研磨面内に混在する（例えば、金属配線及び層間絶縁膜）場合、研磨布が変形可能であることから、研磨レートの大きな材料が余計に研磨されるために発生する現象である。ダマシン配線技術で最も有望な低誘電率膜であるSixCyOz膜は、膜中に-CHx結合を多く含み多孔質であるため機械的強度が低く、ディッシングの問題が生じる。
【０００７】
ディッシングの問題を解決するために後処理用の装置を用意すると、装置スペース及びコストの面で問題となるばかりか、装置間の移動の際に生じるパーティクル汚染も問題となる。
【０００８】
したがって、本発明の目的は、ダマシン配線技術のCMP工程でディッシングが生じないような層間絶縁膜を製造する方法を与えることである。
【０００９】
本発明の他の目的は、別の装置を一切必要としない低コストの層間絶縁膜を製造する方法を与えることである。
【００１０】
【課題を解決するための手段】
上記課題を解決するために、本発明に係る層間絶縁膜を製造する方法は以下の工程から成る。
【００１１】
半導体集積回路の多層配線用層間絶縁膜の製造方法は、
シリコン系炭化水素を材料ガスとして用いてプラズマCVD法により、第１の絶縁膜を形成する工程と、
第１の絶縁膜を形成した後、in-situで連続的にシリコン系炭化水素ガス及び酸化性ガスを材料ガスとして用いてプラズマCVD法により、第１の絶縁膜上に第２の絶縁膜を形成する工程と、
から成る。
【００１２】
好適には、酸化性ガスの流量はシリコン系炭化水素ガスの流量の１.２〜１００倍である。
【００１３】
本発明で使用するシリコン系炭化水素は、一般式SiαOα -1(R)2 α - β +2(OCnH2n+1)で表され、
ここで、α＝１〜３の整数、β＝０〜２の整数、ｎ＝１〜３の整数及びR＝Siに結合されたC1-6炭化水素である。
【００１４】
具体的には、シリコン系炭化水素は、ジメチル・ジメトキシシランを含む。
【００１５】
また具体的には、酸化性ガスは、酸素、亜酸化窒素、オゾン、過酸化酸素、二酸化炭素、アルコール類の少なくとも１つから成る。
【００１６】
一方、半導体集積回路の多層配線用層間絶縁膜は、
シリコン系炭化水素を材料ガスとして用いてプラズマCVD法により形成された、第１の絶縁膜と、
第１の絶縁膜を形成した後、in-situで連続的にシリコン系炭化水素ガス及び酸化性ガスを材料ガスとして用いてプラズマCVD法により、第１の絶縁膜上に形成された第２の絶縁膜と、
から成る。
【００１７】
【発明の実施の態様】
以下、図面を参照しながら本願発明を詳細に説明する。図１は、本発明に係る半導体集積回路の多層配線用層間絶縁膜の製造方法に使用するプラズマCVD装置の略示図である。
【００１８】
プラズマCVD装置1は反応チャンバ6を含む。反応チャンバ6内側には半導体ウエハ4を載置するためのサセプタ3が設けられている。サセプタ3はヒータ2によって支持され、該ヒータ2は半導体ウエハ4を所定の温度（350〜450℃）に維持する。サセプタ3はプラズマ放電のための一方の電極を兼ねており、反応チャンバ6を通じて接地11されている。反応チャンバ6の内側天井部にはサセプタ3と平行に対向して、シャワーヘッド9が設けられている。シャワーヘッド9は底面に多くの細孔を有しており、そこから以下に説明する材料ガスが半導体ウエハ4に向かって均一に噴出される。シャワーヘッド9の中央部には材料ガス導入口5が設けられ、材料ガスはガスライン（図示せず）を通じてシャワーヘッド9に導入される。ガス導入口5は反応チャンバ6から電気的に絶縁されている。シャワーヘッド9はプラズマ放電のためのもう一方の電極を兼ねており、材料ガス導入口5を通じて外部の第1の高周波電源7及び第2の高周波電源8に接続されている。これによって、半導体ウエハ4の近傍にプラズマ反応場が生成される。反応チャンバ6の底部には排気口10が設けられ、外部の真空ポンプ（図示せず）と連結されている。
【００１９】
次に、本発明に係る半導体集積回路の多層配線用層間絶縁膜の製造方法について説明する。本発明に係る多層配線用層間絶縁膜の製造方法は、シリコン系炭化水素を材料ガスとして用いてプラズマCVD法により、第１の絶縁膜を形成する工程を含む。ここで材料ガスは、一般式SiαOα -1(R)2 α - β +2(OCnH2n+1)（ここで、α＝１〜３の整数、β＝０〜２の整数、ｎ＝１〜３の整数及びR＝Siに結合されたC1-6炭化水素）で表されるシリコン系炭化水素であり、好適にはDM-DMOS（ジメチル・ジメトキシシラン）である。他に副原料ガスとして、CO2、アルコール類、少なくとも１つの不飽和結合を含む炭化水素、またはN2を含むことができる。Si/O比を制御する必要がある場合には副原料ガスとしてさらにO2若しくはN2Oを付加することもできる。さらに添加ガスとして、Ar及び／またはHeのような不活性ガスを含むこともできる。
【００２０】
外部真空ポンプ（図示せず）によって真空排気した後、材料ガスは、ガス導入口5からシャワーヘッド9を通じて反応チャンバ6内部に導入される。続いて、第１の高周波電源7及び第２の高周波電源8によって励起高周波パワーが印加され、半導体基板4近傍にプラズマ反応場が形成される。ここで、第１の高周波電源7の周波数は2MHz以上であり、重畳する第２の高周波電源8の周波数は2MHz以下である。選択的に、第１の高周波電源7のみを用いることも可能である。プラズマ中で分解した材料ガス原子が化学反応を起こし、組成SixCyOzの第１の絶縁膜が半導体ウエハ4上に堆積する。
【００２１】
また、本発明に係る多層配線用層間絶縁膜の製造方法は、第１の絶縁膜を形成した後、in-situで連続的にシリコン系炭化水素ガス及び酸化性ガスを材料ガスとして用いてプラズマCVD法により、第１の絶縁膜上に第２の絶縁膜を形成する工程を含む。ここで材料ガスとして用いるシリコン系炭化水素は、一般式SiαOα -1(R)2 α - β +2(OCnH2n+1)（ここで、α＝１〜３の整数、β＝０〜２の整数、ｎ＝１〜３の整数及びR＝Siに結合されたC1-6炭化水素）で表されるシリコン系炭化水素であり、好適にはDM-DMOS（ジメチル・ジメトキシシラン）である。また材料ガスとして用いる酸化性ガスは、酸素、亜酸化窒素、オゾン、過酸化酸素、二酸化炭素、アルコール類の少なくとも１つから成る。以下に詳細に説明するように、鋭意研究を重ねた結果、酸化性ガスの流量をシリコン系炭化水素ガスの流量の１.２〜１００倍に制御することにより、第２の絶縁膜がポリッシングストッパ膜としての機能を果たすことがわかった。
【００２２】
第１の絶縁膜が形成された後、in-situで連続的に材料ガスをガス導入口5からシャワーヘッド9を通じて反応チャンバ6内に導入する。この際、酸化性ガスの流量はシリコン系炭化水素ガスの流量の１.２〜１００倍に制御する。続いて、第１の高周波電源7及び第２の高周波電源8によって励起高周波パワーが印加され、半導体ウエハ4近傍にプラズマ反応場が形成される。ここで、第１の高周波電源7の周波数は2MHz以上であり、重畳する第２の高周波電源8の周波数は2MHz以下である。選択的に、第１の高周波電源7のみを用いることも可能である。プラズマ中で分解した材料ガス原子が化学反応を起こし、組成SiO2の第２の絶縁膜が半導体基板4上に堆積する。
【００２３】
第１の絶縁膜の特徴は誘電率が低いことである。これは、主原料ガス（シリコン系炭化水素）中のSi-C結合がそのまま膜中に取り込まれ、膜の密度が疎となるためである。しかし、第１の絶縁膜は膜中に-CHx結合を多く含み多孔質であるため機械的強度が低いという欠点を有する。本発明者らはこの点に着目し、第１の絶縁膜の欠点を補うべく、機械的強度の高い第２の絶縁膜を第１の絶縁膜上に形成する方法を発明するに至った。第２の絶縁膜の特徴は機械的強度が高いことである。これは、酸化性ガスを過剰に流すことによって、膜中にCが入らず、膜が緻密となるためであると考えられる。
【００２４】
【実施例】
以下、本発明に係る層間絶縁膜の製造方法で形成した絶縁膜の評価実験を行ったので説明する。実験では、主原料ガスとしてDM-DMOS及び1,3ジメトキシテトラメチルジシロキサンを用い、それぞれの場合について第２の絶縁膜の単独評価及び第１の絶縁膜と組み合わせた場合のダマシン構造のCMP研磨試験を行った。
（実験１）
プラズマCVD装置：Eagle 12（日本エー・エス・エム社製）
第１の絶縁膜の成膜条件：
主原料ガス：DM-DMOS 200sccm
添加ガス：He 400sccm
第１のRF周波数： 27.12MHz 2.8W/cm2
第２の絶縁膜の成膜条件：
主原料ガス：DM-DMOS 100sccm
酸化性ガス：O2
第１のRF周波数： 27.12MHz
その他の第２の絶縁膜の成膜条件は表１の通りである。
【００２５】
【表１】

Figure 0004015510
【００２６】
この条件で、まず第２の絶縁膜を１μm成膜し、単独での膜厚分布、屈折率及び硬度を評価した。表２は評価結果を示したものである。
【００２７】
【表２】
Figure 0004015510
【００２８】
CMPのポリッシングストッパとして好適な硬度は6GPa以上である。この実験結果から、第２の絶縁膜の好適な成膜条件は、酸化性ガス／主原料ガスの流量比＝１.２〜１００、圧力100〜400Pa、第１RF高周波パワー＝0.5〜1.5W/cm2であることがわかった。
【００２９】
次に、CMP試験を行ったので説明する。まず、上記装置及び成膜条件で第１の絶縁膜を１μm形成した。その後表１の成膜条件に従いin-situで連続的に第２の絶縁膜を0.1μm形成した。ダマシン構造をCMPで研磨したところ、表１のすべての条件でディッシングは検出されなかった。
【００３０】
【効果】
本発明に係る層間絶縁膜の製造方法によれば、ダマシン配線技術のCMP工程においてポリッシングストッパとして機能する絶縁膜を与えることができた。その結果、低誘電率絶縁膜であるSixCyOz膜のディッシングの問題は解決された。
【００３１】
また、本発明に係る層間絶縁膜の製造方法によれば、従来のプラズマCVD装置をそのまま使用することができるため、後処理用の付加的な装置は一切不要となり、装置スペース及びコストを増大させることはない。
【図面の簡単な説明】
【図１】図１は、本発明に従う半導体集積回路の多層配線用層間絶縁膜の製造方法に使用するプラズマCVD装置の略示図である。
【符号の説明】
1 プラズマCVD装置
2 ヒータ
3 サセプタ
4 半導体ウエハ
5 材料ガス導入口
6 反応チャンバ
7 第１高周波電源
8 第２高周波電源
9 シャワーヘッド
10 排気口
11 接地[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an interlayer insulating film for multilayer wiring of a semiconductor integrated circuit and a manufacturing method thereof, and more particularly to a polishing stopper film for use in Cu multilayer wiring and a manufacturing method thereof.
[0002]
[Prior art]
Semiconductor integrated circuits have been miniaturized with the aim of increasing speed and functionality. Conventionally, Al has been used as a multilayer wiring material for semiconductor integrated circuits, but as the wiring becomes finer and longer distances, disconnection accidents due to electromigration that occur as the current density increases, the resistivity of Al, and the dielectric of the insulating film Signal delay due to rate has become a problem.
[0003]
Cu is attracting attention as a next-generation multilayer wiring material. Cu is strong against disconnection accidents and its resistance is smaller than Al. In 1997, IBM and Motorola developed a technology called Dual-Damascene. Conventionally, an Al film is processed into a convex shape by etching to form a wiring, and then the interlayer is filled with an insulating film. On the other hand, in damascene wiring technology, a trench of a wiring pattern is formed by etching on a flat interlayer insulating film, a Cu thin film is deposited on the entire surface, and then polished by chemical mechanical polishing (CMP). Are used as wiring (for example, see Non-Patent Document 1).
[0004]
[Non-Patent Document 1]
"Next Generation ULSI Process Technology" Realize Inc., February 29, 2000, p.558-565
[0005]
In this damascene wiring technology, application of a low dielectric constant insulating film is essential. Low dielectric constant insulating films include inorganic SOG films by spin coating, aC: F films by plasma CVD using CxFyHz as material gas, SixCyOz films by plasma CVD using silicon-based hydrocarbons as material gas, etc. It has been.
[0006]
[Problems to be solved by the invention]
In the CMP process of damascene wiring technology, polishing is performed using a polishing cloth and a polishing liquid (slurry). However, if the mechanical strength of the insulating film is low, a problem called dishing occurs in which the insulating film part is recessed from the Cu wiring part. . This is because when a material having a different polishing rate is mixed in the same polishing surface (for example, metal wiring and interlayer insulating film), the polishing cloth can be deformed, so that a material having a higher polishing rate is excessively polished. This is a phenomenon that occurs. The SixCyOz film, which is the most promising low dielectric constant film in the damascene wiring technology, has a low mechanical strength because it contains many -CHx bonds in the film and has a problem of dishing.
[0007]
When a post-processing apparatus is prepared to solve the dishing problem, not only the apparatus space and cost are problematic, but also the particle contamination that occurs during movement between apparatuses becomes a problem.
[0008]
Accordingly, an object of the present invention is to provide a method of manufacturing an interlayer insulating film in which dishing does not occur in the CMP process of damascene wiring technology.
[0009]
Another object of the present invention is to provide a method for manufacturing a low-cost interlayer insulating film that does not require any separate apparatus.
[0010]
[Means for Solving the Problems]
In order to solve the above problems, a method of manufacturing an interlayer insulating film according to the present invention includes the following steps.
[0011]
A method of manufacturing an interlayer insulating film for multilayer wiring of a semiconductor integrated circuit is as follows:
Forming a first insulating film by plasma CVD using silicon-based hydrocarbon as a material gas;
After forming the first insulating film, a second insulating film is formed on the first insulating film by plasma CVD using silicon-based hydrocarbon gas and oxidizing gas as material gases continuously in-situ. Forming, and
Consists of.
[0012]
Preferably, the flow rate of the oxidizing gas is 1.2 to 100 times the flow rate of the silicon hydrocarbon gas.
[0013]
The silicon-based hydrocarbon used in the present invention is represented by the general formula Si α O α -1 (R) 2 α - β +2 (OC n H 2n + 1 ),
Here, an integer of α = 1 to 3, an integer of β = 0 to 2, an integer of n = 1 to 3, and C 1-6 hydrocarbon bonded to R = Si.
[0014]
Specifically, the silicon-based hydrocarbon includes dimethyl dimethoxysilane.
[0015]
More specifically, the oxidizing gas is composed of at least one of oxygen, nitrous oxide, ozone, oxygen peroxide, carbon dioxide, and alcohols.
[0016]
On the other hand, the interlayer insulating film for multilayer wiring of a semiconductor integrated circuit is
A first insulating film formed by a plasma CVD method using silicon-based hydrocarbon as a material gas;
After forming the first insulating film, the second insulating film is formed on the first insulating film by plasma CVD using silicon-based hydrocarbon gas and oxidizing gas as material gases continuously in-situ. An insulating film;
Consists of.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic view of a plasma CVD apparatus used in a method for manufacturing an interlayer insulating film for multilayer wiring of a semiconductor integrated circuit according to the present invention.
[0018]
The plasma CVD apparatus 1 includes a reaction chamber 6. A susceptor 3 for placing the semiconductor wafer 4 is provided inside the reaction chamber 6. The susceptor 3 is supported by a heater 2, and the heater 2 maintains the semiconductor wafer 4 at a predetermined temperature (350 to 450 ° C.). The susceptor 3 also serves as one electrode for plasma discharge, and is grounded 11 through the reaction chamber 6. A shower head 9 is provided on the inner ceiling of the reaction chamber 6 so as to face the susceptor 3 in parallel. The shower head 9 has many pores on the bottom surface, from which a material gas described below is uniformly ejected toward the semiconductor wafer 4. A material gas inlet 5 is provided at the center of the shower head 9, and the material gas is introduced into the shower head 9 through a gas line (not shown). The gas inlet 5 is electrically insulated from the reaction chamber 6. The shower head 9 also serves as the other electrode for plasma discharge, and is connected to the external first high frequency power source 7 and second high frequency power source 8 through the material gas inlet 5. As a result, a plasma reaction field is generated in the vicinity of the semiconductor wafer 4. An exhaust port 10 is provided at the bottom of the reaction chamber 6 and is connected to an external vacuum pump (not shown).
[0019]
Next, a method for manufacturing an interlayer insulating film for multilayer wiring of a semiconductor integrated circuit according to the present invention will be described. The method for manufacturing an interlayer insulating film for multilayer wiring according to the present invention includes a step of forming a first insulating film by a plasma CVD method using silicon-based hydrocarbon as a material gas. Here, the material gas is a general formula Si α O α -1 (R) 2 α - β +2 (OC n H 2n + 1 ) (where α = an integer of 1 to 3, β = 0 to 2) N = 1 to 3 and R = C 1-6 hydrocarbon bonded to Si), preferably DM-DMOS (dimethyl dimethoxysilane). In addition, CO 2 , alcohols, hydrocarbons containing at least one unsaturated bond, or N 2 can be contained as a secondary source gas. When it is necessary to control the Si / O ratio, O 2 or N 2 O can be further added as a secondary source gas. Further, an inert gas such as Ar and / or He may be included as an additive gas.
[0020]
After evacuation by an external vacuum pump (not shown), the material gas is introduced into the reaction chamber 6 from the gas inlet 5 through the shower head 9. Subsequently, excitation high frequency power is applied by the first high frequency power source 7 and the second high frequency power source 8 to form a plasma reaction field in the vicinity of the semiconductor substrate 4. Here, the frequency of the first high frequency power supply 7 is 2 MHz or more, and the frequency of the second high frequency power supply 8 to be superimposed is 2 MHz or less. Alternatively, it is possible to use only the first high-frequency power source 7. The material gas atoms decomposed in the plasma cause a chemical reaction, and a first insulating film having the composition SixCyOz is deposited on the semiconductor wafer 4.
[0021]
In the method for manufacturing an interlayer insulating film for multilayer wiring according to the present invention, after forming the first insulating film, plasma is generated using silicon-based hydrocarbon gas and oxidizing gas as material gases continuously in-situ. A step of forming a second insulating film on the first insulating film by a CVD method; The silicon-based hydrocarbon used as the material gas here is a general formula Si α O α -1 (R) 2 α - β +2 (OC n H 2n + 1 ) (where α = an integer of 1 to 3, β = An integer of 0 to 2, an integer of n = 1 to 3, and R = a C 1-6 hydrocarbon bonded to Si), preferably DM-DMOS (dimethyl dimethoxy) Silane). The oxidizing gas used as the material gas is composed of at least one of oxygen, nitrous oxide, ozone, oxygen peroxide, carbon dioxide, and alcohols. As will be described in detail below, as a result of extensive research, the second insulating film becomes a polishing stopper by controlling the flow rate of the oxidizing gas to 1.2 to 100 times the flow rate of the silicon hydrocarbon gas. It was found to function as a membrane.
[0022]
After the first insulating film is formed, the material gas is continuously introduced into the reaction chamber 6 from the gas inlet 5 through the shower head 9 in-situ. At this time, the flow rate of the oxidizing gas is controlled to 1.2 to 100 times the flow rate of the silicon hydrocarbon gas. Subsequently, excitation high frequency power is applied by the first high frequency power source 7 and the second high frequency power source 8 to form a plasma reaction field in the vicinity of the semiconductor wafer 4. Here, the frequency of the first high frequency power supply 7 is 2 MHz or more, and the frequency of the second high frequency power supply 8 to be superimposed is 2 MHz or less. Alternatively, it is possible to use only the first high-frequency power source 7. The material gas atoms decomposed in the plasma cause a chemical reaction, and a second insulating film having a composition SiO 2 is deposited on the semiconductor substrate 4.
[0023]
The first insulating film is characterized by a low dielectric constant. This is because the Si—C bond in the main raw material gas (silicon hydrocarbon) is directly taken into the film and the density of the film becomes sparse. However, since the first insulating film is porous with many -CHx bonds in the film, it has a drawback of low mechanical strength. The present inventors pay attention to this point, and have invented a method of forming a second insulating film having a high mechanical strength on the first insulating film in order to compensate for the drawbacks of the first insulating film. The second insulating film is characterized by high mechanical strength. This is considered to be because when the oxidizing gas is allowed to flow excessively, C does not enter the film and the film becomes dense.
[0024]
【Example】
Hereinafter, an evaluation experiment of an insulating film formed by the method for manufacturing an interlayer insulating film according to the present invention was performed, which will be described. In the experiment, DM-DMOS and 1,3dimethoxytetramethyldisiloxane were used as the main source gases, and in each case, the second insulating film was independently evaluated and the damascene CMP polishing was combined with the first insulating film. A test was conducted.
(Experiment 1)
Plasma CVD equipment: Eagle 12 (manufactured by Japan ASM Co., Ltd.)
Conditions for forming the first insulating film:
Main raw material gas: DM-DMOS 200sccm
Additive gas: He 400sccm
First RF frequency: 27.12MHz 2.8W / cm 2
Conditions for forming the second insulating film:
Main raw material gas: DM-DMOS 100sccm
Oxidizing gas: O 2
First RF frequency: 27.12MHz
The other film formation conditions for the second insulating film are shown in Table 1.
[0025]
[Table 1]
Figure 0004015510
[0026]
Under these conditions, a second insulating film was first formed to a thickness of 1 μm, and the film thickness distribution, refractive index, and hardness alone were evaluated. Table 2 shows the evaluation results.
[0027]
[Table 2]
Figure 0004015510
[0028]
The hardness suitable as a polishing stopper for CMP is 6 GPa or more. From these experimental results, the preferred conditions for forming the second insulating film are as follows: oxidizing gas / main material gas flow ratio = 1.2-100, pressure 100-400 Pa, first RF high frequency power = 0.5-1.5 W / It was found to be cm 2 .
[0029]
Next, a CMP test was performed and will be described. First, 1 μm of a first insulating film was formed using the above apparatus and film forming conditions. Thereafter, a second insulating film was continuously formed in a thickness of 0.1 μm in-situ according to the film formation conditions shown in Table 1. When the damascene structure was polished by CMP, dishing was not detected under all conditions in Table 1.
[0030]
【effect】
According to the interlayer insulating film manufacturing method of the present invention, an insulating film functioning as a polishing stopper can be provided in the CMP process of the damascene wiring technology. As a result, the dishing problem of the SixCyOz film, which is a low dielectric constant insulating film, was solved.
[0031]
In addition, according to the method for manufacturing an interlayer insulating film according to the present invention, since a conventional plasma CVD apparatus can be used as it is, no additional apparatus for post-processing is required, which increases apparatus space and cost. There is nothing.
[Brief description of the drawings]
FIG. 1 is a schematic diagram of a plasma CVD apparatus used in a method for manufacturing an interlayer insulating film for multilayer wiring of a semiconductor integrated circuit according to the present invention.
[Explanation of symbols]
1 Plasma CVD equipment
2 Heater
3 Susceptor
4 Semiconductor wafer
5 Material gas inlet
6 Reaction chamber
7 First high frequency power supply
8 Second high frequency power supply
9 Shower head
10 Exhaust port
11 Ground

Claims (6)

半導体集積回路の多層配線用層間絶縁膜の製造方法であって、
シリコン系炭化水素を材料ガスとして用いてプラズマCVD法により、第１の絶縁膜を形成する工程と、
前記第１の絶縁膜を形成した後、in-situで連続的にシリコン系炭化水素ガス及び酸化性ガスを材料ガスとして用いてプラズマCVD法により、前記第１の絶縁膜上に第２の絶縁膜を形成する工程と、
から成り、
前記シリコン系炭化水素は、ジメチル・ジメトキシシランまたは１，３ジメトキシテトラメチルジシロキサンである、ところの方法。 A method of manufacturing an interlayer insulating film for multilayer wiring of a semiconductor integrated circuit,
Forming a first insulating film by plasma CVD using silicon-based hydrocarbon as a material gas;
After forming the first insulating film, the second insulating film is formed on the first insulating film by plasma CVD using silicon-based hydrocarbon gas and oxidizing gas as material gases continuously in-situ. Forming a film;
Consisting of
The silicon hydrocarbon is dimethyl dimethoxysilane or 1,3 dimethoxytetramethyldisiloxane. 請求項１に記載の方法であって、前記酸化性ガスの流量は前記シリコン系炭化水素ガスの流量の１.２〜１００倍である、ところの方法。The method according to claim 1, wherein the flow rate of the oxidizing gas is 1.2 to 100 times the flow rate of the silicon-based hydrocarbon gas. 請求項１に記載の方法であって、前記酸化性ガスは、酸素、亜酸化窒素、オゾン、過酸化酸素、二酸化炭素、アルコール類の少なくとも１つから成る、ところの方法。2. The method according to claim 1, wherein the oxidizing gas comprises at least one of oxygen, nitrous oxide, ozone, oxygen peroxide, carbon dioxide, and alcohols. 半導体集積回路の多層配線用層間絶縁膜であって、
シリコン系炭化水素を材料ガスとして用いてプラズマCVD法により形成された、第１の絶縁膜と、
前記第１の絶縁膜を形成した後、in-situで連続的にシリコン系炭化水素ガス及び酸化性ガスを材料ガスとして用いてプラズマCVD法により、前記第１の絶縁膜上に形成された第２の絶縁膜と、
から成り、
前記シリコン系炭化水素は、ジメチル・ジメトキシシランまたは１，３ジメトキシテトラメチルジシロキサンである、ところの多層配線用層間絶縁膜。 An interlayer insulating film for multilayer wiring of a semiconductor integrated circuit,
A first insulating film formed by a plasma CVD method using silicon-based hydrocarbon as a material gas;
After forming the first insulating film, the first insulating film formed on the first insulating film by plasma CVD using silicon-based hydrocarbon gas and oxidizing gas as material gases continuously in-situ. Two insulating films;
Consisting of
The silicon-containing hydrocarbon is dimethyl dimethoxysilane or 1,3 dimethoxytetramethyldisiloxane, wherein the interlayer insulating film for multilayer wiring is used. 請求項４に記載の多層配線用層間絶縁膜であって、前記酸化性ガスの流量は前記シリコン系炭化水素ガスの流量の１.２〜１００倍である、ところの多層配線用層間絶縁膜。5. The interlayer insulating film for multilayer wiring according to claim 4, wherein the flow rate of the oxidizing gas is 1.2 to 100 times the flow rate of the silicon-based hydrocarbon gas. 請求項４に記載の多層配線用層間絶縁膜であって、前記酸化性ガスは、酸素、亜酸化窒素、オゾン、過酸化酸素、二酸化炭素、アルコール類の少なくとも１つから成る、ところの多層配線用層間絶縁膜。5. The interlayer insulating film for multilayer wiring according to claim 4, wherein the oxidizing gas comprises at least one of oxygen, nitrous oxide, ozone, oxygen peroxide, carbon dioxide, and alcohols. Interlayer insulation film.
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