JP4007644B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a volatile semiconductor memory device with a refresh operation.
A volatile memory such as a DRAM (Dynamic Random Access Memory) or a synchronous DRAM (SDRAM) needs a refresh operation. This refresh operation is a rewrite operation of the memory cell, and the refresh time is determined by regulation, and the supply currents of various power generation circuits are set corresponding to the number of S / As operating at a time. ing.
[0002]
By the way, recently, a semiconductor memory device has appeared that attempts to subdivide the activation array to reduce current consumption and speed up the access operation. In these chips (semiconductor memory devices), since the number of S / As at the time of refresh is the same as that of the conventional chip, there is a large difference in the current consumption of each power generation circuit between the active time and the refresh time. ing. In order to solve this problem, it has been proposed to provide a plurality of power generation circuits. However, there is a problem in the occupied area and power consumption of the power supply unit, and the power supply unit occupied area and power consumption are not increased. There is a demand for providing a semiconductor memory device capable of performing a refresh operation.
[0003]
[Prior art]
FIG. 1 is a block diagram conceptually showing a memory cell array section and a power generation circuit in an example of a conventional semiconductor memory device. In FIG. 1, reference numeral 101 is a semiconductor memory device (memory chip), 121 to 124 are memory cell array sections, 103 is a power supply voltage generator, and 104 is a boost level generator.
[0004]
The conventional semiconductor memory device (for example, SDRAM) shown in FIG. 1 supplies each power supply voltage to a plurality of (for example, four) memory cell array units 121 to 124 having a common power supply voltage generator 103 and boosted level generator 104. Is configured to do. Here, the power supply voltage generator 103 supplies a power supply voltage to, for example, S / A (sense amplifiers) in the memory cell array units 121 to 124, and the boost level generator 104 supplies the memory cell array units 121 to 124. Generate a boost level used to drive the selected word line at.
[0005]
In a conventional DRAM (SDRAM), the refresh time is determined to be, for example, 8k times / 64 msec. By regulation, and a 256 Mbit DRAM performs 8k refresh operations in 64 milliseconds. ing. In other words, the number of S / A (sense amplifiers) operating at one time is 256M ÷ 8k times = 32k, and S / A four times as large as 8k at the time of normal access (reading or writing). Will work.
[0006]
As a result, the peak current of the S / A operation increases, and as a result, in the semiconductor memory device provided with the power supply voltage generator 103 having the driving capability corresponding to the normal access time (normal operation mode). The current supply capability for the S / A during the refresh operation (in the refresh operation mode) is insufficient, and the S / A takes a longer time to amplify the potential difference between the bit line pairs than during normal access. Conventionally, a word line in one memory cell array unit is selected during normal access, whereas each word line in, for example, four memory cell array units is selected during a refresh operation. ing. Therefore, the boost level generator 104 that drives the word line must drive loads of different magnitudes during normal access (in normal operation mode) and refresh operation (in refresh operation mode). .
[0007]
Here, for example, the refresh operation of the DRAM is a rewrite operation of the memory cell, the sense amplifier (S / A) operates after the word line (WL) rises, and the bit lines (BL, / BL). When the level difference becomes sufficient, the word line is closed, and the refresh operation is performed by repeating these operations. In this series of operations, when the power supply voltage drop (bump down) occurs, the problem is that the rise of the word line is delayed and the sensing operation starts before the data from the memory cell comes out. And the word line is closed when the bit line is not fully opened.
[0008]
FIG. 2 is a block diagram conceptually showing a memory cell array section and a power supply generating circuit in another example of a conventional semiconductor memory device. In FIG. 2, reference numeral 101 is a semiconductor memory device (memory chip), 121 to 124 are memory cell array units, 131 to 134 are power supply voltage generators, and 141 to 144 are boost level generators.
[0009]
The above-described conventional semiconductor memory device shown in FIG. 1 is configured to provide a common power supply unit (power supply voltage generator 103 and boost level generator 104) for a plurality of memory cell array units 121-124. On the other hand, the conventional semiconductor memory device shown in FIG. 2 supplies power to each of the memory cell array units 121 to 124 in order to cope with an increase in current consumption of the S / A (sense amplifier) during the refresh operation. Voltage generators 131 to 134 and boost level generators 141 to 144 are provided so as to correspond to the current consumption during the refresh operation. Here, the plurality of power supply voltage generators 131 to 134 and the boost level generators 141 to 144 may be configured to be activated only during the refresh operation.
[0010]
FIG. 3 is a block circuit diagram showing a configuration of a main part of an example of a conventional semiconductor memory device, FIG. 4 is a timing diagram for explaining a refresh operation of the semiconductor memory device of FIG. 3, and FIG. 2 is a block circuit diagram showing a configuration example of a main part of a memory cell array unit in the semiconductor memory device of FIG.
3 and 5, reference numeral 105 is a precharge control circuit, 106 is a row control circuit (row control circuit), 107 is a word decoder control circuit, and 110 is a sense amplifier control circuit (S / A control circuit). ). In FIG. 5, reference numeral 108 denotes a word decoder, 109 denotes a column decoder, 111 denotes a sense amplifier activation circuit (S / A activation circuit), and 112 denotes a sense amplifier (S / A).
[0011]
As shown in FIG. 3 and FIG. 5, a row address strobe signal / ras is supplied to the row system control circuit 106, and the row system control circuit 106 outputs a signal braz to the word decoder control circuit 107. At the same time, a signal prez is output to the precharge control circuit 105. The word decoder control circuit 107 outputs a signal pwlz to the plurality of word decoders (word decoder strings) 108, the S / A control circuit 110, and the precharge control circuit 105, and the precharge control circuit 105 is a row system. The signal prepz is fed back to the control circuit 106. Then, the S / A control circuit 110 outputs a signal lez to a plurality of S / A (sense amplifier arrays) 112.
[0012]
As shown in FIG. 3, the precharge control circuit 105 includes a NAND gate NAND5 to which signals prez and pwlz are input, a plurality of inverters I51 to I55, a plurality of resistors R51 to R54, and a plurality of capacitors C51 to C54. Configured. The S / A control circuit 110 includes a plurality of inverters I11 to I18, a plurality of resistors R11 to R15, a plurality of capacitors C11 to C15, and a NOR gate NOR1.
[0013]
As shown in FIG. 5, the plurality of word decoders (word decoder strings) 108 receives a signal pwlz from the word decoder control circuit 107 and receives a row address to select a predetermined word line WL. ing. The S / A activation circuit 111 receives the signal lez from the S / A control circuit 110 and supplies signals nsa and psa to a plurality of S / A (sense amplifier arrays) 112.
[0014]
The column decoder 109 receives the column address and selects the corresponding S / A 112. Each S / A 112 receives the signals nsa and psa from the S / A activation circuit 111, and is provided at the intersection of the corresponding bit line BL and / BL and the word line WL selected by the word decoder 108, respectively. The minute potential from the memory cell MC is amplified.
[0015]
Next, the refresh operation of the conventional semiconductor memory device will be described.
As shown in FIG. 4, the refresh operation of the semiconductor memory device of FIG. 3 starts with row-related control in response to the row address strobe signal / ras changing from high level “H” to low level “L”. The output signal brazz (row access signal) and the signal prez of the circuit 106 rise from the low level “L” to the high level “H”, respectively.
[0016]
Further, an output signal pwlz (a signal that is a basis for raising the word line WL) of the word decoder control circuit 107 is generated (changed from the low level “L” to the high level “H”), and from the S / A control circuit 110. The output signal lez for activating the sense amplifier operation is delayed by a predetermined time (delay time DT12) by the resistors R11, R13 to R15, capacitors C11, C13 to C15, etc., and then from the low level “L” to the high level “H”. Stand up. Further, the output signal prepz of the precharge control circuit 105 includes resistors R51 to R54, capacitors C51 to C54, etc. in response to the signal prez changing to the high level “H” while the signal pwlz is at the high level “H”. The signal rises from the low level “L” to the high level “H” with a delay of a predetermined time (delay time DT11). That is, the precharge control circuit 105 generates a signal prepz at a predetermined timing and feeds it back to the row system control circuit 106 to execute a precharge operation.
[0017]
That is, the row system control circuit 106 receives the signal prez, changes the output signal brazz from the high level “H” to the low level “L”, and accordingly the output signal pwlz of the word decoder control circuit 107 is also set to the high level. It changes from “H” to low level “L”. Further, in response to the change of the signal pwlz, the signal lez output from the S / A control circuit 110 is delayed by a predetermined time by the resistors R11 and R12, the capacitors C11 and C12, etc., and then from the high level “H” to the low level “ L "changes.
[0018]
Here, the delay time DT12 in the S / A control circuit 110 and the delay time DT11 in the precharge control circuit 105 are predetermined by the CR delay of the resistor and the capacitor.
FIG. 6 is a circuit diagram showing an example of the S / A activation circuit in the memory cell array portion of FIG. 5, and FIG. 7 is a circuit diagram showing an example of the word decoder in the memory cell array portion of FIG. These S / A activation circuit, S / A, and word decoder have a common configuration in the conventional semiconductor memory device and the semiconductor memory device to which the present invention is applied.
[0019]
As shown in FIG. 6, the S / A activation circuit 111 (11) includes an inverter I3, a P-channel MOS transistor QP3 receiving the power supply voltage (VDD) supplied from the power supply voltage generator, and N Channel type MOS transistors QN31 to QN33 are provided. The S / A 112 (12) includes P-channel MOS transistors QP41 and QP42 and N-channel MOS transistors QN41 and QN42.
[0020]
When the output signal lez from the S / A control circuit 110 is at a low level “L”, the S / A activation circuit 111 switches off the transistors QP3 and QN33 and switches on the transistors QN31 and QN32 to turn on the signals psa and When nsa becomes VDD / 2, the S / A 112 is reset (precharged), and when the signal lez is at the high level “H”, the transistors QP3 and QN33 are switched on and the transistors QN31 and QN32 are switched off. Thus, the signal psa is VDD and the signal nsa is VSS (GND), so that the S / A 112 is in an operating state (activated state).
[0021]
As shown in FIG. 7, word decoder 108 (8) includes NAND gate NAND8, inverter I8, P channel MOS transistors QP81 to QP83 that receive the boosted level (VPP) from the boosted level generator and N channel MOS. Transistors QN81 to QN83 are provided.
The word decoder 108 selects the corresponding word line WL (high level “H”) when both the signal pwlz and the address signal from the word decoder control circuit 107 input to the NAND gate NAND8 are high level “H”. ing.
[0022]
[Problems to be solved by the invention]
As described above, the conventional semiconductor memory device shown in FIG. 1 is provided with a common power supply unit (power supply voltage generator 103 and boosted level generator 104) for a plurality of memory cell array units 121 to 124, and normal access is performed. When the current consumption of the sense amplifier (S / A 112) at the time of reading (at the time of reading or writing) is adopted, the power supply unit (the power supply voltage generator 103 and the boost level generator 104 is increased due to an increase in the current consumption during the refresh operation. ) Insufficient current supply capability causes each power supply voltage to fall below a predetermined level, resulting in a shift in operation timing and a normal refresh operation cannot be performed.
[0023]
That is, as described with reference to FIG. 6, the delay time DT12 in the S / A control circuit 110 and the delay time DT11 in the precharge control circuit 105 are determined in advance by the CR delay of the resistor and the capacitor. In a semiconductor memory device having a power supply circuit suitable for the current consumption required for access, the current supply capability is insufficient during the refresh operation, and each power supply voltage drops below a predetermined level, so timing can be taken well. There wasn't.
[0024]
Further, the conventional semiconductor memory device shown in FIG. 2 has a power supply voltage generator 131-134 and a booster for each of the memory cell array units 121-124 in order to cope with an increase in current consumption of the sense amplifier during the refresh operation. The level generators 141 to 144 are provided. However, when the plurality of power supply voltage generators 131 to 134 and the boost level generators 141 to 144 are provided as described above, the area occupied by the power supply unit is increased and integrated. In addition to hindering conversion, the power consumption was also increased.
[0025]
In view of the problems of the conventional semiconductor memory device described above, the present invention performs a reliable refresh operation without increasing the occupied area of the power supply unit and increasing the power consumption by providing a plurality of power generation circuits. An object of the present invention is to provide a semiconductor memory device that can be used.
[0026]
[Means for Solving the Problems]
Main departure Clearly A memory cell that requires a refresh operation; a word line that selects the memory cell using a boosted level; a sense amplifier that performs a data read operation of the memory cell or a data refresh operation of the memory cell; The number of the sense amplifiers and the number of word lines that operate during the refresh operation are larger than the number of the sense amplifiers and word lines that operate during the read operation, refresh A control signal generation circuit for detecting an operation and generating a control signal, a word decoder for driving the word line, a word decoder control circuit for driving the word decoder, and a row control circuit for controlling the word decoder control circuit And a precharge control circuit that executes a precharge operation of the row-related control circuit, the precharge control circuit receiving the control signal and delaying the timing of the output signal of the word decoder control circuit A semiconductor memory device is provided.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a semiconductor memory device according to the present invention will be described below with reference to the drawings.
FIG. 8 is a block diagram conceptually showing a memory cell array section and a power supply generation circuit in an example of a semiconductor memory device to which the present invention is applied. In FIG. 8, reference numeral 1 is a semiconductor memory device (memory chip), 21 to 24 are memory cell array sections, 3 is a power supply voltage generator, and 4 is a boost level generator.
[0029]
As in the conventional semiconductor memory device shown in FIG. 1 described above, the semiconductor memory device (eg, SDRAM) of this embodiment shown in FIG. 8 includes a plurality of (for example, a common power supply voltage generator 3 and boosted level generator 4). Each power supply voltage is supplied to the four (4) memory cell array units 21 to 24.
FIG. 9 is a block circuit diagram showing the main configuration of an embodiment of the semiconductor memory device according to the present invention, FIG. 10 is a timing diagram for explaining the refresh operation of the semiconductor memory device of FIG. FIG. 11 is a block circuit diagram showing a configuration example of a main part of the memory cell array portion in the semiconductor memory device to which the present invention is applied.
[0030]
9 and 11, reference numeral 5 is a precharge control circuit, 6 is a row system control circuit (row system control circuit), 7 is a word decoder control circuit, and 10 is a sense amplifier control circuit (S / A control circuit). ). In FIG. 11, reference numeral 8 is a word decoder, 9 is a column decoder, 11 is a sense amplifier activation circuit (S / A activation circuit), and 12 is a sense amplifier (S / A).
[0031]
As shown in FIGS. 9 and 11, a row address strobe signal / ras is supplied to the row system control circuit 6, and the row system control circuit 6 outputs a signal brazz to the word decoder control circuit 7. At the same time, a signal prez is output to the precharge control circuit 5. The word decoder control circuit 7 outputs a signal pwlz to the plurality of word decoders 8, the S / A control circuit 10 and the precharge control circuit 5, and the precharge control circuit 5 supplies the row system control circuit 6 with the signal pwlz. The signal prepz is fed back. Then, the S / A control circuit 10 outputs a signal lez to the plurality of S / A 12.
[0032]
Here, in the semiconductor memory device of this embodiment, the control signal refz is supplied to the precharge control circuit 5 and the S / A control circuit 10. The control signal refz is generated by the control signal generation circuit (13). The configuration of the control signal generation circuit will be described in detail later.
As shown in FIG. 9, the precharge control circuit 5 includes a NAND gate NAND5 to which signals prez and pwlz are input, a plurality of inverters I51 to I58, a plurality of resistors R51 to R56, a plurality of capacitors C51 to C56, and a transfer circuit. Gates TG51 and TG52 are provided. Here, as is clear from comparison with the conventional precharge control circuit 105 shown in FIG. 3, in the precharge control circuit 5 of this embodiment, inverters I56 and I57, resistors R55 and R56, and capacitors C55 and C56 are used. A configured delay circuit 50 is added, and the connection of the delay circuit 50 is controlled by a control signal refz.
[0033]
At the time of normal access (during read and write operations), the control signal refz becomes low level “L”, the transfer gate TG51 is switched off and the TG52 is switched on. With a circuit configuration similar to that of the charge control circuit 105, a delay time DT11 is given to the output signal prepz of the precharge control circuit 5 of this embodiment. On the other hand, at the time of the refresh operation, the control signal refz becomes high level “H”, the transfer gate TG51 is switched on and the TG52 is switched off, and the delay circuit 50 is inserted in series to increase the delay time. The output signal prepz of 5 is given a delay time DT1.
[0034]
That is, in the present embodiment, since a common power supply unit (power supply voltage generator 3 and boost level generator 4) is provided for the plurality of memory cell array units 21 to 24, during normal access, A delay time DT11 is given to the output signal prepz of the precharge control circuit 5. During the refresh operation, the power supply section (the power supply voltage generator 3 and the boost level generator 4) lacks the current supply capability, so that each power supply voltage drops below a predetermined level and the operation speed (change in signal level) decreases. However, in order to correspond to this delay, the output signal prepz of the precharge control circuit 5 is given a delay time DT1 larger than the delay time DT11 at the time of normal access to match (delay) the operation timing.
[0035]
Further, as shown in FIG. 9, the S / A control circuit 10 includes a plurality of inverters I11 to I21, a plurality of resistors R11 to R17, a plurality of capacitors C11 to C17, a NOR gate NOR1, and transfer gates TG11 and TG12. It is prepared for. Here, as is apparent from comparison with the conventional S / A control circuit 110 shown in FIG. 3, in the S / A control circuit 10 of this embodiment, inverters I19 and I20, resistors R16 and R17, and capacitors C16, A delay circuit 100 composed of C17 is added, and the connection of the delay circuit 100 is controlled by a control signal refz.
[0036]
During normal access (during normal operation mode: read and write operations), the control signal refz is at a low level “L”, the transfer gate TG11 is switched off, the TG12 is switched on, and the delay circuit 100 is involved. The delay time DT12 is given to the output signal lez of the S / A control circuit 10 of this embodiment by the same circuit configuration as that of the conventional S / A control circuit 110. On the other hand, at the time of the refresh operation (in the refresh operation mode), the control signal refz becomes high level “H”, the transfer gate TG11 is switched on and the TG12 is switched off, and the delay circuit 100 is inserted in series to delay time. The delay time DT2 is given to the output signal lez of the S / A control circuit 10.
[0037]
That is, in the present embodiment, since a common power supply unit (power supply voltage generator 3 and boost level generator 4) is provided for the plurality of memory cell array units 21 to 24, during normal access, A delay time DT12 is given to the output signal lez of the S / A control circuit 10. During the refresh operation, the power supply section (the power supply voltage generator 3 and the boost level generator 4) lacks the current supply capability, so that each power supply voltage drops below a predetermined level and the operation speed (change in signal level) decreases. However, in order to correspond to this delay, the output signal lez of the S / A control circuit 10 is given a delay time DT2 larger than the delay time DT12 at the time of normal access to match (delay) the operation timing.
[0038]
As shown in FIG. 11, a plurality of word decoders (word decoder strings) 8 receive a signal pwlz from the word decoder control circuit 7 and also receive a row address to select a predetermined word line WL. ing. The S / A activation circuit 11 receives the signal lez from the S / A control circuit 10 and supplies the signals nsa and psa to a plurality of S / A (S / A columns) 12.
[0039]
The column decoder 9 receives the column address and selects the corresponding S / A 12. Each S / A 12 receives the signals nsa and psa from the S / A activation circuit 11 and is provided at the intersection of the corresponding bit line BL and / BL and the word line WL selected by the word decoder 8. The minute potential of the memory cell MC is amplified. The configurations of sense amplifier activation circuit (S / A activation circuit) 11, sense amplifier (S / A) 12, and word decoder 8 are the same as those of the conventional semiconductor memory device described with reference to FIGS. Since this is the same as the S / A activation circuit 111, S / A 112, and word decoder 108 in FIG.
[0040]
Next, the refresh operation of the semiconductor memory device of this embodiment will be described.
As shown in FIG. 10, the refresh operation of the semiconductor memory device of FIG. 9 starts with the output of the row control circuit 6 when the row address strobe signal / ras changes from the high level “H” to the low level “L”. The signal brazz (row access signal) and the signal prez rise from the low level “L” to the high level “H”, respectively. Here, during the refresh operation, the control signal refz changes from the low level “L” to the high level “H” at substantially the same timing as the row address strobe signal / ras.
[0041]
Further, an output signal pwlz (a signal that is a basis for raising the word line WL) of the word decoder control circuit 7 is generated (changed from the low level “L” to the high level “H”), and from the S / A control circuit 10. The output signal lez for activating the sense amplifier operation is delayed by a predetermined time (delay time DT2) by the resistors R11, R13 to R17, capacitors C11, C13 to C17, etc. Stand up. Here, the delay time DT2 includes a delay by the delay circuit 100, and due to the delay time DT2, the output voltage of the power supply unit (the power supply voltage generator 3 and the boosted level generator 4) is reduced (voltage drop). The control timing of the word line WL is synchronized with the delay of the operation speed (signal level change). During normal access (reading and writing), the control signal refz is at a low level “L”, the delay circuit 100 is not involved, and the output signal lez of the S / A control circuit 10 is delayed. Time DT12 will be included.
[0042]
Further, the output signal prepz of the precharge control circuit 5 includes resistors R51 to R56, capacitors C51 to C56, etc. in response to the signal prez changing to the high level “H” while the signal pwlz is at the high level “H”. The signal rises from the low level “L” to the high level “H” with a delay of a predetermined time (delay time DT1). That is, the precharge control circuit 5 generates a signal prepz at a predetermined timing and feeds it back to the row control circuit 6 to execute a precharge operation. Here, the delay time DT1 includes a delay due to the delay circuit 50, and the timing of each signal (brasz, pwlz, lez, etc.) due to a delay in the operation speed due to a decrease in the output voltage of the power supply unit due to the delay time DT1. Are supposed to be synchronized. During normal access, the control signal refz is at the low level “L”, the delay circuit 50 is not involved, and the output signal prepz of the precharge control circuit 5 includes the delay time DT11.
[0043]
Further, the row system control circuit 6 receives the signal prez, changes the output signal brazz from the high level “H” to the low level “L”, and accordingly the output signal pwlz of the word decoder control circuit 7 is also set to the high level. It changes from “H” to low level “L”. Further, in response to the change of the signal pwlz, the signal lez output from the S / A control circuit 10 is delayed by a predetermined time by the resistors R11, R12, R16, R17 and the capacitors C11, C12, C16, C17, etc. The level changes from “H” to low level “L”. During normal access, the control signal refz is at a low level “L”, the delay circuit 100 is not involved, and the signal lez is delayed for a predetermined time by the resistors R11, R12, capacitors C11, C12, and the like. It changes from a high level “H” to a low level “L”.
[0044]
As described above, in the semiconductor memory device of this embodiment, at the time of refresh, the delay time in the S / A control circuit 10 is increased from DT12 to DT2, and the delay time in the precharge control circuit 5 is changed from DT11 to DT1. This makes it possible to match the refresh operation with the delay in operation timing caused by insufficient power supply capacity (voltage drop) of the power supply during the refresh operation, and increases the occupied area by providing multiple power generation circuits In addition, a reliable refresh operation can be performed without increasing power consumption.
[0045]
That is, according to the semiconductor memory device of the present embodiment, by delaying the signal lez (delaying the sensing operation) during refresh, the rise of the word line (WL) is delayed due to the voltage drop (bump down) of the power supply. By eliminating the sense operation before the data from the memory cell comes out and further delaying the signal prepz, the word line is closed in a state where the level difference between the bit lines (BL, / BL) is not sufficient. Can be eliminated.
[0046]
12 is a circuit diagram showing an example of a control signal generating circuit in the memory cell array portion of FIG. 11, and FIG. 13 is a block diagram showing the memory cell array portion and the control signal generating circuit in the semiconductor memory device to which the present invention is applied. .
As shown in FIG. 12, the control signal generation circuit (refz generation circuit) 13 includes a command recognition unit 30, a plurality of level detection units 31 to 34, a NOR gate NOR3, and an inverter I3. When the output of 30 or any of the level detectors 31 to 34 becomes a high level “H”, the control signal is raised from the low level “L” to the high level “H”. That is, the refresh operation is recognized by the logic of each command signal (clock enable signal cke, chip select signal / CE, row address strobe signal / ras, column address strobe signal / cas, and write enable signal WE) and each power supply. It is recognized from the voltage drop of the voltage (boost levels VPP1 to VPP4).
[0047]
As shown in FIG. 12, the command recognition unit 30 includes inverters I31 to I33, a NAND gate NAND30, and a NOR gate NOR30, and the chip select signal / CE is at a low level “L” and the row address strobe signal / ras. Is low level “L”, the column address strobe signal / cas is low level “L”, the write enable signal WE is high level “H”, and the clock enable signal cke is low level “L”. A high level “H” signal is output to the NOR gate NOR3.
As shown in FIG. 13, each of the level detectors 31 to 34 resistances the boosted levels VPP1 to VPP4 in each of the memory cell arrays 21 to 24, and the voltage VPP (the output voltage of the control signal generating circuit dedicated boosted level generator 14). For example, the level detection unit 31 is a differential circuit composed of P-channel MOS transistors QP311, QP312 and N-channel MOS transistors QN311 to QN313. The amplifier circuit compares the boosted level VPP1 of the memory cell array 21 with the reference voltage Vr, and outputs a high level “H” to the NOR gate NOR3 when the boosted level VPP1 becomes lower than the reference voltage Vr. .
[0048]
Therefore, the control signal generation circuit 13 shown in FIG. 12 is used when the output of the command recognition unit 30 is at a high level “H” or when the output of any of the level detection units 31 to 34 is at a high level “H”. In addition, the control signal refz is set to the high level “H” to increase the delay time of the output signal prepz of the precharge control circuit 5 and the output signal lez of the S / A control circuit 10 to synchronize the operation timing. It has become. The control signal generation circuit 13 shown in FIG. 12 detects the boost levels VPP1 to VPP4 in each of the memory cell arrays 21 to 24, but recognizes the refresh operation by detecting the normal power supply voltage level and the like. You may comprise as follows. Further, the semiconductor memory device of the present invention is not limited to a DRAM or SDRAM, and can be applied to a nonvolatile semiconductor memory device accompanied by a refresh operation.
[0049]
【The invention's effect】
As described above in detail, according to the semiconductor memory device of the present invention, the refresh operation is performed in accordance with the delay of the operation timing due to the voltage drop during the refresh by delaying the predetermined signal only during the refresh. By providing a plurality of power generation circuits, a reliable refresh operation can be performed without increasing the occupied area of the power supply section and increasing the power consumption.
[Brief description of the drawings]
FIG. 1 is a block diagram conceptually showing a memory cell array section and a power supply generation circuit in an example of a conventional semiconductor memory device.
FIG. 2 is a block diagram conceptually showing a memory cell array section and a power supply generation circuit in another example of a conventional semiconductor memory device.
FIG. 3 is a block circuit diagram showing a main configuration of an example of a conventional semiconductor memory device.
4 is a timing chart for explaining a refresh operation of the semiconductor memory device of FIG. 3;
FIG. 5 is a block circuit diagram showing a configuration example of a main part of a memory cell array portion in a conventional semiconductor memory device.
6 is a circuit diagram showing an example of an S / A activation circuit in the memory cell array portion of FIG. 5;
7 is a circuit diagram showing an example of a word decoder in the memory cell array portion of FIG. 5;
FIG. 8 is a block diagram conceptually showing a memory cell array section and a power supply generation circuit in an example of a semiconductor memory device to which the present invention is applied.
FIG. 9 is a block circuit diagram showing a main configuration of an embodiment of a semiconductor memory device according to the present invention.
10 is a timing chart for explaining a refresh operation of the semiconductor memory device of FIG. 9;
FIG. 11 is a block circuit diagram showing a configuration example of a main part of a memory cell array unit in a semiconductor memory device to which the present invention is applied;
12 is a circuit diagram showing an example of a control signal generation circuit in the memory cell array portion of FIG.
FIG. 13 is a block diagram showing a memory cell array unit and a control signal generating circuit in a semiconductor memory device to which the present invention is applied.
[Explanation of symbols]
1. Semiconductor memory device (memory chip)
3 ... Power supply voltage generator
4 ... Boost level generator
5 ... Precharge control circuit
6 ... Row system control circuit (row system control circuit)
7. Word decoder control circuit
8 ... Word decoder
9 ... Column decoder
10 Sense amplifier control circuit (S / A control circuit)
11 Sense amplifier activation circuit (S / A activation circuit)
12 ... Sense amplifier (S / A)
13. Control signal generation circuit (refz generation circuit)
14 ... Boost level generator dedicated to control signal generation circuit
21 to 24: Memory cell array section
30 ... Command recognition unit
31-34 ... Level detection circuit
50, 100 ... delay circuit

Claims (1)

A memory cell that requires a refresh operation, a word line that selects the memory cell that uses a boost level, and a sense amplifier that performs a data read operation of the memory cell or a refresh operation of the data of the memory cell, The number of the sense amplifiers and the number of word lines that operate during the refresh operation are greater than the number of the sense amplifiers and the number of word lines that operate during the read operation,
A control signal generating circuit for detecting the refresh operation and generating a control signal;
A word decoder for driving the word line;
A word decoder control circuit for driving the word decoder;
A row control circuit for controlling the word decoder control circuit;
A precharge control circuit that executes a precharge operation of the row control circuit,
The semiconductor memory device, wherein the precharge control circuit receives the control signal and delays a timing of an output signal of the word decoder control circuit.

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