JP3994545B2 - Data receiver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data receiving apparatus that generates a clock pulse when a synchronization signal transmitted from a transmission apparatus is received, and samples information data transmitted following the synchronization signal using the clock pulse.
[0002]
[Prior art]
One method for transmitting data at high speed is a bit serial data transmission method.
In this method, a synchronization signal that repeats “0” and “1” for each bit and information data representing character information, image information, etc. in a bit string in units of 8 bits are configured and transmitted as one frame. It is transmitted as transmission data from the side. On the receiving side, when receiving the synchronization signal, for example, a clock pulse having the same frequency and the same phase as the synchronization signal is generated by PLL (Phase-Locked Loop) control, and is transmitted following the synchronization signal using this clock pulse. Sampling information data.
[0003]
This PLL is mainly composed of a closed loop circuit of a voltage controlled oscillator (VCO), a phase comparator, and a low pass filter (LPF). The VCO outputs a clock pulse having a predetermined frequency according to an input voltage. The synchronization signal and the clock pulse output from the VCO are input to the phase comparator, and the phase comparator detects the phase component (phase difference) of both signals and outputs this as a pulse signal (phase difference signal). And output to the LPF.
[0004]
The LPF is mainly composed of a resistor and a capacitor, removes unnecessary noise components contained in the phase difference signal, converts the phase difference signal into a DC voltage, and outputs it to the VCO. The VCO changes the phase of the clock pulse in such a direction that the phase difference disappears, and sends this to the phase comparator. By repeating this operation, the phase of the clock pulse approaches the phase of the synchronization signal, and eventually both phases are matched (this operation is referred to as “phase matching”). Specifically, this phase alignment is performed so that the phase difference between the edges in the same direction between the rising edges (positive edges) of the synchronization signal and the clock pulse is eliminated.
[0005]
However, even if phase adjustment is performed in this way, leakage current is generated in the PLL control circuit, and therefore the frequency and phase of the clock pulse once phase-adjusted gradually change over time, so that sampling of information data In order to perform accurately, it is desirable to perform this phase alignment every frame.
[0006]
[Problems to be solved by the invention]
However, when serial data is received using a PLL as described above, only one transmission path is required, but information data cannot be transmitted while a synchronization signal is being transmitted. There was a problem of inefficiency. In order to improve the transmission efficiency in such a data configuration, it is conceivable to shorten the transmission time of the synchronization signal as much as possible. However, as described above, the PLL is configured by a closed loop circuit that eliminates the phase difference by varying the oscillation frequency of the VCO by the detected phase difference. Therefore, if the phase difference is large, the phase adjustment is performed accordingly. It takes a long time to complete. Therefore, it is necessary to set the transmission time of the synchronization signal to a time necessary for surely performing the phase alignment even when the phase difference between the two signals is the largest, that is, even when the phase is shifted by 180 °. is there. Otherwise, during synchronization signal reception, phase alignment cannot be completed, and information data is sampled using clock pulses of different frequencies, so that accurate information cannot be obtained, resulting in communication reliability. It is because it becomes impossible to secure.
[0007]
Such a problem is not limited to a method of generating a clock pulse using a PLL, but occurs in a data receiving apparatus that generates a clock pulse by performing phase alignment with a received synchronization signal.
The present invention has been made in view of the above-described problems, and in a data receiving apparatus that samples information data with a clock pulse generated by performing phase alignment with a received synchronization signal, The purpose is to shorten the transmission time of the synchronization signal by completing the matching as soon as possible, and consequently improve the transmission efficiency of the information data.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a data receiving apparatus for receiving transmission data including a synchronization signal and information data, the pulse generation means for generating a clock pulse, the received synchronization signal, and the pulse generation means. A phase difference between the same-direction edges and different-direction edges with respect to the clock pulse generated by the step, and selecting means for selecting a combination of edges having the smallest phase difference, so that the phase difference between the selected edges is eliminated. And a phase adjusting means for adjusting the phase of the clock pulse, and a sampling means for sampling the information data based on the clock pulse after the phase adjustment.
[0009]
In addition, the clock pulse generated by the pulse generation means is divided by the same frequency division ratio, and has a frequency division pulse generation means for generating a plurality of frequency division pulses having different phases from each other, the selection means is In place of the clock pulse, a phase difference between the same-direction edge and the opposite-direction edge between each generated divided pulse and the synchronization signal is obtained, and a combination of edges having the smallest phase difference is selected. Features.
[0010]
Further, when the selected division pulse is a pulse divided by using the rising edge of the clock pulse as a trigger, the previous period sampling means executes sampling of the previous period information data at the falling edge of the clock pulse, When the pulse is divided by using the falling edge of the clock pulse as a trigger, the information data is sampled at the rising edge of the clock pulse.
[0011]
The previous transmission data consists of alternating synchronization signals and information data, and the previous phase adjustment means stops adjusting the frequency and phase of the clock pulse while receiving the information data, and the previous synchronization state It is characterized by maintaining.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a data receiving apparatus according to the present invention will be described below.
FIG. 1 is an overall configuration diagram of a data receiving apparatus, and FIG. 2 is a diagram illustrating an example configuration of an input signal 60 transmitted from an external apparatus to the data receiving apparatus.
As shown in FIG. 1, the data receiving apparatus is roughly composed of a PLL circuit unit 20 and a data demodulating unit 35. As shown in FIG. 2, the input signal 60 includes a synchronization signal 61 composed of a pulse train that repeats “0” and “1” for each bit, a start bit 62 in which 9 bits continuously become “1”, Information data 63 formed by connecting a plurality of 9-bit data strings in which “0” is added before 8 bits representing character, image information, etc. is composed of one frame, and is repeatedly transmitted. It has become.
[0013]
The data demodulator 35 is a circuit that samples the information data 63 using the reception CLK 44 generated by the PLL circuit unit 20.
The PLL circuit unit 20 is a circuit that generates a reception CLK 44 based on the synchronization signal 61 transmitted every frame and sends it to the data demodulation unit 35. The PLL circuit unit 20 includes two PLL circuits, that is, a phase comparator 30, an LPF 33, a VCO 34, and a frequency divider 36 in order to reduce the time required to generate the reception CLK 44 as compared with the conventional case. The first PLL circuit 10 and the second PLL circuit 11 comprising the phase comparator 31, LPF 33, VCO 34, and divide-by-37 37 are selectively switched (LPF 33 and VCO 34 are shared with the first PLL circuit 10). Yes. Hereinafter, the circuit configuration of the PLL circuit unit 20 will be described.
[0014]
The VCO 34 is a known voltage-controlled oscillator that changes the frequency according to the applied voltage. The VCO 34 generates a reception CLK 44 according to the output voltage of the LPF 33 and outputs the reception CLK 44 to the data demodulator 35 and the two frequency dividers 36 and 37.
FIG. 3 is a graph showing the frequency characteristics of the reception CLK 44 with respect to the input voltage of the VCO 34. From this figure, it can be seen that this VCO 34 has a characteristic that the frequency of the received reception CLK 44 increases linearly when the input voltage rises. In addition, since the transmission speed (frequency) of the input signal 60 is constant, a crystal oscillator having a high stability and a small amount of change is used.
[0015]
Returning to FIG. 1, the divide-by-two 36 is composed of a flip-flop circuit that operates at the rising edge (positive edge) of the reception CLK 44 generated by the VCO 34, and divides the reception CLK 44 by two by two. 2 is generated and output to the phase comparator 30 and the phase difference detector 32.
The divide-by-two 37 is composed of a flip-flop circuit that operates at the falling edge (negative edge) of the reception CLK 44, and generates a divide-by-two CLK 48 (see FIG. 2) obtained by dividing the reception CLK 44 by two. It outputs to the comparator 31 and the phase difference detector 32. Since the frequency-divided CLK 48 is divided by using the negative edge of the received CLK 44 as a trigger, the phase is delayed by 90 ° from the frequency-divided CLK 47.
[0016]
The phase comparator 30 is a circuit that generates a phase difference signal 38 corresponding to the phase difference between the received synchronization signal 61 and the half-divided CLK 47 and outputs this to the LPF 33.
Further, since it is constituted by a charge pump circuit, when there is no phase difference, the output terminal is in a high impedance state and no current flows through the LPF 33. The phase comparator 1 operates only when the output terminal of the phase comparator selector 50 becomes “0”, and when it is “1”, the operation is stopped and the output terminal is brought into a high impedance state.
[0017]
Here, the phase comparator 30 can receive the lock signal 321. When this signal is “0”, the synchronization signal 61 and the edge in the same direction of the frequency-divided CLK 47 (positive edges and The negative edges are synchronized (see FIG. 4A), and when “1”, the opposite edges (positive edge and negative edge) of the synchronization signal 61 and the frequency-divided CLK 47 are synchronized. (See FIG. 4B). In the present embodiment, hereinafter, synchronizing both the same direction edges or different direction edges to bring both signals into the state shown in FIG. 4A or 4B is referred to as “phase alignment”. In addition, even if it synchronizes with the same direction edge, it synchronizes with the edge of a different direction, and the positive edge of the synchronizing signal 61 and reception CLK44 does not change. This is because the frequency-divided CLK 47 is a signal divided by the positive edge of the reception CLK 44. The circuit configuration of the phase comparator 1 will be described later.
[0018]
Returning to FIG. 1, the phase comparator 31 has the same configuration as that of the phase comparator 30, and generates a phase difference signal 40 corresponding to the phase difference between the received synchronization signal 61 and the half-divided CLK 48, and outputs the phase difference signal 40 to the LPF 33. Output to. Further, the operation is performed only when the output terminal of the phase comparator selection unit 49 becomes “0”, and when it is “1”, the operation is stopped and the output terminal is brought into a high impedance state.
[0019]
Further, the lock signal 322 can be input. When this signal is “0”, it operates so as to synchronize the synchronization signal 61 and the edge in the same direction of the divide-by-two CLK 48, and “1”. Sometimes it operates to synchronize different direction edges. This operation is the same as that of the phase comparator 30.
The LPF 33 is a known low-pass filter circuit composed of a resistor and a capacitor. Upon receiving the phase difference signal 38 or the phase difference signal 40, the LPF 33 removes a high frequency component and noise and smoothes it to convert it into a DC voltage. This is output to the VCO 34 described above.
[0020]
The phase comparator selectors 49 and 50 are each composed of an OR gate, and receive the phase difference signal 46 from the phase difference detector 32 and the hold signal 45 from the data demodulator 35.
The phase difference detector 32 detects the phase difference between the synchronizing signal 61 and the half-divided CLK 47, and the synchronizing signal 61 and the half-divided CLK 48, respectively, and according to the magnitude of the phase difference, the phase difference signal 46, the lock This circuit outputs signals 321 and 322.
[0021]
When the hold signal 45 from the data demodulator 35 is “0” and the phase difference signal 46 becomes “0”, the output terminal of the phase comparator selector 50 becomes “0”, and the first PLL circuit 10 When the phase difference signal 46 becomes “1”, the output terminal of the phase comparator selector 49 becomes “0”, and the second PLL circuit 11 is configured. When the lock signal 321 becomes “0”, the phase comparator 30 synchronizes at the same direction edge as described above, and when it becomes “1”, synchronization occurs at the opposite direction edge. Similarly, when the lock signal 322 becomes “0”, the phase comparator 31 is synchronized at the same direction edge, and when it is “1”, it is synchronized at the opposite direction edge. The circuit configuration of the phase difference detector 32 will be described later.
[0022]
In the data receiving apparatus having such a configuration, when receiving the synchronization signal 61, the data demodulating unit 35 outputs an enable signal 42 that is “0” for a predetermined time to the phase difference detector 32 (FIG. 2). As will be described later, when the signal is “0”, the phase difference detector 32 outputs the output levels (“0”) of the phase difference signal 46 and the lock signals 321 and 322 according to the detected phase difference. Or “1”). At this time, since the hold signal 45 is “1” (FIG. 2), the output signals of the phase comparator selectors 49 and 50 are both “1”, and the phase comparators 30 and 31 are stopped. State.
[0023]
The data demodulator 35 changes the enable signal 42 from “0” to “1” and simultaneously sets the hold signal 45 to “0” (FIG. 2). As a result, one of the phase comparators 30 and 31 operates according to the output level of the phase difference signal 46 to form one of the first or second PLL circuits 10 and 11, and the lock signals 321 and 322. Phase matching is performed according to the output level.
[0024]
The data demodulator 35 counts the number of pulses of the received synchronization signal 61, and when this reaches a predetermined count, the hold signal 45 is changed from “0” to “1”. This control can be easily performed if the transmission time (number of pulses) of the synchronization signal 61 is determined in advance. When the hold signal 45 becomes “1”, the outputs of the phase comparator selectors 49 and 50 become “1”. As a result, the output terminals of the phase comparators 30 and 31 are in a high impedance state as described above, and the PLL closed loop control is stopped. Even in this case, since the charge accumulated in the capacitor of the LPF 33 is held, the reception CLK 44 is fixed at a frequency immediately before the PLL control is stopped.
[0025]
The data demodulator 35 samples the start bit 62 and the information data 63 using the reception CLK 44. The start bit 62 is a signal that is continuously “1” for 9 bits as described above, and is inserted between the synchronization signal 61 and the information data 63. As a result, the data receiving device side can clearly distinguish the synchronization signal 61 and the information data 63. Further, since the information data 63 has a data structure in which one “0” is added before an 8-bit data string indicating character information or the like, the data receiving apparatus has the next data “0”. It can be determined that 8 bits are a data string. When the reception of the information data 63 is completed and the synchronization signal 61 of the next frame is sent, the data demodulator 35 changes the enable signal 42 from “1” to “0”. Thereafter, the above operation is repeated, and the information data 63 of each frame is sampled.
[0026]
FIG. 5 is a diagram illustrating a circuit configuration of the phase difference detector 32.
The phase difference detector 32 includes exclusive OR gates (Ex. OR) 51 and 90, comparators 54, 57 and 93, a DATA flip-flop (D-FF) 55, and the like.
Ex. An input signal 60 and a divide-by-2 CLK 47 are input to the OR 51. This Ex. The OR 51 outputs a pulse signal 511 corresponding to the phase difference between the synchronization signal 61 in the input signal 60 and the divide-by-2 CLK 47. For example, in a state where there is no phase difference between both signals, a pulse waveform as shown in FIG. When the phase difference is very small, the waveform is as shown in FIG. 6B. When the phase difference is larger than 90 °, the waveform is as shown in FIG. 6C.
[0027]
This pulse signal 511 is sent to the 3-state buffer 52. The enable signal 42 from the data demodulator 35 is input to the control terminal 521 of the 3-state buffer 52. The 3-state buffer 52 operates only when the enable signal 42 is “0”, and outputs the pulse signal 511 to the LPF 53 as it is. When the enable signal 42 is “1”, the output is in a high impedance state so that no current is supplied.
[0028]
The LPF 53 is a known low-pass filter circuit including a resistor and a capacitor, and smoothes the pulse signal 511 into a DC voltage.
FIG. 7 is a graph showing the output voltage characteristics of the LPF 53. The vertical axis represents the output voltage value of the LPF 53, and the horizontal axis represents Ex. The phase difference between the positive edges of the synchronizing signal 61 input to the OR 51 and the divided by two CLK 47 is shown. From the figure, when the phase difference is 180 °, the output voltage is the maximum voltage Vcc, when the phase difference is 0 ° and 360 °, the minimum voltage is 0, and when it is 45 ° and 315 °, it is 1/4 times Vcc. When the voltage is VTH1, 135 ° and 225 °, the voltage VTH2 is 3/4 times Vcc. Here, a positive phase difference indicates a case where the half-divided CLK 47 is delayed from the synchronization signal 61, and a negative indicates a case where the phase difference is advanced.
[0029]
Returning to FIG. 5, the output voltage of the LPF 53 is output to the comparators 54 and 57, respectively. This comparator 54 compares the voltage values of the signals input to the input terminals 541 and 542 and outputs a signal (“0” or “1”) corresponding to the sign of the input terminal with the larger voltage value. This is a voltage comparator. The comparator 57 is also configured with a comparator similar to the comparator 54.
[0030]
The reference voltage VTH1 is applied to the input terminal 541 of the comparator 54, and the reference voltage VTH2 is applied to the input terminal 572 of the comparator 57. The reference voltages VTH1 and VTH2 are set to the same voltage as VTH1 and VTH2 in FIG.
The output signals of the comparators 54 and 57 are input to the AND gate 58, and the output signal of the AND gate 58 is output to the D0 terminal of the D-FF 55.
[0031]
The D-FF 55 detects the signal level (“0” or “1”) at the D0 terminal when the signal at the CLK terminal, that is, the rising edge when the enable signal 42 changes from “0” to “1” is detected. This is a known flip-flop circuit that outputs the same signal as a phase difference signal 46 from the Q terminal. The D-FF 55 maintains the signal level at the Q terminal in the current state until the next rising edge is input to the CLK terminal, that is, until the synchronization signal 61 of the next frame is received. Thus, the phase difference signal 46 is not changed within one frame. That is, the first PLL circuit 10 and the second PLL circuit 11 are not switched. The output signal of the comparator 54 is input to the D1 terminal of the D-FF 55. When a rising edge is input to the CLK terminal, the signal at that time is output from the Q1 terminal as the lock signal 321 and the phase comparator 30. Sent to.
[0032]
Ex. An input signal 60 and a divide-by-2 CLK 48 are input to the OR 90. This Ex. The OR 90 outputs a pulse signal 901 corresponding to the phase difference between the synchronization signal 61 of the input signal 60 and the frequency-divided CLK 48. The waveform of the signal 901 is almost the same as that of the pulse signal 511 described above.
This pulse signal 901 is sent to the 3-state buffer 91. The enable signal 42 is input to the control terminal 911 of the 3-state buffer 91. When the enable signal 42 becomes “0”, the three-state buffer 91 operates, and the pulse signal 901 is output to the low-pass filter (LPF) 92 as it is. When the enable signal 42 is “0”, the output terminal is set to a high impedance state so that no current is supplied to the LPF 92.
[0033]
The LPF 92 is composed of the same low-pass filter circuit as the LPF 53 described above, and the output voltage characteristics are the same (FIG. 7). The output voltage of the LPF 92 is output to the comparator 93. The comparator 93 is a known voltage comparator similar to the comparator 57 described above. A reference voltage VTH3 (a voltage that is ½ times Vcc in FIG. 7) is applied to the input terminal 931 of the comparator 93. The output signal of the comparator 93 is output to the D2 terminal of the D-FF 55. When the rising edge is input to the CLK terminal, the signal at the D2 terminal at that time is output from the Q2 terminal as the lock signal 322 and sent to the phase comparator 31.
[0034]
In such a configuration, Ex. When the phase difference between the synchronization signal 61 input to the OR 51 and the frequency-divided CLK 47 is 0 ° to 45 °, 45 ° to 135 °, 135 ° to 225 °, 225 ° to 315 ° The operation of the phase difference detector 32 in the case of 315 ° to 360 ° will be described with reference to FIG.
[0035]
FIG. 8 is a schematic diagram showing the phase relationship between the synchronization signal 61 and the half-divided CLKs 47 and 48.
Here, the interval between adjacent positive edges of the synchronization signal 61 is set to 360 ° (one cycle), and the positive edge of the synchronization signal 61 is determined at a position of 0 °. Further, as described above, the half-divided CLK 48 is in a state in which the phase is always delayed by 90 ° from the half-divided CLK 47.
[0036]
When the phase difference between the synchronization signal 61 and the half-divided CLK 47 is within a range up to 45 ° (FIG. 8A), the output voltage of the LPF 53 is smaller than VTH1 from FIG. The output terminal is “0”, and the output terminal of the AND gate 58 is “0”. At this time, when the enable signal 42 changes from “0” to “1”, a rising edge is input to the CLK terminal, the Q terminal (phase difference signal 46) is “0”, and the Q1 terminal (lock signal 321) is “0”. Is latched. As a result, the first PLL circuit 10 shown in FIG. 1 operates and the phase comparator 30 synchronizes at the same direction edge of the synchronization signal 61 and the divide-by-2 CLK 47. That is, as shown in FIG. 8A, the phase difference is the smallest among the phase differences between the same direction edges and the different direction edges of the synchronization signal 61 and the divided frequency CLK 47 and the synchronized signal 61 and the divided frequency CLK 48. Synchronization is established between the positive edge of the synchronization signal 61 and the positive edge of the divide-by-2 CLK 47, which are between the edges. If the phase difference is small, the amount of phase adjustment can be reduced accordingly, so that the time required for phase alignment can be shortened. In this case, since the phase difference between the synchronization signal 61 and the half-divided CLK 48 exceeds 90 °, the output voltage of the LPF 92 is larger than Vth3 from FIG. 7, and the Q2 terminal (lock signal 322) is “1”. It becomes. However, since the phase comparator 31 is not operating at this time, the first PLL circuit 10 is not affected.
[0037]
Subsequently, when the phase difference between the synchronizing signal 61 and the divide-by-2 CLK 47 is within the range of 45 ° to 135 ° (FIG. 8B), the output voltage of the LPF 53 is Vth1 and Vth2 from FIG. The Q terminal becomes “1” and the second PLL circuit 11 operates. Further, the Q1 terminal is “1”. At this time, since the phase difference between the positive edges of the divide-by-two CLK 48 and the synchronization signal 61 exceeds 90 °, the output voltage of the LPF 92 becomes larger than Vth3. Therefore, the Q2 terminal is “1”. Thereby, the phase comparator 31 operates so as to synchronize the different direction edges. That is, as shown in FIG. 8B, synchronization is established between the negative edge of the synchronizing signal 61 and the positive edge of the divided-by-two CLK 48 having the smallest phase difference in this case.
[0038]
Further, when the phase difference between the synchronizing signal 61 and the divide-by-2 CLK 47 is in the range from 135 ° to 225 ° (FIG. 8C), the output voltage of the LPF 53 exceeds Vth2 from FIG. , Q terminal becomes “0”, and the first PLL circuit 10 operates. The Q1 terminal is “1” and the Q2 terminal is “1”. Thereby, the phase comparator 30 operates so as to synchronize the different direction edges. That is, as shown in FIG. 8C, synchronization is established between the negative edge of the synchronizing signal 61 and the positive edge of the divided-by-2 CLK 47, which have the smallest phase difference in this case.
[0039]
Further, when the phase difference between the synchronizing signal 61 and the frequency-divided CLK 47 is within a range from 225 ° to 315 ° (FIG. 8 (d)), the output voltage of the LPF 53 is Vth1 and Vth2 from FIG. Therefore, the Q terminal becomes “1”, and the second PLL circuit 11 operates. The Q1 terminal is “1” and the Q2 terminal is “1”. Thereby, the phase comparator 31 operates so as to synchronize the same direction edges. In other words, as shown in FIG. 8D, synchronization is established between the positive edge of the synchronization signal 61 and the positive edge of the divide-by-two CLK 48, which have the smallest phase difference in this case.
[0040]
When the phase difference is from 315 ° to 360 °, the output voltage of the LPF 53 is smaller than Vth1, so that the Q terminal becomes “0” and the first PLL circuit 10 operates. The Q1 terminal is “0” and the Q2 terminal is “0”. Thereby, the phase comparator 30 operates so as to synchronize the same direction edges. That is, as in FIG. 8A, synchronization is established between the positive edge of the synchronization signal 61 and the positive edge of the divided-by-two CLK 48, which have the smallest phase difference in this case.
[0041]
As described above, the phase difference detector 32 sets the output level (“0” or “1”) of the phase difference signal 46 and the lock signals 321 and 322 so that the edges having the smallest phase difference are synchronized with each other. Since it is configured, phase alignment can be performed quickly regardless of any phase difference between the synchronization signal 61 and the half-divided CLKs 47 and 48. As a result, the time required to generate the reception CLK 44 can be shortened compared to the conventional method of synchronizing the edges in the same direction, so that the transmission time of the synchronization signal 61 can be shortened accordingly, resulting in transmission efficiency. Can be improved.
[0042]
Further, in FIG. 8, the case where the phase of the half-divided CLK 47 is delayed from the phase of the synchronization signal 61 has been described, but conversely, the same applies to the case where the phase of the positive edge of the half-divided CLK 47 is advanced. Result. Of course, the same applies to the case where the phase difference from the synchronization signal 61 is considered with reference to the two-divided CLKs 47 and 48. In addition, in the figure, the phase difference between the half-divided CLK 47 and the positive edge of the synchronizing signal 61 is used as a reference. However, the phase difference between the half-divided CLK 48 and the positive edge of the synchronizing signal 61 is also the reference. If the output levels of the phase difference signal 46 and the lock signals 321 and 322 are set so that the small edges are synchronized, the same result is obtained.
[0043]
FIG. 9 is a diagram showing a circuit configuration of the phase comparator 30, and FIG. 10 shows a signal waveform in the circuit of the phase comparator 30. First, the circuit operation will be described with reference to the signal waveform of FIG. 10A in the case where the phase of the half-divided CLK 47 is delayed within the range of 45 ° from the synchronization signal 61.
The phase comparator 30 includes a D-FF 70, differentiating circuits 71A and 71B, selectors 73, 81, and 82.
[0044]
The D-FF 70 is a flip-flop that latches the synchronization signal 61 input to the D terminal at the positive edge of the half-divided CLK 47 input to the T terminal. In FIG. 8A, since the phase of the divide-by-2 CLK 47 is delayed from the phase of the synchronization signal 61, the Q terminal of the D-FF 70 is “1” and the QB terminal is “0”.
Only when the differential circuit 71A detects the positive edge and the negative edge of the input synchronization signal 61, and the differential circuit 71B detects the positive edge and the negative edge of the input 2-divided CLK 47, the differential circuit 71A outputs a negative differential pulse. This is a known differentiation circuit for outputting. The output signals 80A and 80B of each circuit are output to the asynchronous set D-FF 72.
[0045]
Asynchronous set D-FF72 sets the Q terminal to “1”, the QB terminal to “0” when the SB terminal becomes “0”, and the D terminal is always “0”. When a negative edge signal is input, the flip-flop circuit sets the Q terminal to “0” and the QB terminal to “1”.
Accordingly, a pulse signal 76 as shown in FIG. 10A is output to the Q terminal, and a pulse signal 77 in a state where the pulse signal 76 is inverted is output to the QB terminal.
[0046]
The selector 73 is a known switching circuit that outputs the signal of the A terminal to the Y terminal as it is when the S terminal becomes “0”, and outputs the signal of the B terminal as it is to the Y terminal when it becomes “1”. The same applies to the other selectors 81 and 82.
Since the Q terminal of the D-FF 70 is “1” from the above, the signal of the B terminal is output to the Y terminal of the selector 73. Further, when the phase of the divide-by-2 CLK 47 is delayed within a range of 45 ° from the synchronization signal 61 (in the case of FIG. 8A), the lock signal from the phase difference detector 32 as described above. Since 321 becomes “0”, the selector 81 outputs the signal of the A terminal to the Y terminal. That is, the pulse signal 77 output from the QB terminal of the asynchronous set D-FF 72 is output from the Y terminal of the selector 81. The output signal 39 of the phase comparator selection unit 50 is a signal for operating the first PLL circuit 10 and is “0” here, so the output signal of the OR gate 79 has the same waveform as the pulse signal 77. Become. On the other hand, since the S terminal of the selector 82 is “0”, the signal 97 of the Y terminal is “1”. The 3-state buffer 74 operates when the output of the OR gate 79 becomes “0”, and outputs the signal 97 as it is, so that the output signal (phase difference signal) 38 is a pulse signal 77 as shown in FIG. Is the same waveform as that obtained by inverting (the same waveform as the signal 76). That is, the three-state buffer 74 operates only when the phase difference signal 38 is “1”, and current is supplied to the LPF 33 (charging). As a result, the output voltage of the LPF 33 rises and is output from the VCO 34. And the phase of the divide-by-2 CLK 47 advances. When “0”, the 3-state buffer 74 does not operate, so that the output terminal is in a high impedance state, and no current is supplied to the LPF 33.
[0047]
Next, a circuit operation in the case where the phase of the half-divided CLK 47 is delayed within the range of 135 ° to 180 ° with respect to the synchronization signal 61 will be described with reference to FIG.
In this case, the Q terminal of the D-FF 70 is “1” and the QB terminal is “0”. Accordingly, the selector 73 outputs the signal at the B terminal as it is to the Y terminal. Further, since the lock signal 321 in this case is “1”, a signal input to the B terminal of the selector 81, that is, a signal obtained by inverting the signal 78 from the Y terminal of the selector 73 at the NOT gate 84 is input. This is output from the Y terminal. Further, since the S terminal of the selector 82 is “1”, the signal 97 of the Y terminal is “0”. Therefore, as shown in FIG. 10B, the phase difference signal 38 has a waveform similar to that of the pulse signal 76. That is, the three-state buffer 74 operates only when the phase difference signal 38 is “−1”, draws electric charge from the LPF 33 (discharges it), and lowers the output voltage of the LPF 33. As a result, the frequency output from the VCO 34 is lowered, and the phase of the divide-by-two CLK 47 is delayed. When “0”, the three-state buffer 74 does not operate, so the output terminal is in a high impedance state, and no current is supplied to the LPF 33.
[0048]
FIG. 10C is a waveform diagram in the case where the phase of the half-divided CLK 47 is delayed within the range of 180 ° to 225 ° with respect to the synchronization signal 61.
In this case, since the Q terminal of the D-FF 70 is “0” and the QB terminal is “1”, the selector 73 outputs the signal of the A terminal as it is to the Y terminal. Since the lock signal 321 is “1”, a signal obtained by inverting the signal 78 from the Y terminal of the selector 73 is output from the Y terminal of the selector 81. Since the S terminal of the selector 82 is “1”, the signal 97 at the Y terminal is “1”, and the phase difference signal 38 is the same as in FIG. The phase will advance.
[0049]
FIG. 10D is a waveform diagram in the case where the phase of the divide-by-2 CLK 47 is delayed within the range of 315 ° to 360 ° with respect to the synchronization signal 61.
In this case, since the Q terminal of the D-FF 70 is “0” and the QB terminal is “1”, the selector 73 outputs the signal of the A terminal as it is to the Y terminal. Further, since the lock signal 321 becomes “0”, the signal 78 from the Y terminal of the selector 73 is output as it is from the Y terminal of the selector 81. Since the S terminal of the selector 82 is “0”, the signal 97 at the Y terminal is “0”, and the phase difference signal 38 is the same as in FIG. The phase is delayed.
[0050]
As described above, the phase comparator 30 is configured to generate the phase difference signal 38 according to the magnitude of the phase difference not only between the same direction edges but also between the different direction edges. By switching the output level of the signal 321, the first PLL circuit 10 can synchronize edges in the same direction or in different directions.
[0051]
Although not shown, since the phase comparator 31 has the same configuration, in the second PLL circuit 11, the synchronization signal 61 and the divide-by-two CLK 48 can be synchronized either in the same direction edge or in different direction edges. It has become.
As described above, the PLL circuit unit 20 switches between the first PLL circuit 10 and the second PLL circuit 11 based on the magnitude of the phase difference between the synchronization signal 61 and the divided CLKs 47 and 48, and at the same direction edge or the different direction edge. Since they are configured so that they can be synchronized with each other, synchronization can be achieved faster than in the conventional case where synchronization is achieved only with the edges in the same direction. Accordingly, the transmission time of the synchronization signal 61 can be made shorter than that in the prior art, and as a result, the transmission efficiency can be improved without degrading the reliability.
[0052]
The data demodulating unit 35 is sent next to the synchronization signal 61 when the phase alignment is performed between the synchronization signal 61 and the divide-by-2 CLK 47 (when performed by the first PLL circuit 10). The incoming start bit 62 and information data 63 are latched and sampled at the timing of the negative edge of the reception CLK 44 as shown in FIG.
In this case, since the negative edge of the reception CLK 44 appears at the center position of 1 bit of the information data 63, if the latch is performed at the negative edge, even if the phase of the reception CLK 44 is slightly shifted, the signal level (“0” or “1”) is not erroneously recognized and reliability can be improved.
[0053]
On the other hand, when the phase alignment is performed by the second PLL circuit 11, it is latched at the timing of the positive edge of the reception CLK 44. This is a signal generated by dividing the divide-by-two CLK 48 by two at the timing of the negative edge of the reception CLK 44, so that the negative edge of the reception CLK 44 is synchronized with the positive edge and the negative edge of the information data 63. This is because a positive edge appears at the center position of 1 bit of the information data 63.
[0054]
FIG. 11 is a diagram showing a latch switching unit 351 in the data demodulating unit 35. As described above, when the first PLL circuit 10 is selected, the phase difference signal 46 becomes “0”. The selector 352 is a known switching circuit that outputs a signal from the A terminal when “0” is input to the S terminal and a signal from the B terminal from the Y terminal when “1” is input. In this case, since the S terminal becomes “0”, the received CLK 44 is sent as it is to the 8-bit shift register. Although the 8-bit shift register is not shown, when the information data 63 is input, it is latched at the negative edge of the reception CLK 44 for each bit.
[0055]
On the other hand, when the second PLL circuit 11 is selected, the phase difference signal 46 becomes “1” and the S terminal of the selector 352 becomes “1”, so that the received CLK 44 is inverted by the NOT gate 353 and Y It is output from the terminal and sent to the 8-bit shift register.
Since the 8-bit shift register is a circuit that latches the information data 63 at the negative edge as described above, if the reception CLK 44 is inverted before being input to the 8-bit shift register, the positive edge of the reception CLK 44 is substantially reduced. This is the same as latching the information data 63 at the timing.
[0056]
Needless to say, the present invention is not limited to the above embodiment, and the following modifications can be considered.
(1) In the above-described embodiment, the first and second PLL circuits 10 and 11 are selectively switched. However, the reception CLK 44 may be generated only by the first PLL circuit 10. In this case, since there is no divide-by-two CLK 48, the edges having the smaller phase difference are synchronized between the same direction edges of the synchronization signal 61 and the divide-by-two CLK 47 or between the different direction edges. The output level of the lock signal 321 is set. Even in this case, the time required for phase alignment can be shortened as compared with the conventional case where synchronization is performed only between edges in the same direction. Further, the circuit configuration is simplified and the cost can be reduced. In this case, the information data 63 may be sampled at the falling edge of the reception CLK 44.
[0057]
(2) In the above embodiment, the half-divided CLKs 47 and 48 obtained by dividing the reception CLK 44 by two are generated, and phase matching is performed between them and the synchronization signal 61. It will never be done. For example, even if two pulse signals divided by four are generated by shifting the phase by 90 °, and phase alignment is performed between them and the synchronization signal 61, the time required for phase alignment can be shortened similarly to the above. An effect can be obtained. The same can be said even when the frequency division is not performed, that is, when the frequency dividers 36 and 37 are removed. If the frequency is not divided, the frequency of the reception CLK 44 and the input signal 60 are the same. Therefore, if these are synchronized between the same direction edges or different direction edges, the sampling edge becomes the rising edge or falling edge of the information data 63. For example, if the phase of the reception CLK 44 is slightly shifted, the signal level is erroneously recognized. Therefore, in such a case, if a known phase adjustment circuit capable of shifting the phase by, for example, 180 degrees is configured instead of the above-described latch switching unit 351, the rising or falling edge of the reception CLK having a shifted phase is configured. The edge is located at approximately the center of 1 bit of the information data 63. Therefore, no error is recognized even if sampling is performed at any edge, and reliability can be improved.
[0058]
Further, if a plurality of frequency-divided pulses having different phases are generated and phase alignment is performed between them and the synchronization signal 61, it is possible to obtain an effect that the time required for phase alignment can be further shortened. . For example, a third PLL circuit for generating a half-divided clock 471 (not shown) having a phase delayed by 45 ° from the above-mentioned half-divided CLK 47 and phase-synchronizing this with the synchronizing signal 61 is newly provided. Then, in the phase difference detector 32, the first to third PLL circuits are arranged so as to obtain the edge having the smallest phase difference between the two-divided CLKs 47, 48, 471 and the synchronization signal 61 and to synchronize the edges. One of them to work. In this way, the PLL circuit to be operated can be selected based on the phase difference between the three generated half-divided CLKs 47, 48, and 471. Therefore, the amount of phase adjustment is less than that described above, and the time required for phase alignment Can be shortened.
[0059]
(3) In the above embodiment, the reception CLK 44 is generated from the synchronization signal 61 using the first and second PLL circuits 10 and 11, but the present invention is not limited to this, and the synchronization signal 61 and the phase Any circuit that can generate the received CLK 44 by performing the matching can be applied.
[0060]
【The invention's effect】
As described above, according to the present invention, the phase difference between the same-direction edge and the different-direction edge between the received synchronization signal and the clock pulse generated by the pulse generation means is obtained, and the edge having the smallest phase difference is obtained. Since the combination is selected and the phase of the clock pulse is adjusted so that there is no phase difference between the edges, the phase of the clock pulse is adjusted to eliminate the phase difference between the edges in the same direction as before. Compared with this method, the amount of phase adjustment is small, and the time required for phase adjustment can be shortened. As a result, the transmission time of the synchronization signal can be shortened accordingly, and as a result, the transmission efficiency can be improved.
[Brief description of the drawings]
FIG. 1 is an overall configuration diagram of a data receiving apparatus according to an embodiment of the present invention.
FIG. 2 is a diagram showing a configuration example of an input signal transmitted from an external device to the data receiving device.
FIG. 3 is a diagram illustrating frequency characteristics of a reception CLK with respect to an input voltage of a VCO in the data reception device.
FIG. 4A is a diagram showing a state in which the synchronization signal and the same direction edge (positive edges and negative edges) of the frequency-divided CLK are synchronized, and FIG. It is a figure which shows the state which synchronized the different direction edge (positive edge and negative edge) with frequency division CLK.
FIG. 5 is a diagram illustrating a circuit configuration of a phase difference detector.
FIG. 6 is a diagram illustrating a waveform of a pulse signal output in accordance with a phase difference between a synchronization signal and a half-divided CLK.
FIG. 7 is a diagram illustrating output voltage characteristics of an LPF.
FIG. 8 is a schematic diagram showing a phase relationship between a synchronization signal input to a phase difference detector and a divided CLK by two.
FIG. 9 is a diagram illustrating a circuit configuration of a phase comparator.
FIG. 10 is a diagram showing signal waveforms in the circuit of the phase comparator.
FIG. 11 is a diagram illustrating a configuration of a latch switching unit in the data demodulating unit.
[Explanation of symbols]
10 First PLL circuit
11 Second PLL circuit
20 PLL circuit
30, 31 Phase comparator
32 Phase detector
33, 53, 92 LPF
34 VCO
35 Data demodulator
36, 37 Divider
38, 40, 46 Phase difference signal
42 Enable signal
44 Receive CLK
45 Hold signal
47, 48 2 divided by CLK
49, 50 Phase comparator selector
51, 90 Ex. OR
52, 74, 91 3-state buffer
54, 57, 93 Comparator
55, 70 D-FF
58 AND gate
60 Input signal
61 Sync signal
62 Start bit
63 Information data
71A, 71B Differentiation circuit
72 Asynchronous Set D-FF
73, 81, 82, 352 selector
79 OR gate
84, 353 NOT gate
321, 322 Lock signal

Claims (4)

A data receiving device for receiving transmission data including a synchronization signal and information data,
Pulse generation means for generating a clock pulse;
Selection means for obtaining a phase difference between the same direction edge and the opposite direction edge of the received synchronization signal and the clock pulse generated by the pulse generation means, and selecting a combination of edges having the smallest phase difference;
Phase adjusting means for adjusting the phase of the clock pulse so that the phase difference between the selected edges is eliminated;
A data receiving apparatus comprising: sampling means for sampling the information data based on the clock pulse after the phase adjustment. Dividing the clock pulse generated by the pulse generating means by the same frequency dividing ratio and generating a plurality of divided pulses having different phases from each other,
The selecting means obtains a phase difference between the same-direction edge and the different-direction edge of each of the generated divided pulses and the synchronization signal instead of the clock pulse, and determines a combination of edges having the smallest phase difference. The data receiving device according to claim 1, wherein the data receiving device is selected. If the selected divided pulse is a pulse divided by using the rising edge of the clock pulse as a trigger, the previous period sampling means executes sampling of the previous period information data at the falling edge of the clock pulse, 3. The data receiving apparatus according to claim 2, wherein the data is sampled at the rising edge of the clock pulse when the pulse is divided by using the falling edge as a trigger. Transmission data for the previous period consists of alternating synchronization signals and information data. During the reception of information data, the previous phase adjustment means stops adjusting the frequency and phase of the clock pulse and maintains the previous synchronization state. The data receiving device according to claim 1, wherein the data receiving device is a data receiving device.

Images