JP3960600B2 - Direction finding device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a direction detection device that detects a direction of arrival of a received signal using a super resolution method.
[0002]
[Prior art]
There is known a direction detection device using a so-called super-resolution method in which a plurality of antenna elements are arranged and a reception signal from each antenna element is statistically processed to detect the arrival direction of the reception signal. (For example, refer to Patent Document 1).
[0003]
FIG. 4 shows an example of the configuration of a conventional direction finding device using the super resolution method. In FIG. 4, the direction detecting device 3 includes a plurality (n) of antenna elements 11 to 1n arranged in a specific direction, and a plurality (n) of antenna elements connected corresponding to the plurality (n) of antenna elements. ) Frequency conversion circuits 21 to 2n and a plurality (n) of analog / digital conversion conversion circuits (A / D conversion circuits) connected to the plurality of (n) frequency conversion circuits 21 to 2n, respectively. ) 31 to 3n, a plurality (n) of IQ detection circuits 41 to 4n connected to the plurality of (n) A / D conversion circuits 31 to 3n, and a plurality of (n) IQs. A plurality (n) of memory circuits 51 to 5n connected corresponding to the detection circuits 41 to 4n, respectively, and a plurality (n) of the plurality of (n) memory circuits 51 to 5n connected correspondingly. Phase adjustment circuits 61 to 6n, And a superresolution processing circuit 7 for being connected in common to these multiple (n) pieces of phase adjustment circuits 61 to 6n.
[0004]
In the above-described configuration, the signals with unknown arrival directions received by the antenna elements 11 to 1n are first converted into intermediate frequency signals by the frequency conversion circuits 21 to 2n, and then digitally converted by the A / D conversion circuits 31 to 3n. Converted to a signal. Next, phase detection is performed by digital signal processing in the IQ detection circuits 41 to 4n, and the output data is stored in the memory circuits 51 to 5n. When the stored detection output data is read out from the super-resolution processing circuit 7 at an appropriate timing, the phase adjustment circuits 61 to 6n perform phase correction caused by variations in the transmission line length between the receiving systems. Then, it is sent to the super resolution processing circuit 7. The super resolution processing circuit 7 performs statistical processing on these data to calculate the direction of arrival of the received signal.
[0005]
Next, an example of a detailed configuration of the super resolution processing circuit 7 is shown in FIG. In FIG. 5, a super-resolution processing circuit 7 is connected in common to a plurality (n) of phase adjustment circuits 61 to 6n corresponding to the antenna elements 11 to 1n, and includes an autocorrelation matrix calculation circuit 71, an eigenvalue / The eigenvector calculation circuit 72, the mode vector calculation circuit 73, the noise subspace projection length calculation circuit 74, and the projection length minimum calculation circuit 75 are configured.
[0006]
In this configuration, when the super-resolution processing circuit 7 receives the data from the phase adjustment circuits 61 to 6n, the auto-correlation matrix calculation circuit 71 first calculates the auto-correlation matrix for these data, and the obtained auto-correlation matrix is obtained. Based on this, the eigenvalue / eigenvector calculation circuit 72 calculates the eigenvalue and eigenvector. From this eigenvector, a signal subspace and a noise subspace characterized by the number of received signals can be extended, and these are orthogonal complement spaces. These eigenvalues and eigenvectors are sent to the noise subspace projection length calculation circuit 74. Further, the mode vector calculation circuit 73 calculates data representing each output of the antenna elements 11 to 1n as a function of the arrival angle of the received signal based on their arrangement, that is, a mode vector, and a noise subspace projection length calculation circuit. 74.
[0007]
On the other hand, in the noise subspace projection length calculation circuit 74, a noise subspace is created based on the eigenvalue and eigenvector from the eigenvalue / eigenvector calculation circuit 72, and the mode vector from the mode vector calculation circuit 73 is projected onto this noise subspace. Then, the projection length is calculated. The calculated projection length is sent to the projection length minimum calculation circuit 75. Then, the projection length minimum calculation circuit 75 calculates the arrival angle at which the projection length of the received mode vector is minimized, and outputs it as the arrival direction of the received signal.
[0008]
As described above, in the direction finding device using the super resolution method, the received signals from the plurality of arranged antenna elements are statistically processed, so that the angle resolution in the arranged direction is increased and the arrival direction of the received signals is increased. Can be detected with high accuracy, and a plurality of targets existing in close proximity within the beam width can be separated.
[0009]
However, when a large number of antenna elements are arranged, the opening area of each antenna element is limited and the antenna gain is limited. In particular, when the signals received by the respective antenna elements are supplied as they are to the subsequent processing circuits as in the conventional direction finding device 3 described above, a sufficient received signal level cannot be secured for a weak signal.
[0010]
For this reason, a super-resolution array antenna device is proposed in which the aperture formed by the arrangement of a large number of antenna elements is divided into a plurality of sub-arrays, and the received signal is synthesized in units of sub-arrays to increase reception sensitivity. (For example, refer to Patent Document 2). When sub-arrays are used to synthesize received signals from multiple (m) antenna elements, it is theoretically possible to obtain a reception sensitivity that is √m times that of a single antenna element. ing.
[0011]
However, by configuring the subarray, the effective coverage is narrowed due to the periodicity of the phase determined by the relationship between the subarray interval and the wavelength of the received signal. Furthermore, since the combination of a plurality of antenna elements constituting each sub-array is fixed when dividing into sub-arrays, it is difficult to set the reception sensitivity of the apparatus appropriately according to the operation status.
[0012]
[Patent Document 1]
Japanese Patent Laid-Open No. 10-268016 (page 7, FIG. 2)
[0013]
[Patent Document 2]
JP-A-8-271609 (page 7, FIG. 1)
[0014]
[Problems to be solved by the invention]
As described above, in the conventional direction finding device using the super-resolution method, the angle resolution is enhanced by arranging a large number of antenna elements, but there is a limit to the antenna gain that can be obtained with each antenna element. In order to solve this problem, it is difficult to secure the coverage when the sub-array is configured to improve the antenna gain.
[0015]
The present invention has been made in consideration of the above-described circumstances, and an object of the present invention is to provide a direction detection device that can appropriately secure reception sensitivity necessary for direction detection without impairing angular resolution and coverage.
[0016]
[Means for Solving the Problems]
In order to achieve the above object, a direction detecting device according to a first aspect of the present invention corresponds to a plurality (n) antenna elements arranged in a specific direction and a plurality (n) antenna elements arranged in a specific direction. A plurality of (n) frequency conversion circuits connected, a plurality (n) A / D conversion circuits connected corresponding to the plurality (n) frequency conversion circuits, and a plurality (n) of these A plurality of (n) IQ detection circuits connected corresponding to the A / D conversion circuits, and a plurality (n) memory circuits connected corresponding to the plurality (n) IQ detection circuits; A plurality of (n) phase adjustment circuits connected to the plurality of (n) memory circuits, and outputs from the plurality (n) phase adjustment circuits, the antenna elements constituting the sub-array Were shifted one by one according to the order of the sequence based on the number (m) of A plurality of (n−m + 1) combining circuits combined in a combination of each, and a plurality of (n−m + 1) combining circuits connected in common, and a signal subspace and a noise subspace which is an orthogonal complement space thereof, And a super-resolution processing circuit for detecting the direction of arrival of the signals received by the plurality of (n) antenna elements arranged as described above.
[0017]
The direction detecting device of the second aspect of the invention includes a plurality (n) of antenna elements arranged in a specific direction and a plurality (n) of antenna elements connected corresponding to the arranged (n) antenna elements. ) Frequency conversion circuits, a plurality (n) A / D conversion circuits connected to the plurality (n) frequency conversion circuits, and a plurality (n) A / D conversion circuits. (N) IQ detection circuits connected corresponding to the plurality, (n) memory circuits connected corresponding to the (n) IQ detection circuits, and these (n) A plurality of (n) phase adjustment circuits connected corresponding to a plurality of memory circuits, and the number of the antenna elements constituting a sub-array that is set in advance with outputs from the plurality (n) phase adjustment circuits Shifted one by one according to the order of the sequence based on (m) A combination circuit that combines each combination and outputs (n−m + 1) combined signals, and is connected to the combination circuit and arranged in a signal subspace and a noise subspace that is its orthogonal complement space. And a super resolution processing circuit for detecting the arrival direction of signals received by a plurality of (n) antenna elements.
[0018]
According to the present invention, a signal received by a plurality (n) of antenna elements is obtained by combining a plurality (m) of combinations obtained by shifting one by one according to the arrangement order of the antenna elements (n By performing super-resolution processing on the (−m + 1) synthesized signals, a direction finding device with improved reception sensitivity can be obtained without impairing the effective coverage.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a direction finding device according to the present invention will be described below with reference to FIGS. The same components as those of the conventional direction detecting device 3 and the super resolution circuit 7 shown in FIGS. 4 and 5 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0020]
(First embodiment)
FIG. 1 is a configuration diagram showing a first embodiment of a direction finding device according to the present invention. The direction detecting device 1 includes a plurality (n) of antenna elements 11 to 1n arranged in a specific direction and a plurality (n) of frequencies connected to the plurality of (n) antenna elements. Conversion circuits 21 to 2n and a plurality (n) of analog / digital conversion conversion circuits (A / D conversion circuits) 31 to 3n connected to the plurality of (n) frequency conversion circuits 21 to 2n, respectively. A plurality (n) of IQ detection circuits 41 to 4n connected to the plurality of (n) A / D conversion circuits 31 to 3n, and a plurality of (n) IQ detection circuits 41 to 41 A plurality (n) of memory circuits 51 to 5n connected corresponding to 4n and a plurality (n) of phase adjustments connected corresponding to the plurality (n) of memory circuits 51 to 5n, respectively. Circuits 61 to 6n, and these (n ) A plurality (n) of combinations of m, which is the number of antenna elements constituting the sub-array, while shifting the outputs from the phase adjustment circuits 61 to 6n one by one according to the arrangement order of the antenna elements 11 to 1n. −m + 1) synthesis circuits 81 to 8 (n−m + 1), and a super-resolution processing circuit 7 commonly connected to the plurality (n−m + 1) synthesis circuits 81 to 8 (n−m + 1) It is composed of
[0021]
Further, as shown in FIG. 5, the super resolution processing circuit 7 includes an autocorrelation matrix calculation circuit 71, an eigenvalue / eigenvector calculation circuit 72, a mode vector calculation circuit 73, a noise subspace projection length calculation circuit 74, And a projection length minimum calculation circuit 75. In the super resolution processing circuit 7, a signal subspace characterized by the number of received signals and a noise subspace that is an orthogonal complement space are stretched based on the data from the synthesis circuits 81 to 8 (n−m + 1). An eigenvector that can be used is calculated, and the mode vector is projected onto the noise subspace to determine the arrival direction of the received signal.
[0022]
In the above configuration, the signals with unknown arrival directions received by the antenna elements 11 to 1n are first converted into intermediate frequency signals in the frequency conversion circuits 21 to 2n, and then converted into digital signals in the A / D conversion circuits 31 to 3n. Is converted to Next, phase detection is performed by digital signal processing in the IQ detection circuits 41 to 4n, and the output data is stored in the memory circuits 51 to 5n. When the stored detection output data is read out from the super-resolution processing circuit 7 at an appropriate timing, the phase adjustment circuits 61 to 6n perform phase correction caused by variations in the transmission line length between the receiving systems. The corrected detection output data 61a to 6na are sent to the synthesis circuits 81 to 8 (n−m + 1).
[0023]
In the combining circuits 81 to 8 (n−m + 1), the corrected detection output data 61a to 6na from the phase adjustment circuits 61 to 6n are m pieces of antenna elements 11 to 1n, which are the number of antenna elements constituting the subarray. They are synthesized in combinations that are shifted one by one according to the sequence. At this time, the combination of these data synthesized in each of the synthesis circuits is as follows when, for example, 10 antenna elements (n = 10) and the number of antenna elements constituting the subarray is 4 (m = 4). become that way. That is, the number of combining circuits is seven (n−m + 1). First, the combining circuit 81 combines the data from the phase adjustment circuits 61 to 64 corresponding to the reception signals of the four antenna elements 11 to 14, and The composite data 81a is output. Next, the combining circuit 82 shifts by one in the arrangement order of the antenna elements, combines the data from the phase adjustment circuits 62 to 65 corresponding to the reception signals of the antenna elements 12 to 15, and outputs the combined data 82a. Thereafter, they are sequentially synthesized in the same combination, and the synthesis circuit 87 synthesizes the data from the phase adjustment circuits 67 to 610 and outputs synthesized data 87a. The synthesized data 81 a to 8 (n−m + 1) a from these synthesis circuits are sent to the super resolution processing circuit 7.
[0024]
When the super resolution processing circuit 7 receives the composite data 81a to 8 (n−m + 1) a, the autocorrelation matrix calculation circuit 71 first calculates an autocorrelation matrix for these data as shown in FIG. Next, the eigenvalue and eigenvector calculation circuit 72 calculates the eigenvalue and eigenvector based on the obtained autocorrelation matrix. From this eigenvector, a signal subspace and a noise subspace characterized by the number of received signals can be extended, and these are orthogonal complement spaces. Then, the calculation result is sent to the noise subspace projection length calculation circuit 74. The mode vector calculation circuit 73 calculates data representing each output of the antenna elements 11 to 1n as a function of the arrival angle of the received signal based on their arrangement, that is, a mode vector, and similarly calculates a noise subspace projection length. It is sent to the circuit 74.
[0025]
On the other hand, in the noise subspace projection length calculation circuit 74, a noise subspace is created based on the eigenvalue and eigenvector from the eigenvalue / eigenvector calculation circuit 72, and the mode vector from the mode vector calculation circuit 73 is projected onto this noise subspace. Then, the projection length is calculated. The calculated projection length is sent to the projection length minimum calculation circuit 75. Then, the projection length minimum calculation circuit 75 calculates the arrival angle at which the projection length of the received mode vector is minimized, and outputs it as the arrival direction of the received signal.
[0026]
In the first embodiment of the present invention, the signals received by a plurality (n) of antenna elements 11 to 1n are respectively one by one according to the order of arrangement, which is m, which is the number of antenna elements constituting the subarray. Super-resolution processing is performed on (n−m + 1) synthesized signals obtained by synthesizing with the shifted combinations. FIG. 2 shows the relationship between the antenna gain, the angular resolution, and the coverage when a sub-array is formed and a received signal is synthesized.
[0027]
FIG. 2 (a) shows a case where the sub-array in the present invention is configured and a received signal is synthesized, and FIG. 2 (b) models a case where the sub-array is not configured. In FIG. 2 (a), the signals received by the antenna elements 11 to 1n are combined by being overlapped between the subarrays, so that the antenna spacing is the same as when the subarray is not configured (FIG. 2 (b)). Since the sub-arrays are arranged, the antenna gain can be increased without narrowing the desired coverage, and the receiving sensitivity of direction detection can be improved.
[0028]
(Second Embodiment)
FIG. 3 is a block diagram showing a second embodiment of the direction finding device according to the present invention. The direction detection device 2 is different from the first embodiment described above in the circuit configuration between the phase adjustment circuits 61 to 6n and the super resolution processing circuit 7, and only the difference will be described.
[0029]
The direction detecting device 2 according to the second embodiment includes a selection / synthesis circuit 9 and a subarray element number setting circuit 10. The selection combining circuit 9 combines the corrected detection output data 61a to 6na from the phase adjustment circuits 61 to 6n based on the number m of antenna elements constituting the subarray from the subarray element number setting circuit 10, and the combined data 9a1 to 9a. (N−m + 1) is sent to the super resolution processing circuit 7. The subarray element number setting circuit 10 sends the number m of antenna elements constituting the subarray preset by the setting operation to the selection / combination circuit 9.
[0030]
In the above-described configuration, the corrected detection output data 61a to 6na from the phase adjustment circuits 61 to 6n are output from the antenna elements 11 to 1n by m, which is the number of antenna elements constituting the sub-array, in the selection / synthesis circuit 9. They are combined in a combination shifted one by one according to the arrangement order, and (n−m + 1) pieces of combined data 9a1 to 9a (n−m + 1) are output. Here, m is the number of antenna elements constituting the sub-array set by the sub-array element number setting circuit 10, and the value can be changed by setting operation.
[0031]
The combined data 9 a 1 to 9 a (n−m + 1) output from the selection combining circuit 9 includes, for example, ten antenna elements (n = 10), and the number of antenna elements constituting the sub-array from the sub-array element number setting circuit 10 is four. In the case of (m = 4), it is as follows. That is, the number of combined data to be output is seven (n−m + 1), and combined data 9a1 that combines the data from the phase adjustment circuits 61 to 64 corresponding to the reception signals of the four antenna elements 11 to 14 and the antenna The synthesized data 9a2 obtained by synthesizing the data from the phase adjustment circuits 62 to 65 corresponding to the received signals of the elements 12 to 15, and then synthesized by a combination shifted one by one in the arrangement order of the antenna elements 11 to 1n. Seven data up to synthesized data 9a7 obtained by synthesizing data from the phase adjustment circuits 67 to 610 corresponding to 110 received signals are output.
[0032]
On the other hand, when the number m of antenna elements constituting the sub-array is changed to 3, for example, from the state described above by the setting operation, the output from the selective combining circuit 9 is as follows. That is, the number of combined data to be output is eight (n−m + 1), and combined data 9a1 that combines the data from the phase adjustment circuits 61 to 63 corresponding to the reception signals of the three antenna elements 11 to 13 and the antenna The synthesized data 9a2 obtained by synthesizing the data from the phase adjustment circuits 62 to 64 corresponding to the received signals of the elements 12 to 14, and then synthesized by a combination shifted one by one in the order of arrangement of the antenna elements 11 to 1n. Eight data of the combined data 9a8 obtained by combining the data from the phase adjustment circuits 68 to 610 corresponding to the received signal 110 are output.
[0033]
The synthesized data from these selective synthesis circuits is sent to the super resolution processing circuit 7, and the super resolution processing circuit 7 performs statistical processing to calculate the arrival direction of the received signal.
[0034]
In the second embodiment of the present invention, the signals received by a plurality (n) of antenna elements 11 to 1n are respectively one by one according to the order of arrangement, which is the number m of antenna elements constituting the subarray. Super-resolution processing is performed on (n−m + 1) synthesized signals obtained by synthesizing with the shifted combinations. Thereby, similarly to the first embodiment of the present invention, it is possible to improve the direction detection reception sensitivity while ensuring the coverage.
[0035]
Further, in the present embodiment, the antenna gain of the subarray can be changed by changing the setting of the number m of antenna elements constituting the subarray. As a result, it is possible to obtain appropriate reception sensitivity according to the operation status of the apparatus.
[0036]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, the direction detection apparatus which can ensure the coverage area of direction detection and can improve a receiving sensitivity appropriately according to an operation condition can be obtained.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing a first embodiment of a direction finding device according to the present invention.
FIG. 2 is an explanatory diagram modeling the relationship between antenna gain and coverage when a received signal is synthesized by configuring a sub-array.
FIG. 3 is a configuration diagram showing a second embodiment of the direction finding device according to the present invention.
FIG. 4 is a configuration diagram showing an example of a conventional direction finding device using a super resolution method.
FIG. 5 is a configuration diagram showing an example of a super resolution processing circuit.
[Explanation of symbols]
1, 2 and 3 direction detection device 7 super resolution processing circuit 9 selection synthesis circuit 10 subarray element number setting circuit 11 to 1n antenna element 21 to 2n frequency conversion circuit 31 to 3n A / D conversion circuit 41 to 4n IQ detection circuit 51 to 5n memory circuits 61 to 6n phase adjustment circuits 81 to 8 (n−m + 1) synthesis circuit

Claims (2)

A plurality (n) of antenna elements arranged in a specific direction;
A plurality of (n) frequency conversion circuits connected corresponding to the plurality of (n) antenna elements arranged;
A plurality of (n) A / D conversion circuits connected to the plurality of (n) frequency conversion circuits;
A plurality (n) of IQ detection circuits connected corresponding to the plurality of (n) A / D conversion circuits;
A plurality (n) of memory circuits connected to the plurality of (n) IQ detection circuits;
A plurality (n) of phase adjustment circuits connected to the plurality of (n) memory circuits;
A plurality (n) of combinations of the outputs from the plurality (n) of phase adjustment circuits are combined in units of m, which are shifted one by one according to the arrangement order based on the number (m) of the antenna elements constituting the subarray. -M + 1) synthesis circuits;
Arrival of signals received by a plurality of (n) antenna elements arranged in common by a signal subspace and a noise subspace which is an orthogonal complement space connected in common to the plurality (n−m + 1) combining circuits. A direction detection apparatus comprising a super-resolution processing circuit for detecting a direction. A plurality (n) of antenna elements arranged in a specific direction;
A plurality of (n) frequency conversion circuits connected corresponding to the plurality of (n) antenna elements arranged;
A plurality of (n) A / D conversion circuits connected to the plurality of (n) frequency conversion circuits;
A plurality (n) of IQ detection circuits connected corresponding to the plurality of (n) A / D conversion circuits;
A plurality (n) of memory circuits connected to the plurality of (n) IQ detection circuits;
A plurality (n) of phase adjustment circuits connected to the plurality of (n) memory circuits;
The outputs from the multiple (n) phase adjustment circuits are combined in m combinations that are shifted one by one in accordance with the arrangement order based on the number (m) of the antenna elements constituting the preset subarray. A combining circuit that outputs (n−m + 1) combined signals;
A super-resolution processing circuit that is connected to this synthesis circuit and detects the direction of arrival of signals received by a plurality of (n) antenna elements arranged in the signal subspace and a noise subspace that is an orthogonal complementary space thereof. A direction detecting device characterized by comprising:

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