JP3943117B2 - Active matrix display device and driving method thereof - Google Patents

Description

  The present invention relates to an active matrix display device capable of improving display quality by reducing flicker and a driving method thereof.

  An active matrix liquid crystal display device is known as one of conventional image display devices. As shown in FIG. 19, the liquid crystal display device includes a liquid crystal panel 1, a scanning line driving circuit 2, a signal line driving circuit 3, and a buffer circuit 4.

  The liquid crystal panel 1 includes a matrix substrate 11, a counter substrate 12 provided in parallel with the matrix substrate 11, and liquid crystal (not shown) filled between the substrates 11 and 12. On the matrix substrate 11, a plurality of scanning lines G (0)... G (3) and a plurality of signal lines S (0)... S (3) intersecting with each other, and display cells 13 arranged in a matrix form. Is provided. On the counter substrate 12, the counter electrode 16 shown in FIG. 19 is provided in common for each display cell 13. Here, although the case where the counter electrode 16 is provided on the counter substrate 12 is shown, there is an IPS (In Plane Switching) structure in which the counter electrode 16 is provided on the matrix substrate 12.

As shown in FIG. 20, the display cell 13 includes a thin film transistor (TFT) 14 that is a switching element and a liquid crystal capacitor _CLC . The source of the TFT 14 is connected to the signal line S (i), and the gate of the TFT 14 is connected to the scanning signal line G (j). The display electrodes 15 serving as one electrode of the liquid crystal capacitance C _LC, the signal lines output from the driving circuit 3 to the signal line S (i) a signal voltage Vsp · Vsn the drain voltage Vd through the source and drain of the TFT 14 ( i, j). In addition, the counter electrode 16 serving as the other electrode of the liquid crystal capacitance C _LC, a common voltage Vcom is applied to output from the buffer circuit 4.

As a result, when the potential difference between the drain voltage Vd (i, j) and the common voltage Vcom is applied to the liquid crystal capacitor _CLC , the transmittance or reflectance of the liquid crystal 17 sandwiched between the electrodes 15 and 16 is modulated. , An image corresponding to the input image data is displayed on the display cells 13. Furthermore, in each display cell 13, since the charge accumulated in the liquid crystal capacitance C _LC is held for a certain period, even if OFF is TFT14 display of the image is maintained accordingly.

A method of displaying images by scanning (writing) one after another as in the above driving method is called a refresh method. The write signal voltage Vsp · Vsn to the display cell 13, is further period to hold the signal voltage Vsp · Vsn by the liquid crystal capacitance C _LC, is called a refresh period.

In this liquid crystal display device, as shown in FIG. 21, when a gate pulse having a potential difference (Vgh−Vgl) is output from the scanning line driving circuit 2 to the scanning line G (j) in the first refresh period Tv1, the TFT 14 Is turned on, the positive signal voltage Vsp output from the signal line drive circuit 3 to the signal line S (i) during that time is written into the display cell 13 and thereafter held by the liquid crystal capacitor _CLC . In the next refresh period Tv1, the negative signal voltage Vsn output from the signal line driving circuit 3 to the signal line S (i) is similarly written to the display cell 13 while the TFT 14 is ON. Held. In the liquid crystal display device, in order to prevent the deterioration of the liquid crystal due to the application of the DC voltage, the liquid crystal is AC-driven, for example, for each dot by repeatedly applying such signal voltages Vsp and Vsn having different polarities.

The luminance characteristics of the liquid crystal is held in the liquid crystal capacitance C _LC, determined by the effective value of the voltage difference between the signal voltage Vsp · Vsn and the common voltage Vcom (effective voltage Vrms (P1) · Vrms (N1 )) . Therefore, if the effective voltages Vrms (P1) · Vrms (N1) are not equal, a change in luminance occurs at each refresh period, so that flicker appears in the display image. As a result, the display quality is significantly lowered and residual DC that causes deterioration of the liquid crystal is applied to the liquid crystal.

In order to eliminate the above inconvenience, the conventional liquid crystal display device is provided with an offset adjustment circuit 31 made of a variable resistor, for example, as shown in FIG. In the offset adjustment circuit 31, the power supply voltage Vref is adjusted by the offset adjustment circuit 31 so that the effective voltages Vrms (P1) and Vrms (N1) are equal to each other, thereby changing the common voltage Vcom. Flicker can be suppressed by adjusting the common voltage Vcom.
JP-A-8-184809, date of publication: July 16, 1996 JP 2000-56738 A, date of publication: February 25, 2000

  Incidentally, depending on the liquid crystal display device, as shown in FIG. 21, a high-speed refresh display mode (display mode A) in which display is performed in a short refresh period Tv1, and a low-speed refresh display mode (display mode B in which display is performed in a long refresh period Tv2). ) And display may be switched. In this case, even if the signal voltages Vsp and Vsn are written and held, the effective voltages Vrms (P2) and Vrms (N2) in the refresh periods Tv2 and Tv2 are not equal. This is due to the following operating characteristics of the TFT.

First, as shown in FIG. 21, when the signal voltage Vsp is written and held, the TFT off voltage Voff (P) is the difference between the high holding potential and the potential Vgl, and when the signal voltage Vsn is written and held, The off voltage Voff (N) of the TFT is the difference between the low holding potential and the potential Vgl. Further, as shown in the characteristics of Vgd-Id (Vgd indicates a gate-drain voltage and Id indicates a drain current) in FIG. 22, the TFT is not an ideal switch, and a leak current flows even when it is off. The leakage current corresponding to the off voltage Voff (N) is different in magnitude from the leakage current corresponding to the off voltage Voff (P). For this reason, in both cases where the signal voltages Vsp and Vsn are written and held, the amount of leakage discharge at the time of holding the voltage is different. As a result, the effective voltage Vrms (P2) and Vrms (N2) based on the common voltage Vcom are Will fall, and these will be imbalanced. Therefore, since the influence becomes more prominent when the refresh cycle becomes longer, a luminance change occurs every time the refresh cycle changes. As a result, flicker occurs and the quality of the display image is remarkably lowered.

  Note that the case where the refresh cycle changes is the case where the display mode is changed by computer display, the case where the TV display mode (NTSC or PAL) is switched, and the case where low frequency driving or pause driving is performed for the purpose of reducing power consumption. .

  Further, the effective voltage Vrms (P2) · Vrms (N2) is also imbalanced by a leakage current generated in the liquid crystal itself and other factors (a leakage current of the liquid crystal capacitance itself). Therefore, in order to suppress the occurrence of flicker due to these factors, it is necessary to eliminate the above-described imbalance in effective voltage regardless of the length of the refresh period.

  The present invention has been made in view of the above circumstances, and provides an active matrix display device and a driving method thereof that can eliminate an imbalance in effective voltage even when refresh periods of different lengths are mixed. It is intended to provide.

  In the active matrix display device and the driving method thereof according to the present invention, a plurality of display electrodes provided in a matrix, a counter electrode provided opposite to the display electrode to which a common voltage is applied, and a scanning line are selected. In an active matrix display device comprising: an active element that writes a signal voltage to the display electrode when it is applied; and a storage capacitor that holds a drive voltage determined by the signal voltage written to the display electrode and a common voltage. In order to solve this problem, the level of the signal voltage is varied by the level changing means in accordance with the length of the write holding period for writing the signal voltage and holding the drive voltage.

  For example, in the liquid crystal display device, as described above, since the optical response of the liquid crystal is determined by the effective value of the drive voltage held in the storage capacitor, the drive voltage varies depending on the length of the write holding period (refresh period). Effective value is different. On the other hand, the effective value of the driving voltage determined by the signal voltage and the common voltage is changed by changing the level of the signal voltage by the level changing means of the display device.

  In order to change the level of the signal voltage, it is preferable that an AC voltage is used as the signal voltage, and the amplitude central potential of the AC voltage is set as the level to be different for each write holding period having a different length. As described above, when the signal voltage is alternating current, the effective value of the drive voltage is changed by changing the amplitude center potential (level).

  In the above driving method, it is preferable to provide a non-scanning period during which a signal voltage is not written after the scanning period in which the signal voltage is written to the display electrodes for one screen. In this way, scanning is not performed in the non-scanning period, so that the drive-related circuits can be paused.

  In the above driving method, the active matrix display device is preferably a reflective active matrix liquid crystal display device including a reflective electrode in the display electrode.

  As described above, the active matrix display device and the driving method thereof according to the present invention include a plurality of display electrodes provided in a matrix, and a counter electrode provided to face the display electrodes and to which a common voltage is applied. An active matrix type comprising an active element for writing a signal voltage to the display electrode when a scanning line is selected, and a holding capacitor for holding a drive voltage determined by the signal voltage written to the display electrode and a common voltage In the display device, the signal voltage is written and the level of the signal voltage is varied according to the length of the write holding period for holding the drive voltage.

  In this way, by changing the level of the signal voltage, the effective value of the drive voltage determined by the signal voltage and the common voltage is changed. In order to change the level of the signal voltage, it is preferable to use a plurality of AC voltages as the signal voltage, and to switch the amplitude center potential of the AC voltage as the level by the voltage switching means for each of the write holding periods having different lengths. . Therefore, the imbalance in the effective value of the drive voltage can be eliminated by appropriately changing the amplitude center potential of the AC voltage. Therefore, it is possible to suppress the occurrence of flicker and improve the quality of the display image.

  In the above driving method, a driving-related circuit is provided in the non-scanning period by providing a non-scanning period in which the signal voltage is not written after the scanning period in which the signal voltage is written to the display electrodes for one screen. Can be paused. Therefore, power consumption can be reduced. In addition, even if an imbalance occurs in the holding voltage between the positive and negative polarities due to the leakage characteristics of the TFT, the occurrence of such an imbalance can be avoided by not performing scanning in the non-scanning period.

  In the above driving method, the active matrix display device is a reflective active matrix liquid crystal display device including a reflective electrode in the display electrode, so that a reflective active matrix type driven at a low frequency in a portable information terminal or the like. The effect of flicker that tends to appear in a liquid crystal display device can be greatly reduced.

  The active matrix display device and the driving method thereof according to the present invention are suitable for use in, for example, a reflective active matrix liquid crystal display device used for a portable information terminal or the like. Even if the low-speed refresh display mode that emphasizes power is switched as necessary, the influence of flicker that tends to appear in such a liquid crystal display device can be greatly reduced.

[Reference Form 1]
First, a first reference embodiment that is a reference of the present invention will be described with reference to FIGS. 1 to 3 and FIG.

  As shown in FIG. 1, the liquid crystal display device according to the first embodiment has a liquid crystal panel 1, a scanning line driving circuit 2, a signal line driving circuit 3, and a buffer circuit as in the conventional liquid crystal display device described above. 4, but an offset voltage setting unit 5 and a control unit 6 are further added.

  The liquid crystal panel 1 includes a matrix substrate 11, a counter substrate 12 provided in parallel with the matrix substrate 11, and liquid crystal (not shown) filled between the substrates 11 and 12. On the matrix substrate 11, a plurality of scanning lines G (0)... G (3) and a plurality of signal lines S (0)... S (3) intersecting with each other, and display cells 13 arranged in a matrix form. Is provided.

As shown in FIG. 20, the display cell 13 is surrounded by two adjacent scanning lines G (j) · G (j + 1) and two adjacent signal lines S (i) · S (i + 1). Formed in the region. The display cell 13 includes a thin film transistor (hereinafter referred to as TFT) 14 that is a switching element, and a liquid crystal capacitor _CLC . Depending on the panel, an auxiliary capacitor may be provided in parallel with the liquid crystal capacitor _CLC , but the description thereof is omitted for the sake of simplicity.

  The TFT 14 has a gate connected to the scanning line G (j) and a source signal connected to the signal line S (i). The source signals are the positive signal voltage Vsp and the negative signal voltage Vsn. When displaying a plurality of gradations, signal voltages for positive polarity and negative polarity may be required, respectively, but the description thereof is omitted for simplification.

The liquid crystal capacitor C _LC includes a display electrode 15 connected to the TFT 14, a counter electrode 16 facing the display electrode 15, and a liquid crystal 17 sandwiched between the electrodes 15 and 16. The counter electrode 16 is provided on the counter substrate 12 so as to be common to all the display cells 13.

In such a display cell 13, the display electrode 15 is connected to the signal line S (i) through the drain and source of the TFT 14, and the gate of the TFT 14 is connected to the scanning line G (j). Further, the common voltage Vcom output from the buffer circuit 4 is applied to the counter electrode 16. As a result, a voltage is written from the signal line S (i) while the TFT 14 is ON, and the transmittance or reflectance of the liquid crystal is modulated by the potential difference between this voltage and the common voltage Vcom. An image corresponding to the input image data is displayed. Furthermore, in each display cell 13, the charge accumulated in the liquid crystal capacitance C _LC is held for a certain period, even if OFF is TFT14 display of the image is maintained accordingly.

  The scanning line driving circuit 2 shifts a start pulse given from the outside at the timing of the clock, and further passes a gate pulse to be described later for selecting the scanning lines G (0)... G (3) via the buffer circuit. Output. On the other hand, the signal line driving circuit 3 shifts the start pulse given from the outside at the timing of the clock, samples the video data based on the shift pulse, and holds it to hold the video data for one line in the buffer circuit. To the scanning lines S (0)... S (3).

  The offset setting unit 5 includes resistors 5a and 5b and a changeover switch 5c.

  In both resistors 5a and 5b as voltage setting means, a DC reference potential Vref1 is applied to one end and the other end is grounded. Further, the resistors 5a and 5b are variable resistors, so that the offset can be adjusted, and the first voltage Vcom1 and the second voltage Vcom2 are taken out from the respective taps. The first voltage Vcom1 is input to one contact of the changeover switch 5c, and the second voltage Vcom2 is input to the other contact of the changeover switch 5c. The change-over switch 5c switches either the first voltage Vcom1 or the second voltage Vcom2 that is input in accordance with a control signal CONT1 from the control unit 6 described later, and outputs it to the buffer circuit 4.

  The buffer circuit 4 outputs one of the input first voltage Vcom1 or second voltage Vcom2 to the counter electrode 16 as a common voltage Vcom. The first voltage Vcom1 is the voltage level of the common voltage Vcom in the display mode A in which high speed refresh is performed, and the second voltage Vcom2 is the voltage level of the common voltage Vcom in the display mode B in which low speed refresh is performed.

  The control unit 6 is a system controller including a CPU and the like, and has a function of switching between the display mode A and the display mode B. For example, when the present liquid crystal display device is incorporated into a mobile phone, in display mode A, a high-speed refresh operation is performed in a normal display state such as during a call. In the display mode B, a low-speed refresh operation is performed in the minimum necessary display state such as during standby. In a general liquid crystal display device used for a television or a computer monitor, the following display modes A and B may be used. For example, the display modes A and B may be changed by changing the display mode by computer display, switching the TV display mode (NTSC or PAL), low frequency drive or pause drive for the purpose of reducing power consumption. There is a case.

  Here, the switching operation of the common voltage Vcom in the liquid crystal display device configured as described above will be described.

When attention is paid to an arbitrary display cell 13 and the liquid crystal 17 is AC driven for each writing scan, as shown in FIG. 2, in the display mode A, in the first refresh period Tv1, the potential difference ( When a gate pulse (gate ON voltage Vgh, gate OFF voltage Vgl) of (Vgh−Vgl) is output from the scanning line driving circuit 2 to the scanning line G (j), the TFT 14 is turned on. The signal voltage Vsp having the positive polarity output from 3 to the signal line S (i) is written into the display cell 13 and thereafter held by the liquid crystal capacitor _CLC . In the next refresh period Tv1, the negative signal voltage Vsn output from the signal line driving circuit 3 to the signal line S (i) is similarly written to the display cell 13 while the TFT 14 is ON. Held.

  In the display mode A, in the offset voltage setting unit 5, the changeover switch 5 c is switched to the resistor 5 a side by the “H” level control signal CONT 1 from the control unit 6. As a result, the first voltage Vcom1 is selected as the common voltage Vcom and applied to the counter electrode 16. Then, the effective voltage Vrms (P1) applied to the liquid crystal 17 in the first refresh period Tv1 and the effective voltage Vrms (N1) applied to the liquid crystal 17 in the next refresh period Tv1 are determined based on the first voltage Vcom1. Are almost equal.

  On the other hand, in the display mode B, similarly to the display mode A, the signal voltage Vsp is written and held in the first refresh period Tv2, and the signal voltage Vsn is written and held in the next refresh period Tv2. Is called. However, in the display mode B, in the offset voltage setting unit 5, the changeover switch 5c is switched to the resistor 5b side by the “L” level control signal CONT1 from the control unit 6. As a result, the common voltage Vcom is switched to the second voltage Vcom2 higher than the first voltage Vcom1 and applied to the counter electrode 16. Then, the effective voltage Vrms (P3) applied to the liquid crystal 17 in the first refresh period Tv2 and the effective voltage Vrms (N3) applied to the liquid crystal 17 in the next refresh period Tv2 are determined based on the second voltage Vcom2. Are almost equal.

  As described above, in the liquid crystal display device according to the first embodiment, the offset voltage setting unit 5 switches the level of the common voltage Vcom according to the display modes A and B having different refresh periods Tv1 and Tv2. Yes. Thereby, different common voltages Vcom (first and second voltages Vcom1 and Vcom2) are set in the refresh periods Tv1 and Tv2. Therefore, the common voltage Vcom is appropriately set as described above for the imbalance between the positive effective voltage and the negative effective voltage caused by the difference in the leakage discharge amount when the TFT 14 is turned off between the display modes A and B. Can be almost eliminated.

Therefore, flicker appearing in the displayed image is greatly suppressed, and the quality of the display image can be improved. In the first embodiment, the storage capacitor is composed only of the liquid crystal capacitor _CLC . However, the auxiliary capacitor may be configured by combining the liquid crystal capacitor _CLC and the auxiliary capacitor. The electrode structure may be a so-called IPS mode configuration in which the counter electrode 16 is formed on the matrix substrate 11.

  Subsequently, a modified example of the first embodiment will be described.

  In the liquid crystal display device according to this modification, as shown in FIG. 3A, the offset voltage setting unit 5 includes resistors 5e to 5h as voltage setting means instead of the resistors 5a and 5b described above. Instead of the changeover switch 5c, a changeover switch 5i is provided.

  A reference potential Vref1 is applied to one end of each of the resistors 5e and 5f. The other end of the resistor 5e is connected to one contact of the changeover switch 5i, and the other end of the resistor 5f is connected to the other contact of the changeover switch 5i. One ends of the resistors 5g and 5h are both grounded. The other end of the resistor 5g is connected to one contact of the changeover switch 5i, and the other end of the resistor 5h is connected to the other contact of the changeover switch 5i.

  The changeover switch 5 i connects the contact point to which the resistors 5 e and 5 g are connected to the buffer circuit 4 when the control signal CONT 1 from the control unit 6 is at “H” level. The changeover switch 5i connects the contact point to which the resistors 5f and 5h are connected to the buffer circuit 4 when the control signal CONT1 is at "L" level.

  In such a configuration, in the display mode A, in the offset voltage setting unit 5, the changeover switch 5i connects the resistors 5e and 5g in series, so that the reference potential Vref1 is divided by the resistors 5e and 5g and the first voltage is applied. A voltage Vcom1 is obtained. On the other hand, in the display mode B, since the changeover switch 5i connects the resistors 5f and 5h in series, the reference potential Vref1 is divided by the resistors 5f and 5h to obtain the second voltage Vcom2.

  In the offset voltage setting unit 5 using the resistors 5a and 5b described above, a current always flows through the resistors 5a and 5b without being connected to the changeover switch 5c. For this reason, as more display modes having different lengths are set, the number of resistance setting circuits increases, and power consumption increases due to current flowing through all of them. On the other hand, according to the above configuration, since the resistance pair of any one of the resistors 5e and 5g or the resistors 5f and 5h is not connected by the changeover switch 5i, no current flows through the resistance pair. Therefore, even if the number of resistance setting circuits increases as more display modes having different lengths are set, the power consumption does not increase.

  Further, in the liquid crystal display device according to another modification, as shown in FIG. 3B, the offset voltage setting unit 5 includes resistors 5j and 5k connected in series instead of the resistors 5a and 5b in FIG. Have. The resistors 5j and 5k as voltage setting means are variable resistors, and the first voltage Vcom1 and the second voltage Vcom2 are taken out from the respective taps. The first voltage Vcom1 is input to one contact of the changeover switch 5c, and the second voltage Vcom2 is input to the other contact of the changeover switch 5c.

  In such a configuration, in the display mode A, the changeover switch 5c is connected to the low-potential-side resistor 5j in the offset voltage setting unit 5, so that the first voltage Vcom1 is obtained as the common voltage Vcom. On the other hand, in the display mode B, the changeover switch 5c is connected to the high potential side resistor 5k, so that the second voltage Vcom2 is obtained as the common voltage Vcom.

  In the above configuration, since the resistors 5j and 5k are connected in series, even when a larger number of common voltage levels are required as the display modes having different lengths are set, the signal levels can be extracted. The number of taps may be increased. Therefore, even when a large voltage level of the common voltage Vcom is required, the current path through which the current flows does not increase, so that the power consumption does not increase.

  In the first embodiment, a resistor is used as the voltage setting unit. However, a capacitor that can divide the voltage may be used. This is the same in the embodiments and reference embodiments described later.

[Reference form 2]
The second embodiment of the present invention will be described below with reference to FIGS. In the second embodiment, the same reference numerals are given to the components having the same functions as those in the first embodiment, and the description thereof is omitted.

  As shown in FIG. 4, the liquid crystal display device according to the second embodiment is similar to the liquid crystal display device according to the first embodiment described above, the liquid crystal panel 1, the scanning line driving circuit 2, the signal line driving circuit 3, And a buffer circuit 4. Further, the present liquid crystal display device includes an offset voltage setting unit 7 and a control unit 8 instead of the offset voltage setting unit 5 and the control unit 6 (see FIG. 1) of the first embodiment. In the present liquid crystal display device, unlike the liquid crystal display device of the first embodiment, the common voltage Vcom applied to the counter electrode 16 (see FIG. 20) is fixed at a constant value, while the signal voltage Vsp · Vsn applied to the signal line drive circuit 3 is fixed. Is offset according to the display mode.

  The offset voltage setting unit 7 includes resistors 7a to 7d and changeover switches 7e and 7f.

  In each of the resistors 7a to 7d as voltage setting means, the reference potential Vref2 is applied to one end and the other end is grounded. Further, the resistors 7a to 7d are variable resistors, so that the offset can be adjusted. From each tap, the first voltage Vsp1, the second voltage Vsp2, the first voltage Vsn1, and the second voltage Vsn2 can be adjusted. It is taken out.

  The first voltage Vsp1 is input to one contact of the changeover switch 7e, and the second voltage Vsp2 is input to the other contact of the changeover switch 7e. The change-over switch 7e switches either the first voltage Vsp1 or the second voltage sp2 that is input in accordance with a control signal CONT2 from the control unit 8 described later, and outputs it to the signal line drive circuit 3. On the other hand, the first voltage Vsn1 is input to one contact of the changeover switch 7f, and the second voltage Vsn2 is input to the other contact of the changeover switch 7f. The change-over switch 7f switches either the first voltage Vsn1 or the second voltage sn2 input in synchronization with the change-over switch 7e by the control signal CONT2 and outputs it to the signal line drive circuit 3.

  The control unit 8 is a system controller including a CPU and the like, and has a function of switching between the display mode A and the display mode B in the same manner as the control unit 6 (see FIG. 1) of the first embodiment. The control unit 8 outputs an “H” level control signal CONT2 when the display mode A is set, and outputs an “L” level control signal CONT2 when the display mode B is set.

  Here, the switching operation of the signal voltages Vsp and Vsn in the liquid crystal display device configured as described above will be described.

When attention is paid to an arbitrary display cell 13 and the liquid crystal 17 is AC driven for each writing scan, as shown in FIG. 5, in the display mode A, the potential difference ( When a gate pulse (gate ON voltage Vgh, gate OFF voltage Vgl) of (Vgh−Vgl) is output from the scanning line driving circuit 2 to the scanning line G (j), the TFT 14 is turned on. The signal voltage Vsp having the positive polarity output from 3 to the signal line S (i) is written into the display cell 13 and thereafter held by the liquid crystal capacitor _CLC . In the next refresh period Tv1, the negative signal voltage Vsn output from the signal line driving circuit 3 to the signal line S (i) is similarly written to the display cell 13 while the TFT 14 is ON. Held.

  In the display mode A, in the offset voltage setting unit 7, the changeover switches 7 e and 7 f are switched to the resistors 7 a and 7 c by the “H” level control signal CONT 2 from the control unit 8. As a result, the first voltages Vsp1 and Vsn1 are selected as the signal voltages Vsp and Vsn, respectively, and applied to the signal line driving circuit 3. Then, the effective voltage Vrms (P1) applied to the liquid crystal 17 in the first refresh period Tv1 and the effective voltage Vrms (N1 applied to the liquid crystal 17 in the next refresh period Tv1 are determined based on the first voltages Vsp1 and Vsn1. ) Is almost equal.

  On the other hand, in the display mode B, similarly to the display mode A, the signal voltage Vsp is written and held in the first refresh period Tv2, and the signal voltage Vsn is written and held in the next refresh period Tv2. Is called. However, in the display mode B, in the offset voltage setting unit 7, the changeover switches 7e and 7f are switched to the resistances 7b and 7d by the control signal CONT2 of “L” level from the control unit 8. As a result, the signal voltages Vsp and Vsn are switched to the second voltages Vsp2 and Vsn2 lower than the first voltages Vsp1 and Vsn1, respectively, and applied to the signal line drive circuit 3. Then, the effective voltage Vrms (P4) applied to the liquid crystal 17 in the first refresh period Tv2 and the effective voltage Vrms (N4) applied to the liquid crystal 17 in the next refresh period Tv2 are determined based on the second voltages Vsp2 and Vsn2. ) Is almost equal.

  As described above, in the liquid crystal display device according to the present embodiment, the offset voltage setting unit 7 simultaneously switches the levels of the signal voltages Vsp and Vsn according to the display modes A and B having different refresh periods Tv1 and Tv2. I have to. Thus, different signal voltages Vsp · Vsn (first voltage Vsp1 · Vsn1 and second voltage Vsp2 · Vsn2) are set in the refresh periods Tv1 and Tv2, respectively. Therefore, the imbalance between the effective voltage of the positive polarity and the effective voltage of the negative polarity caused by the difference in the amount of leakage discharge when the TFT 14 is turned off between the display modes A and B can be obtained by appropriately adjusting the signal voltages Vsp and Vsn as described above. It can be almost eliminated by setting.

  Therefore, flicker appearing in the displayed image is greatly suppressed, and the quality of the display image can be improved.

  Subsequently, a modification of the second embodiment will be described.

  Also in the liquid crystal display device according to this modification, the configuration as shown in FIGS. 3A and 3B can be adopted as the offset voltage setting unit 7. Specifically, as shown in FIG. 6A, the offset voltage setting unit 7 has resistors 7g to 7n as voltage setting means instead of the resistors 7a to 7d, and the change-over switch 7e. Instead of 7f, changeover switches 7o and 7p are provided.

  In such a configuration, in the display mode A, in the offset voltage setting unit 7, the changeover switch 7o connects the resistors 7g and 7i in series with the control signal CONT2 at the “H” level, and the changeover switch 7p Since 7k · 7m are connected in series, the reference potential Vref2 is divided by the resistors 7g · 7i and 7k · 7m to obtain the first voltage Vsn1 · Vsp1. On the other hand, in the display mode B, the changeover switch 7o connects the resistors 7h and 7j in series and the changeover switch 7p connects the resistors 7l and 7n in series by the “L” level control signal CONT2. Vref2 is divided by resistors 7h · 7j and resistors 7l · 7n to obtain second voltage Vsn2 · Vsp2.

  In the liquid crystal display device according to another modified example, as shown in FIG. 6B, the offset voltage setting unit 7 has resistors 7r to 7u connected in series instead of the resistors 7a to 7d of FIG. ing. The resistors 7r to 7u as voltage setting means are variable resistors, and the first voltage Vsp1, the second voltage Vsp2, the first voltage Vsn1, and the second voltage Vsn2 are taken out from the respective taps. The first voltages Vsp1 and Vsn1 are input to one contact of the changeover switches 7e and 7f, respectively, and the second voltages Vsp2 and Vsn2 are input to the other contact of the changeover switches 7e and 7f, respectively.

  In such a configuration, in the display mode A, the changeover switches 7e and 7f are connected to the resistors 7r and 7t in the offset voltage setting unit 7, so that the first voltages Vsp1 and Vsn1 are obtained as the signal voltages Vsp and Vsn. It is done. On the other hand, in the display mode B, since the changeover switches 7e and 7f are connected to the resistors 7s and 7u, the first voltages Vsp2 and Vsn2 are obtained as the signal voltages Vsp and Vsn.

  In the configuration shown in FIGS. 6A and 6B, as in the configuration of FIGS. 3A and 3B in the first embodiment, the current path through which the current flows when the signal voltage Vsp · Vsn is not output is provided. Since it does not increase, power consumption is not increased.

  In the liquid crystal display device according to another modification, only one of the signal voltages Vsp and Vsn is offset, and the other is fixed to a constant value. In order to realize this, the offset voltage setting unit 7 in FIG. 4 is configured such that, for example, the resistor 7b and the changeover switch 7e are omitted, and the signal voltage Vsp is obtained directly from the resistor 7a. As a result, as shown in FIG. 7, the constant signal voltage Vsp is written and held in the first refresh period Tv2, and switched from the first voltage Vsn1 to the second voltage Vsn2 in the next refresh period Tv2. Writing and holding of the signal voltage Vsn is performed.

  In this liquid crystal display device, since the signal voltage Vsp is fixed to a constant value, the offset amount of the signal voltage Vsn (the absolute value of the difference between the first voltage Vsn1 and the second voltage Vsn2) is the effective voltage Vrms (P5). The effective voltage Vrms (N5) is set to be equal.

  Further, even if the signal voltage Vsn is fixed to a constant value and only the signal voltage Vsp is offset, the effective voltage Vrms (P5) and the effective voltage Vrms (N5) can be made equal.

  In the configuration as described above, since only one of the signal voltages Vsp and Vsn is offset, the configuration of the offset voltage setting unit 7 can be simplified.

[Reference form 3]
The third embodiment of the present invention will be described below with reference to FIGS. In the third embodiment, the same reference numerals are given to components having the same functions as those in the first and second embodiments, and the description thereof is omitted.

  As shown in FIG. 8, the liquid crystal display device according to the third embodiment is similar to the liquid crystal display device according to the second embodiment described above, the liquid crystal panel 1, the scanning line driving circuit 2, the signal line driving circuit 3, A buffer circuit 4 and a control unit 8 are provided. In addition, the present liquid crystal display device includes an offset voltage setting unit 9 instead of the offset voltage setting unit 7 (see FIG. 4) of the reference mode 2. In the present liquid crystal display device, unlike the liquid crystal display device in the second embodiment, the voltage effective value imbalance in the refresh periods Tv1 and Tv2 due to the leakage current when the TFT 14 (see FIG. 20) is off when the refresh cycle is long is corrected. To do.

  The offset voltage setting unit 9 includes resistors 9a to 9d and changeover switches 9e and 9f.

  In each of the resistors 9a to 9d as voltage setting means, the reference potential Vref2 is applied to one end and the other end is grounded. Further, the resistors 9a to 9d are variable resistors, and the offset can be adjusted, and the first voltage Vsp1, the third voltage Vsp3, the first voltage Vsn1, and the third voltage Vsn3 can be adjusted from the respective taps. It is taken out. The third voltages Vsp3 and Vsn3 compensate for the decrease in the holding voltage due to the leakage current when the TFT 14 is off in the refresh period Tv2 in which the voltage holding period is longer than the second voltage Vsp2 and Vsn2 (see FIG. 5). The voltage is taken into account according to the length of the refresh period Tv2.

  The first voltage Vsp1 is input to one contact of the changeover switch 9e, and the third voltage Vsp3 is input to the other contact of the changeover switch 9e. The change-over switch 9e switches either the first voltage Vsp1 or the third voltage sp3 that is input by the control signal CONT2 from the control unit 8 and outputs it to the signal line drive circuit 3. On the other hand, the first voltage Vsn1 is input to one contact of the changeover switch 9f, and the third voltage Vsn3 is input to the other contact of the changeover switch 9f. The changeover switch 9f switches either the first voltage Vsn1 or the third voltage sn3 input in synchronization with the changeover switch 9e by the control signal CONT2 and outputs it to the signal line drive circuit 3.

  In the liquid crystal display device configured as described above, the switching operation of the signal voltages Vsp and Vsn is performed by the offset voltage setting unit 9 in the same manner as the liquid crystal display device of the second embodiment. As a result, in the display mode A, the offset voltage setting unit 9 selects the first voltages Vsp1 and Vsn1 as the signal voltages Vsp and Vsn, respectively, and applies them to the signal line drive circuit 3. Then, the effective voltage Vrms (P1) applied to the liquid crystal 17 in the first refresh period Tv1 and the effective voltage Vrms (N1 applied to the liquid crystal 17 in the next refresh period Tv1 are determined based on the first voltages Vsp1 and Vsn1. ) Is almost equal.

  On the other hand, in the display mode B, the signal voltages Vsp and Vsn are written and held in the same manner as in the display mode A. However, here, writing and holding of the third voltage Vsp3 higher than the first voltage Vsp1 is performed in the first refresh period Tv2, and writing and holding of the third voltage Vsn3 lower than the first voltage Vsn1 are performed in the next refresh period Tv2. Retention is performed.

  In the liquid crystal display device of Reference Mode 2, if the amount of leak discharge when the TFT 14 is turned off increases due to the longer refresh period Tv2, the holding voltage is greatly reduced in the refresh period Tv2. Therefore, as shown in FIG. 5 of the second embodiment, when the signal voltage Vsp / Vsn having the same amplitude is applied in the refresh periods Tv1 and Tv2, | Vrms (P1) | = | Vrms (N1) | and | Vrms Even if (P4) | = | Vrms (N4) |, | Vrms (P1) |> | Vrms (P4) | and | Vrms (N1) |> | Vrms (N4) |, the refresh period Tv2 The display quality at is reduced.

  On the other hand, in the liquid crystal display device according to the third embodiment, since the third voltage Vsp3 · Vsn3 including the compensation for the leakage discharge amount is applied as the signal voltage in the refresh period Tv2, the effective voltage Vrms (N1) · Vrms (N6), Vrms (P1), and Vrms (P6) are all equal, and display quality can be maintained even if the refresh period is different.

  Of course, the offset voltage setting unit 9 of the present liquid crystal display device may be configured in the same manner as the offset voltage setting unit 7 of FIGS. 6A and 6B in the second embodiment. As a result, an increase in power consumption can be avoided also in the present liquid crystal display device.

Embodiment
An embodiment of the present invention will be described with reference to FIGS. 10 to 12 as follows. In the present embodiment, components having the same functions as those of the reference embodiments 1 and 2 described above are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 10, the liquid crystal display device according to the present embodiment is similar to the liquid crystal display device according to the second embodiment described above, the liquid crystal panel 1, the scanning line driving circuit 2, the signal line driving circuit 3, A buffer circuit 4 and a control unit 8 are provided. In addition, the present liquid crystal display device includes an offset voltage setting unit 21 instead of the offset voltage setting unit 7 (see FIG. 4) according to the second embodiment. In the present liquid crystal display device, unlike the liquid crystal display device of the reference embodiment 2, as shown in FIG. 11, the source signal Vs is inverted every horizontal line, and the amplitude central potential of the source signal Vs, that is, the level of the source signal Vs is set. Offset. As will be described later, the source signal Vs is a pulse signal Vs (ref having the amplitude of the difference between the signal voltage Vsp (first voltage Vsp1 and second voltage sp2) and the signal voltage Vsn (first voltage Vsn1 and second voltage sn2). ) (See FIG. 10).

  As shown in FIG. 10, the offset voltage setting unit 21 includes resistors 21a and 21b, a changeover switch 21c, and an AC coupling capacitor 21d.

  In each of the resistors 21a and 21b, the reference potential Vref3 is input to one end, and the other end is grounded. Further, the resistors 21a and 21b are variable resistors, so that the offset can be adjusted, and the amplitude center potential Vs (offset1) on the high potential side and the amplitude center potential Vs (offset2) on the low potential side from each tap. And are taken out.

  The amplitude center potential Vs (offset1) is input to one contact of the changeover switch 21c, and the amplitude center potential Vs (offset2) is input to the other contact of the changeover switch 21c. The changeover switch 21 c switches either the amplitude center potential Vs (offset 1) or the amplitude center potential Vs (offset 2) that is input according to the control signal CONT 2 from the control unit 8 and outputs it to the signal line drive circuit 3. The AC coupling capacitor 21d has an amplitude of a difference between the signal voltages Vsp and Vsn at one end, and a pulse signal Vs (ref) for determining the polarity for each horizontal line is input, and the other end is an output terminal of the changeover switch 21c. Connected to the side.

  In the liquid crystal display device configured as described above, the offset voltage setting unit 21 outputs either the amplitude center potential Vs (offset1) or the amplitude center potential Vs (offset2) by the switching operation of the changeover switch 21c. Then, the pulse signal Vs (ref) from which the DC component is removed by the AC coupling capacitor 21d is superimposed on it. As a result, different source signals Vs1 and Vs2 are applied to the signal line drive circuit 3 in the refresh periods Tv1 and Tv2, respectively.

  First, in display mode A, the offset voltage setting unit 21 selects the source signal Vs1 and applies it to the signal line drive circuit 3. Then, as shown in FIG. 11, in the first refresh period Tv1, the first voltage Vsp1 · Vsn1 (value in the circle) of the source signal Vs1 is written and held during the gate pulse period, while the next refresh period At Tv1, the voltage of the first voltage Vsn1 of the source signal Vs1 is written and held during the gate pulse period. At this time, the effective voltage Vrms (P1) applied to the liquid crystal 17 in the first refresh period Tv1 and the effective voltage Vrms (N1) applied to the liquid crystal 17 in the next refresh period Tv1 are the first voltages Vsp1 and Vsn1. It is almost equal by setting the value of.

  On the other hand, in the display mode B, the offset voltage setting unit 21 selects the source signal Vs2. Then, similarly to the display mode A, the second voltage Vsp2 · Vsn2 (value in a circle) of the source signal Vs2 is written and held. As a result, the effective voltage Vrms (P7) and the effective voltage Vrms (N7) are substantially equal to each other as in the liquid crystal display device according to the second embodiment.

  As described above, in the liquid crystal display device according to the present embodiment, the quality of the display image can be improved by offsetting the source signal Vs that is inverted every horizontal line as in the liquid crystal display device according to the second embodiment. it can.

  In this embodiment, the amplitudes of the source signals Vs (source signals Vs1 and Vs2) are constant, but the amplitudes of the source signals Vs1 and Vs2 may be varied. Specifically, the amplitude of the source signal Vs2 is set larger than the amplitude of the source signal Vs1.

  As shown in FIG. 12, the source voltage Vs1 and Vs2 having different amplitudes are generated by the offset voltage setting unit 21 using AC coupling capacitors 21e and 21f instead of the aforementioned AC coupling capacitors 21d, and amplitude changing means. As a resistor 21g (variable resistor). One end of the AC coupling capacitor 21e is input with the pulse signal Vs (ref), and the other end is connected to an input terminal on the resistor 21b side of the changeover switch 21c. One end of the AC coupling capacitor 21f receives the pulse signal Vs (ref) via the resistor 21g, and the other end is connected to the input terminal on the resistor 21a side of the changeover switch 21c.

  In the offset voltage setting unit 21, the source signal Vs1 having a small amplitude is obtained by reducing the amplitude of the pulse signal Vs (ref) by the resistor 21g. On the other hand, the source signal Vs2 having a larger amplitude than the source signal Vs1 is obtained from the AC coupling capacitor 21e. When such source signals Vs1 and Vs2 having different amplitudes are used, a voltage including the amount of leakage discharge compensation is applied to the refresh period Tv2 as in the liquid crystal display device of the third embodiment. Therefore, the effective voltages Vrms (N1), Vrms (N2), Vrms (P1), and Vrms (P2) can all be made equal.

[Reference form 4]
The fourth embodiment of the present invention will be described below with reference to FIGS. In this reference embodiment, components having functions equivalent to those of the components in the above-described reference embodiment 1 are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 13, the liquid crystal display device according to the fourth embodiment has a liquid crystal panel 1, a scanning line driving circuit 2, a signal line driving circuit 3, A buffer circuit 4 and a control unit 6 are provided. Further, the present liquid crystal display device includes an offset voltage setting unit 22 in place of the offset voltage setting unit 5 (see FIG. 1) of the first embodiment. In the present liquid crystal display device, unlike the liquid crystal display device of the first embodiment, as shown in FIG. 14, a common signal Vcom (AC) that is inverted every horizontal line is used as a common voltage (AC voltage), and the common signal The amplitude center potential of Vcom (AC), that is, the level of the common signal Vcom (AC) is offset. The common signal Vcom (AC) has an amplitude that is the difference between the minimum value and the maximum value, and is provided outside the offset voltage setting unit 22 and is inverted (a pulse signal Vcom (ref) described later). From a well-known circuit for generating.

  As shown in FIG. 13, the offset voltage setting unit 22 includes resistors 22a and 22b, a changeover switch 22c, and AC coupling capacitors 22d and 22e.

  The resistors 22a and 22b as voltage setting means both have a constant reference potential Vref input at one end and the other end grounded. Further, the resistors 22a and 22b are variable resistors, so that the offset can be adjusted, and the amplitude center potential Vcom (offset1) on the high potential side and the amplitude center potential Vcom (offset2) on the low potential side from each tap. And are taken out.

  The amplitude center potential Vcom (offset1) is input to one contact of the changeover switch 22c, and the amplitude center potential Vcom (offset2) is input to the other contact of the changeover switch 22c. The changeover switch 22c switches either the amplitude center potential Vcom (offset1) or the amplitude center potential Vcom (offset2) that is input by the control signal CONT1 from the control unit 6 and outputs it to the counter electrode 16 (see FIG. 20). To do. The AC coupling capacitors 22d and 22e both receive a pulse signal Vcom (ref) that is inverted every horizontal line at one end. The other end of the AC coupling capacitor 22d is connected to an input terminal on the side of the resistor 22a in the changeover switch 22c, and the other end of the AC coupling capacitor 22e is connected to an input terminal on the side of the resistor 22b in the changeover switch 22c.

  In the liquid crystal display device configured as described above, the offset voltage setting unit 22 outputs either the amplitude center potential Vcom (offset1) or the amplitude center potential Vcom (offset2) by the switching operation of the changeover switch 22c. Then, the pulse signal Vcom (ref) from which the DC component is removed by the AC coupling capacitors 22d and 22e is superimposed on it. As a result, the first and second signals Vcom1 and Vcom2 that are different in the refresh periods Tv1 and Tv2 are applied to the counter electrode 16, respectively.

First, in the display mode A, the first signal Vcom1 is selected as the common signal Vcom (AC) by the offset voltage setting unit 22 and applied to the counter electrode 16. Then, as shown in FIG. 14, in the first refresh period Tv1, the difference voltage (value in a circle) between the voltage of the source signal Vs captured during the gate pulse period and the common signal Vcom (AC) is written. On the other hand, in the next refresh period Tv1, the difference voltage having the opposite polarity to the above difference voltage is written and held during the gate pulse period. At this time, the effective voltage Vrms (P1) of the liquid crystal driving voltage V _CLC in the first refresh period Tv1 and the effective voltage Vrms (N1) of the liquid crystal driving voltage V _CLC in the next refresh period Tv1 are values of the first signal Vcom1. It is almost equal by setting.

  In FIG. 14, the source signal Vs is drawn as a direct current for simplification, but in actuality, it may be a pulse signal having the same phase or opposite phase to the common signal Vcom (AC). When the source signal Vs is 2V DC and the common signal Vcom (AC) has a minimum value of 0V and a maximum value of 4V, the polarity of the liquid crystal drive voltage is inverted between ± 2V.

  On the other hand, in the display mode B, the offset signal setting unit 22 selects the second signal Vcom2 as the common signal Vcom (AC). Then, similarly to the display mode A, the differential voltage (value in the circle) is written and held. As a result, the effective voltage Vrms (P8) and the effective voltage Vrms (N8) are substantially equal, as in the liquid crystal display device of the first embodiment.

  As described above, in the liquid crystal display device according to the fourth embodiment, the liquid crystal display according to the first embodiment is also obtained by offsetting the amplitude center potential (common voltage level) of the common signal Vcom (AC) that is inverted every horizontal line. Similar to the apparatus, the quality of the display image can be improved.

[Reference Form 5]
The fifth embodiment of the present invention will be described below with reference to FIGS. In this reference embodiment, components having the same functions as those in the reference embodiment 4 described above are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 15, the liquid crystal display device according to the fifth embodiment is similar to the liquid crystal display device according to the fourth embodiment described above, the liquid crystal panel 1, the scanning line driving circuit 2, the signal line driving circuit 3, A buffer circuit 4 and a control unit 6 are provided. Further, the present liquid crystal display device includes an offset voltage setting unit 23 instead of the offset voltage setting unit 22 (see FIG. 13) of the fourth embodiment. In the present liquid crystal display device, the amplitude center potential of the common signal Vcom (AC) is offset in the refresh periods Tv1 and Tv2 as in the liquid crystal display device in the fourth embodiment, but the amplitude is further varied.

  The offset voltage setting unit 23 includes resistors 23a and 23b, a changeover switch 23c, and an AC coupling capacitor 23d having functions equivalent to those of the resistors 22a and 22b, the changeover switch 22c, and the AC coupling capacitors 22d and 22e in the offset voltage setting unit 22, respectively. -It has 23e, and also has resistance 23f as an amplitude change means. Unlike the offset voltage setting unit 22, the offset voltage setting unit 23 inputs the pulse signal Vcom (ref) to the AC coupling capacitor 23d via a resistor 23f that is a variable resistor.

  In the offset voltage setting unit 23, the amplitude of the pulse signal Vcom (ref) is reduced by the resistor 23f, and the first common voltage Vcom1 having the reduced amplitude AC1 is obtained. On the other hand, the second common voltage Vcom2 having the amplitude AC2 larger than the amplitude AC1 is obtained from the AC coupling capacitor 23e. Thereby, not only the center potential but also the first and second common voltages Vcom1 and Vcom2 having different amplitudes are obtained. The common voltages Vcom1 and Vcom2 are applied to the counter electrode 16 in the refresh periods Tv1 and Tv2.

First, in the display mode A, the first common voltage Vcom1 is selected as the common signal Vcom (AC) by the changeover switch 23 and applied to the counter electrode 16. Then, as shown in FIG. 16, in the first refresh period Tv1, the difference voltage (value in the circle) between the voltage of the source signal Vs captured during the gate pulse period and the first common voltage Vcom1 is written and held. On the other hand, in the next refresh period Tv1, the difference voltage having the opposite polarity to the above-described difference voltage is written and held during the gate pulse period. At this time, the effective voltage Vrms (P1) of the liquid crystal driving voltage V _CLC in the first refresh period Tv1 and the effective voltage Vrms (N1) of the liquid crystal driving voltage V _CLC in the next refresh period Tv1 are the first common voltage Vcom1. It is almost equal by setting the value.

On the other hand, in the display mode B, the changeover switch 23 selects the second common signal Vcom2 as the common signal Vcom (AC). Then, similarly to the display mode A, the differential voltage (value in the circle) is written and held. Thereby, the effective voltage Vrms (P9) and the effective voltage Vrms (N9) are substantially equal to each other as in the liquid crystal display device of the first embodiment. In addition, since the amplitude of the common signal Vcom (AC) is increased in the refresh period Tv2, the amplitude of the liquid crystal driving voltage V _CLC is increased. Therefore, similarly to the liquid crystal display device of Reference Embodiment 3 described above, a long refresh period Tv2 can prevent a decrease in holding voltage caused by leak discharge when the TFT 14 is turned off. Therefore, the effective voltages Vrms (N1), Vrms (N9), Vrms (P1), and Vrms (P9) can all be made equal.

  Further, in the liquid crystal display device according to the fifth embodiment, as in the liquid crystal display device according to the fourth embodiment, the quality of the display image can be improved by offsetting the common signal Vcom (AC) that is inverted every horizontal line. Can do.

In FIG. 16, the source signal Vs is drawn as a direct current for simplification, but in actuality, it may be a pulse signal having the same or opposite phase as the common signal Vcom (AC). In the display mode A, when the source signal Vs is DC of 2V and the common signal Vcom (AC) is AC of 4V, the polarity of the liquid crystal driving voltage V _CLC is inverted between ± 2V. Similarly, in the display mode B, when the source signal Vs is DC of 2V, and the amplitude of the common signal Vcom (AC) (difference between H level and L level) is the same 5V AC, the liquid crystal drive voltage V _CLC reverses polarity between voltages of ± 2.5V.
In such a case, the effective voltages Vrms (N1), Vrms (N9), Vrms (P1), and Vrms (P9) are all equal.

  In the present embodiment and the above-described reference embodiment, the AC driving method for field or frame inversion or line inversion has been described. However, the present invention is also applicable to other known inversion driving methods such as dot inversion and source inversion. it can.

Further, in the present embodiment and the above-described reference embodiment, the driving method of the liquid crystal display device and the liquid crystal display device using the same have been described. However, a liquid crystal with a so-called auxiliary capacitor in which the liquid crystal capacitor and the auxiliary capacitor are configured in parallel. The present invention can also be applied to a display device or an IPS mode liquid crystal display device in which a counter electrode is provided on the same matrix substrate side as the TFT. Further, the display device is not limited to an active matrix liquid crystal display device, but may be an EL (Electro Luminescence) display device or the like. The display device can be mounted on a mobile phone, a pocket game machine, a PDA (Personal Digital Assistants), a mobile TV, a remote control, a notebook personal computer, and other mobile terminals. These portable devices are often driven by a battery, and are equipped with a display device capable of reducing power consumption while maintaining good display quality, thereby facilitating long-time driving.

  Further, in the present embodiment and the above-described reference embodiment, the voltage state of each display cell 13 is held in a non-scanning period longer than the scanning period after the scanning period in which writing to the display cells 13 for one screen is completed. You may do it. Thereby, since scanning is not performed in the non-scanning period, the driving-related circuit can be paused. Therefore, power consumption can be reduced. Further, as described above, when the period during which the display cell 13 holds the voltage becomes long, the holding voltage is unbalanced between the positive and negative polarities due to the leakage characteristics of the TFT. On the other hand, as described above, the level of the common voltage Vcom and the common signal Vcom (AC) or the signal voltage Vsp · Vsn and the source signal Vs (in the case of alternating current, the amplitude center potential) is made different, so that such an imbalance can be obtained. Can be avoided.

[Configuration of liquid crystal display device]
Here, a configuration example of the liquid crystal display device common to the above-described embodiment and reference embodiment will be described with reference to FIGS. Here, a reflective liquid crystal display device having an auxiliary capacitor provided in parallel with the liquid crystal capacitor will be described as an example.

FIG. 17 shows a cross-sectional configuration of the liquid crystal panel 1. This figure corresponds to a CC cross-sectional view of FIG. The liquid crystal panel 1 is a reflective active matrix liquid crystal panel, in which a liquid crystal 17 such as a nematic liquid crystal is sandwiched between a matrix substrate 11 and a counter substrate 12, and TFTs 14 as active elements are formed on the matrix substrate 11. It has a basic configuration. In this embodiment, a TFT is used as an active element, but an active element other than MIM (Metal Insulator Metal) or TFT can also be used. On the upper surface of the counter substrate 12, a phase difference plate 41, a polarizing plate 42, and an antireflection film 43 for controlling the state of incident light are provided in this order. An RGB color filter 44 and a transparent counter electrode 16 are provided in this order on the lower surface of the counter substrate 12. Color display is possible by the color filter 44.

  In each TFT 14, a part of the scanning line provided on the matrix substrate 11 is used as a gate electrode 45, and a gate insulating film 46 is formed thereon. An i-type amorphous silicon layer 47 is provided at a position facing the gate electrode 45 across the gate insulating film 46, and two n + -type amorphous silicon layers 48 are formed so as to sandwich the channel region of the i-type amorphous silicon layer 47. ing. A data electrode 49 forming a part of a signal line is formed on the upper surface of one n + -type amorphous silicon layer 48, and the drain electrode extends from the upper surface of the other n + -type amorphous silicon layer 48 to the upper surface of the flat portion of the gate insulating film 46. 50 is drawn out and formed. One end of the drain electrode 50 on the side opposite to the extraction start position is connected to a rectangular auxiliary capacitance electrode pad 15a facing the auxiliary capacitance wiring 53 as shown in FIG. An interlayer insulating film 51 is formed on the upper surface of the TFTs 14. A reflective electrode 15 b is provided on the upper surface of the interlayer insulating film 51. The reflective electrodes 15b are reflective members for performing reflective display using ambient light. In order to control the direction of light reflected by the reflective electrodes 15b, fine irregularities are formed on the surface of the interlayer insulating film 51.

  Further, each reflective electrode 15 b is electrically connected to the drain electrode 50 through a contact hole 52 provided in the interlayer insulating film 51. That is, the voltage applied from the data electrode 49 and controlled by the TFT 14 is applied from the drain electrode 50 to the display electrode 15 through the contact hole 52, and the liquid crystal 17 is driven by the voltage between the reflective electrode 15 b and the counter electrode 16. Driven. That is, the auxiliary capacitor electrode pad 15 a and the reflective electrode 15 b are electrically connected to each other, and the liquid crystal 17 is interposed between the reflective electrode 15 b and the counter electrode 16. As described above, the auxiliary capacitor electrode pad 15 a and the reflective electrode 15 b constitute the pixel electrode 15. In the case of a transmissive liquid crystal display device, a transparent electrode arranged so as to correspond to each of the electrodes is a pixel electrode.

  Further, the liquid crystal panel 2 includes a scanning line G (j)... For supplying a scanning signal to the gate electrode 45 of the TFT 14 as shown in FIG. Signal lines S (i)... For supplying data signals to the data electrodes 49 are provided on the matrix substrate 11 so as to be orthogonal to each other. Further, auxiliary capacity wirings 53 as auxiliary capacity electrodes for forming auxiliary capacity of pixels are provided between the auxiliary capacity electrode pads 15a. The auxiliary capacitance wirings 53... Are formed on the matrix substrate 11 at positions other than the scanning lines G (j)... On the matrix substrate 11 so that a part of the auxiliary capacitance wirings 53 and the auxiliary capacitance electrode pads 15a. j) It is provided in parallel with. The auxiliary capacitance lines 53 are not limited to this case, and may be provided so as to avoid the positions of the scanning lines G (j). In FIG. 18, the reflective electrodes 15b are partially omitted so that the positional relationship between the auxiliary capacitor electrode pads 15a and the auxiliary capacitor wirings 53 becomes clear. Moreover, the unevenness | corrugation of the surface of the interlayer insulation film 51 in FIG. 17 is not illustrated in FIG.

  Since the reflective active matrix liquid crystal display device as described above does not require a backlight that consumes a large amount of power, the reflective active matrix liquid crystal display device suitably used for portable information terminals including mobile phones is used. Thus, even if the high-speed refresh display mode that supports moving image display and the low-speed refresh display mode that emphasizes power saving are switched as necessary, the influence of flicker that tends to appear in such a liquid crystal display device should be greatly reduced. Can do.

It is a block diagram which shows the structure of the liquid crystal display device which concerns on the 1st reference form of this invention. It is a wave form diagram which shows the drive operation | movement of the said liquid crystal display device. (A) And (b) is a circuit diagram which shows the other structure of the offset voltage setting part in the said liquid crystal display device. It is a block diagram which shows the structure of the liquid crystal display device which concerns on the 2nd reference form of this invention. FIG. 5 is a waveform diagram showing a driving operation of the liquid crystal display device of FIG. 4. (A) And (b) is a circuit diagram which shows the other structure of the offset voltage setting part in the liquid crystal display device of FIG. It is a wave form diagram which shows the drive operation of the liquid crystal display device which concerns on the modification of the 2nd reference form of this invention. It is a block diagram which shows the structure of the liquid crystal display device which concerns on the 3rd reference form of this invention. It is a wave form diagram which shows the drive operation of the liquid crystal display device of FIG. It is a block diagram which shows the structure of the liquid crystal display device which concerns on embodiment of this invention. FIG. 11 is a waveform diagram showing a driving operation of the liquid crystal display device of FIG. 10. It is a block diagram which shows the structure of the liquid crystal display device which concerns on the modification of embodiment of this invention. It is a block diagram which shows the structure of the liquid crystal display device which concerns on the 4th reference form of this invention. It is a wave form diagram which shows the drive operation of the liquid crystal display device of FIG. It is a block diagram which shows the structure of the liquid crystal display device which concerns on the 5th reference form of this invention. FIG. 16 is a waveform diagram showing a driving operation of the liquid crystal display device of FIG. 15. It is sectional drawing which shows the structure of the liquid crystal display device which concerns on embodiment and reference form of this invention. It is a top view which shows the structure of the liquid crystal display device of FIG. It is a block diagram which shows the structure of the conventional liquid crystal display device. It is an equivalent circuit diagram which shows the structure of the display cell in the conventional and liquid crystal display device of this invention. It is a wave form diagram which shows the drive operation | movement of the conventional liquid crystal display device. It is a graph which shows the general operating characteristic of TFT.

Explanation of symbols

5. 7, 9 Offset voltage setting means (level changing means)
5a / 5b resistance (voltage setting means)
5e-5h Resistance (voltage setting means)
5i selector switch (voltage switching means)
7e, 7f changeover switch (voltage switching means)
7p / 7g selector switch (voltage switching means)
7r-7u resistance (voltage setting means)
6.8 Control unit 9e / 9f changeover switch (voltage switching means)
9a-7d resistance (voltage setting means)
14 TFT (active element)
15 Display electrode 16 Counter electrode 17 Liquid crystal 21 Offset voltage setting means (level changing means)
21c selector switch (voltage switching means)
21a / 21b resistance (voltage setting means)
21g resistance (amplitude changing means)
22.23 Offset voltage setting means (level changing means)
22c selector switch (voltage switching means)
22a / 22b resistance (voltage setting means)
23a / 23b resistance (voltage setting means)
23c selector switch (voltage switching means)
23f Resistance (amplitude changing means)
G (j) Scan line Tv1, Tv2 Refresh period (write retention period)

Claims (8)

A plurality of display electrodes provided in a matrix, a counter electrode provided opposite to the display electrode, to which a common voltage is applied, and an active element that writes a signal voltage to the display electrode when a scanning line is selected And a driving method for driving an active matrix display device comprising a holding capacitor for holding a driving voltage determined by a signal voltage written to the display electrode and a common voltage,
An AC voltage is used as the signal voltage, and a voltage that compensates for a decrease in holding of the driving voltage is added to the amplitude center potential of the AC voltage according to the length of the writing holding period that is a period of holding the driving voltage. for each of the write holding period are different, the driving method of the active matrix display device characterized by varying the amplitude center potential of the AC voltage. 2. The driving of an active matrix display device according to claim 1, wherein the amplitude center potential of the AC voltage when the write holding period is short is higher than the amplitude center potential when the write holding period is long. Way . A plurality of display electrodes provided in a matrix, a counter electrode provided opposite to the display electrode, to which a common voltage is applied, and an active element that writes a signal voltage to the display electrode when a scanning line is selected And a driving method for driving an active matrix display device comprising a holding capacitor for holding a driving voltage determined by a signal voltage written to the display electrode and a common voltage,
An AC voltage is used as the signal voltage, and a voltage that compensates for a decrease in the holding of the driving voltage is added to the amplitude of the AC voltage according to the length of the writing holding period that holds the driving voltage . A driving method of an active matrix display device, characterized in that the amplitude of the AC voltage is varied every time the holding period is different. 4. The method of driving an active matrix display device according to claim 3, wherein the amplitude of the AC voltage when the write holding period is long is larger than the amplitude when the write holding period is short . After the scanning period for writing a signal voltage to the display electrodes of one screen, longer than the scanning period, claims 1 and providing a non-scan period not to write the signal voltage in any one of 4 A driving method of the active matrix display device described. The active matrix display device, an active matrix display device according to any one of claims 1 to 5, characterized in that a reflective active matrix liquid crystal display device comprising a reflective electrode on the display electrode Driving method. A plurality of display electrodes provided in a matrix, a counter electrode provided opposite to the display electrode, to which a common voltage is applied, and an active element that writes a signal voltage to the display electrode when a scanning line is selected And an active matrix display device comprising a storage capacitor that holds a driving voltage determined by a signal voltage written to the display electrode and a common voltage,
Level change means for writing the signal voltage and changing the level of the signal voltage according to the length of the write holding period for holding the drive voltage,
The level changing means adds a voltage that compensates for the holding decrease of the driving voltage to the level of the signal voltage according to the length of the writing holding period, and increases the amplitude center potential of the AC voltage as the signal voltage. An active matrix display device characterized in that it is varied for each of the different write holding periods. 8. The active matrix according to claim 7 , wherein the level changing means includes amplitude changing means for changing the amplitude of the AC voltage as the signal voltage for each of the write holding periods having different lengths. Type display device.

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