JP3938801B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, for example, a synchronous SRAM (Static Random Access Memory) having a sense amplifier drive timing control unit and a technique particularly effective for use in improving its test function.
[0002]
[Prior art]
There is a so-called synchronous SRAM that operates synchronously according to a predetermined clock signal. In addition, such a synchronous SRAM is provided with a so-called sense amplifier drive timing control unit, which automatically controls the phase of the sense amplifier drive signal to the optimum value based on the phase of the dummy data output from the dummy cell. A method for increasing the access time of an eggplant SRAM is known.
[0003]
[Problems to be solved by the invention]
Prior to the present invention, the inventors of the present application developed a synchronous SRAM including a sense amplifier drive timing control unit, and faced the following problems in the process. That is, the sense amplifier drive timing control unit SADC of the synchronous SRAM includes a phase comparison circuit PC, an up / down counter U / DC, and a variable delay circuit VD, as shown in FIG. Among these, the phase comparison circuit PC compares the phase of the sense amplifier drive signal SC output from the variable delay circuit VD and the dummy data DD output from the dummy cell of the dummy array DM, and selects the up signal UP or the down signal DN. Effective level.
[0004]
On the other hand, the up / down counter U / DC includes 6-bit unit counter circuits UCT0 to UCT5 that operate synchronously according to the counter control signal CC output from the counter control circuit CCTL, and the up / down counter U / DC outputs an up signal UP or In response to the effective level of the down signal DN, it is selectively counted up or down. The variable delay circuit VD forms the sense amplifier drive signal SC by delaying the phase of the internal control signal SP output from a clock driver (not shown), and the delay time is output from the up / down counter U / DC. 6-bit complementary output signals S1 * to S32 * (Here, for example, the non-inverted output signal S1 and the inverted output signal S1B are represented by adding * as the complementary output signal S1 *. A so-called inverted signal that is selectively set to a low level when it is enabled is selectively switched in accordance with the end of its name with B. The same applies hereinafter. As a result, the phase of the sense amplifier drive signal SC is controlled so as to have an optimum phase relationship with respect to the dummy data DD, thereby speeding up the access time of the synchronous SRAM.
[0005]
However, in the synchronous SRAM, the function of the sense amplifier drive timing control unit itself is confirmed even though the phase of the sense amplifier drive signal SC that determines the access time is automatically controlled by the sense amplifier drive timing control unit SADC. However, no means for determining the margin is prepared. As a result, it becomes difficult to bring the margin of the sense amplifier drive signal SC close to the limit, and the access time of the synchronous SRAM cannot be increased as expected, and the number of test steps for the synchronous SRAM increases, thereby reducing the cost. Is inhibited.
[0006]
An object of the present invention is to increase the access time of a synchronous SRAM or the like having a sense amplifier drive timing control unit, reduce the number of test steps for the synchronous SRAM or the like, and reduce the cost thereof.
[0007]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0008]
[Means for Solving the Problems]
The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, a test that is selectively specified by setting the mode control signal supplied from the second input terminal to an effective level in a synchronous SRAM or the like that operates synchronously according to the clock signal and includes a sense amplifier drive timing control unit. Set the mode. A counter control signal for synchronizing the up / down counter is generated based on the clock signal in the normal operation mode, and based on the test clock signal supplied from the third input terminal in the test mode. The up signal and the down signal for counting up or down the up / down counter are formed according to the up signal or the down signal output from the phase comparison circuit in the normal operation mode, and the first signal in the test mode. Are formed in accordance with the phase control signal supplied from the input terminal.
[0009]
According to the above-described means, the up / down counter is arbitrarily counted up or down from the external test apparatus based on the phase control amount determined by the automatic control of the sense amplifier drive timing control unit, and the phase of the sense amplifier drive signal Can be controlled arbitrarily. As a result, the margin of the sense amplifier drive signal can be brought close to the limit, the access time of the synchronous SRAM can be increased, and the test man-hours related to the sense amplifier drive timing control unit of the synchronous SRAM can be reduced, thereby reducing the cost. Can be achieved.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing an embodiment of a synchronous SRAM to which the present invention is applied. Based on this figure, the outline of the configuration and operation of the synchronous SRAM of this embodiment will be described first. The circuit elements constituting each block in FIG. 1 are not particularly limited, but are known MOSFETs (metal oxide semiconductor field effect transistors. In this specification, MOSFETs are collectively referred to as insulated gate field effect transistors). It is formed on a single semiconductor substrate such as single crystal silicon by an integrated circuit manufacturing technique. The synchronous SRAM of this embodiment includes nine memory mats MAT0 to MAT8. The configuration and operation of these memory mats will be described by taking the memory mat MAT0 as an example.
[0011]
In FIG. 1, the synchronous SRAM of this embodiment includes nine memory mats MAT0 to MAT8, each of which has 16 memory arrays M0 as represented by the memory mat MAT0. ˜MF (here, additional numbers such as more than 10 memory arrays are represented by alphabets, the same applies hereinafter) are the basic components. Each of memory arrays M0-MF includes a predetermined number of sub-word lines arranged in parallel in the horizontal direction in the drawing and a predetermined set of complementary bit lines arranged in parallel in the vertical direction. Static memory cells are arranged in a lattice form at the intersections of these sub-word lines and complementary bit lines.
[0012]
Memory mats MAT0 to MAT8 further include a predetermined number of main word lines arranged in parallel to the sub word lines of memory arrays M0 to MF, respectively. Sub word lines constituting memory arrays M0 to MF are logically coupled to corresponding main word lines via a sub word line driving circuit (not shown), and these main word lines are coupled to X address decoder XD on the left side. . An X + 1 bit internal X address signal is supplied from the X address buffer XB to the X address decoder XD. The X address buffer XB is supplied with the X address signals AX0 to AXi via the X address signal input terminals AX0 to AXi and the internal clock signal CKI from the clock generation circuit CG.
[0013]
The X address buffer XB captures and holds the X address signals AX0 to AXi inputted from the address input terminals AX0 to AXi according to the internal clock signal CKI, and forms the internal X address signal based on these X address signals. And supplied to the X address decoder XD. The X address decoder XD decodes the internal X address signal supplied from the X address buffer XB, and alternatively sets the corresponding main word lines of the memory mats MAT0 to MAT8 to a selection level such as the ground potential VSS. The selection level of the main word line is combined with unit selection signals U0 to UF output from a unit address decoder UD described later in the sub word line driving circuits of the memory arrays M0 to MF, whereby the memory mats MAT0 to MAT8 are designated. Sub-word lines corresponding to memory arrays M0-MF are alternatively set to a selection level such as power supply voltage VCC.
[0014]
Next, complementary bit lines constituting memory arrays M0 to MF of memory mats MAT0 to MAT8 are coupled to corresponding write drivers W0 to WF, precharge circuits P0 to PF, and Y switches Y0 to YF below. These Y switches Y0 to YF are alternatively connected to corresponding complementary common data lines, and further connected to corresponding sense amplifiers S0 to SF. The write drivers W0 to WF are commonly supplied with 9-bit write data from the data input buffer IB and are commonly supplied with the read / write signal RW from the write enable signal buffer WB. The precharge circuits P0 to PF are commonly supplied with an equalize control signal EQB from a timing generation circuit (not shown), and the Y switches Y0 to YF are commonly provided with a bit line selection signal of a predetermined bit from the Y address decoder YD. Supplied. Further, the read / write signal RW is commonly supplied from the write enable signal buffer WB to the sense amplifiers S0 to SF, and the output signal from the variable delay circuit VD of the sense amplifier drive timing control unit SADC, that is, the sense amplifier drive signal. SC is supplied in common.
[0015]
The write drivers W0 to WF are selectively activated according to the read / write signal RW supplied from the write enable signal buffer WB, and are supplied from the previous access device via the data input terminals DI0 to DI8 and the data input buffer IB. A predetermined complementary write signal is selectively formed based on the 9-bit write data. These complementary write signals are written into selected memory cells of the memory arrays M0 to MF designated via corresponding complementary bit lines.
[0016]
On the other hand, the precharge circuits P0 to PF of the memory mats MAT0 to MAT8 include a predetermined number of unit circuits provided corresponding to the respective complementary bit lines of the memory arrays M0 to MF, and each of these unit circuits has a P channel. Includes three precharge MOSFETs of the type. The precharge MOSFETs constituting the unit circuits of the precharge circuits P0 to PF are selectively turned on in response to the low level of the equalize control signal EQB, and non-inverted and inverted of the corresponding complementary bit lines of the memory arrays M0 to MF. The signal line is precharged to a high level like the power supply voltage VCC.
[0017]
Y switches Y0-YF include a predetermined set of switch MOSFET pairs provided corresponding to the complementary bit lines of memory mats M0-MF. These switch MOSFET pairs are selectively turned on when the corresponding bit of the bit line selection signal output from the Y address decoder YD is set to the high level, and the corresponding complementary bit lines of the memory arrays M0 to MF The complementary common data lines, that is, the corresponding sense amplifiers S0 to SF are selectively connected.
[0018]
The sense amplifiers S0 to SF are selectively activated according to the read / write signal RW supplied from the write enable signal buffer WB and the sense amplifier drive signal SC output from the variable delay circuit VD of the sense amplifier drive timing control unit SADC. Then, the read signal output from the selected memory cell of the memory arrays M0 to MF is amplified. These read signals are alternatively selected by the data selector DSEL and then output from the data output buffer OB to the preceding access device via the data output terminals DO0 to DO8.
[0019]
The synchronous SRAM of this embodiment further includes a dummy array DM, a write driver DW, a precharge circuit DP and a Y switch DY provided corresponding thereto, a clock driver CD, a variable delay circuit VD, a phase comparison circuit PC, A counter control circuit CCTL and a sense amplifier drive timing control unit SADC including an up / down counter U / DC are provided. Among these, the dummy array DM includes a predetermined number of dummy cells that steadily hold data of logic “0”, and a read signal thereof is one of the phase comparison circuits PC of the sense amplifier drive timing control unit SADC as dummy data DD. To the input terminal.
[0020]
The output signal of the variable delay circuit VD, that is, the sense amplifier drive signal SC is supplied to the other input terminal of the phase comparison circuit PC of the sense amplifier drive timing control unit SADC, and the output signal, that is, the up signal up (first up signal). ) And the down signal dn (first down signal) are supplied to the counter control circuit CCTL. The counter control circuit CCTL is further supplied with the internal clock signal CKI from the clock generation circuit CG, and supplied with the 6-bit complementary output signals S1 * to S32 * from the up / down counter U / DC. In a predetermined test mode, a mode control signal, that is, a phase comparison disable signal TPD is supplied via an input terminal TPD (second input terminal), and also via an input terminal TPC (first input terminal). A phase control signal TPC is supplied, and a test clock signal TCK is further supplied via an input terminal TCK (third input terminal).
[0021]
The counter control circuit CCTL is based on the up signal up and the down signal dn, the internal clock signal CKI, the phase comparison disable signal TPD, the phase control signal TPC, and the test clock signal TCK, and the counter control signal CC and the up signal UP (first signal). 2 up signal) and down signal DN (second down signal) are selectively formed and supplied to the up / down counter U / DC. The up / down counter U / DC operates synchronously according to the counter control signal CC. The counter mode is selectively set to the count-up mode when the up signal UP is set to a valid level, that is, a high level, and the down signal DN is valid. When the level is set to the high level, the countdown mode is selectively set.
[0022]
The variable delay circuit VD selectively delays the phase of the internal signal SP output from the clock driver CD corresponding to the complementary output signals S1 * to S32 * of the up / down counter U / DC, and sense amplifier drive signal SC. Is generated. As a result, the sense amplifier drive signal SC has an optimum phase relationship with respect to the dummy data DD, that is, the read speed of the memory array, thereby speeding up the access time of the synchronous SRAM. The specific configuration and operation of each part of the sense amplifier drive timing control unit SADC will be described in detail later.
[0023]
FIG. 2 shows a circuit diagram of an embodiment of the phase comparison circuit PC included in the sense amplifier drive timing control unit SADC of FIG. A specific configuration and operation of the phase comparison circuit PC included in the sense amplifier drive timing control unit SADC of the synchronous SRAM of this embodiment will be described with reference to FIG. FIG. 2 also shows a circuit diagram of the dummy array DM and the corresponding write driver DW and precharge circuit PD. In the following circuit diagrams, MOSFETs with an arrow attached to the channel (back gate) portion are P-channel type, and are distinguished from N-channel MOSFETs without an arrow.
[0024]
In FIG. 2, the dummy array DM includes a predetermined number of dummy cells DC coupled substantially in parallel, and each of these dummy cells DC is P-channel MOSFETs P1 and P2 and N-channel MOSFETs N1 and N2 as illustrated in FIG. including. Among these, the drains connected in common to the MOSFETs P1 and N1 are non-inverted dummy bit lines BDT (here, non-inverted dummy bit lines BDT that are selectively set to the high level when they are enabled) via the N-channel type selection MOSFET N3. The inverted signal is coupled to the end of its name with T or nothing. The same applies to the following, and the commonly coupled drains of the MOSFETs P2 and N2 are inverted via the N-channel type selection MOSFET N4. Coupled to dummy bit line BDB. In this embodiment, the commonly coupled gates of the MOSFETs P1 and N1 constituting the dummy cell DC are coupled to the power supply voltage VCC, and the commonly coupled gates of the MOSFETs P2 and N2 are coupled to the ground potential VSS.
[0025]
Needless to say, the MOSFETs P1 and P2 and the MOSFETs N1 to N4 constituting the dummy cell DC correspond to the P-channel and N-channel MOSFETs constituting the static memory cells of the memory arrays M0 to MF of the memory mats MAT0 to MAT8, respectively. However, the gates of the MOSFETs P1 and N1 are coupled to the power supply voltage VCC, and the gates of the MOSFETs P2 and N2 are coupled to the ground potential VSS, so that the dummy cell DC is inverted with the read level of the non-inverted dummy bit line BDT at the low level. Data of so-called logic “0” that sets the dummy bit line BDB to the high level is constantly held.
[0026]
The gates of selection MOSFETs N3 and N4 of a predetermined number of dummy cells DC provided in the dummy array DM are commonly coupled to a dummy sub word line SWD, and this dummy sub word line SWD is connected to a NOR gate NO1 constituting a sub word line driving circuit. Coupled to the output terminal. One input terminal of the NOR gate NO1 is coupled to the dummy main word line MWDB, and the other input terminal is coupled to the ground potential VSS. As a result, the dummy cell sub word line SWD is selectively set to the high level when the dummy main word line MWDB is set to the low level, and in response to this, the non-inverted dummy bit line BDT and the inverted dummy bit line BDB Then, a read signal of the logic “0” is output.
[0027]
On the other hand, the write driver DW includes a pair of N-channel write MOSFETs N5 and N6 provided between the non-inverted and inverted signal lines of the complementary dummy bit line BD * and the ground potential VSS. The gates of these write MOSFETs N5 and N6 are coupled to the output terminals of NOR gates NO2 and NO3, respectively, and both input terminals of the NOR gates NO2 and NO3 are coupled to the power supply voltage VCC. As a result, the output signals of the NOR gates NO2 and NO3 are constantly set to the low level, and the write MOSFETs N5 and N6 are constantly turned off. As described above, the write driver DW does not substantially function, but corresponds to the capacitive load coupled to the complementary bit lines of the memory arrays M0 to MF of the memory mats MAT0 to MAT8. Can be made.
[0028]
The precharge circuit DP includes three P-channel type precharge MOSFETs P3 to P5 provided between the power supply voltage VCC and the non-inverted and inverted signal lines of the complementary dummy bit line BD *. An equalize control signal EQB is commonly supplied to the gates of these precharge MOSFETs P3 to P5. Thereby, the precharge MOSFETs P3 to P5 constituting the precharge circuit DP are selectively turned on in response to the low level of the equalize control signal EQB, and the non-inverted and inverted signal lines of the complementary dummy bit line BD * are set to the high level. Precharge.
[0029]
Next, although not particularly limited, the phase comparison circuit PC includes two latch circuits in which NAND gates NA1 and NA2 and NA5 and NA6 are cross-coupled. Among these, the other input terminal of the NAND gate NA1 constituting the preceding latch circuit is supplied with an inverted signal of the dummy data DD via the inverter V1, and the other input terminal of the NAND gate NA2 is connected via the inverters V2 and V3. The sense amplifier drive signal SC is supplied.
[0030]
On the other hand, the other input terminal of the NAND gate NA5 constituting the rear stage latch circuit is supplied with an inverted signal of the non-inverted output signal of the previous stage latch circuit by the NAND gate NA3, and the other input terminal of the NAND gate NA6 has its inverted output signal. An inverted signal is supplied by the NAND gate NA4. An output signal of the NOR gate NO5 is commonly supplied to the other input terminals of the NAND gates NA3 and NA4. Further, the output signal of the NAND gate NA5, that is, the non-inverted output signal of the subsequent latch circuit becomes the up signal up after passing through the inverter V5, and the output signal of the NAND gate NA6, that is, its inverted output signal becomes the down signal dn after passing through the inverter V6. .
[0031]
The output signal of the NOR gate NO4 is supplied to one input terminal of the NOR gate NO5, and the inverted signal from the inverter V4 is supplied to the other input terminal. An inverted signal of the dummy data DD is supplied to one input terminal of the NOR gate NO4 via the inverter V1, and the sense amplifier drive signal SC is supplied to the other input terminal via the inverters V2 and V3.
[0032]
As is apparent from the description of the precharge circuit DP, the non-inverted dummy bit line BDT is precharged to a high level such as the normal power supply voltage VCC, and when the dummy sub word line SWD is set to the selected level, the dummy array DM When a predetermined number of dummy cells DC constituting the same are simultaneously selected, they are rapidly brought to the low level. Further, as will be described later, the sense amplifier drive signal SC is normally set to a low level, and is selectively set to a high level at a predetermined timing when the synchronous SRAM is selected in the read mode.
[0033]
When the synchronous SRAM is not selected, the dummy data DD is set to a high level by precharging, and the sense amplifier drive signal SC is set to a low level. For this reason, the other input terminals of the NAND gates NA1 and NA2 are both at the low level, and the non-inverted and inverted output signals of the preceding latch circuit composed of these NAND gates NA1 and NA2 are both at the high level. At this time, the output signal of the NOR gate NO4 is set to the high level by setting the dummy data DD and the sense amplifier drive signal SC to the high level or the low level, respectively, and thereby the output signals of the inverter V4 and the NOR gate NO5 are set to the low level. . The latter-stage latch circuit composed of the NAND gates NA5 and NA6 holds the previous set state or reset state when the output signals of the NAND gates NA3 and NA4 receive the low level of the output signal of the NOR gate NO5 and become high level.
[0034]
When the synchronous SRAM is selected, the dummy data DD changes from a high level to a low level at a timing commensurate with the read operation speed of the memory arrays M0 to MF, and the sense amplifier drive signal SC also has a delay time of the variable delay circuit VD. It is set to high level at a predetermined timing according to the above. At this time, when the phase of the sense amplifier drive signal SC is slightly delayed and the dummy data DD changes to the low level prior to the sense amplifier drive signal SC, the output signal of the NAND gate NA1 constituting the preceding latch circuit becomes the low level first, In response to this, the output signal of the NAND gate NA2 is fixed at the high level regardless of the high level change of the sense amplifier drive signal SC. Further, in response to the low level change of the dummy data DD, the output signal of the NOR gate NO4 becomes the low level, and the output signal of the NOR gate NO5 is temporarily set to the high level for a short time corresponding to the delay time of the inverter V4.
[0035]
That is, the pre-stage latch circuit is in a reset state in response to the dummy data DD changing to the low level prior to the change in the high level of the sense amplifier drive signal SC, but the low level of the non-inverted and inverted output signals and The high level is transmitted to the subsequent latch circuit in response to the temporary high level of the output signal of the NOR gate NO5. As a result, the latter-stage latch circuit is also reset, and in response to this, the up signal up is set to the high level and the down signal dn is set to the low level.
[0036]
On the other hand, when the synchronous SRAM is selected, if the phase of the sense amplifier drive signal SC is slightly faster and the sense amplifier drive signal SC changes to a high level prior to the dummy data DD, the NAND gate NA2 is used in the preceding latch circuit. In response to this, the output signal of the NAND gate NA1 is fixed to the high level regardless of the change in the low level of the dummy data DD. Further, in response to the low level change of the sense amplifier drive signal SC, the output signal of the NOR gate NO4 becomes the low level, and the output signal of the NOR gate NO5 is temporarily set to the high level for a short time corresponding to the delay time of the inverter V4.
[0037]
In other words, the pre-stage latch circuit is in a set state in response to the sense amplifier drive signal SC changing to the high level prior to the change of the low level of the dummy data DD. The low level is transmitted to the subsequent latch circuit in response to the temporary high level of the output signal of the NOR gate NO5. As a result, the latter-stage latch circuit is also set, and in response to this, the up signal up is set to the low level and the down signal dn is set to the high level.
[0038]
As described above, the phase comparison circuit PC of the sense amplifier drive timing control unit SADC compares the phase of the dummy data DD output from the dummy array DM with the phase of the sense amplifier drive signal SC output from the variable delay circuit VD. It acts to selectively set the signal up or the down signal dn to the high level. The up signal up and the down signal dn are supplied to the counter control circuit CCTL. The high level and low level of the up signal up and the down signal dn are set until the next time the output signal of the NOR gate NO5 is temporarily set to the high level, that is, the synchronous SRAM is selected in the read mode next. The dummy data DD and the sense amplifier drive signal SC are held until the phase comparison operation is performed.
[0039]
FIG. 3 shows a circuit diagram of an embodiment of the counter control circuit CCTL included in the sense amplifier drive timing control unit SADC of FIG. Based on this figure, the specific configuration and operation of the counter control circuit CCTL included in the sense amplifier drive timing control unit SADC of the synchronous SRAM of this embodiment will be described.
[0040]
In FIG. 3, the counter control circuit CCTL includes two edge-triggered flip-flops FF1 and FF2 that are substantially connected in series, and another D-type flip-flop FF3. Among them, the internal clock signal CKI is supplied to the non-inverted clock input terminal C of the flip-flops FF1 and FF3, and the inverted clock input terminal CB of the flip-flop FF1 (here, a horizontal line is added above C in the circuit diagram). In the description of the specification, an inverted clock input terminal is indicated by adding B after C. In the following description, the inverted signal is supplied by the inverter V7. The non-inverted clock input terminal C and the inverted clock input terminal CB of the flip-flop FF2 are supplied with the non-inverted output signal Q of the flip-flop FF1, that is, Q1 and the inverted output signal QB, respectively, and the inverted output signal QB, that is, Q2B is , And supplied to the first input terminal of the NAND gate NA7.
[0041]
The phase comparison disable signal TPD is supplied to the data input terminal D of the flip-flop FF3 from the input terminal TPD via the inverters V8 and V9. Further, the non-inverted output signal Q, that is, Q3 of the flip-flop FF3 is supplied to one input terminal of the NAND gate NA9, and the inverted output signal QB, that is, Q3B, is supplied to the third input terminal of the NAND gate NA7. The second input terminal of the NAND gate NA7 is supplied with the non-inverted output signal Q of the flip-flop FF1, that is, Q1, and the other input terminal of the NAND gate NA9 is supplied with the test clock signal from the input terminal TCK via the inverters VA and VB. TCK is supplied.
[0042]
The output signal of the NAND gate NA7 is supplied to one input terminal of the NAND gate NA8, and the output signal of the NAND gate NA9 is supplied to the other input terminal. The output signal of the NAND gate NA8 becomes the counter control signal CC for the counter control circuit CCTL after passing through the inverter VG.
[0043]
From the above, the flip-flops FF1 and FF2 function as so-called frequency dividing circuits, and act to divide the cycle of the internal clock signal CKI by a quarter. Further, the flip-flop FF3 acts as a latch circuit for fetching, and synchronizes the phase comparison disable signal TPD input asynchronously from the external test apparatus with the internal clock signal CKI, so that the test mode of the synchronous SRAM is unstable. It works to prevent it.
[0044]
When the phase comparison disable signal TPD supplied from the external test apparatus via the input terminal TPD is set to the low level and the synchronous SRAM is set to the normal operation mode, the counter control circuit CCTL outputs the inverted output of the flip-flop FF3. Signal Q3B is set to the high level. For this reason, the counter control signal CC is formed based on the non-inverted output signal Q1 of the flip-flop FF1 and the inverted output signal Q2B of the flip-flop FF2, and has a cycle that is a quarter of the internal clock signal CKI. The On the other hand, when the phase comparison disable signal TPD is set to the high level and the synchronous SRAM is set to the predetermined test mode, the non-inverted output signal Q3 of the flip-flop FF3 is set to the high level in the counter control circuit CCTL. For this reason, the counter control signal CC is formed based on the test clock signal TCK input from the external test device via the input terminal TCK, and thereby the cycle of the counter control circuit CCTL can be arbitrarily set. .
[0045]
Counter control circuit CCTL further includes a NAND gate NAA receiving up signal up and a NAND gate NAD receiving down signal dn. The other input terminals of the NAND gates NAA and NAD are commonly supplied with the inverted output signal Q3B of the flip-flop FF3, and the output signals are supplied to one input terminals of the NAND gates NAC and NAF, respectively. The output signal of the NAND gate NAB is supplied to the other input terminal of the NAND gate NAC, and the output signal of the NAND gate NAE is supplied to the other input terminal of the NAND gate NAF.
[0046]
One input terminal of the NAND gate NAB is supplied with a phase control signal TPC from an external test device via the input terminal TPC and inverters VC and VD, and one input terminal of the NAND gate NAE is an inverted signal by the inverter VE. Is supplied. A non-inverted output signal Q3 of the flip-flop FF3 is commonly supplied to the other input terminals of the NAND gates NAB and NAE.
[0047]
The output signal of the NAND gate NAC is supplied to one input terminal of the NAND gate NAG, and the output signal of the NAND gate NAF is supplied to one input terminal of the NAND gate NAH. The other input terminal of the NAND gate NAG is supplied with the inverted signal of the output signal of the NOR gate NO6 by the inverter VF, and the other input terminal of the NAND gate NAH is supplied with the output signal of the NAND gate NAK. Output signals of the NAND gates NAI and NAJ are supplied to one and other input terminals of the NOR gate NO6, respectively, and output signals of the NOR gates NO7 and NO8 are supplied to one and other input terminals of the NAND gate NAK, respectively.
[0048]
Non-inverted output signals S32, S16 and S8 of the up / down counter U / DC are respectively supplied to the first to third input terminals of the NAND gate NAI and the NOR gate NO7, and the first to third inputs of the NAND gate NAJ and the NOR gate NO8 are supplied. The non-inverted output signals S4, S2 and S1 are supplied to the input terminals, respectively. The output signal of the NAND gate NAG becomes the up signal UP for the up / down counter U / DC after passing through the inverter VH, and the output signal of the NAND gate NAH becomes the down signal DN after passing through the inverter VI.
[0049]
For these reasons, when the synchronous SRAM is set to the normal operation mode and the inverted output signal Q3B of the flip-flop FF3 is set to the high level, the up signal UP is the high level of the up signal up output from the phase comparison circuit PC. Level, and the complementary output signals S1 * to S32 * of the up / down counter U / DC are all logic “1”, that is, the count value of the up / down counter U / DC is not the maximum value. It is said. Further, the down signal DN is such that the down signal dn output from the phase comparison circuit PC is set to the high level, and the complementary output signals S1 * to S32 * of the up / down counter U / DC are all logic “0”, that is, the count value. Is selectively set to a high level on the condition that is not the minimum value.
[0050]
On the other hand, when the synchronous SRAM is set to a predetermined test mode and the non-inverted output signal Q3 of the flip-flop FF3 is set to the high level, the up signal UP is set to the phase control signal TPC input from the external test device to the high level. And the complementary output signals S1 * to S32 * of the up / down counter U / DC are all set to logic “1”, that is, the count value of the up / down counter U / DC is not the maximum value. Is done. Further, the down signal DN is such that the phase control signal TPC input from the external test apparatus is set to the low level, and the complementary output signals S1 * to S32 * of the up / down counter U / DC are all logic “0”, that is, the count value. Is selectively set to a high level on the condition that is not the minimum value.
[0051]
As described above, the counter control circuit CCTL generates the counter control signal CC for the up / down counter U / DC, the divided signal of the internal clock signal CKI, or the external signal according to the phase comparison disable signal TPD supplied from the external test apparatus. Are selectively formed based on the test clock signal TCK supplied from the test apparatus, and the up signal UP and the down signal DN are supplied as the up signal up and the down signal dn supplied from the phase comparison circuit PC or an external test apparatus. Is selectively formed on the basis of the phase control signal TPC supplied from. As a result, in the synchronous SRAM of this embodiment, the counter control signal CC is selectively stopped to stop the stepping operation of the up / down counter U / DC, or the up signal UP and the down signal DN are transmitted to the phase control signal TPC. Thus, the up / down counter U / DC can be arbitrarily counted up or down, so that the margin for the read operation of the synchronous SRAM can be determined accurately and efficiently. In addition, the phase comparison disable signal TPD input asynchronously from the external test apparatus is synchronized with the internal clock signal CKI by the flip-flop FF3, thereby stabilizing the switching of the synchronous SRAM to the test mode.
[0052]
FIG. 4 shows a circuit diagram of an embodiment of the up / down counter U / DC included in the sense amplifier drive timing control unit SADC of FIG. Based on this figure, the specific configuration and operation of the up / down counter U / DC included in the sense amplifier drive timing control unit SADC of the synchronous SRAM of this embodiment will be described. The up / down counter U / DC includes six unit counter circuits UCT0 to UCT5. In the following description, all the unit counter circuits UCT0 to UCT5 will be described with an example of the unit counter circuit UCT0.
[0053]
In FIG. 4, the up / down counter U / DC is not particularly limited, but includes six unit counter circuits UCT0 to UCT5 coupled in series. Each of these unit counter circuits is represented by a unit counter circuit UCT0. As described above, the NOR gate NO9 which receives the up signal UP and the down signal DN at one and the other input terminals respectively, and two latch circuits in which the NAND gates NAN and NAO and the NAND gates NAR and NAS are cross-coupled, respectively.
[0054]
The output signal of the NOR gate NO9 is supplied in common to one input terminal of the NOR gates NOA and NOB. The other input terminal of the NOR gate NOA is supplied with the output signal of the NAND gate NAS, that is, the inverted output signal of the subsequent latch circuit, and the other input terminal of the NOR gate NOB is supplied with the output signal of the NAND gate NAR, that is, its non-inverted output signal. Is done. The output signals of the NOR gates NOA and NOB are input to the other input terminal via the NAND gates NAL and NAM that commonly receive the counter control signal CC, and the inverting set input terminal and the inverting reset input terminal of the preceding latch circuit composed of the NAND gates NAN and NAO. Are supplied respectively. The output signals of the NAND gates NAN and NAO, that is, the non-inverted and inverted output signals of the preceding latch circuit are connected to the other input terminals via the NAND gates NAP and NAQ that commonly receive the inverted signal of the counter control signal CC by the inverter VJ. It is supplied to the inverting set input terminal and the inverting reset input terminal of the latter latch circuit, respectively. The non-inverted output signal of the subsequent latch circuit becomes the non-inverted output signal S1 of the unit counter circuit UCT0, and the inverted output signal becomes the inverted output signal S1B.
[0055]
The up signal UP is further supplied to one input terminal of the NAND gate NAT, and the down signal DN is further supplied to one input terminal of the NAND gate NAU. The other input terminal of the NAND gate NAT is supplied with the non-inverted output signal of the latter-stage latch circuit, and the other input terminal of the NAND gate NAU is supplied with the inverted output signal. The output signal of the NAND gate NAT becomes the up signal UP for the next unit counter circuit UCT1 after passing through the inverter VK, and the output signal of the NAND gate NAU becomes the down signal DN after passing through the inverter VL.
[0056]
Therefore, the state of the pre-stage latch circuit of the unit counter circuit UCT0 is inverted every time the counter control signal CC is set to the high level and either the up signal UP or the down signal DN is set to the high level. In response to the low level change of the counter control signal CC, the stage latch circuit changes its state in order to inherit the state of the previous stage latch circuit. When the up signal UP is set to the high level, the non-inverted output signal of the unit counter circuit UCT0 is transmitted as the up signal UP to the next stage unit counter circuit UCT1, and when the down signal DN is set to the low level. The inverted output signal of the unit counter circuit UCT0 is transmitted as the down signal DN. As a result, the counter mode of the up / down counter U / DC formed by serially coupling the six unit counter circuits UCT0 to UCT5 is set to the count-up mode when the up signal UP is at a high level, and the down signal DN is at a high level. When the level is set, the countdown mode is set.
[0057]
FIG. 5 shows a circuit diagram of an embodiment of the variable delay circuit VD included in the sense amplifier drive timing control unit SADC of FIG. A specific configuration and operation of the variable delay circuit VD included in the sense amplifier drive timing control unit SADC of the synchronous SRAM of this embodiment will be described with reference to FIG.
[0058]
In FIG. 5, the variable delay circuit VD includes eight clocked inverters CV1 to CV8, although not particularly limited. Among these, an internal signal SP as an original signal of the sense amplifier drive signal SC is supplied from the clock driver CD to the input terminal of the clocked inverter CV5, and an inverted signal by the inverter VQ is supplied to the input terminal of the clocked inverter CV3. Is supplied. The internal signal SP is supplied to the input terminal of the clocked inverter CV1 via the inverters VQ and VR, and the internal signal SP is further supplied to the input terminal of the clocked inverter CV2 via the two inverters VS and VT. Is supplied. The input terminal of clocked inverter CV4 is coupled to the output terminals of clocked inverters CV1 and CV2, and the input terminal of clocked inverter CV6 is coupled to the output terminals of clocked inverters CV3 and CV4. The commonly coupled output terminals of clocked inverters CV5 and CV6 are coupled to the input terminal of clocked inverter CV7.
[0059]
The output signal of the NAND gate NAV is supplied to the gates of the P-channel MOSFET outside the clocked inverter CV1 and the N-channel MOSFET outside the clocked inverter CV2, and the N-channel MOSFET and the clocked inverter CV2 outside the clocked inverter CV1 are supplied. An inversion signal by the inverter VM is supplied to the gate of the P-channel MOSFET outside. Similarly, the output signal of the NAND gate NAW is supplied to the gates of the P-channel MOSFET outside the clocked inverter CV3 and the N-channel MOSFET outside the clocked inverter CV4, and the N-channel MOSFET and the clock outside the clocked inverter CV3 are supplied. An inverted signal from the inverter VN is supplied to the gate of the P-channel MOSFET outside the inverter CV4. The output signal of the NAND gate NAX is supplied to the gates of the P-channel MOSFET outside the clocked inverter CV5 and the N-channel MOSFET of the clocked inverter CV6, and the N-channel MOSFET and the clocked inverter CV6 outside the clocked inverter CV5. The inverted signal from the inverter VO is supplied to the gate of the P-channel MOSFET.
[0060]
A non-inverted output signal S16 and an inverted output signal S32B of the up / down counter U / DC are supplied to two input terminals of the NAND gate NAV, respectively. The two input terminals of the NAND gate NAW are supplied with the inverted output signal S16B and the non-inverted output signal S32, respectively, and the two input terminals of the NAND gate NAX are supplied with the non-inverted output signals S16 and S32, respectively.
[0061]
Therefore, when the complementary output signals S16 * and S32 of the up / down counter U / DC are both set to logic “1”, the internal signal SP output from the clock driver CD is the shortest signal path, that is, the clocked inverter. It is transmitted to the clocked inverter CV7 only through CV5, and the phase delay amount is minimized. When the complementary output signal S16 * is set to logic "0" and the complementary output signal S32 * is set to logic "1", the next short signal path, that is, the inverter VQ is clocked through the clocked inverters CV3 and CV6. When the complementary output signal S16 is set to logic "1" and the complementary output signal S32 * is set to logic "0" when transmitted to the inverter CV7, the next short signal path, that is, the inverters VQ and VR to the clocked inverters CV1, CV4 and It is transmitted to the clocked inverter CV7 via CV6. When the complementary output signals S16 * and S32 * are both logic "0", the internal signal SP is clocked from the longest signal path, that is, the inverters VQ, VR, VS and VT through the clocked inverters CV2, CV4 and CV6. Is transmitted to the inverter CV7, and the phase delay amount is maximized.
[0062]
The output signal of the clocked inverter CV7 is supplied to the input terminal of the clocked inverter CV8 via the inverter VU. The output signal of the clocked inverter CV8 passes through the inverters VV and VW, and then senses the sense amplifiers S0 to SF. It becomes the amplifier drive signal SC. The gates of the outer P-channel MOSFETs constituting clocked inverters CV7 and CV8 are coupled to the gates of P-channel MOSFETs P5 and P6, and the gates of the outer N-channel MOSFETs are coupled to the gate of N-channel MOSFET NG.
[0063]
The MOSFETs P5 and N6 have a so-called current mirror configuration by commonly coupling their gates and drains. The drain of MOSFET P5 is coupled to ground potential VSS through N-channel MOSFET N7 and N-channel MOSFETs N8 and NC, N9 and ND, NA and NE, and NB and NF coupled in parallel, respectively. An inverted signal of the internal signal ZZ by the inverter VP is supplied to the gate of the MOSFET N7. Further, the non-inverted output signals S1, S2, S4 and S8 of the up / down counter U / DC are supplied to the gates of the MOSFETs N8 to NB, respectively, and the gates of the MOSFETs NC to NF are coupled to the power supply voltage VCC. The internal signal ZZ is selectively set to the high level when the synchronous SRAM is set to the standby mode.
[0064]
For these reasons, the MOSFET N7 is selectively turned on under the condition that the synchronous SRAM is not in the standby state. The MOSFETs N8 to NB are selectively turned on on condition that the corresponding complementary output signals S1 * to S8 * of the up / down counter U / DC are set to logic “1”, and the MOSFETs NC to NF are stationary. Automatically turned on. For this reason, a current corresponding to the logical value of the 4-bit complementary output signals S1 * to S8 * of the up / down counter U / DC flows through the MOSFET P5, and this current passes through the MOSFETs P6 and NG coupled to the current mirror. To the P-channel and N-channel MOSFETs outside the clocked inverters CV7 and CV8. As a result, the operating speeds of the clocked inverters CV7 and CV8 are selectively switched, thereby switching the delay times of the clocked inverters CV7 and CV8.
[0065]
Needless to say, the operating speed of the clocked inverters CV7 and CV8 is increased by increasing the operating current, and is decreased by decreasing the operating current. Therefore, the delay time of the clocked inverters CV7 and CV8 with respect to the internal signal SP is finely adjusted according to the logical values of the complementary output signals S1 * to S8 *, and both of these complementary output signals S1 * to S8 * are logically “0”. Is the maximum when both are set to logic “1”, and the minimum when both are set to logic “1”.
[0066]
As described above, the phase delay amount with respect to the internal signal SP of the variable delay circuit VD is selectively selected according to the logical values of the complementary output signals S16 * and S32 * of the up / down counter U / DC. The operation speeds of the clocked inverters CV7 and CV8 are selectively switched by selectively increasing or decreasing according to the remaining complementary output signals S1 * to S8 * of the up / down counter U / DC. The phase of the sense amplifier drive signal SC is compared with the phase of the dummy data DD output from the dummy array DM by the phase comparison circuit PC, and the up / down counter U / DC is output according to the output signal, that is, the up signal up and the down signal dn. Are selectively counted up or down. As a result, the phase of the sense amplifier drive signal SC is brought as close as possible to the phase of the dummy data DD, thereby eliminating a useless margin of the sense amplifier drive signal SC and increasing the access time of the synchronous SRAM.
[0067]
FIG. 6 shows a signal waveform diagram of one embodiment of the sense amplifier drive timing control unit SADC of the synchronous SRAM of FIG. The specific operation and characteristics of the sense amplifier drive timing control unit SADC included in the synchronous SRAM of this embodiment will be described with reference to FIG. FIG. 6 illustrates an example in which the initial value of the up / down counter U / DC is n and changes from n−1 to n + 2 by counting up or counting down.
[0068]
In FIG. 6, the clock signal CK, that is, the internal clock signal CKI is divided by the flip-flops FF1 and FF2 of the counter control circuit CCTL, and the non-inverted output signal Q1 of the flip-flop FF1 having a half cycle is divided into four minutes. The non-inverted output signal Q2 of the flip-flop FF2 having a period of 1 is formed.
[0069]
When the phase comparison disable signal TPD input from the external test device via the input terminal TPD is set to the low level and the synchronous SRAM is set to the normal operation mode, the counter control circuit CCTL performs non-inversion of the flip-flop FF1. On the condition that the output signal Q1 is set to the high level and the non-inverted output signal Q2 of the flip-flop FF2 is set to the low level, the counter control signal CC (not shown) is selectively set to the high level. In response to the high level of the up signal up or the down signal dn output from the phase comparison circuit PC, the up signal UP or the down signal DN for the up / down counter U / DC is selectively set to the high level. Therefore, in the up / down counter U / DC, at the falling edge of the counter control signal CC, that is, at the falling edge of the non-inverted output signal Q1 of the flip-flop FF1 when the non-inverted output signal Q2 of the flip-flop FF2 is at the low level. Synchronously, a count-up or count-down operation is selectively performed, and the count value is counted up from n to n + 1, then counted down to n, and further counted up to n + 1.
[0070]
Next, the phase comparison disable signal TPD is set to a high level by an external test device, and the synchronous SRAM is set to a predetermined test mode. At this time, the high-level phase control signal TPC is input to the input terminal TPC with a delay of about 10 ns (nanoseconds), and the test clock signal TCK is input with a delay of about 10 ns from the high level of the phase control signal TPC. The
[0071]
In the counter control circuit CCTL of the synchronous SRAM, the flip-flop FF3 is set in response to the rising edge of the first internal clock signal CKI from the high level change of the phase comparison disable signal TPD, and the non-inverted output signal Q3 is high. Level. Further, the up signal UP is set to the high level in response to the high level of the non-inverted output signal Q3 of the flip-flop FF3 and the high level of the phase control signal TPC, and the counter control signal CC synchronized with the test clock signal TCK is formed. The Thus, the up / down counter U / DC is counted up in response to the falling edge of the test clock signal TCK, that is, the counter control signal CC, and the count value becomes n + 2. Further, after the phase control signal TPC is set to the high level, the down signal DN is set to the high level, and the count value of the up / down counter U / DC is counted down to n + 1.
[0072]
As described above, in the synchronous SRAM of this embodiment, the phase comparison operation by the phase comparison circuit PC is selectively stopped in accordance with the phase comparison disable signal TPD input from the external test apparatus via the input terminal TPD. The count value of the down counter U / DC is held. At this time, the up / down counter U / DC selectively operates in synchronization with the test clock signal TCK input from the external test apparatus via the input terminal TCK, and the counter mode is input from the external test apparatus. The count-up mode or the count-down mode is selectively set according to the phase control signal TPC input via the terminal TPC. Therefore, in the synchronous SRAM of this embodiment, the up / down counter U / DC is arbitrarily controlled from an external test apparatus based on the phase control amount determined by the automatic control of the sense amplifier drive timing control unit SADC. Thus, the phase of the sense amplifier drive signal can be controlled. As a result, the margin of the sense amplifier drive signal can be brought close to the limit, the access time of the synchronous SRAM can be increased, and the test man-hours related to the sense amplifier drive timing control unit of the synchronous SRAM can be reduced, thereby reducing the cost. Can be achieved.
[0073]
Note that the phase comparison disable signal TPD input asynchronously from an external test apparatus is synchronized with the internal clock signal CKI by the flip-flop FF3, so that the operation mode of the synchronous SRAM can be switched at an inconvenient timing. And switching to the test mode can be stabilized.
[0074]
The effects obtained from the above embodiments are as follows. That is,
(1) A synchronous SRAM or the like that operates synchronously according to a clock signal and includes a sense amplifier drive timing control unit is selectively designated by setting the mode control signal supplied from the second input terminal to an effective level. A counter control signal for providing a test mode and operating the up / down counter synchronously is formed based on a clock signal in the normal operation mode, and a test clock signal supplied from the third input terminal in the test mode. The up signal and the down signal for counting up or down the up / down counter are formed according to the first up signal or down signal output from the phase comparison circuit in the normal operation mode. In the test mode, according to the phase control signal supplied from the first input terminal In this way, the up / down counter is arbitrarily counted up or down from an external test device based on the phase control amount determined by the automatic control of the sense amplifier drive timing control unit, and the sense amplifier drive signal is intentionally The effect that the phase can be controlled is obtained.
[0075]
(2) According to the item (1), the margin of the sense amplifier drive signal can be brought close to the limit and the synchronous SRAM can be speeded up.
(3) According to the above item (1), it is possible to reduce the number of test steps related to the synchronous SRAM, particularly the sense amplifier drive timing control unit, and to reduce the cost thereof.
[0076]
(4) In the above items (1) to (3), a synchronous SRAM is provided by providing a flip-flop for taking in and synchronizing the mode control signal for setting the synchronous SRAM in the test mode in accordance with the clock signal. The operation mode can be prevented from being switched at an inconvenient timing, and the switching to the test mode can be stabilized.
[0077]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the synchronous SRAM can include an arbitrary number of memory mats, and the number of memory arrays and peripheral portions provided in each memory mat can be arbitrarily set. The block configuration of the synchronous SRAM including the sense amplifier drive timing control unit SADC is not restricted by this embodiment, and the names and combinations of the activation control signal and the test control signal, the effective level, etc. can take various embodiments. .
[0078]
In FIG. 2, FIG. 3, FIG. 4 and FIG. 5, the specific circuit configurations of the phase comparison circuit PC, the counter control circuit CCTL, the up / down counter U / DC, and the variable delay circuit VD are as long as the basic logic conditions are observed. Various embodiments may be adopted. In FIG. 4, the up / down counter U / DC can include an arbitrary number of unit counter circuits, and the control method of the counter mode is also arbitrary. In FIG. 6, the specific time relationship and absolute level of each signal including the clock signal CK do not limit the present invention.
[0079]
In the above description, the case where the invention made mainly by the present inventor is applied to the synchronous SRAM, which is the field of use behind the present invention, has been described. However, the present invention is not limited to this. The present invention can also be applied to various semiconductor memories including a timing control unit and various digital systems including the same. The present invention can be widely applied to a semiconductor memory device including at least a sense amplifier drive timing control unit and a device or system including the same.
[0080]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, a test that is selectively specified by setting the mode control signal supplied from the second input terminal to an effective level in a synchronous SRAM or the like that operates synchronously according to the clock signal and includes a sense amplifier drive timing control unit. A counter control signal for synchronizing the up / down counter is generated based on the clock signal in the normal operation mode, and the test clock signal supplied from the third input terminal is used in the test mode. And forming an up signal and a down signal for counting up or down the up / down counter according to the first up signal or down signal output from the phase comparison circuit in the normal operation mode, In the test mode, the phase control signal supplied from the first input terminal In this way, the up / down counter is arbitrarily counted up or down from an external test device based on the phase control amount determined by the automatic control of the sense amplifier drive timing control unit, and the sense amplifier is intentionally driven. The phase of the signal can be controlled. As a result, the margin of the sense amplifier drive signal can be brought close to the limit, the access time of the synchronous SRAM can be increased, and the test man-hours related to the sense amplifier drive timing control unit of the synchronous SRAM can be reduced, thereby reducing the cost. Can be achieved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a synchronous SRAM to which the present invention is applied.
2 is a circuit diagram showing one embodiment of a phase comparison circuit and related portions included in the sense amplifier drive timing control circuit of the synchronous SRAM of FIG. 1; FIG.
3 is a circuit diagram showing one embodiment of a counter control circuit included in the sense amplifier drive timing control circuit of the synchronous SRAM of FIG. 1; FIG.
4 is a circuit diagram showing an embodiment of an up / down counter included in the sense amplifier drive timing control circuit of the synchronous SRAM of FIG. 1; FIG.
5 is a circuit diagram showing one embodiment of a variable delay circuit included in the sense amplifier drive timing control circuit of the synchronous SRAM of FIG. 1; FIG.
6 is a signal waveform diagram showing one embodiment of a sense amplifier drive timing control circuit of the synchronous SRAM of FIG. 1. FIG.
7 is a block diagram showing an example of a sense amplifier drive timing control circuit of a synchronous SRAM developed by the present inventors prior to the present invention. FIG.
[Explanation of symbols]
MAT0 to MAT8 ... Memory mat, M0 to MF ... Memory array, DM ... Dummy array, W0 to WF ... Write driver, DW ... Dummy array write driver, P0 to PF ... Precharge circuit, DP ... ... Dummy array precharge circuit, Y0 to YF ... Y switch, DY ... Dummy array Y switch, S0 to SF ... Sense amplifier, DSEL ... Data selector, XD ... X address decoder, XB ... X Address buffer, YD: Y address decoder, YB: Y address buffer, UD: Unit address decoder, UB: Unit address buffer, IB: Data input buffer, WB: Write enable signal buffer, OB: Data Output buffer, CG ... Clock generation circuit, SADC ... Sense amplifier Dynamic timing controller, CD ...... clock driver, VD ...... variable delay circuit, PC ...... phase comparator circuit, CCTL ...... counter control circuit, U / DC ...... up-down counter.
CK: Clock signal or input terminal thereof, CKI: Internal clock signal, CEB: Chip enable signal or input terminal thereof, AX0 to AXi: X address signal or input terminal thereof, DI0 to DI8: Input data or data Input terminal, AY0 to AYj ... Y address signal or its input terminal, WEB ... Write enable signal or its input terminal, AU0 to AUk ... Unit address signal or its input terminal, DO0 to DO8 ... Output data or data output Terminal, TPD: Test phase comparison disable signal or its input terminal, TCK: Test clock signal, TPC: Test phase control signal.
MWDB ... dummy main word line, SWD ... dummy sub word line, BDT ... non-inverted dummy bit line, BDB ... inverted dummy bit line, EQB ... equalize control signal, DD ... dummy data, SC ... sense amplifier Drive signal, up, UP ... up signal, dn, DN ... down signal.
FF1 to FF3... Flip-flop, Q1 to Q3... Flip-flop output signal, CC... Counter control signal, S1, S2, S4, S8, S16, S32. S8B, S16B, S32B... Inverted counter output signal.
UCT0 to UCT5: Unit counter circuit.
CV1 to CV8: Clocked inverter.
P1 to P6... P channel MOSFET, N1 to NF... N channel MOSFET, V1 to VX... Inverter, NA1 to NAX... NAND gate, NO1 to NOB.

Claims (3)

A sense amplifier that is selectively activated according to a sense amplifier drive signal;
In the normal operation mode, the phase of the sense amplifier drive signal is controlled in accordance with the dummy data output from the dummy cell. In the predetermined test mode, the sense amplifier drive signal is controlled in accordance with the phase control signal supplied from the first input terminal. A sense amplifier drive timing control unit for controlling the phase ;
The sense amplifier drive timing controller is
A phase comparison circuit that compares the phases of the sense amplifier drive signal and the dummy data and selectively sets the first up signal or down signal to an effective level;
In a normal operation mode, the second up signal or down signal is selectively set to an effective level based on the first up signal or down signal, and in the test mode, the second up signal is set in accordance with the phase control signal. A counter control circuit for selectively setting the signal or the down signal to an effective level;
An up / down counter that operates in accordance with a counter control signal, is selectively counted up in response to an effective level of the second up signal, and is selectively counted down in response to an effective level of the second down signal;
A semiconductor memory device comprising: a variable delay circuit that selectively reduces or increases the phase delay of the sense amplifier drive signal in accordance with the output signal of the up / down counter . In claim 1 ,
The semiconductor memory device operates synchronously according to a clock signal and is selectively set to the test mode in response to an effective level of a mode control signal supplied from a second input terminal.
The counter control circuit includes a flip-flop that captures the mode control signal according to the clock signal,
The counter control signal is formed by dividing the clock signal in the normal operation mode, and is formed based on the test clock signal supplied from the third input terminal in the test mode. There is provided a semiconductor memory device. It operates in a plurality of modes including a first mode that is a normal operation mode and a second mode that is a test mode ,
A sense amplifier drive timing controller for outputting a sense amplifier drive signal;
In a semiconductor memory device having a dummy cell for supplying dummy data to the sense amplifier drive timing control unit,
In the first mode, the sense amplifier drive timing control unit outputs the sense amplifier drive signal according to the dummy data and the first clock signal,
In the second mode, the sense amplifier drive timing control unit outputs the sense amplifier drive signal according to the second clock signal and the third clock signal,
The sense amplifier drive timing control unit includes a phase comparison circuit, a counter control circuit, and an up / down counter,
In the first mode, the phase comparison circuit outputs an up signal or a down signal, and the counter control circuit receives the input of the up signal or the down signal,
The second mode, the counter control circuit is a semiconductor memory device which is characterized that you and the second clock signal and the third clock signal is input.

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