JP3930614B2 - High-speed imaging device and high-speed imaging device - Google Patents

Description

【００１０】
【発明が解決しようとする課題】
上述した従来のＦＴ型ＣＣＤ撮像素子にあっては、並列読出しチャンネル分に応じた高速撮像化は達成できるものの、１画面当たりの読出し画素数を減らして読み出す手法の「部分読出し」が実際上、時間短縮という観点からは効かないという状況にある。つまり、上述した図５に示す構成の素子において、例えば読出しチャンネル３〜６、１１〜１４までの中央部分の読出しに必要な時間と、読出しチャンネル１〜１６の全ての読出しに必要な時間とは全く同じであるから、１画面の画素数を減らして読み出す、いわゆる部分読出しの効果は出ない。
【００１１】
光学的マスクなどの構造体を使用しないで電気的に部分読出しができれば、部分読出しを行うときと行わないときとで、１種類の撮像素子でありながら、違う撮像速度（フレームレート）に対処できる。
【００１２】
しかしながら、従来のＦＴ型ＣＣＤ撮像素子にあっては、部分読出しの効果、すなわち、部分読出しに拠る読出し時間短縮の効果が実際上、出ないから、１つの撮像素子で違う値の撮影速度に対処できない。これにより、撮像対象が要求する高速撮影速度（フレームレート）が異なる場合、撮像素子そのものを交換しなければならないなど、汎用性に欠けるという問題があった。
【００１３】
さらに、従来のＦＴ型ＣＣＤ撮像素子では、部分読出しの効果が無いために並列読出しと部分読出しとを併用しても意味が無いから、撮像高速化の面において貢献できるのは並列読出しだけである。したがって、撮影の高速化の面でも物足りないという状況にあった。
【００１４】
本発明は、このような従来技術が有する問題に鑑みてなされたもので、部分読出しが効かないとされていた従来のＦＴ型ＣＣＤ撮像素子において、部分読出しを可能にし、この部分読出しの実行、非実行の態様を通して、異なる撮像速度 （フレームレート）にも対処でき、汎用性の高い撮像素子および撮像装置を提供することを、その目的とする。
【００１５】
また、本発明は、部分読出しが効かないとされていた従来のＦＴ型ＣＣＤ撮像素子において、そのように汎用性を高めるとともに、撮影の高速化も一層推し進めた撮像素子および撮像装置を提供することを、別の目的とする。
【００１６】
【課題を解決するための手段】
上記目的を達成させるため、本発明の一側面によれば、光信号を電荷に変換する２次元配列の複数の受光部から成る受光領域と、前記複数の受光部それぞれの蓄積電荷を垂直転送路に沿って垂直転送して一時的に前記全受光部の電荷を蓄積する複数の蓄積部から成る蓄積領域と、前記複数の蓄積部の蓄積電荷を水平方向に並列に読み出す複数の読出しチャンネルから成る出力部とを備えた高速度撮像素子が提供される。前記複数の読出しチャンネルのそれぞれに前記蓄積領域の複数の蓄積部により形成される水平方向１ラインの読出し画素数を不均一に割り当てたことを特徴とする。
【００１７】
例えば、前記不均一割当ての読出し画素数は第１の数と第２の数の２種類であって、前記第１の数は第２の数よりも小さく設定してある。好適には、前記複数の読出しチャンネルの内、前記蓄積領域の水平方向の中央部に位置している読出しチャンネルが前記第１の数に等しい前記読出し画素数の前記出力転送を担当し、かつ、前記蓄積領域の水平方向における前記中央部の両側に位置している読出しチャンネルが前記第２の数に等しい前記読出し画素数の前記出力転送を担当するように配列されている。
【００１８】
例えば、前記第１の数は前記第２の数の半分である。この場合、好適には、前記蓄積領域は前記受光領域の前記垂直方向の両側に分割して形成された第１および第２の蓄積領域から成り、前記出力部は前記第１および第２の蓄積領域それぞれに対応して分割して形成された第１および第２の出力部から成る。
【００１９】
好適な一例として、前記受光領域の受光部および前記蓄積領域の蓄積部の水平方向の数は５１２個で形成され、前記第１および第２の出力部それぞれの前記読出しチャンネルの数は１２個で形成され、この１２個の読出しチャンネルの内の前記水平方向の両側それぞれ２個の読出しチャンネルは前記第２の数の電荷の出力転送を担当し、かつ、前記水平方向の中央部８個の読出しチャンネルは前記第１の数の電荷の出力転送を担当するように配列され、前記第１の数は３２個かつ前記第２の数は６４個に設定されている。例えば、前記受光領域の前記垂直方向には２５６個の前記受光部が配列されている。
【００２０】
本発明の別な側面によれば、光信号を電荷に変換する２次元配列の複数の受光部から成る受光領域と、前記複数の受光部それぞれの蓄積電荷を垂直転送路に沿って垂直転送して一時的に前記全受光部の電荷を蓄積する複数の蓄積部から成る蓄積領域と、前記複数の蓄積部の蓄積電荷を水平方向に並列に読み出す複数の読出しチャンネルら成る出力部とを備えた撮像素子を有する高速度撮像装置が提供される。前記複数の読出しチャンネルのそれぞれに前記蓄積領域の複数の蓄積部により形成される水平方向１ラインの読出し画素数を不均一に割り当てる一方で、前記受光領域の複数の受光部の電荷を前記蓄積領域および前記出力部を介して読み出す電荷読出し手段を備えたことを特徴とする。
【００２１】
例えば、前記電荷読出し手段は、前記受光領域の受光部全部の蓄積電荷を読み出す第１の撮像モードおよび前記受光領域の受光部の内の前記不均一割当てに応じた一部の受光部のみの蓄積電荷を読み出す第２の撮像モードを選択的に指定する指定手段と、この指定手段により指定された撮像モードに応じた前記蓄積電荷の読出しを行う読出し実行手段とを備える。
【００２２】
【発明の実施の形態】
以下、本発明の１つの実施の形態を図１〜図４を参照して説明する。
【００２３】
図１に示す高速度撮像装置は、エリアイメージセンサ１１と、このセンサ１１に接続された駆動回路１２および処理回路１３と、処理回路１３に接続されたモニタ１４とを備える。
【００２４】
エリアイメージセンサ１１は、対物レンジなどの光学系１１ａと、この光学系１１ａを介して受光面に入射する光を電荷信号に変換するＣＣＤ撮像素子１１ｂとを備える。このＣＣＤ撮像素子１１ｂは、例えば２相駆動方式の各種の駆動信号により駆動されるようになっている。
【００２５】
ＣＣＤ撮像素子１１ｂは、半導体の薄膜積層技術によって、例えばｎ⁻基板上に形成した１チップのフレーム・インターライン・トランスファ型（ＦＴ型；フレーム・トランスファ型とも呼ばれる）のＣＣＤ撮像素子から成る。なお、図２において、ｘ軸方向を水平（横）方向、ｙ軸方向を垂直（縦）方向と便宜上呼ぶことにする。
【００２６】
図２に模式的に示すように、このＣＣＤ撮像素子１１ｂでは、かかる薄膜積層技術によって、垂直方向の中央部に形成された受光領域２１と、この受光領域２１の垂直方向両側に分割して形成された第１、第２の蓄積領域２２ａ，２２ｂと、第１、第２の蓄積領域２２ａ，２２ｂに隣接して形成された出力部としての第１、第２の水平レジスタ２３ａ，２３ｂとを備える。
【００２７】
受光領域２１は非遮光状態に形成されるとともに、この実施形態では５１２画素（水平方向）×２５６画素（垂直方向）分の複数の受光部ＬＰ…ＬＰをｘｙ面に２次元的に配列して成る。各受光部ＬＰはフォトダイオードで形成されている。ここで、垂直方向または水平方向の同一列の受光部ＬＰをラインと呼ぶことにする。
【００２８】
各受光部ＬＰは、１フレームの画像を形成する画素信号の素になる電荷を生成する。つまり、各受光部ＬＰには入射光量に対応した電荷が蓄積される。この受光領域２１には、駆動回路１２から第１転送信号ｉ ｔｏ ｓ信号（ここでは２相駆動方式で、位相の１８０°異なるｉ ｔｏ ｓ１信号とｉ ｔｏ ｓ２信号の２つから成る；図４参照）が供給される。このため、ｉ ｔｏ ｓ信号のパルス波形が反転する度に、各受光部ＬＰの蓄積電荷が垂直方向に画素単位で転送される。
【００２９】
本実施形態では電荷転送の高速化を図るため、図２に示す如く、蓄積領域を垂直方向の上下に２分割するチップ構造を採用している。このため、受光領域２１の垂直方向上半分の領域の各受光部ＬＰの蓄積電荷は、上側の第１の蓄積領域２２ａに転送され、反対に、下半分の領域の各受光部ＬＰの蓄積電荷は、下側の第２の蓄積領域２２ｂに転送される。
【００３０】
第１、第２の蓄積領域２２ａ，２２ｂはそれぞれ、５１２画素（水平方向）×１２８画素（垂直方向）分の電荷蓄積部をｘｙ面に２次元配列したチップ構造を有する。この第１、第２の記憶領域２２ａ，２２ｂは遮光されている。電荷蓄積部は垂直方向の転送路を形成し、この各電荷蓄積部を介して画素単位で垂直方向に蓄積電荷を転送できるようになっている。つまり、この両蓄積領域２２ａ，２２ｂは新たな電荷蓄積は行わず、駆動回路１２から供給される第２転送信号ｓ ｔｏ ｈ信号（ここでは２相駆動方式で、位相の１８０°異なるｓ ｔｏ ｈ１信号とｓ ｔｏ ｈ２信号の２つから成る；図４参照）に応答して、受光領域２１から転送されてきた電荷をさらに第１、第２の水平レジスタ２３ａ，２３ｂそれぞれに画素毎で渡す。第１、第２の蓄積領域２２ａ，２２ｂはその合計で、受光領域２１と同じ画素サイズを有するから、電荷転送を繰り返すことで、受光領域２１の全受光部ＬＰの蓄積電荷を全て格納できる。
【００３１】
出力部としての第１、第２の水平レジスタ２３ａ，２３ｂは、本発明の特徴の構造面での主要部を成すものである。図２に示す如く、水平レジスタ２３ａ，２３ｂはそれぞれ、図２に示す如く構造的に並列読出し用に１２分割され、図２中の下側の第２の水平レジスタ２３ｂがそれぞれ独立した読出しチャンネル１〜１２を形成し、上側の第１の水平レジスタ２３ａがそれぞれ独立した読出しチャンネル１３〜２４を形成している。読出しチャンネル１〜２４はそれぞれ、第１、第２の蓄積領域２２ａ，２２ｂで水平方向に割り当てた画素数分の垂直転送路からの転送電荷を並列に１回で読み出し、これを時系列に水平転送する機能を有する。
【００３２】
ただし、各読出しチャンネルは従来方式とは異なり、不均一に分割されている。本実施形態の場合、図３に示す如く、第１、第２の水平レジスタ２３ａ，２３ｂにおいて、受光領域および蓄積領域それぞれの水平方向中央部に割り当てた２５６画素に相当する読出しチャンネル３〜１０および１５〜２２のそれぞれは、蓄積領域２２ａ，２２ｂの水平方向における３２画素分の垂直転送路からの水平転送を担うように割り振られている。また、かかる中央部の水平方向両側に位置する読出しチャンネル１，２，１１，１２および１３，１４，２３，２４のそれぞれは、蓄積領域２２ａ，２２ｂの水平方向における６４画素分の垂直転送路からの水平転送を担うように割り振られている。これにより、第１、第２の水平レジスタ２３ａ，２３ｂ夫々が水平方向の５２６（＝６４×４＋３２×８）画素分の全部の水平転送を賄っている。
【００３３】
この水平転送は、駆動回路１２から水平レジスタ２３ａ，２３ｂに夫々供給される第３転送信号ｈ（ここでは２相駆動方式で、位相の１８０°異なるｈ１信号とｈ２信号の２つから成る；図４参照）と前述した第２転送信号ｓ ｔｏ ｈ信号とが共働してなされる。受光領域２１の全蓄積電荷が第１、第２の蓄積領域２２ａ，２２ｂに別かれて転送され、その全部が第１、第２の蓄積領域２２ａ，２２ｂに蓄積完了したタイミングで、第２転送信号ｓ ｔｏ ｈ信号のパルス波形が１回立ち上がる（立ち下がる）。これに付勢されて、水平方向１ライン分の蓄積電荷が第１、第２の記憶領域２２ａ，２２ｂから第１、第２の水平レジスタ２３ａ，２３ｂにそれぞれ転送される。その後、位相が１８０°異なる第３転送信号ｈ１，ｈ２の立上がりによって、第１、第２の蓄積領域２２ａ，２２ｂの読出しチャンネル１〜２４のそれぞれから割当て数画素数分の水平方向の蓄積電荷が画素毎に水平転送される。
【００３４】
これにより、中央部の読出しチャンネル３〜１０および１５〜２２のそれぞれから３２個の画素数分の蓄積電荷が順次読み出され、同時に、両側の読出しチャンネル１，２，１１，１２および１３，１４，２３，２４のそれぞれから６４個のそれが順次読み出される。
【００３５】
このように、受光領域２１の全部を１画面とする場合（フル画面の場合）、各読出しチャンネルからの読出し画素数に６４個と３２個との相違はあるが、１画面の読出し時間に関わるのは６４個の方である。中央部の読出しチャンネル３〜１０および１５〜２２では読出し画素数が少ない分（半分）、早く読出しが終了するだけである。このため、後述するように、フル画面で撮像するフル画面モードの場合、第３転送信号ｈ１、ｈ２のパルス数は多い方の読出し数に合わせて設定しておけばよく、６４個と３２個の双方に個別に合わせたパルス数の第３転送信号を設定する必要はない。
【００３６】
第１、第２の水平レジスタ２３ａ，２３ｂの読出しチャンネル１〜２４には、それぞれ、出力アンプ２４が接続されている。この出力アンプ２４も同一チップ上に積層形成されている。このため、読出しチャンネル１〜２４のそれぞれから読み出された蓄積電荷は出力アンプ２４を介して処理回路１３に送出される。
【００３７】
駆動回路１２は、本発明の電荷読出し手段を構成する回路であり、上述した如く２相駆動方式でセンサ１１を駆動するに必要な駆動信号を出力する。これを実行するため、駆動回路１２は、基準となるタイミング信号（クロック）を発生するタイミング信号発生器１２ａと、タイミング信号から各種の駆動信号を生成し出力する駆動信号発生器１２ｂと、画面モードを選択するスイッチ１２ｃとを備える。このスイッチはＣＰＵに置き換えて構成してもよい。
【００３８】
駆動信号発生器１２ｂは、例えばタイミング信号の所定数を計測するカウンタおよびそのカウント値に応答してパルス信号（駆動信号）を発生するパルス発生器を複数組備えて構成される。
【００３９】
駆動信号には上述した如く、受光領域２１から蓄積領域２２ａ，２２ｂに電荷転送するための第１転送信号ｉ ｔｏ ｓ信号、蓄積領域２２ａ，２２ｂから水平レジスタ２３ａ，２３ｂに電荷転送するための第２転送信号ｓ ｔｏ ｈ信号、および、水平レジスタ２３ａ，２３ｂから画素単位で電荷を読み出すための第３転送信号ｈのほか、出力アンプ２４をリセットするために常に連続的に与えられるリセット信号ｒｇ（図４参照）、及び、蓄積領域から水平レジスタへの転送を許可する信号や出力アンプに出力を許可する信号（図示せず）が含まれる。
【００４０】
また、スイッチ１２ｃを操作することによって駆動信号発生器１２ｂに画面モードを指定できるようになっている。本実施形態の場合、いずれも高速撮像モードに属するが、「フル画面モード」と「部分画面モード」の２種類の画面モードが用意されている。フル画面モードは、受光領域２１の５１６×２５６画素分全体の蓄積電荷で広い１画面を形成できるモードである。また、部分画面モードは、受光領域２１の中央部の２５６×２５６画素分の蓄積電荷で狭めの１画面を形成できるモードである。
【００４１】
フル画面モードおよび部分画面モードは本発明の第１および第２の撮像モードに相当し、またスイッチは本発明の指定手段に相当する。
【００４２】
スイッチ１２ｃを介してフル画面モードを駆動信号発生器１２ｂに指定すると、駆動信号発生器は第３転送信号ｈ（ｈ１，ｈ２）のパルス数を、並列読出しに関わる不均一割当て画素数の内の多い方の数に自動的に切替える。この多い方の数は本実施形態の場合、６４個である。また、部分画面モードを同様に指定すると、駆動信号発生器は第３転送信号ｈ（ｈ１，ｈ２）のパルス数を、並列読出しに関わる不均一割当て画素数の内の少ない方の数に自動的に切替える。この少ないの数は本実施形態の場合、３２個である。このように第３転送信号のパルス数を切替えることで、後述するように、部分画面モードのときの転送時間の更なる短縮が図られる。駆動信号発生器１２ｂ及び前述した処理回路１３は本発明の読出し実行手段にも相当する。
【００４３】
処理回路１３は、波形整形（ノイズ除去）、増幅回路、補正回路などの信号処理回路を備えるとともに、画像表示のためのＡ／Ｄ変換器、フレームメモリ、Ｄ／Ａ変換器を備える。これにより、センサ１１から順次読み出される電荷信号が画像信号に処理され、モニタ１４に１フレームの画像として表示される。
【００４４】
続いて、本実施形態に係る高速度撮像装置の動作を、センサ１１の転送動作を中心にして説明する。
【００４５】
駆動回路１２から図４に例示するシーケンスで、第１の第１転送信号ｉ ｔｏ ｓ信号、第２転送信号ｓ ｔｏ ｈ信号、第３転送信号ｈ、および、リセット信号ｒｇなどの駆動信号がセンサ１１に出力される。
【００４６】
あるタイミングで１画面の転送が開始されたとすると、第１転送信号ｉ ｔｏ ｓ信号および第２転送信号ｓ ｔｏ ｈ信号のパルス波形は同じタイミングにて、論理レベルＨ，Ｌ間で立ち上がり、および立ち下がる。このパルス数は、受光領域２１の垂直方向のライン数（受光部数）と同一に設定されている。ここでは、１２８（＝２５６／２）個のパルス波形となり、これにより、受光領域２１の全受光部の蓄積電荷が第１、第２の蓄積領域２２ａ，２２ｂに別れて一次的に蓄積される。
【００４７】
このようにして蓄積領域２２ａ、２２ｂへの電荷転送が完了すると、第２の転送信号ｓ ｔｏ ｈ信号のパルス波形が１回立ち下がり、および立ち下がる。これに応答し、第１、第２の蓄積領域２２ａ、２２ｂのそれぞれにて、最初に、最も水平レジスタに近い位置に蓄積されている水平方向１ライン分の蓄積電荷が第１、第２の水平レジスタ２３ａ，２３ｂにそれぞれ一度に転送される。
【００４８】
いまの場合、スイッチ１２ｃにより「フル画面モード」が指定されているとすると、多い方の６４個のパルス数の第３転送信号ｈ（ｈ１，ｈ２）が撮像素子１１ｂに供給される。これにより、読出しチャンネル１〜２４それぞれからチャンネル担当分の電荷が水平転送されるから、第１、第２の水平レジスタ２３ａ，２３ｂ全体では、水平方向の２ライン分の蓄積電荷が水平転送により並列に読み出される。
【００４９】
上述した一連の各ラインの並列読出しは、第１、第２の水平レジスタ２３ａ，２３ｂそれぞれにて、水平方向のライン数（１２８＝２５６／２）分の繰り返しにより実施される。これにより、フル画面モードのときの１画面分の電荷読出しが並列読出しによって高速に実施される。この後、再び、第１、第２転送信号が前述のように供給され、次画面分の電荷転送が同様に繰り返される。この定期的な電荷読出を繰り返すことで、連続画像に対する電荷信号が得られる。
【００５０】
このようにして読み出された各フレーム（画面）分の電荷は処理回路１３を経て、例えばスローモーション再生によりモニタ１４に表示される。
【００５１】
「フル画面モード」のときは以上のように転送処理される。このモード時の１画面分の電荷読出し時間Ｆｔは、
【外２】

【００５２】
これに対し、図２に示す如く受光領域２１の中央部に黒枠で囲んだ領域で部分撮像（部分読出し）を行うものとする。この場合、スイッチ１２ｃから「部分画面モード」を指定する。これにより、少ない方の３２個のパルス数の第３転送信号ｈ（ｈ１，ｈ２）が撮像素子１１ｂに供給される。したがって、読出しチャンネル１〜２４それぞれからチャンネル担当分の電荷が、前述と同様にライン毎に水平転送される。このとき、両側の読出しチャンネル１、２、１１、１２および１３、１４、２３、２４の読出し電荷は処理回路で無視され、中央部の読出しチャンネル３〜１０および１５〜２２の読出し電荷のみが処理回路で採用される。したがって、実質的に、中央部の読出しチャンネル３〜１０および１５〜２２のみの電荷読出しとなり、両側の読出しチャンネル１、２、１１、１２および１３、１４、２３、２４に対して第３転送信号ｈのパルス数が合わないことは問題にならない。
【００５３】
この中央部の読出しチャンネルのみで実質的に行われる各ラインの並列読出しは、第１、第２の水平レジスタ２３ａ，２３ｂそれぞれにて、水平方向のライン数（１２８＝２５６／２）分、繰り返して実施される。これにより、部分画面モードのときの中央部の部分画面分の電荷読出しが並列読出しおよび部分読出しの並行処理によって非常に高速に実施される。この後、再び、第１、第２転送信号が前述のように供給され、次フレームの部分画面分の電荷転送が同様に繰り返される。この定期的な電荷読出を繰り返すことで、連続画像に対する部分画面の電荷信号が得られる。
【００５４】
このようにして読み出された各フレーム（画面）分の電荷は処理回路１３を経て、例えばスローモーション再生によりモニタ１４に表示される。
【００５５】
【外３】

【００５６】
つまり、この部分画面モードのときの読出し時間Ｆｔ′をフル画面モードのときのそれ（Ｆｔ）と比べてみると、水平読出しの時間が半分の「１２８×３２Ｐｔ」になっていることが分かる。これは、水平レジスタ２３ａ，２３ｂを、読出し画素数の不均一割当てに基づく並列読出しができるように構成し、それを駆動できるようにしたことで初めて可能になることである。従来のように、均一割当てに拠る並列読出しのみの場合には達成し得なかった時間短縮効果である。
【００５７】
【外４】

【００５８】
このように、本実施形態によれば、部分読出しが効かないとされていたＦＴ型ＣＣＤ撮像素子であっても、並列読出しに加えて、電子的な部分読出しを実行できる。このため、並列読出しをベースにして、この処理に加えて部分読出しを行うときと、行わないときとで、異なる撮像速度（フレームレート）を得ることができる。上述の実施形態の場合、部分読出し行わないとき（並列読出しのみのとき）がフル画面モード、２０００ＦＰＳに対応し、部分読出しを行うとき（並列読出し＋部分読出しのとき）が部分画面モード、３２００ＦＰＳに対応する。したがって、異なるフレームレートに対処できる汎用性の高い撮像素子および撮像装置を提供することができる。
【００５９】
また、部分読出しを行えるようにすることで、１画面当たりの記録画素数を減らすことができ、部分画面モード時には並列読出しおよび部分読出しの共働によって、従来のＦＴ型ＣＣＤ撮像素子よりも一層高速に撮像でき、スローモーション撮影などに更に好適なものになる。
【００６０】
なお、上述した実施形態では、受光領域の複数の受光部の蓄積電荷を垂直方向の上下両側に別けて転送する両側転送方式のＦＴ型ＣＣＤ撮像素子を説明したが、本発明は必ずしもそのような構造のチップに限定されるものではない。例えば、受光領域の複数の受光部の蓄積電荷を垂直方向の一方の側のみに形成した蓄積領域に転送する片側転送方式のチップにも同様に、本発明を適用できる。
【００６１】
また、本発明において、部分画面モード時の部分画面の位置は必ずしも上述したように、受光領域の中央部に限定されるものではない。部分画面を中央部に設定する方が画面全体に対して画像の中心がずれることがないという利点はあるものの、この不都合を受容できるときは、部分画面の中心位置が受光領域の中心位置からずれた位置に設定してもよい。
【００６２】
本発明は、前述した実施形態およびその変形例に記載のものに限定されることなく、請求項記載の発明の要旨を逸脱しない範囲で適宜に変形可能である。
【００６３】
【発明の効果】
以上説明したように、本発明にかかる高速度撮像素子および高速度撮像装置によれば、出力部の複数の読出しチャンネルのそれぞれに水平方向１ラインの読出し画素数を不均一に割り当てた撮像素子とし、また、この撮像素子から不均一割当てに応じて蓄積電荷を読み出すことができるようにしたため、従来、機構的に部分読出しの恩恵に浴することができないとされていた並列読出しのＦＴ型ＣＣＤ撮像素子であっても、部分読出しを確実に行うことができ、これにより、同一のＦＴ型ＣＣＤ撮像素子で異なるフレームレートに的確に対処できるから、撮影対象を広げることができ、素子の汎用性を向上させることができる。また、部分読出し機能の付加によって、並列読出しと部分読出しの両方の高速化機能が有効に効き、一層の高速読出しを実現することができる。
【図面の簡単な説明】
【図１】本発明の実施形態に係る高速度撮像装置の構成例を示す概略ブロック図。
【図２】実施形態に係るＦＴ型ＣＣＤ撮像素子の構造を模式的に示す図。
【図３】読出し画素数の不均一割当てを模式的に説明する水平レジスタ付近の部分説明図。
【図４】実施形態における読出し制御の概略を示すタイミングチャート。
【図５】従来例を説明するＦＴ型ＣＣＤ撮像素子の構造を模式的に示す図。
【符号の説明】
１１ エリアイメージセンサ
１１ｂ ＣＣＤ撮像素子
１２ 駆動回路（電荷読出し手段）
１２ａ タイミング信号発生器
１２ｂ 駆動信号発生器（読出し実行手段）
１２ｃ スイッチ（指定手段）
１３ 処理回路
１４ モニタ
２１ 受光領域
２２ａ，２２ｂ 垂直転送路を有する第１，第２の蓄積領域（蓄積領域）
２３ａ，２３ｂ 第１，第２の水平レジスタ（出力部）
ＬＰ 受光部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a high-speed imaging device and a high-speed imaging device using a frame interline transfer type CCD (Charge Coupled Device). In particular, the present invention relates to a high-speed imaging device and a high-speed imaging device that can execute parallel readout and partial readout of charges.
[0002]
[Prior art]
High-speed imaging is useful in various fields such as slow motion playback. To perform slow motion playback, capture images at a speed higher than the standard speed (30 screens / second for NTSC, 25 screens / second for PAL), and play back the image data at the standard speed. Can see. For example, when image data captured at a speed n times the standard speed is reproduced at the standard speed, the movement of the subject can be observed by slowing down to 1 / n. As is well known, this slow-motion image is not only useful for analyzing athletes' movements and determining the outcome of sports, but it is also very useful for dynamic research in various academic research and industrial production fields. is doing.
[0003]
In general, as one method of such high-speed imaging, it is known to increase the reaction speed by increasing the clock frequency of an imaging element such as a CCD type imaging element or a MOS type imaging element. However, since there is a certain physical limitation on the reaction speed of the image sensor itself, there is a limit to increasing the imaging speed by increasing the clock frequency.
[0004]
In order to realize a higher speed than this limit, there is a so-called parallel reading method in which charges are read out in parallel with a plurality of outputs from the image sensor. For example, if the number of readouts is changed to 4 in parallel for a 30-screen / second standard image sensor with a 1-output configuration, the imaging speed can be increased to 120 screens / second in principle.
[0005]
A conventional example of such parallel reading is shown in FIG. In this conventional example, a frame transfer type (frame, interline, transfer type) CCD image pickup device is implemented so as to perform 16 parallel readouts.
[0006]
In FIG. 1, a CCD image pickup device 101 includes a light-receiving region 102 in a non-light-shielded state, a storage region 103 in a light-shielded state, and an output unit 104 on a single chip integrated circuit. In the light receiving area 102, for example, a plurality of light receiving portions corresponding to 512 pixels in the horizontal direction × 256 pixels in the vertical direction are two-dimensionally arranged. The storage area 103 is divided into first and second storage areas 103a and 103b by separating the storage parts for the plurality of light receiving parts on both sides in the vertical direction of the light receiving area. Further, the output unit 104 includes first and second horizontal registers 104a and 104b disposed adjacent to the first and second accumulation regions on both sides in the vertical direction. The first and second horizontal registers 104 a and 104 b have, for example, eight parallel read channels 1 to 8 and 9 to 16, respectively, and the charge of the light receiving unit is read from each read channel via the output amplifier 105. A drive signal is supplied to the CCD image pickup device from an external drive circuit (not shown). Thereby, parallel reading of 16 channels is possible.
[0007]
When light enters each light receiving portion of the light receiving region 102, the light is converted into electric charge in intensity. Accumulated charges in all the light receiving portions are transferred to the accumulation region in units of pixels by a drive signal supplied from the outside. Here, half of the light receiving portion of the light receiving area 102 is transferred separately to the first and second accumulation areas 103a and 103b. By this divided transfer, the transfer time is shortened. In the first and second accumulation regions 103a and 103b, charges are transferred in the vertical direction in units of pixels in response to the drive signal. By repeating the charge transfer to the first and second accumulation regions 103a and 103b for each pixel, the state where the charges of all the light receiving portions are temporarily accumulated in all the accumulation portions of the first and second accumulation regions can be obtained. can get.
[0008]
Next, when a driving signal is supplied from the outside to the first and second horizontal registers 104a and 104b, the charges accumulated in each accumulation unit of the accumulation region are read out from each readout channel in units of pixels. In this case, the number of read pixels (the number of storage units in the horizontal direction) assigned to each read channel of each of the first and second horizontal registers 104a and 104b is all equal (for example, 64). Thereby, parallel reading of 16 channels can be performed.
[0009]
[Outside 1]

[0010]
[Problems to be solved by the invention]
In the above-described conventional FT type CCD image pickup device, although high-speed imaging according to the parallel readout channels can be achieved, the “partial readout” method of reading out by reducing the number of readout pixels per screen is actually The situation is not effective from the viewpoint of time reduction. That is, in the element having the configuration shown in FIG. 5 described above, for example, the time required for reading the central portion of the read channels 3 to 6 and 11 to 14 and the time required for reading all of the read channels 1 to 16 are: Since they are exactly the same, there is no effect of so-called partial reading, in which reading is performed with a reduced number of pixels on one screen.
[0011]
If partial readout can be performed electrically without using a structure such as an optical mask, it is possible to cope with different imaging speeds (frame rates) even when partial readout is performed, even though it is a single type of image sensor. .
[0012]
However, with the conventional FT CCD image sensor, the effect of partial readout, that is, the effect of shortening the readout time due to partial readout is practically not produced, so that one image sensor copes with different values of photographing speed. Can not. As a result, when the high-speed shooting speed (frame rate) required by the imaging target is different, there is a problem that the imaging device itself needs to be replaced, and the versatility is lacking.
[0013]
Furthermore, in the conventional FT type CCD image pickup device, since there is no effect of partial reading, there is no point in using parallel reading and partial reading together. Therefore, only parallel reading can contribute in terms of speeding up imaging. . Therefore, it was in a situation where the shooting speed was not satisfactory.
[0014]
The present invention has been made in view of the above-described problems of the prior art. In the conventional FT type CCD image pickup device which has been considered to be ineffective for partial readout, partial readout is possible, and execution of this partial readout is performed. It is an object of the present invention to provide a highly versatile imaging device and imaging apparatus that can cope with different imaging speeds (frame rates) through non-execution modes.
[0015]
Further, the present invention provides an imaging device and an imaging device that improve the versatility and further increase the speed of imaging in the conventional FT CCD imaging device that is considered to be ineffective for partial readout. For another purpose.
[0016]
[Means for Solving the Problems]
In order to achieve the above object, according to one aspect of the present invention, a light receiving region composed of a plurality of light receiving portions in a two-dimensional array for converting an optical signal into electric charges, and a vertical transfer path for storing accumulated charges in the light receiving portions. A storage region composed of a plurality of storage units that temporarily transfer the charges of all the light-receiving units along the vertical direction, and a plurality of readout channels that read the stored charges of the plurality of storage units in parallel in the horizontal direction. A high-speed imaging device including an output unit is provided. The number of readout pixels in one horizontal line formed by the plurality of storage units of the storage region is non-uniformly assigned to each of the plurality of readout channels.
[0017]
For example, there are two types of readout pixels with non-uniform allocation: a first number and a second number, and the first number is set smaller than the second number. Preferably, among the plurality of readout channels, a readout channel located at a central portion in the horizontal direction of the accumulation region is responsible for the output transfer of the readout pixel number equal to the first number, and Readout channels located on both sides of the central portion in the horizontal direction of the accumulation region are arranged to handle the output transfer of the read pixel number equal to the second number.
[0018]
For example, the first number is half of the second number. In this case, it is preferable that the storage region is composed of first and second storage regions formed by being divided on both sides of the light receiving region in the vertical direction, and the output unit has the first and second storage regions. It consists of first and second output portions formed by being divided corresponding to each region.
[0019]
As a preferred example, the number of light receiving portions of the light receiving region and the number of storage portions of the storage region in the horizontal direction are 512, and the number of readout channels of each of the first and second output portions is twelve. Of the twelve read channels, two read channels on both sides in the horizontal direction are in charge of output transfer of the second number of charges, and eight horizontal central read-outs are formed. The channels are arranged to take charge of the output transfer of the first number of charges, the first number being set to 32 and the second number being set to 64. For example, 256 light receiving units are arranged in the vertical direction of the light receiving region.
[0020]
According to another aspect of the present invention, a light receiving region composed of a plurality of light receiving portions in a two-dimensional array for converting an optical signal into electric charges, and a charge stored in each of the light receiving portions are vertically transferred along a vertical transfer path. And a storage area composed of a plurality of storage sections for temporarily storing the charges of all the light receiving sections, and an output section consisting of a plurality of readout channels for reading out the stored charges of the plurality of storage sections in parallel in the horizontal direction. A high-speed imaging device having an imaging element is provided. The number of readout pixels in one horizontal line formed by the plurality of storage portions of the storage region is non-uniformly assigned to each of the plurality of read channels, while the charges of the plurality of light receiving portions of the light receiving region are allocated to the storage region And charge reading means for reading out via the output unit.
[0021]
For example, the charge reading means stores only a part of the light receiving units according to the first imaging mode for reading the accumulated charges of all the light receiving units in the light receiving region and the non-uniform allocation of the light receiving units in the light receiving region. Designation means for selectively designating a second imaging mode for reading out charges, and readout execution means for reading out the accumulated charges according to the imaging mode designated by the designation means.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
[0023]
The high-speed imaging device shown in FIG. 1 includes an area image sensor 11, a drive circuit 12 and a processing circuit 13 connected to the sensor 11, and a monitor 14 connected to the processing circuit 13.
[0024]
The area image sensor 11 includes an optical system 11a such as an objective range, and a CCD image sensor 11b that converts light incident on the light receiving surface via the optical system 11a into a charge signal. The CCD image pickup device 11b is driven by various drive signals of a two-phase drive system, for example.
[0025]
The CCD image pickup element 11b is formed by, for example, n using a semiconductor thin film lamination technique.⁻It consists of a one-chip frame interline transfer type (FT type; also called frame transfer type) CCD image sensor formed on a substrate. In FIG. 2, the x-axis direction is referred to as a horizontal (horizontal) direction, and the y-axis direction is referred to as a vertical (vertical) direction for convenience.
[0026]
As schematically shown in FIG. 2, the CCD image pickup device 11 b is formed by dividing the light receiving region 21 formed in the central portion in the vertical direction and both sides of the light receiving region 21 in the vertical direction by the thin film stacking technique. First and second storage areas 22a and 22b, and first and second horizontal registers 23a and 23b as output sections formed adjacent to the first and second storage areas 22a and 22b. Prepare.
[0027]
The light receiving region 21 is formed in a non-light-shielding state, and in this embodiment, a plurality of light receiving portions LP... LP for 512 pixels (horizontal direction) × 256 pixels (vertical direction) are two-dimensionally arranged on the xy plane. Become. Each light receiving portion LP is formed of a photodiode. Here, the light receiving portions LP in the same column in the vertical direction or the horizontal direction are referred to as lines.
[0028]
Each light-receiving unit LP generates a charge that is a source of a pixel signal that forms an image of one frame. That is, charges corresponding to the amount of incident light are accumulated in each light receiving portion LP. The light receiving region 21 is supplied with a first transfer signal i from the drive circuit 12. to s signal (in this example, i is a two-phase drive system and the phase is 180 ° different i to s1 signal and i to consisting of two of the s2 signals; see FIG. 4). For this reason, i to Each time the pulse waveform of the s signal is inverted, the accumulated charge in each light receiving portion LP is transferred in the vertical direction in units of pixels.
[0029]
In the present embodiment, in order to increase the speed of charge transfer, a chip structure in which the accumulation region is divided into two in the vertical direction as shown in FIG. 2 is adopted. For this reason, the accumulated charge of each light receiving portion LP in the upper half region of the light receiving region 21 in the vertical direction is transferred to the upper first accumulation region 22a, and conversely, the accumulated charge of each light receiving portion LP in the lower half region. Is transferred to the lower second storage area 22b.
[0030]
Each of the first and second accumulation regions 22a and 22b has a chip structure in which charge accumulation portions for 512 pixels (horizontal direction) × 128 pixels (vertical direction) are two-dimensionally arranged on the xy plane. The first and second storage areas 22a and 22b are shielded from light. The charge storage unit forms a transfer path in the vertical direction, and the stored charge can be transferred in the vertical direction pixel by pixel through the charge storage unit. That is, both the storage areas 22a and 22b do not perform new charge accumulation, and the second transfer signal s supplied from the drive circuit 12 is not used. to h signal (in this case, it is a two-phase drive system, and the phase is 180 ° different. to h1 signal and s to In response to the two h2 signals (see FIG. 4), the charges transferred from the light receiving region 21 are further transferred to the first and second horizontal registers 23a and 23b for each pixel. Since the first and second accumulation regions 22a and 22b have the same pixel size as the light receiving region 21, the accumulated charges of all the light receiving portions LP in the light receiving region 21 can be stored by repeating charge transfer.
[0031]
The first and second horizontal registers 23a and 23b as output units constitute the main part in the structural aspect of the features of the present invention. As shown in FIG. 2, each of the horizontal registers 23a and 23b is structurally divided into twelve for parallel reading as shown in FIG. 2, and the lower second horizontal register 23b in FIG. To 12 and the upper first horizontal register 23a forms independent read channels 13 to 24, respectively. Each of the read channels 1 to 24 reads the transfer charges from the vertical transfer paths corresponding to the number of pixels allocated in the horizontal direction in the first and second accumulation regions 22a and 22b at a time in parallel and horizontally reads them in time series. It has a function to transfer.
[0032]
However, unlike the conventional method, each read channel is divided unevenly. In the case of the present embodiment, as shown in FIG. 3, in the first and second horizontal registers 23a and 23b, read channels 3 to 10 corresponding to 256 pixels assigned to the horizontal central portions of the light receiving area and the accumulation area, respectively. Each of 15 to 22 is assigned so as to carry out horizontal transfer from a vertical transfer path of 32 pixels in the horizontal direction of the storage areas 22a and 22b. Further, the readout channels 1, 2, 11, 12 and 13, 14, 23, 24 located on both sides of the central portion in the horizontal direction are respectively connected from the vertical transfer path for 64 pixels in the horizontal direction of the storage regions 22a, 22b. Are assigned to handle horizontal transfer. Thereby, the first and second horizontal registers 23a and 23b each cover the entire horizontal transfer of 526 (= 64 × 4 + 32 × 8) pixels in the horizontal direction.
[0033]
This horizontal transfer is made up of a third transfer signal h (here, two-phase drive system, h1 signal and h2 signal which are 180 ° different in phase, respectively) supplied from the drive circuit 12 to the horizontal registers 23a and 23b; 4) and the second transfer signal s described above. to This is done in cooperation with the h signal. All the accumulated charges in the light receiving area 21 are transferred separately to the first and second accumulation areas 22a and 22b, and the second transfer is performed at the timing when all the accumulated charges are completed in the first and second accumulation areas 22a and 22b. Signal s to The pulse waveform of the h signal rises (falls) once. As a result, the accumulated charges for one horizontal line are transferred from the first and second storage areas 22a and 22b to the first and second horizontal registers 23a and 23b, respectively. Thereafter, with the rising edges of the third transfer signals h1 and h2 having a phase difference of 180 °, horizontal accumulated charges corresponding to the number of allocated pixels are respectively obtained from the read channels 1 to 24 of the first and second accumulation regions 22a and 22b. Horizontal transfer is performed for each pixel.
[0034]
As a result, the stored charges corresponding to the number of 32 pixels are sequentially read from each of the central readout channels 3 to 10 and 15 to 22, and at the same time, the readout channels 1, 2, 11, 12 and 13, 14 on both sides are simultaneously read. , 23, 24 are sequentially read out of 64 pieces.
[0035]
As described above, when the entire light receiving area 21 is one screen (in the case of a full screen), the number of pixels read from each readout channel is different from 64 to 32, but it relates to the readout time of one screen. There are 64 people. In the readout channels 3 to 10 and 15 to 22 in the central part, the readout is completed only as soon as the number of readout pixels is small (half). For this reason, as will be described later, in the case of the full screen mode in which an image is captured on the full screen, the number of pulses of the third transfer signals h1 and h2 may be set according to the larger number of readouts, 64 and 32. It is not necessary to set the third transfer signal having the number of pulses individually matched to both of the above.
[0036]
An output amplifier 24 is connected to each of the read channels 1 to 24 of the first and second horizontal registers 23a and 23b. The output amplifier 24 is also laminated on the same chip. Therefore, the accumulated charge read from each of the read channels 1 to 24 is sent to the processing circuit 13 through the output amplifier 24.
[0037]
The drive circuit 12 is a circuit constituting the charge reading means of the present invention, and outputs a drive signal necessary for driving the sensor 11 by the two-phase drive method as described above. In order to execute this, the drive circuit 12 includes a timing signal generator 12a that generates a reference timing signal (clock), a drive signal generator 12b that generates and outputs various drive signals from the timing signal, and a screen mode. And a switch 12c for selecting. This switch may be replaced with a CPU.
[0038]
The drive signal generator 12b includes, for example, a counter that measures a predetermined number of timing signals and a plurality of pulse generators that generate a pulse signal (drive signal) in response to the count value.
[0039]
As described above, the drive signal includes the first transfer signal i for transferring charges from the light receiving region 21 to the storage regions 22a and 22b. to s signal, second transfer signal s for transferring charges from storage regions 22a and 22b to horizontal registers 23a and 23b to In addition to the h signal and the third transfer signal h for reading out charges from the horizontal registers 23a and 23b in units of pixels, a reset signal rg (see FIG. 4) that is continuously given to reset the output amplifier 24. In addition, a signal for permitting transfer from the storage area to the horizontal register and a signal for permitting output to the output amplifier (not shown) are included.
[0040]
Further, the screen mode can be designated for the drive signal generator 12b by operating the switch 12c. In the present embodiment, all belong to the high-speed imaging mode, but two types of screen modes, “full screen mode” and “partial screen mode”, are prepared. The full screen mode is a mode in which a wide single screen can be formed with the accumulated charges of the entire light receiving area 21 corresponding to 516 × 256 pixels. Further, the partial screen mode is a mode in which one narrow screen can be formed with the accumulated charges of 256 × 256 pixels in the center of the light receiving region 21.
[0041]
The full screen mode and the partial screen mode correspond to the first and second imaging modes of the present invention, and the switch corresponds to the designation means of the present invention.
[0042]
When the full screen mode is designated to the drive signal generator 12b via the switch 12c, the drive signal generator determines the number of pulses of the third transfer signal h (h1, h2) among the number of non-uniformly allocated pixels related to parallel reading. Automatically switch to the larger number. In this embodiment, the larger number is 64. If the partial screen mode is designated in the same manner, the drive signal generator automatically sets the number of pulses of the third transfer signal h (h1, h2) to the smaller number of non-uniformly assigned pixels related to parallel reading. Switch to. In the case of this embodiment, this small number is 32. By switching the number of pulses of the third transfer signal in this way, the transfer time in the partial screen mode can be further shortened as will be described later. The drive signal generator 12b and the processing circuit 13 described above also correspond to the read execution means of the present invention.
[0043]
The processing circuit 13 includes signal processing circuits such as waveform shaping (noise removal), an amplifier circuit, and a correction circuit, and also includes an A / D converter, a frame memory, and a D / A converter for image display. Thereby, the charge signal sequentially read out from the sensor 11 is processed into an image signal and displayed on the monitor 14 as an image of one frame.
[0044]
Subsequently, the operation of the high-speed imaging device according to the present embodiment will be described focusing on the transfer operation of the sensor 11.
[0045]
In the sequence illustrated in FIG. 4 from the drive circuit 12, the first first transfer signal i to s signal, second transfer signal s to Drive signals such as the h signal, the third transfer signal h, and the reset signal rg are output to the sensor 11.
[0046]
If the transfer of one screen is started at a certain timing, the first transfer signal i to s signal and second transfer signal s to The pulse waveform of the h signal rises and falls between logic levels H and L at the same timing. The number of pulses is set to be the same as the number of lines in the vertical direction of the light receiving region 21 (the number of light receiving portions). Here, 128 (= 256/2) pulse waveforms are obtained, and as a result, the accumulated charges in all the light receiving portions of the light receiving region 21 are temporarily stored separately in the first and second storage regions 22a and 22b. .
[0047]
When the charge transfer to the storage regions 22a and 22b is completed in this way, the second transfer signal s. to The pulse waveform of the h signal falls once and falls. In response to this, in each of the first and second accumulation regions 22a and 22b, first, the accumulated charges for one horizontal line accumulated at the position closest to the horizontal register are first and second. The data is transferred to the horizontal registers 23a and 23b at a time.
[0048]
In this case, if the “full screen mode” is designated by the switch 12c, the third transfer signal h (h1, h2) having the larger number of 64 pulses is supplied to the image sensor 11b. As a result, the charge corresponding to the channel is horizontally transferred from each of the read channels 1 to 24. Therefore, in the entire first and second horizontal registers 23a and 23b, the accumulated charges for two horizontal lines are paralleled by the horizontal transfer. Is read out.
[0049]
The parallel reading of the series of lines described above is performed by repeating the number of lines in the horizontal direction (128 = 256/2) in each of the first and second horizontal registers 23a and 23b. Thereby, charge reading for one screen in the full screen mode is performed at high speed by parallel reading. Thereafter, the first and second transfer signals are again supplied as described above, and the charge transfer for the next screen is repeated in the same manner. By repeating this periodic charge reading, a charge signal for a continuous image can be obtained.
[0050]
The charges for each frame (screen) read out in this way are displayed on the monitor 14 through the processing circuit 13, for example, by slow motion reproduction.
[0051]
In the “full screen mode”, the transfer process is performed as described above. The charge read time Ft for one screen in this mode is
[Outside 2]

[0052]
On the other hand, as shown in FIG. 2, it is assumed that partial imaging (partial readout) is performed in a region surrounded by a black frame at the center of the light receiving region 21. In this case, “partial screen mode” is designated from the switch 12c. As a result, the third transfer signal h (h1, h2) having the smaller number of 32 pulses is supplied to the image sensor 11b. Accordingly, the charge for each channel from the read channels 1 to 24 is horizontally transferred for each line as described above. At this time, the reading charges of the reading channels 1, 2, 11, 12, and 13, 14, 23, 24 on both sides are ignored by the processing circuit, and only the reading charges of the reading channels 3 to 10 and 15 to 22 in the center are processed. Adopted in the circuit. Therefore, the charge readout is substantially performed only in the central readout channels 3 to 10 and 15 to 22, and the third transfer signal is supplied to the readout channels 1, 2, 11, 12 and 13, 14, 23, 24 on both sides. It is not a problem that the number of pulses of h does not match.
[0053]
The parallel readout of each line substantially performed only by the central readout channel is repeated by the number of horizontal lines (128 = 256/2) in each of the first and second horizontal registers 23a and 23b. Implemented. As a result, charge reading for the partial screen in the central portion in the partial screen mode is performed at a very high speed by parallel processing of parallel reading and partial reading. Thereafter, the first and second transfer signals are again supplied as described above, and the charge transfer for the partial screen of the next frame is similarly repeated. By repeating this periodic charge reading, a partial screen charge signal for a continuous image can be obtained.
[0054]
The charges for each frame (screen) read out in this way are displayed on the monitor 14 through the processing circuit 13, for example, by slow motion reproduction.
[0055]
[Outside 3]

[0056]
That is, comparing the readout time Ft ′ in the partial screen mode with that (Ft) in the full screen mode, it can be seen that the horizontal readout time is halved to “128 × 32 Pt”. This is possible only when the horizontal registers 23a and 23b are configured so as to be able to perform parallel reading based on the non-uniform allocation of the number of readout pixels, and can be driven. This is a time shortening effect that cannot be achieved in the case of only parallel reading based on uniform allocation as in the prior art.
[0057]
[Outside 4]

[0058]
As described above, according to the present embodiment, even in the case of an FT-type CCD image pickup device that is supposed to be ineffective for partial readout, electronic partial readout can be executed in addition to parallel readout. Therefore, on the basis of parallel reading, it is possible to obtain different imaging speeds (frame rates) depending on whether partial reading is performed in addition to this processing or not. In the case of the above-described embodiment, when partial reading is not performed (when only parallel reading is performed), the full screen mode corresponds to 2000 FPS, and when partial reading is performed (when parallel reading + partial reading is performed), the partial screen mode is set to 3200 FPS. Correspond. Therefore, it is possible to provide a highly versatile imaging device and imaging apparatus that can cope with different frame rates.
[0059]
In addition, by enabling partial readout, the number of recording pixels per screen can be reduced, and in the partial screen mode, the parallel readout and partial readout can be combined to achieve higher speed than the conventional FT type CCD image sensor. Therefore, it is more suitable for slow motion photography.
[0060]
In the above-described embodiment, the double-side transfer type FT CCD image pickup device that transfers the accumulated charges of the plurality of light receiving portions in the light receiving region separately to the upper and lower sides in the vertical direction has been described. It is not limited to the structure chip. For example, the present invention can be similarly applied to a one-side transfer type chip that transfers accumulated charges of a plurality of light receiving portions of a light receiving region to a storage region formed only on one side in the vertical direction.
[0061]
In the present invention, the position of the partial screen in the partial screen mode is not necessarily limited to the central portion of the light receiving region as described above. Setting the partial screen to the center has the advantage that the center of the image does not shift with respect to the entire screen, but if this inconvenience can be accepted, the center position of the partial screen is shifted from the center position of the light receiving area. It may be set at a different position.
[0062]
The present invention is not limited to those described in the above-described embodiments and modifications thereof, and can be appropriately modified without departing from the gist of the invention described in claims.
[0063]
【The invention's effect】
As described above, according to the high-speed imaging device and the high-speed imaging device according to the present invention, the imaging device is configured such that the number of readout pixels in one horizontal line is non-uniformly allocated to each of the plurality of readout channels of the output unit. In addition, since the stored charge can be read out from the image pickup device in accordance with the non-uniform assignment, the parallel read-out FT type CCD image pickup, which has conventionally been considered to be unable to take advantage of partial read out mechanically. Even in the case of an element, partial reading can be performed reliably, and by this, different frame rates can be dealt with accurately with the same FT CCD image sensor, so that the object to be photographed can be expanded, and the versatility of the element can be increased. Can be improved. Further, by adding the partial read function, the speed-up function for both parallel read and partial read is effective, and higher-speed read can be realized.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram illustrating a configuration example of a high-speed imaging device according to an embodiment of the present invention.
FIG. 2 is a diagram schematically showing the structure of an FT CCD image sensor according to an embodiment.
FIG. 3 is a partial explanatory view in the vicinity of a horizontal register for schematically explaining non-uniform allocation of the number of readout pixels.
FIG. 4 is a timing chart showing an outline of read control in the embodiment.
FIG. 5 is a diagram schematically showing the structure of an FT CCD image sensor for explaining a conventional example.
[Explanation of symbols]
11 Area image sensor
11b CCD image sensor
12 Drive circuit (charge reading means)
12a Timing signal generator
12b Drive signal generator (reading execution means)
12c switch (specifying means)
13 Processing circuit
14 Monitor
21 Light receiving area
22a, 22b First and second storage areas (storage areas) having vertical transfer paths
23a, 23b First and second horizontal registers (output unit)
LP receiver

Claims (8)

In a high-speed imaging device of a high-speed imaging device having a full screen mode and a partial screen mode,
A light receiving region composed of a plurality of light receiving portions in a two-dimensional array for converting an optical signal into electric charges, and charges accumulated in each of the light receiving portions are vertically transferred along a vertical transfer path to temporarily charge all the light receiving portions. An accumulation region composed of a plurality of accumulation units for accumulating, and an output unit consisting of a plurality of readout channels for reading out the accumulated charges of the plurality of accumulation units in parallel in the horizontal direction ,
The accumulation region is composed of first and second partial accumulation regions formed by being divided in the vertical direction of the light receiving region,
The output unit is an output unit composed of first and second partial output units that are divided and formed so as to correspond to the first and second partial accumulation regions, respectively. An output unit from which the accumulated charge is read out from both of the second partial output units, and in the partial screen mode, from the first partial output unit;
Among the plurality of readout channels, the number of pixels in the horizontal direction of each storage unit read from each readout channel corresponding to the first partial output unit is defined as a first pixel number, and the second partial output unit When the number of pixels in the horizontal direction of each storage unit read from each readout channel corresponding to the second pixel number is set, the first pixel number is set smaller than the second pixel number,
A high-speed imaging device. In the invention of claim 1 ,
The high-speed imaging device, wherein the first number of pixels is half of the second number of pixels . In the invention of claim 1 ,
The first partial storage region and the first partial output unit are respectively located in the horizontal center of the storage region and the output unit , and the second partial storage region and the second partial output unit. Are respectively located on both sides of the central part ,
High-speed image sensor. In the invention of claim 3 ,
The number of light receiving portions of the light receiving region and the number of storage portions of the storage region in the horizontal direction is 512, the number of readout channels corresponding to the first partial output unit is 8 and the center portion. The number of the read channels corresponding to the second partial output portion provided on both sides of each of the two is formed by two,
The first number of pixels is 32 , and the second number of pixels is 64 .
High-speed image sensor. In the invention of claim 4 ,
A high-speed imaging device in which 256 light receiving portions are arranged in the vertical direction of the light receiving region. In the invention of claim 1 ,
The accumulation area is composed of first and second accumulation areas formed on both sides of the light receiving area in the vertical direction, and the output unit is divided corresponding to each of the first and second accumulation areas. A high-speed imaging device comprising first and second output portions formed in the manner described above. In a high-speed imaging device having a full screen mode and a partial screen mode,
A light receiving region composed of a plurality of light receiving portions in a two-dimensional array for converting an optical signal into electric charges, and charges accumulated in each of the light receiving portions are vertically transferred along a vertical transfer path to temporarily charge all the light receiving portions. A high-speed imaging device comprising: a storage region composed of a plurality of storage units for storing a plurality of storage channels; and an output unit composed of a plurality of readout channels for reading out the stored charges of the plurality of storage units in parallel in a horizontal direction;
A designation means for selectively designating the full screen mode and the partial screen mode;
Prepared,
The accumulation area is composed of first and second partial accumulation areas formed by being divided in the vertical direction of the light receiving area,
The output unit is an output unit including first and second partial output units that are divided and formed corresponding to the first and second partial accumulation regions, respectively, and is the first in the full screen mode. The stored charge is read from both the first and second partial output units, and in the partial screen mode, from the first partial output unit,
Among the plurality of readout channels, the number of pixels in the horizontal direction of each storage unit read from each readout channel corresponding to the first partial output unit is defined as a first pixel number, and the second partial output unit When the number of pixels in the horizontal direction of each storage unit read from each readout channel corresponding to the second pixel number is set, the first pixel number is set smaller than the second pixel number,
A high-speed imaging device. In the invention of claim 7,
Charge read execution means for reading out the accumulated charges in the first and second partial accumulation regions in the full screen mode, and reading out the accumulated charges in the first partial accumulation region in the partial screen mode;
Is a high-speed imaging device.

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