JP3929357B2 - Demodulator circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
[0002]
The present invention relates to a demodulation circuit used for a mobile communication receiver or the like.
[0003]
[Prior art]
[0004]
Conventionally, as a technique in such a field, for example, there is one described in US Pat. No. 6,104,238.
[0005]
FIG. 2 is a circuit diagram of the conventional demodulation circuit described in the above specification.
[0006]
The demodulating circuit includes a filter (BPF) 1 capable of controlling a pass frequency, a detector (DET) 2 that detects an output signal of the filter 1 to generate a baseband signal SBASE, and a baseband signal SBASE. A DC detector (DC) 3 that extracts the DC offset voltage VOFFSET and a comparator (SL) 4 that compares the baseband signal SBASE and the DC offset voltage VOFFSET and outputs data OUT are included.
[0007]
The demodulating circuit further includes a tuning circuit 5 that outputs a control voltage VTUNE for adjusting the frequency characteristics of the filter 1 and the detector 2. The tuning circuit 5 holds a voltage controlled oscillator (VCO) 6, a phase detector (PD) 7 that detects a phase difference between the output signal of the voltage controlled oscillator 6 and the reference frequency FREF, and an output of the phase detector 7. It consists of a register 8. The output signal of the register 8 is fed back as a control voltage for the voltage controlled oscillator 6 and is given to the adder 9 as the control voltage VTUNE.
[0008]
The adder 9 is further supplied with a DC offset voltage VOFFSET output from the DC detector 3, and the addition result is output as a control signal SCONT for the filter 1 and the detector 2.
[0009]
In such a demodulating circuit, the frequency-modulated input signal IN is selected by the filter 1 as a signal of a predetermined channel and detected by the detector 2 to obtain a baseband signal SBASE. The baseband signal SBASE is smoothed by the DC detector 3 constituted by an integrating circuit, and is supplied to the comparator 4 and the adder 9 as a DC offset voltage VOFFSET. In the comparator 4, the baseband signal SBASE is compared with the DC offset voltage VOFFSET, and the comparison result is output as data OUT.
[0010]
On the other hand, the DC offset voltage VOFFSET given to the adder 9 is added to the control voltage VTUNE output from the tuning circuit 5 and used as a control signal SCONT for the filter 1 and the detector 2. As a result, the center frequency of the filter 1 and the DC potential fluctuation of the baseband signal SBASE output from the detector 2 are controlled.
[0011]
[Problems to be solved by the invention]
[0012]
However, the conventional demodulation circuit has the following problems.
[0013]
The DC detector 3 composed of an integrating circuit smoothes the input baseband signal SBASE with a constant time constant to generate a DC offset voltage VOFFSET. The DC offset voltage VOFFSET follows the relatively slow DC potential fluctuation of the baseband signal SBASE to obtain error-free data OUT.
[0014]
By the way, in many mobile communication systems, burst transmission is performed instead of continuous transmission. For this reason, in the demodulation circuit, the DC potential of the baseband signal output from the detector fluctuates dynamically. In order to compensate for such a rapid fluctuation of the DC potential, a system is employed in which a code string called a preamble pattern is added to the head of the original data, and this is transmitted in bursts as one block.
[0015]
The code length of the preamble pattern differs depending on the mobile communication system to be applied, but there is also a very short system such as 4 bits. Therefore, in order to correctly demodulate the preamble pattern, the demodulation circuit needs to follow the dynamic fluctuation of the DC potential of the received signal at high speed.
[0016]
On the other hand, data transmitted and received in the mobile communication system includes a pattern in which the same code (“H” or “L”) continues. Therefore, the demodulation circuit needs to slowly follow the DC potential fluctuation of the baseband signal in order to demodulate the same code continuous pattern without error.
[0017]
As described above, a demodulating circuit such as a mobile communication system is required to have a conflicting operation of compensating for fluctuations in DC potential with respect to a burst signal at high speed and receiving the same code continuous pattern without error. The demodulator circuit cannot satisfy both operations at the same time.
[0018]
The present invention solves the problems of the prior art, and provides a demodulation circuit capable of compensating for fluctuations in DC potential with respect to a burst signal at high speed and receiving the same code continuous pattern without error. .
[0019]
[Means for Solving the Problems]
[0020]
In order to solve the above problems, a first invention of the present invention is a demodulation circuit, wherein a demodulator circuit detects a frequency-modulated input signal and outputs a baseband signal, and amplifies the baseband signal. And an amplifier that biases and outputs the amplified signal to a DC potential corresponding to the control voltage, and a drive current that is switched according to the current control signal, and a potential difference between the reference voltage and the signal output from the amplifier, and the A differential amplifier that outputs a current corresponding to a drive current; a capacitor that is charged by a current output from the differential amplifier, generates the control voltage, and supplies the control voltage to the amplifier; the reference voltage and the amplifier A comparator that compares the potentials of the signals output from the unit and outputs the comparison result as demodulated data.
[0021]
According to the first invention, since the demodulation circuit is configured as described above, the following operation is performed.
[0022]
The input signal is detected by the detection unit as a baseband signal and supplied to the amplification unit. The baseband signal is amplified by the amplifying unit and is biased to a DC potential corresponding to the control voltage generated by the capacitor and output. A signal output from the amplifying unit is applied to the differential amplifying unit, and a current corresponding to the potential difference from the reference voltage and the driving current is output from the differential amplifying unit and applied to the capacitor. The capacitor is charged by a current supplied from the differential amplifier, and a control voltage is generated and applied to the amplifier. By this feedback operation, the DC potential of the signal output from the amplifying unit is controlled to be the reference voltage.
[0023]
Therefore, if the drive current of the differential amplifier is increased according to the current control signal, the response speed of the feedback operation is increased. On the contrary, if the current control signal is switched so as to reduce the drive current of the differential amplifier, the response speed of the feedback operation becomes slow. The output signal of the amplifier controlled so that the DC potential becomes the reference voltage at the response speed switched by the current control signal is compared with the reference voltage by the comparator, and demodulated data is output.
[0024]
According to a second aspect of the present invention, in the demodulation circuit, a detection unit that detects a frequency-modulated input signal that is input in a burst manner and outputs a baseband signal, and an amplification unit and a differential amplification unit similar to the first invention A capacitor and a comparator; a pattern detection unit that detects a specific bit pattern included in the demodulated data output from the comparator and outputs a detection signal; and the differential amplification during a period when the input signal does not exist A current control signal that outputs the current control signal that switches the drive current to be increased, and outputs the current control signal that switches the drive current to decrease when the detection signal is given. ing.
[0025]
According to the second invention, the following operation is performed.
[0026]
When there is no input signal, a current control signal for switching the drive current to be increased is output from the current control unit to the differential amplification unit. When an input signal is input, this input signal is detected by a detection unit and converted into a baseband signal and given to the amplification unit. The baseband signal supplied to the amplifying unit is amplified and biased to a DC potential corresponding to the control voltage generated by the capacitor, and is supplied to the differential amplifying unit. In the differential amplifier, a current corresponding to the potential difference between the signal output from the amplifier and the reference voltage and the drive current is output and applied to the capacitor. The capacitor is charged with a current supplied from the differential amplifier, and the voltage is fed back to the amplifier as a control voltage.
[0027]
By this feedback operation, the DC potential of the signal output from the amplifying unit is controlled to become the reference voltage at a fast response speed, and is compared with the reference voltage by the comparator to output demodulated data. As a result, when the input signal rises, a correct demodulated data can be obtained immediately in response.
[0028]
The demodulated data is given to the pattern detection unit. When a specific bit pattern in the demodulated data is detected, a detection signal is output from the pattern detection unit to the current control unit. As a result, a current control signal for switching the drive current to be reduced is output from the current control unit to the differential amplification unit. As a result, the current output from the differential amplifier to the capacitor is reduced, the tracking speed of the control voltage charged in the capacitor is reduced, and the same continuous code can be demodulated without error.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
[0030]
FIG. 1 is a configuration diagram of a demodulation circuit showing an embodiment of the present invention.
[0031]
The demodulation circuit includes a detection unit 10 that detects a frequency-modulated input signal IN and outputs baseband differential signals S10a and S10b. On the output side of the detection unit 10, an amplification unit 20 is provided. Is connected.
[0032]
The amplifying unit 20 amplifies the input differential signals S10a and S10b to a predetermined amplitude, and biases the amplified signal to a DC potential corresponding to the control voltage VCT and outputs the amplified signal. Differential signals S10a and S10b input from the detection unit 10 are supplied to gates of N-channel MOS transistors (hereinafter referred to as “NMOS”) 21a and 21b of the amplification unit 20, respectively.
[0033]
The sources of the NMOSs 21a and 21b are connected to the ground potential GND via current sources 22a and 22b, respectively, and a resistor 23 is connected between the sources of the NMOSs 21a and 21b. The drains of the NMOSs 21a and 21b are connected to the ground potential GND through the current source 24 and NMOS 25, respectively, and are connected to the power supply potential VDD through P-channel MOS transistors (hereinafter referred to as "PMOS") 26a and 26b, respectively. ing.
[0034]
PMOSs 27a and 27b constituting current mirror circuits are connected to the PMOSs 26a and 26b, respectively. That is, the drain and gate of the PMOS 26a are connected to the gate of the PMOS 27a, and the source of the PMOS 27a is connected to the power supply potential VDD. Similarly, the drain and gate of the PMOS 26b are connected to the gate of the PMOS 27b, and the source of the PMOS 27b is connected to the power supply potential VDD.
[0035]
The drain of the PMOS 27a is connected to the drain and gate of the NMOS 28a, and the source of the NMOS 28a is connected to the ground potential GND. The drain of the PMOS 27b is connected to the node N1, and the drain of the NMOS 28b is connected to the node N1. The gate and source of the NMOS 28b are connected to the gate of the NMOS 28a and the ground potential GND, respectively.
[0036]
Resistors 29 a and 29 b are respectively connected between the node N 1 and the power supply potential VDD and the ground potential GND, and a signal S 20 that is an output signal of the amplifying unit 20 is output from the node N 1 and applied to the differential amplifying unit 30. It is supposed to be.
[0037]
The differential amplifier 30 outputs a current according to the potential difference between the signal S20 and the reference voltage VTH and the drive current. The current output from the differential amplifying unit 30 is charged in the capacitor and is supplied to the amplifying unit 20 as the control voltage VCT. The magnitude of the drive current of the differential amplifier 30 can be switched by the current control signal ICT.
[0038]
The signal S20 and the reference voltage VTH are respectively supplied to the gates of the PMOSs 31 and 32 of the differential amplifier 30. The drains of the PMOSs 31 and 32 are connected to the ground potential GND via NMOSs 33 and 34, respectively. The gates of these NMOSs 33 and 34 are commonly connected to the drain of the PMOS 32.
[0039]
The sources of the PMOSs 31 and 32 are connected in common, and a drive current is supplied from the power supply potential VDD via the two current sources 35 and 36. The current source 35 always supplies a constant current. On the other hand, the current source 36 supplies a constant current when the current supply signal ICT is given (when “H”), and when the current supply signal ICT is not given (when “L”). The current supply is stopped.
[0040]
One end of a capacitor 40 is connected to the drain of the PMOS 31, and the other end of the capacitor 40 is connected to the ground potential GND. The voltage charged in the capacitor 40 is supplied to the gate of the NMOS 25 of the amplifying unit 20 as the control voltage VCT.
[0041]
The signal S20 output from the amplifying unit 20 is further supplied to the first input side of the comparator (CMP) 50, and the reference voltage VTH is supplied to the second input side of the comparator 50. The comparator 50 compares the voltages applied to the first and second input sides, and outputs the comparison result as binary demodulated data OUT of “H” and “L”. Note that the reference voltage VHT is the same as that applied to the gate of the PMOS 32 of the differential amplifier 30, and is generated by, for example, dividing the power supply potential VDD by 1/2 with the resistors 61 and 62.
[0042]
The demodulated data OUT is output as a demodulated output signal and is given to the pattern detection unit 70. The pattern detection unit 70 includes, for example, a shift register and a bit-by-bit comparison gate. The demodulated data OUT output from the comparator 50 is sequentially shifted and held in the shift register, and matches a specific bit pattern such as a preamble. When this occurs, the detection signal PTN is output. The detection signal PTN is supplied to the current control unit 80.
[0043]
The current control unit 80 generates a current supply signal ICT for the current source 36 of the differential amplifier 30 based on the detection signal PTN. The current control unit 80 is configured by, for example, a set / reset type flip-flop, and is set when a power-down signal PDN is given, and outputs an “H” current supply signal ICT, and is given a detection signal PTN. When reset, the current supply signal ICT of “L” is output.
[0044]
FIG. 3 is a signal waveform diagram showing an example of the operation of FIG. The operation of FIG. 1 will be described below with reference to FIG.
[0045]
At time T0 in FIG. 3, when the input signal IN does not exist and the power-down signal PDN is “H”, the differential signal S10a output from the detection unit 10 has a constant offset voltage. . Thus, the demodulated data OUT output from the comparator 50 is “L”, and the detection signal PTN output from the pattern detection unit 70 is also “L”. The current control signal ICT output from the current controller 80 is “H”, and a constant current is supplied from the current source 36.
[0046]
In the amplifying unit 20, the signal S20 at the node N1 is determined by the potential difference between the differential signals S10a and S10b and the control voltage VCT. When the potential difference between the differential signals S10a and S10b is 0, if the current flowing through the NMOS 25 is equal to the current of the current source 24, the potential of the signal S20 is supplied from the resistors 29a and 29b by the current mirror circuit composed of the NMOSs 28a and 28b. This is a divided voltage value of the potential VDD. For example, if the resistors 29a and 29b have the same resistance value, the potential of the signal S20 becomes the voltage divided value VDD / 2.
[0047]
When the control voltage VCT increases, the current flowing through the NMOS 25 increases and the potential of the signal S20 increases. Conversely, when the control voltage VCT decreases, the current flowing through the NMOS 25 decreases and the potential of the signal S20 decreases. Therefore, the potential difference between the differential signals S10a and S10b is compensated by the control voltage VCT.
[0048]
In the differential amplifier 30, the reference voltage VTH is applied to the gate of the PMOS 32. Therefore, if the signal S20 applied to the gate of the PMOS 31 is equal to the reference voltage VTH, the current supplied from the current sources 35 and 36 flows to the PMOSs 31 and 32 in half. The current flowing in the PMOS 32 flows to the ground potential GND via the NMOS 34 as it is. Further, since the gates of the NMOSs 33 and 34 are commonly connected, the magnitudes of currents flowing through the PMOSs 33 and 34 are the same. Therefore, the current flowing through the PMOS 31 flows as it is to the ground potential GND via the NMOS 33, and there is no current flowing into the capacitor 40 side.
[0049]
When the potential of the signal S20 becomes lower than the reference voltage VTH, the current flowing through the PMOS 31 increases and the current flowing through the PMOS 32 decreases. As a result, a difference in current flowing through the PMOSs 31 and 32 flows from the drain of the PMOS 31 into the capacitor 40, and the control voltage VCT increases. When the control voltage VCT rises, as described above, the current flowing through the NMOS 25 increases and the signal S20 rises.
[0050]
Conversely, when the potential of the signal S20 becomes higher than the reference voltage VTH, the current flowing through the PMOS 31 decreases and the current flowing through the PMOS 32 increases. As a result, the difference between the currents flowing through the PMOSs 31 and 32 flows from the capacitor 40 to the drain of the NMOS 33, and the control voltage VCT decreases. When the control voltage VCT decreases, the current flowing through the NMOS 25 decreases and the signal S20 decreases. By such a feedback operation, the DC potential of the signal S20 is controlled to match the reference voltage VTH.
[0051]
Here, the fluctuation of the DC potential of the signal S20 decreases as the capacity of the capacitor 40 increases, and increases as the current supply amount of the current sources 35 and 36 increases. That is, if the capacitance of the capacitor 40 is constant, the current supply amount of the current sources 35 and 36 is increased so that the fluctuation of the DC potential of the differential signals S10a and S10b matches the reference voltage VTH at high speed. Follow. On the contrary, by reducing the current supply amount of the current sources 35 and 36, the fluctuation of the DC potential of the differential signals S10a and S10b follows slowly so as to coincide with the reference voltage VTH.
[0052]
At time T1, the power down signal PDN becomes “L” and the input signal IN is waited.
[0053]
At time T2, a preamble pattern at the beginning of the input signal IN is started. As a result, the differential signal S10a output from the detector 10 becomes a baseband signal biased with the reference voltage VTH, and the DC potential changes in a step-like manner. In response to this, the direct current potential of the signal S20 output from the amplifying unit 20 also fluctuates rapidly. The fluctuation of the DC potential of the signal S20 is returned to the original reference voltage VTH by the feedback operation by the control voltage VCT from the differential amplifier 30. At this time, since the current source 36 of the differential amplifying unit 30 is in an operating state by the current control signal ICT, the DC potential of the signal S20 recovers to the reference voltage VTH following the potential fluctuation at high speed. Thus, the signal S20 is correctly demodulated by the comparator 50, and the demodulated data OUT including the preamble pattern is output. The demodulated data OUT is given to the pattern detection unit 70.
[0054]
When a specific bit pattern such as a preamble pattern in the demodulated data OUT is detected by the pattern detection unit 70 at time T 3, a detection signal PTN is output from the pattern detection unit 70 and is supplied to the current control unit 80. As a result, the current control signal ICT output from the current controller 80 becomes “L”, and the operation of the current source 36 in the differential amplifier 30 is stopped. As a result, the DC potential of the signal S20 output from the amplifying unit 20 changes so as to converge slowly to the reference voltage VTH.
[0055]
If the data in the differential signal S10a continuously has the same sign during the period of time T4 to T5, the potential of the differential signal S10a becomes lower than the reference voltage VTH. At this time, the potential of the signal S20 does not immediately become the reference voltage VTH but changes so as to slowly approach the reference voltage VTH. Therefore, the demodulated data OUT output from the comparator 50 is the same as the data in the differential signal S10a.
[0056]
When the input signal IN stops at time T6, the demodulated data OUT output from the comparator 50 also becomes “L”.
[0057]
When the power down signal PDN becomes “H” at time T7, the current control signal ICT output from the current control unit 80 becomes “H”, and the state returns to the same state as at time T0.
[0058]
As described above, the demodulation circuit according to the present embodiment includes the differential amplifier 30 whose current supply capability is controlled by the current control signal ICT. As a result, when the input signal IN is on standby, the current supply capability of the differential amplifier 30 is increased so that the fluctuation of the offset voltage of the detected differential signal S10 can be followed quickly, and a specific bit pattern such as a preamble pattern can be obtained. During the data reception after detecting, there is an advantage that the current supply capability can be reduced and the same code reception capability can be increased.
[0059]
In addition, this invention is not limited to the said embodiment, A various deformation | transformation is possible. Examples of this modification include the following.
[0060]
(A) The circuit configuration of the amplifying unit 20 is not limited to the illustrated one. In other words, any baseband signal supplied from the detection unit 10 may be amplified to a predetermined level and biased to a DC potential corresponding to the control voltage VCT and output.
[0061]
(B) The circuit configuration of the differential amplifier 30 is not limited to the illustrated one. That is, a signal corresponding to the potential difference between the signal S20 and the reference voltage VTH given from the amplifying unit 20 is fed back to the amplifying unit 20 as the control voltage VCT, and the magnitude of the drive current is switched by the current control signal ICT. I just need it. For example, the current sources 35 and 36 are connected to the power supply potential VDD side, but may be provided on the ground potential GND side.
[0062]
(C) Although the reference voltage VTH is generated by dividing the power supply potential VDD by the resistors 61 and 62 having the same resistance value, the value of the reference voltage VTH and the generation circuit are not limited to this.
[0063]
(D) In the current control unit 80, when the power down signal PDN becomes “H”, the current control signal ICT is switched to “H” to enable the operation of the current source 36. Any signal timing may be used as long as the current control signal ICT can be switched to “H” before the input is started.
[0064]
【The invention's effect】
[0065]
As described above in detail, according to the first invention, the differential amplifier is driven by the driving current switched according to the current control signal and outputs a current corresponding to the potential difference between the reference voltage and the signal output from the amplifying unit. And a capacitor that feeds back the control voltage charged with the current output from the differential amplifier to the amplifier. This makes it possible to switch the response speed by switching the magnitude of the drive current with the current control signal, compensates for fluctuations in the DC potential with respect to the burst signal at high speed, and receives the same code continuous pattern without error. be able to.
[0066]
According to the second invention, when the input signal does not exist, switching is performed so as to increase the drive current of the differential amplifier, and when the specific bit pattern is detected by the pattern detector, the drive current is decreased. A current control unit for outputting a current control signal for switching to Thereby, it is set so that the response speed of the bias voltage control of the amplifying unit is increased in the no-signal state, and the response time at the rising edge of the input signal can be shortened. Further, when data reception is started, the response speed of the bias voltage control of the amplifying unit is set to be slow, and even if the same code continues, it can be demodulated without error.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a demodulation circuit showing an embodiment of the present invention.
FIG. 2 is a circuit diagram of a conventional demodulation circuit.
FIG. 3 is a signal waveform diagram showing an example of the operation of FIG. 1;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Detection part 20 Amplification part 30 Differential amplification part 35,36 Current source 40 Capacitor 50 Comparator 70 Pattern detection part 80 Current control part

Claims (2)

A detection unit for detecting a frequency-modulated input signal and outputting a baseband signal;
An amplifying unit for amplifying the baseband signal and biasing the amplified signal to a direct current potential according to a control voltage and outputting it;
A differential amplifier that is driven by a drive current that is switched according to a current control signal, and that outputs a potential difference between a reference voltage and a signal output from the amplifier and a current corresponding to the drive current;
A capacitor that is charged by a current output from the differential amplifier, generates the control voltage, and supplies the control voltage to the amplifier;
A comparator that compares the reference voltage and the potential of the signal output from the amplifier, and outputs the comparison result as demodulated data;
A demodulation circuit comprising: A detection unit that detects the input signal that is frequency-modulated and input in a burst manner and outputs a baseband signal;
An amplifying unit for amplifying the baseband signal and biasing the amplified signal to a direct current potential according to a control voltage and outputting it;
A differential amplifier that is driven by a drive current that is switched according to a current control signal, and that outputs a potential difference between a reference voltage and a signal output from the amplifier and a current corresponding to the drive current;
A capacitor that is charged by a current output from the differential amplifier, generates the control voltage, and supplies the control voltage to the amplifier;
A comparator that compares the reference voltage and the potential of the signal output from the amplifier, and outputs the comparison result as demodulated data;
A pattern detection unit that detects a specific bit pattern included in the demodulated data and outputs a detection signal;
When the input signal is not present, the current control signal for switching to increase the drive current of the differential amplifier is output, and when the detection signal is given, the drive current is switched to be reduced. A current control unit that outputs the current control signal;
A demodulation circuit comprising:

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