JP3928414B2 - DIGITAL DATA RECORDING / REPRODUCING METHOD, DIGITAL DATA RECORDING / REPRODUCING DEVICE, AND RECORDING MEDIUM - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention can be suitably used for a digital data reproduction method, a digital data recording method, a digital data reproduction device, and a digital data recording device that use error correction techniques for removing errors, particularly error correction by product codes. Further, the present invention can be suitably used for a digital data reproducing apparatus and a digital data recording apparatus that perform interleaving on a plurality of lines of data in byte units.
[0002]
[Prior art]
The present invention can be widely applied to digital data reproduction systems and recording systems that perform error correction of product codes. Here, a DVD data reproduction system and data recording system will be described as an example.
[0003]
A DVD (digital versatile disc) is a medium having a capacity about seven times that of a CD (compact disc). Examples of media for recording data on a DVD include DVD-RAM, DVD-R, and DVD-RW. The recordable media is the most promising field as seen in the recent CD-R growth.
[0004]
In the error correction of the current DVD, interleaving is performed in units of rows for data consisting of a plurality of rows. How this interleaving is performed at the time of recording and at the time of reproduction will be described below using the DVD-RAM format as an example.
[0005]
First, an outline of processing at the time of recording data recorded on the DVD-RAM will be described with reference to FIG. The main data to be recorded is divided in units of 2048 bytes, and as shown in FIG. 4, a 4-byte data identification signal ID 401 and an error detection code parity IED (ID Error Detection Code) 402 of 2-byte ID are provided at the beginning of each. And a 6-byte RSV (reservation bytes) 403 as a spare area, a total of 12 bytes are added, and a 4-byte error detection code parity (EDC) is added to the 2060-byte data string, and 2064-byte ( Configure data unit 1 (304) before scrambling. Next, the main data portion of 2048 bytes is subjected to scramble processing according to the scramble rule determined by the value of the ID portion of data unit 1, and the data unit 1 (305) of 12 rows × 172 bytes (after scramble) is applied. Become. Further, 16 bytes of outer code parity (PO) is added to each of 172 columns (vertical direction) of 16 data units 1 of 192 rows × 172 bytes, which can be obtained by superimposing 16 (scrambled) data units 1. Then, an inner code parity (PI) of 10 bytes is added to each of 208 rows (in the horizontal direction) including PO to form one ECC block (307) which is a 182 rows × 208 bytes cross-Reed-Solomon code. After that, PO interleaving is performed by sandwiching the 16 rows of PO sections (including the 16 rows of PI) as 13 rows of each data unit 1 row by row, and 16 data units 2 (308) (that is, 13 rows). 1 data unit 2), and after being subjected to 8/16 modulation to convert all data from 8 bits to 16 bits, a 26 SYNC code is added per 1 data unit 2 to 16 data units 3 (309).
[0006]
Hereinafter, each data unit configuration will be described in detail.
[0007]
As shown in FIG. 4, the data unit 1 (305) (after scrambled) includes 2048-byte main data, 4-byte data identification signal ID 401, and 2-byte ID error detection code parity IED (ID Error Detection code) 402, 6 bytes RSV (reservation bytes) 403 as a reserved area, and 4 bytes of error detection code EDC (Error Detection Code) 404 in total in a format of 172 bytes × 12 rows, This is a data unit formed by scrambling the 2048-byte main data part.
[0008]
16 data units 1 (306) (after scrambled) is a data field of 172 bytes × 192 rows formed by overlapping 16 data units 1 (305) as shown in FIG. Predetermined error correction data is added to 16 data units 1 (306) (after scrambled) to form one ECC block 307 which is an error correction code.
[0009]
1 ECC block 307 is a unit of error correction processing in DVD, and as shown in FIG. 6, 16 data units 1 are information data (main data), and each of 172 columns is an RS (208, 192, 17) code. After forming the outer code (16 bytes of outer code parity PO502 is added as error correction data), 208 lines including PO502 in the same direction as the main data arrangement and the DVD recording direction are RS (182, 172, 11) is a product code (cross-Reed-Solomon code) formed by forming an inner code (adding an inner code parity PI501 as error correction data).
[0010]
The data unit 2 (308) is a data unit after the ECC block 307 is formed, and each row of 16 rows of PO502 is inserted into each data unit including PI501 as shown in FIG. 7 (PO interleave). A data unit composed of 182 bytes × 13 rows.
[0011]
As shown in FIG. 8, the data unit 3 (309) has eight types (SY0 to SY7) of synchronization signals (SYNC) 801 at the head of every 91 bytes of the data unit 2, and SYNC0 (SYNC code 0) at the head of the unit. Each row is identified by a data string obtained by applying 8/16 modulation for converting 8-bit data into 16-bit data by cyclically repeating SY1 to SY4 and SY5, SY6, and SY7. Further, at the time of reproduction from the method of attaching the SYNC 801, the position of the data being reproduced in the data unit 3 can be specified by the generation pattern of the SYNC 801.
[0012]
After such conversion from the data unit 1 to 3 is performed, the data modulated on the DVD is recorded after being subjected to NRZI (Non Return to Zero) conversion.
[0013]
Here, the arrangement of the main data recorded on the DVD is not changed at all during the data conversion process such as scramble, ECC encoding, PO interleaving, and the like. And the order is the same. Therefore, at the time of reproduction, the data recorded on the DVD is performed in the reverse process of the data processing performed in FIG.
[0014]
Hereinafter, conventional data processing during DVD reproduction will be described with reference to FIG.
[0015]
While determining the position in the data unit 3 (902) using the SYNC 801, 8/16 demodulation is performed to generate the data unit 2 (903). Next, the PO interleave is canceled while determining the position of the data unit 2 in the ECC block 307 using the ID 401, and the ECC block 901 corresponding to the ECC block 307 before error correction is formed.
[0016]
Since playback data from a DVD contains errors that occur due to various factors, error correction for inner codes in the same sequence as the data recorded on the DVD allows a maximum of 5 bytes for each inner code (usually error correction) In this example, each piece of data constituting the code is represented by a word such as “word” or “symbol”, but here, an explanation will be made using “byte” as an example of the data unit), and error correction is performed. In error correction, an error of up to 16 bytes included in each outer code is corrected, and the error is removed. After that, the ECC block (901) removes the PI501 and PO502 of the error correction data to form 16 data units 1 (305) shown in FIG.
[0017]
The data in data unit 1 (305) is descrambled (304), and after performing error detection processing using EDC to confirm that no error correction has occurred in the error correction processing, ID, IED, Restored to RSV and 2048-byte main data (303).
[0018]
The above is the outline of the data signal processing performed at the time of recording and reproducing the DVD.
[0019]
[Problems to be solved by the invention]
In the error correction processing described with reference to FIG. 9 during reproduction of a DVD, error correction of an inner code having the same sequence as data recorded on the DVD is performed.
[0020]
As described above, DVD error correction is performed in units of ECC blocks that are product codes. In error correction of the ECC block, after performing error correction for the inner code, error correction for the outer code is further performed in order to correct an error that could not be corrected by this code.
[0021]
In the correction of the outer code, it is possible to perform erasure correction performed by determining the error position using the correction result of the inner code. For example, the relationship between the data arrangement on the DVD and the data arrangement on the ECC block does not disperse the error for consecutive errors as indicated by the black portion in FIG. After the error correction with respect to the error code occurs, correction of several places becomes impossible, and error correction with respect to the outer code is performed by performing erasure correction using the result as error position information.
However, when a short burst error that occurs randomly as shown by the black part in FIG. 10A overlaps with a specific outer code, the error correction for the inner code corrects the burst error. If the error correction becomes impossible and the number exceeds the number that can be corrected by the outer code, the correction becomes impossible by many outer codes. (B-1) and 10 (B-2) in FIG. 10 will be described later.
[0022]
Further, as the recording data is increased in density to increase the capacity, an error of about 1 or 2 bytes generated due to dust, scratches, etc. of the current DVD becomes a short burst error. That is, it is expected that the average length (number of bytes) of the target error will increase and the number of cases where correction will not be possible will increase.
[0023]
Although the error correction capability can be improved by increasing the amount of error correction data added to the main data, there is a problem that the recording efficiency is lowered because the redundancy is increased accordingly. In other words, the recording capacity of the main data decreases as the recording capacity of the error correction data increases. Generally, in a recording medium, securing the recording capacity is one of the most important issues, and it is necessary to improve the error correction capability without reducing the recording efficiency.
[0024]
As a countermeasure against these errors, there is an invention described in JP-A-8-125548. The present invention is a method of distributing the error over the entire product code by rearranging the data within a predetermined product code as a unit of several bytes. There is a possibility that correction ability cannot be secured. This is because the burst error is distributed in the outer code direction by rearranging between rows, and the error is distributed to the area that should originally be corrected, and as a result, the uncorrectable area returns and increases. Because there is.
[0025]
On the other hand, in the present invention, as will be described later, since rearrangement is not performed between rows, errors are not distributed to outer codes, and the correction capability for burst errors can be maintained.
[0026]
Further, while the invention described in Japanese Patent Laid-Open No. 8-125548 does not change the rearrangement rule for each row, the present invention changes the rearrangement rule for each row. Error correction can be performed efficiently.
[0027]
As another countermeasure, there are inventions described in JP-A-3-266264 and JP-A-9-54956. These inventions are intended to increase resistance to burst errors by arranging words included in codes in the column and row directions so as to be separated from each other by a predetermined distance or more.
[0028]
However, the present invention is different from the present invention in that the rearrangement rule is not changed for each line and the rearrangement is performed across a plurality of lines, and the burst error length may not be maintained. .
[0029]
An object of the present invention is to provide a technique with improved error correction capability that can solve the above problems.
[0030]
[Means for Solving the Problems]
In the present invention, to solve the above problemsAs an example, the structure described in the claims is used.
[0040]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described with reference to the drawings. Here also, a DVD data reproduction system and data recording system will be described as examples.
FIG. 1 is an example showing a data processing process during recording when the present invention is applied to the current DVD logical format shown in FIG.
[0041]
FIG. 1 will be described briefly. The main data to be recorded is divided in units of 2048 bytes, and as shown in FIG. 4, an IED (ID Error Detection Code) of a 4-byte data identification signal ID 401 and an error detection code parity of 2-byte ID at the head of each. 402, and 6 bytes RSV (reservation bytes) 403 as a reserved area, a total of 12 bytes are added, and a 4-byte error detection code parity (EDC) is further added to the 2060-byte data string. Construct data unit 1 (304) (before scramble). Next, the main data portion of 2048 bytes is subjected to scramble processing according to the scramble rule determined by the value of the ID portion of data unit 1, and the data unit 1 (305) of 12 rows × 172 bytes (after scramble) is applied. Become. Further, 16 data units 1 (305) (16 scrambled) can be overlapped and 16 data units 1 (306) of 192 rows x 172 bytes can be overlaid on each of 182 columns (vertical direction). Parity (PO) is added, then 10 bytes of inner code parity (PI) is added to each of the 208 rows (in the horizontal direction) including PO, and one ECC block that is a 182 row × 208 bytes cross-Reed-Solomon code ( 307). Next, the data in each row of the ECC block is rearranged in units of 1 byte according to each rule, and the ECC block 101 is obtained. After that, PO interleaving is performed by sandwiching the PO portion of 16 rows (including the PI of 16 rows) as the 13th row of each data unit 1 by row, and 16 data units 2 (102) (that is, 13 rows) 1 data unit 2), and after being subjected to 8/16 modulation to convert all data from 8 bits to 16 bits, a 26 SYNC code is added per 1 data unit 2 to 16 data units 3 (103).
[0042]
In FIG. 1, PI interleaving is performed immediately after the ECC block is generated, but PI interleaving may be performed after the data unit 2 is configured or after the data unit 3 is configured. That is, PI interleaving can be performed at an arbitrary time after the ECC block is generated.
[0043]
Hereinafter, PI interleaving will be described. To give a specific example, PI interleaving means interleaving processing for rearranging the order of 182 bytes of data (inner code) of each row of the ECC block of the DVD as shown in FIG. That is, it shows a process of rearranging the order of the bytes of a data string comprising a plurality of bytes constituting an error correction code (explained on the assumption that “word” and “symbol” as data units are bytes). Here, an error correction code refers to a code in which error correction data is added to desired data to be recorded, and an ECC block that is a product code will be described here as an example. The rearrangement is described as being performed for one row of the inner code, that is, the data unit 1 (part corresponding to the main data) and the parity. It is also possible to carry out only for the part 1 or only for the parity part, in which case there is no correlation between the inner codes of 208 rows in the ECC block. The use of different conversion rules (interleave rules) Fi (x) (= y) is more effective in terms of error dispersion, but at least two types of conversion rules (interleave rules) F1 (x), Even if this PI interleaving is performed using F2 (x), it is possible to obtain the effect of distributing errors, and the data Di, 0, Di, 1, Di, 2,. The data constituting the inner code of the i-th row of the ECC block is shown, and Di, 171, Di, 172, ..., Di, 181 correspond to the inner code parity PI, and therefore PI in the data string of (A). The data sequence (B) generated by performing interleaving is not necessarily an inner code.
[0044]
It is also possible to perform PI interleaving for rearranging the data recording order between a plurality of inner codes. In this case, it is possible to obtain a higher correction capability for random errors, but the burst error length becomes shorter.
[0045]
FIG. 11 is a diagram showing the ECC block (101) after the PI interleaving in FIG. This shows a state where each row of the ECC block of FIG. 6 is converted by performing PI interleaving.
[0046]
When actually recording on the disc, the data of the 16 data units 3 described above are recorded in the order of the data in the inner code direction. Next, data processing during reproduction will be described.
[0047]
FIG. 12 shows the flow of data conversion when the data generated after the data conversion of FIG. 1 is recorded on a DVD and reproduced.
[0048]
In FIG. 12, the data recorded on the DVD is subjected to 8/16 demodulation while determining the position in the data unit 3 using the SYNC 801, and the data unit 2 (1203) is generated. Next, the PO interleaving is canceled while determining the position of the data unit 2 in the ECC block 307 using the ID 401, and the ECC block (1201) shown in FIG. 11 subjected to the PI interleaving process is formed. Thereafter, the conversion rule Gi (y), which is the inverse conversion of Fi (x) shown in FIG. 13, that is, the conversion of returning the symbol string (A) formed by rearranging the data during modulation back to the PI code (B) is performed. PI deinterleaving is performed on each row and restored to the ECC block (901) of FIG. 6, and thereafter, error correction for the inner code is performed up to a maximum of 5 bytes for each inner code as in the conventional method. Error correction up to 16 bytes included in each outer code is performed by error correction for the code (306). Thereafter, the ECC block removes the error correction data PI and PO necessary for the error correction processing, is restored to the 16 data units 1 (305) shown in FIG. 5, is unscrambled (304), It shows that after performing the used error detection processing, ID, IED, RSV and 2048-byte main data (303) are obtained again. Note that the conversion rules Fi (x) and Gi (x) may be stored on the device side as predetermined rules, and the conversion rules Fi (x) and Gi (x) are recorded for each medium. However, the apparatus side may read the information. In the latter case, the apparatus side first reads the conversion rules Fi (x) and Gi (x) and then performs the above processing. Further, the conversion rules Fi (x) and Gi (x) may be determined for each disk, may be determined for each ECC block, and may be determined for each frame.
[0049]
The rearrangement of the data string is performed for each row of the ECC block as described above. That is, not only the main data (306) but also the entire data sequence of the ECC block including the parity of the inner code parity (PI) and the outer code parity (PO) is rearranged.
[0050]
However, in the DVD used as an example in this description, since the position in the ECC block is determined using the ID when performing the normal demodulation processing as shown in FIG. 12, if the ID is also subjected to PI interleave processing at the time of recording, the ECC is ECC. When different PI interleaving is applied to all the rows, the PI interleaving conversion rule y = Fi (x) of the row including the ID is not known, and x = Gi (y used for PI deinterleaving when restoring the data string ) Cannot be determined, and it is very difficult to find an ID.
[0051]
Therefore, information indicating the position in the product code, ID and IED (IED is also required when ID reliability is required) are excluded from data interleaving, and identification information such as ID and IED is included in the line including this information. Only the 176-byte data except the PI interleave process is performed. By doing so, it is possible to easily detect the ID and determine x = Gi (y) when performing PI deinterleaving.
When this is applied to a DVD, the data unit 2 (102) in FIG. 1 is as shown in FIG. In this case, since data excluding ID and IED are to be scrambled, identification information including EDC, RSV, etc. cannot be obtained until PI interleaving is solved and decoded into the original inner code.
[0052]
Therefore, if the information necessary before forming the ECC block at the time of reproduction is included in RSV or the like, the effect of PI interleaving is slightly weakened. However, like ID, the data is also excluded from the interleaving target. Similar effects can be obtained.
[0053]
Further, when ID and IED are excluded from the target of PI interleaving as shown in FIG. 14, the conversion rule Fi (x) of the inner code including ID and IED is set to x = 1,. In the case of indicating a position address such as shown in FIG. 5, devise that Fi (n) = n (n = 1, 2, 3, 4, 5, 6) or limit x and Fi (x) from 6 to 182 To do.
[0054]
Reference is again made to FIG. FIG. 2 is an example of a diagram showing how data is arranged when PI interleaving is applied to the inner code described with reference to FIG. 6 according to the PI interleaving conversion rule Fi (x). The inner code is a data string of 182 bytes, (A) shows the inner code after the addition of PI and PO, (B) shows the internal code 182 by performing PI interleaving according to the conversion rule Fi (x) and rearranging the data order. Indicates a byte data string. Here, (B) shows an example in which data is rearranged every thirteen, but the conversion rule Fi (x) is not limited to this, and any conversion rule that discontinuously arranges may be used.
[0055]
As shown in FIGS. 10A to 10D, a plurality of types of conversion rules Fi (x) are prepared for different PI interleaving, and in the case of DVD, a maximum of 208 types are prepared, and different conversion rules are applied for each inner code. Since the number of errors on the outer code in the ECC block is averaged, the number of cases where error correction for the outer code becomes possible increases. Thus, it is possible to improve the correction capability by performing different PI interleaving on the inner code and recording it on the recording medium. Also, this effect becomes even greater when decoding is repeated.
[0056]
Next, a method for realizing this PI interleave conversion rule as a circuit will be described. First, an example of the configuration of a DVD recording / reproducing apparatus when the present invention is applied will be described with reference to FIG. Here, a recording / reproducing apparatus will be described as an example, but the present invention can also be applied to a reproduction-only apparatus and a recording-only apparatus.
[0057]
1501 is a recording medium such as a DVD, 1502 is a pickup for recording and reproducing data on the recording medium 1501, and 1503 is a spindle motor for rotating the disk. A servo 1504 controls the optical pickup 1502 and the like. Reference numeral 1505 denotes a read channel that performs waveform equalization processing, binarization, and synchronization clock generation of an analog reproduction signal read from the recording medium 1501. 1506 includes a demodulating circuit 1507 for demodulating the read data by 8/16, and an error correcting circuit (1507, 1508) for performing an error removing process included in the data. This RAM is temporarily stored. A RAM 1509b temporarily stores data during recording. This may be combined with 1509a. Reference numeral 1514 denotes a laser driver. Reference numeral 1512 denotes a modulation circuit that performs recording data modulation processing. Reference numeral 1513 denotes an encoding processing circuit that includes an error correction code that adds error correction code parity PI and PO, a scramble circuit that performs scramble processing, and the like. . Reference numeral 1515 denotes an interface for performing data input / output control with a host device, and reference numeral 1516 denotes a microcomputer that controls the system. It is also possible to use a microcomputer as an error correction code generation circuit for adding error correction code parity PI and PO.
[0058]
Reference numeral 1517 denotes a PI interleave circuit (a signal processing circuit for rearranging the data in the inner code as shown in FIG. 2), and reference numeral 1518 denotes a PI deinterleave circuit (a signal processing circuit for canceling the PI interleave). 13 is performed). That is, 1517 is for rearranging the order of the bytes for the data sequence consisting of a plurality of bytes constituting the error correction code, and 1518 is for rearranging the order of the bytes forming the data sequence for the rearranged data sequence. The data sequence is returned to the order before the sorting.
[0059]
The PI interleave circuit 1517 has an SRAM and a register that can store at least 182 bytes of data in a system that performs PI interleaving closed within one inner code. After recording, an ECC block is generated from the RAM 1509b in units of inner codes. After reading the data and temporarily storing it in the register in the read-out sequence, that is, in the form of an inner code, the data in the register is again stored in the RAM 1509b while converting the data sequence according to a predetermined PI interleave conversion rule. Will be written.
[0060]
The PI deinterleave circuit 1518 has a register or SRAM that can store at least 182 bytes of data in a system with PI interleaving closed within one inner code, and at the time of playback processing after data is read from the DVD In 8), immediately after the 8/16 demodulation, data is read out from the RAM 1509a in units of inner codes, and the data is temporarily stored in the register in that order, and then the data order is converted again in the RAM 1509a while converting the data order according to a predetermined PI interleave conversion rule. Write the data. Further, this PI deinterleave circuit 1518 increases the number of built-in SRAMs and registers, and is arranged immediately after the demodulation circuit in the decode processing circuit 1508. The data output from the demodulation circuit is directly input to the register, and is equivalent to the inner code. The same processing is possible even in a configuration in which the byte data string is arranged and then the data on the register is arranged in the RAM 1509a while performing PI deinterleaving.
[0061]
Next, the PI interleave circuit and the PI deinterleave circuit in FIG. 15 will be described. FIG. 19 shows an M sequence generation circuit 1901 (a circuit that generates a maximum periodic sequence, and 255 is the maximum periodic sequence (= M sequence) when an 8-bit register is used). An example of the circuit 1517 is shown. Here, it is assumed that the inner code read from the RAM 1509b is already stored in the shift register 1902. As a write control signal to the RAM 1509b, there is a write request signal, an address of the RAM 1509b (in this case, 1 to 182 for convenience), and write data. Is received.
[0062]
In this circuit, the shift register 1902 shifts when a write request acceptance signal is input, that is, when data is written. Similarly, the M-sequence generation circuit 1901 similarly receives a write request acceptance signal, or the signal 1 to 255 generated by the M-sequence generation circuit 1901 (the width of the value does not need to be 1 to 255. The inner code is 182. Here, PI interleaving is considered for all the data in the inner code, so the output from the 8-bit M-sequence generation circuit is used). If it is, it changes to the next value. The write request signal is output when the address generated by the M series generation circuit 1901 is determined to be 182 or less by the request generation determination circuit 1903.
[0063]
This is because when the address created by the M-sequence generation circuit 1901 exceeds 183, the PI interleave processing cannot be performed, and the address is skipped.
[0064]
FIG. 20 shows an example of a PI deinterleave circuit 1518 that defines a PI interleave conversion rule using the M-sequence generation circuit 1901. Here, it is assumed that the data string read from the RAM 1509a is already stored in the register 2001.
As a write control signal to the RAM 1509a, there are a write request signal, an address of the RAM 1509a, and write data. When the write request signal is output, a write request acceptance signal indicating that data has been written from the RAM 1509a is input.
[0065]
In this circuit, when the value of the M sequence generation circuit 1901 that is the same as the M sequence generation circuit 1901 defining the PI interleave conversion rule exceeds 183, the M sequence generation circuit 1901 outputs the next value. When the value is 182 or less, a write request is generated, and 1-byte data of the data string selected by the value of the M-sequence generation circuit 1901 is written to the address indicated by the counter 2002. Since a write request acceptance signal is input when writing is performed, the counter 2002 for generating an address indicates the next value, and the M-sequence generation circuit 1901 also indicates the next value.
[0066]
Even in this circuit, when the value generated by the M-sequence generation circuit 1901 exceeds 183, PI deinterleaving cannot be performed, and thus a mechanism for skipping the value is necessary. That is, in a random number generation circuit such as the M-sequence generation circuit 1901, the identification information such as ID and IED is processed so as not to be subject to PI interleaving so that the identification information can be easily detected. .
[0067]
In these circuits, when the address is 1 to 6 in the request generation determination circuit in the inner code including the ID, it is treated the same as 183 or more (the original inner code on the RAM 1509b, that is, stored in the register 1902) It is not necessary to write the ID and IED to the RAM 1509b when overwriting a data string in which PI interleaving is applied to the inner code, and when storing it in another area on the RAM 1509b, the ID and IED are written at a predetermined position. Add).
[0068]
However, the countermeasure for the inner code including the ID can be easily realized by adding an offset to the address.
[0069]
19 and FIG. 20, the M sequences that define the PI interleaving rules can be generated in the following combinations (multiple types (208 or more necessary for different interleaving conversion rules for all inner codes on a DVD)). .
[0070]
This can be easily realized only by combining the following 1 and 2.
1. Change the feedback type of the shift register that generates the M series (corresponding to the relationship between FIG. 16A and FIG. 16B).
2. Rearrange the position of data output from the shift register (corresponding to the relationship between FIG. 16A and FIG. 17A)
For example, the feedback rule of the circuit that generates the M-sequence is changed in the unit of the data unit 2 in FIG. 1, that is, the unit of the data unit in FIG. If the rearranged positions are rearranged, 208 different PI interleave conversion rules can be obtained.
[0071]
Further, as shown in FIG. 17B, different M sequences are generated even if the polarity of a certain bit is changed. However, in this case, 0 may be output from the M series, and the value obtained when all the registers are 0. In FIG. 17B, the address of AA (= 170) in hexadecimal is not generated. However, it can be used as an M sequence that defines the PI interleaving rule. Similarly, it is obvious that the address can be converted using a logic circuit that combines logical sum, logical product, and negation.
[0072]
As shown in FIG. 23A, a value obtained by adding a different value in each row (however, a fixed value in the same row) to the value output from the M-sequence generation circuit 1901 in FIGS. 16A, 16B, 17A, and 17B shown previously. Is also an M-sequence, and can be used as the PI interleave conversion rule of the present invention. In this case, however, the carry to the ninth bit (MSB) generated by addition is ignored.
[0073]
Further, the addition circuit 2302 in this figure is a multiplication circuit 2303 as shown in FIG. 23B, and a fixed value corresponding to each row is represented by a finite field GF (2⁸) The value obtained by multiplication above is also an M series, and can be used as the PI interleave conversion rule of the present invention. The row counter 2301 counts the position of the inner code in the product code, that is, the row address.
[0074]
In addition, in order to achieve the object of performing PI interleaving according to the present invention, that is, a method for generating a plurality of PI interleave conversion rules that is the simplest in circuit for uniformly distributing burst errors that occur randomly in units of several bytes to all outer codes. As an example, there is a method of changing the initial value of the M-sequence generation circuit 1901 in FIG. 19 according to the row. This means that M sequences generated from the same M sequence generation circuit 1901 are generated in a shifted manner. As an example, there is a method of substituting a row address as an initial value of a PI interleave conversion rule. As a result, at least 182 types of PI interleave conversion rules are generated. However, in order to use different PI interleave conversion rules in all 208 lines, it is necessary to combine with other PI interleave conversion rule generation methods. Note that any method other than the above example may be used as long as the M series can be changed according to the row.
[0075]
The PI interleave circuit 1517 and the PI deinterleave circuit 1518 of FIG. 15 can be realized by another method without using the M-sequence generation circuit 1901.
[0076]
This is a method of realizing the PI interleave conversion rule with a ROM or a circuit as shown in FIGS. This is particularly effective when only a few PI interleave conversion rules are required. Further, a higher effect can be expected in that the address can be set freely such that the PI interleaving rule manages the distance between adjacent data on the inner code in order to improve random characteristics.
[0077]
Further, there is a method of using an arithmetic sequence as a PI interleave conversion rule other than the M series.
[0078]
Here, as the PI interleaving rule, any 182 numbers may be used as the DVD PI interleaving rule, so 0 to 181 are used.
[0079]
This is a method of rearranging the arrangement of inner codes according to an arithmetic sequence. For example, when a sequence of numbers increasing by 3 is used, 0, 3, 6, 9, ..., 177, 180, 1, 4, 7, ..., 178, In this method, the data positions on the inner code are rearranged according to the PI interleaving rules of 181, 2, 5, 8, ..., 176, 179.
[0080]
In this case, it is necessary to use a constant that is different for each row as an increment. However, when a number that is relatively prime to 182 is used as a constant, for a number that exceeds 181, a number obtained by subtracting 182 from that number is used. If the numbers that are not relatively prime are constants, for example, in the case of 2, 0, 2, 4, 8,..., 180, 0, 2, 4,. Therefore, a mechanism such as adding 1 when exceeding 182 is necessary so that the same number is not twice.
[0081]
Also, if most of the random burst errors that are targeted are 10 bytes or less, it is better to select 11 or more as the increment constant.
[0082]
However, when an arithmetic sequence is used, when 182 bytes are used as an inner code, the case where 1 is selected as a constant and the case where 181 is selected are the same for the purpose of distributing errors to different outer codes. It should be noted that it is a thing.
[0083]
This is 0, 1, 2, 3, 4,..., 181 when 1 is selected as a constant, and 0, 181, 180,..., 4, 3, 2, 1 when 181 is selected. This is because the left and right numbers are the same when the left and right are different.
[0084]
FIG. 24 shows an example of a circuit for generating an arithmetic sequence (only numbers that are relatively prime with 182 are used except for 1).
[0085]
In this figure, the value output from the 8-bit register 2401 is an arithmetic sequence, and an increment corresponding to the value of the row address is obtained in accordance with the inner code, that is, as many different sequences as possible depending on the row. A constant is selected and switched for use.
[0086]
An example in which the equidistant sequence is applied to the PI interleave circuit 1517 and the PI deinterleave circuit 1518 in FIG. 15 is shown in FIGS. This can be configured by simply replacing the previously described M-sequence generation circuit 1901 of FIGS. 19 and 20 with the arithmetic sequence generation circuit 2501 of FIG.
[0087]
FIG. 19 is taken as an example of the M-sequence generation circuit 1901 of the PI interleave circuit 1517 in FIG. 15, and the method of arranging the data of the inner code at an address corresponding to the M-sequence one byte at a time is shown. There is a method of using the PI deinterleave circuit 1518 as the PI interleave circuit 1517 and arranging the data at the position on the inner code generated in the M sequence in the M sequence order.
[0088]
The PI deinterleave circuit 1518 corresponding to this is shown in FIG.
[0089]
As a matter of course, when different M sequences are used, even when this method is used, the purpose of distributing burst errors on different outer codes can be achieved.
[0090]
However, when this method is used, burst errors cannot be distributed over different outer codes by changing the initial value of the M sequence by row.
[0091]
The relationship between the two types of PI interleaving methods is the same in the arithmetic sequence generator circuit 2501 described with reference to FIG. 25 of the PI interleave circuit 1517 and FIG. 26 of the PI deinterleave circuit 1518.
[0092]
The PI interleave conversion rule can be constituted not only by one method but also by several combinations including the introduced M series and the arithmetic sequence, and a circuit for realizing it can also be realized by a combination of each element.
[0093]
Further, in order to generate a large number of PI interleave conversion rules, the M-sequence generation circuit 1901 may be combined with the ROM and address decoders 1801 and 1802 generated by the circuit.
[0094]
Further, it is necessary to consider the PI interleave conversion rule from the circuit, and in order to perform the conversion process at high speed, as shown in FIG. 21, it is possible to simultaneously perform PI interleaving using a plurality of lines using the same conversion rule. As shown, PI interleaving can be performed simultaneously in a plurality of bytes (2 bytes in FIG. 22) within the same inner code. That is, it is possible to arrange a plurality of bytes as a set and rearrange the order of the set in units of the set.
In actual circuitization, an optimum PI interleaving method may be selected in consideration of the RAM bus width and data arrangement in accordance with the required processing speed. In addition, it is necessary to consider the circuit scale at the time of realization and the improvement in performance obtained by the present invention.
[0095]
In addition, these figures show an example of PI interleaving in units of 2 bytes, but the number of inner codes to which the same PI interleaving is actually applied may be 3 or more.
[0096]
Although the case where the present invention is applied to a DVD as an example has been described through this embodiment, the present invention is effective in a digital data recording / reproducing apparatus and a digital data recording / reproducing method including a product code.
[0097]
It should be noted that the inner code used in the description corresponds to the outer code when recording on the recording medium is performed according to the arrangement of the outer code of the product code. Further, the PI interleave circuit 1517 and the PI deinterleave circuit 1518 have been described by exemplifying the signal processing circuit using the M series and the arithmetic sequence, but other pseudo-random number generation circuits and the like may be used.
[0098]
The digital data recording / reproducing apparatus and the digital data recording / reproducing method have been described so far. However, the present invention can also be applied to a recording medium, that is, a disc itself. Specifically, an error correction code composed of a plurality of data strings in which the order of words forming the data string is rearranged according to a rule determined for each data string is recorded in the recording area of the disk. As for the rearrangement of the word order here, for example, the order of words other than the identification information is rearranged, rearranged according to a plurality of different rules determined for each data string, and rearranged as a set of a plurality of words. A method similar to the method described so far in the description of the digital data recording / reproducing apparatus and the digital data recording / reproducing method can be applied.
[0099]
Data is recorded on the disc in the order of data in the inner code direction of the error correction code.
[0100]
【The invention's effect】
Each line of product code is byte-interleaved according to different rules for each line, and short burst errors of several bytes to several tens of bytes are rearranged using different rules for each line, and distributed so that there is as little correlation as possible. As a result, even when correction is impossible in the past without changing the burst correction length, the number of errors is averaged, so that the probability that more errors can be corrected increases. In addition, iterative correction having an excellent ability for random errors can also correct more errors with the same or fewer iterations in many cases than before.
[0101]
[Brief description of the drawings]
FIG. 1 is a diagram showing a data processing flow during recording when the present invention is used in a DVD.
FIG. 2 shows an example of PI interleaving.
FIG. 3 is a diagram showing a data processing flow during DVD recording.
FIG. 4 is a diagram showing a data unit 1 after being scrambled.
FIG. 5 is a diagram showing 16 data units 1 after scrambling.
FIG. 6 is a diagram showing an ECC block.
FIG. 7 is a diagram showing 16 data units 2;
FIG. 8 is a diagram showing a data unit 3;
FIG. 9 is a diagram showing an example of a data processing flow when reproducing a DVD.
FIG. 10 is a diagram illustrating an effect when PI interleaving is performed on a short burst error and a long burst error.
FIG. 11 is a diagram showing one ECC block after PI interleaving.
FIG. 12 is a diagram showing a data processing flow during reproduction when the present invention is used on a DVD.
FIG. 13 is a diagram showing an example of processing for releasing PI interleaving.
FIG. 14 is a diagram showing an example of a data unit 2 after PI interleaving.
FIG. 15 is a diagram showing an example of a DVD recording / reproducing apparatus to which the present invention is applied.
FIG. 16 is a diagram illustrating an example of an M-sequence generation circuit.
FIG. 17 is a diagram showing an example of an M-sequence generation circuit.
FIG. 18 is a diagram showing an example when an address generation circuit is configured using an address decoder;
FIG. 19 shows an example of a PI interleave circuit.
FIG. 20 is a diagram illustrating an example of a PI deinterleave circuit (a circuit that releases PI interleave).
FIG. 21 is a diagram showing an example of PI interleaving for performing two inner codes with one PI interleave conversion rule.
FIG. 22 is a diagram showing an example of PI interleaving for performing one inner code in units of 2 bytes.
FIG. 23 is a diagram showing an example of an M-sequence generation circuit.
FIG. 24 is a diagram showing an example of an arithmetic sequence generator circuit;
FIG. 25 shows an example of a PI interleave circuit.
FIG. 26 is a diagram showing an example of a PI deinterleave circuit (a circuit for canceling PI interleave).
[Explanation of symbols]
1501 ... DVD, 1502 ... Pickup, 1503 ... Spindle motor, 1504 ... Servo, 1505 ... Read channel, 1506 ... Decoder, 1507 ... ID detection circuit, 1508 ... Decode processing circuit, 1509a ... RAM, 1509b ... RAM, 1511 ... Encoder, 1512: Modulation circuit, 1513: Encoding processing circuit, 1514 ... LD driver, 1515 ... Interface, 1516 ... Microcomputer, 1517 ... PI interleave circuit, 1518 ... PI deinterleave circuit, 1601 ... Register, 1602 ... EXOR, 1701 ... Inverter, 1904 ... OR circuit.

Claims (20)

A data recording method for recording data on a recording medium,
Of the plurality of data strings constituting the error correction code formed in the process of recording data on the recording medium , the first data string has the order of the words forming the first data string according to the first rule. Reordering, reordering the order of the words forming the second data string according to a second rule different from the first rule, and recording the second data string on the recording medium. A characteristic data recording method. The data recording method according to claim 1, wherein
The data recording method, wherein the error correction code is a product code composed of a plurality of error correction codes, and the data string is an error correction code constituting a product code. The data recording method according to claim 1, wherein
The data ordering method is characterized in that the rearrangement of the order of the words is performed by rearranging the order of words other than the identification information among the words constituting the data string according to a rule determined for each data string. The data recording method according to claim 2, wherein
The rearrangement of the order of the words is characterized by rearranging the order of the words constituting the main data string and the parity data string among the words constituting the error correction code according to a rule determined for each error correction code. Data recording method. The data recording method according to claim 1, wherein
The rearrangement of the word order is data in which the order of the words constituting the data string is rearranged according to one rule of the rearrangement order of plural types of words used in the error correction code. Recording method. The data recording method according to claim 1, wherein
6. The data recording method according to claim 1, wherein the rearrangement of the word order is performed with a plurality of words as a set. The data recording method according to claim 1, wherein
The data recording method, wherein the rule determined for each data string is a rule according to an M series. The data recording method according to claim 1, wherein
The data recording method, wherein the rule determined for each data string is a rule according to an arithmetic sequence. A data recording method for recording data on a recording medium,
Adding error correction data to the data to be recorded on the recording medium to generate an error correction code;
Among the plurality of data strings constituting the error correction code , the first data string is rearranged in the order of the words forming the first data string according to the first rule, and the second data string is Rearranging the order of the words forming the second data string according to a second rule different from the first rule;
Modulate the data sequence in which the order of the words is rearranged,
A data recording method comprising: recording the modulated data string on the recording medium. A data reproduction method for reproducing data recorded by modulation on a recording medium,
Demodulate a plurality of data strings recorded on the recording medium,
The plurality of data strings which are the demodulated, the first data sequence rearranges the order of the words forming the first data string by the first rule, the second data string of the first Rearranging the order of the words forming the second data string according to a second rule different from the rule;
Correcting an error contained in the data sequence in which the order of the words is rearranged;
A data reproduction method comprising reproducing data in which the error is corrected. A data recording device for recording data on a recording medium,
Of the plurality of data strings constituting the error correction code for recording data on the recording medium , the first data string is rearranged in the order of the words forming the first data string according to the first rule. And the second data string has a signal processing circuit for rearranging the order of the words forming the second data string according to a second rule different from the first rule. apparatus. The data recording apparatus according to claim 11, wherein
The data processing apparatus, wherein the signal processing circuit rearranges the order of words other than the identification information among the words constituting the data string. The data recording apparatus according to claim 11, wherein
The signal processing circuit rearranges the order of words constituting main data and parity among the words constituting the data string. The data recording apparatus according to claim 11, wherein
The data processing apparatus, wherein the signal processing circuit rearranges the order of words constituting the data string as a set of a plurality of words. A data recording device for recording data on a recording medium,
A circuit for generating an error correction code for recording data on the recording medium;
The plurality of data strings constituting the said error Ri correction code, the first data sequence rearranges the order of the words forming the first data string by the first rule, the second data string is the A signal processing circuit for rearranging the order of the words forming the second data string according to a second rule different from the first rule ;
A modulation circuit that modulates a data sequence in which the order of words is rearranged by the signal processing circuit;
A data recording apparatus for recording the modulated data string on the recording medium. A data reproduction device for reproducing data recorded by modulation on a recording medium,
A demodulation circuit for demodulating a plurality of data strings recorded on the recording medium;
Among the plurality of data strings demodulated by the demodulation circuit , the first data string is rearranged in the order of the words forming the first data string according to the first rule, and the second data string is A signal processing circuit for rearranging the order of the words forming the second data string according to a second rule different from the first rule ;
A circuit for correcting an error included in a data string in which the order of words is rearranged by the signal processing circuit,
A data reproducing apparatus for reproducing data in which the error is corrected. A recording medium having a recording area for recording data,
In the recording area, the first data sequence rearranges the order of the words forming the first data string by the first rule, the second which is different from the second data string is the first rule recording medium in which an error correction code composed of a plurality of data strings subjected to more sort order of words forming the second data string to the rules is characterized in that it is recorded. The recording medium according to claim 17 ,
In the recording area, an error correction code composed of a plurality of data strings in which the order of words other than the identification information is rearranged among the words constituting the data string is recorded according to a rule determined for each data string. A recording medium characterized by the above. The recording medium according to claim 17 ,
In the recording area, an error correction comprising a plurality of data strings in which the order of the words constituting the main data string and the parity data string among the words constituting the data string is rearranged according to the rules determined for each data string. A recording medium on which a code is recorded. The recording medium according to claim 17 ,
In the recording area, an error correction code composed of a plurality of data strings in which the order of words constituting the data string is rearranged as a set according to a rule determined for each data string is recorded. A recording medium characterized by the above.

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