JP3927263B2 - Method for measuring delay characteristics between terminals of integrated circuits - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for measuring delay characteristics between terminals of an integrated circuit, and in particular, the delay time from the transition time of an input-side logic value to the transition time of an output-side logic value of the integrated circuit is based on a change in a predetermined parameter. The present invention relates to a measurement method in which a delay characteristic indicating how to change is obtained for each terminal between a specific input terminal and an output terminal by operation simulation of an integrated circuit.
[0002]
[Prior art]
The integration degree and operation speed of semiconductor integrated circuits have been improved year by year, and it is expected that higher integration and higher speed will be required in the future. In order to achieve such high integration and high speed, it is necessary to operate the individual elements constituting the integrated circuit under extremely severe conditions. In designing the circuit, the signal delay characteristics are analyzed. The work to do becomes indispensable. As a method for analyzing such delay characteristics, a method generally used conventionally is a method of executing a simulation using a circuit simulator. In this method, when various waveform patterns are applied to the input terminal of an integrated circuit, the delay time required for the logic signal to propagate through the circuit and eventually change in the logic value of the output terminal is obtained by simulation. It is done. Normally, parameters such as the load capacity connected to the subsequent stage of the integrated circuit to be measured, the input waveform rounding, and the operating temperature are set, and how the delay time changes depending on the change of each parameter value. The delay characteristics shown are required. In particular, the inter-terminal delay characteristics measured for various parameter values from the transition of the logic value of a specific input terminal to the transition of the logic value of a specific output terminal are important for designing an integrated circuit. In general, the inter-terminal delay characteristic is measured for each terminal.
[0003]
[Problems to be solved by the invention]
In an integrated circuit in desk theory, the delay characteristics between certain terminals are uniquely determined regardless of the logic state of other terminals, but in an actual integrated circuit, the influence of the logic state of other terminals Will change slightly. For example, consider a logic circuit in which the logic value of the output terminal Y transitions from 1 to 0 when the logic value of the input terminal A transitions from 0 to 1. In this case, the delay time d from the time of the 0 → 1 transition of the logic value of the input terminal A to the time of the 1 → 0 transition of the logic value of the output terminal Y depends on the state of the logic value of another input terminal. Change. For example, when the input terminal B is maintained at the logical value 0 and the input terminal C is maintained at the logical value 1, and when both the input terminals B and C are maintained at the logical value 1, the delay time d. There is a difference. Therefore, the delay characteristic between specific terminals A-Y is not uniquely determined, and a plurality of delay characteristics are defined according to the logic states of the other input terminals B and C. Therefore, when a plurality of delay characteristics are obtained in this way by circuit simulation, one of the delay characteristics is selected and used according to a predetermined selection condition. For example, if a selection condition of “selecting a characteristic showing the longest delay time” is determined in advance, the worst characteristic (slowest characteristic) is selected from among a plurality of delay characteristics.
[0004]
As described above, in the conventional method for measuring the delay characteristics between terminals, one characteristic is selected and used based on a predetermined selection condition between terminals for which a plurality of delay characteristics are defined as a result of simulation. Therefore, efficient processing has not necessarily been performed. In other words, useless simulation is performed for the delay characteristics that are not finally selected. In the future, there is a tendency for more accurate delay characteristics to be measured for highly integrated circuits, and it is expected that enormous operations using enormous amounts of data will be required to execute simulations. Is done. Therefore, more efficient processing for reducing the calculation burden is indispensable.
[0005]
Therefore, an object of the present invention is to provide a method for measuring the delay characteristic between terminals, which can reduce the calculation burden by more efficient processing.
[0006]
[Means for Solving the Problems]
  (1) In the first aspect of the present invention, how the delay time from the transition time of the input-side logic value to the transition time of the output-side logic value of the integrated circuit changes based on a change in a predetermined parameter The delay characteristic indicating whether toA device having a circuit simulator unit and a characteristic selection unit was used.In the measurement method for obtaining each of the terminals between the specific input terminal and the output terminal by the operation simulation of the integrated circuit,
  The circuit simulator sectionA circuit information file indicating each component constituting the integrated circuit to be measured and the connection relationship between these components.inputStages,
  The circuit simulator sectionAn input waveform file that collects many combinations of waveform patterns indicating the logical values or transition states of all input terminals of an integrated circuit.inputStages,
  The circuit simulator sectionAnalytical conditions indicating the parameters required for simulation and multiple measurement points for those parametersinputStages,
  The circuit simulator sectionAbout the set parametersSetA specific fixed pointinputStages,
  The circuit simulator sectionCircuit information file and input waveform fileOn the basis of the,In a state where the parameter value is fixed at a fixed point, an operation simulation is performed when each waveform pattern in the input waveform file is given to each input terminal of the integrated circuit, and a delay time is measured for each terminal. ,
  Based on the result of this measurement, the characteristic selectorFor terminals between which a plurality of n delay times are defined based on a plurality of n waveform patterns, a specific waveform pattern satisfying a predetermined selection condition is selected for the delay time, and 1 based on one waveform pattern. Selecting a waveform pattern between terminals for which only a delay time is defined, creating a new input waveform file by excluding unnecessary waveform patterns that were not selected from the input waveform file,
  The circuit simulator unit inputs a new input waveform file;
  The circuit simulator sectionCircuit information file and new input waveform fileOn the basis of the,Performs an operation simulation when each waveform pattern in a new input waveform file is applied to each input terminal of the integrated circuit in multiple states with parameter values set for each measurement point, and delay time between each terminal To measure the delay characteristics between each terminal,
  Is to do.
[0007]
  (2) According to a second aspect of the present invention, in the method for measuring delay characteristics between terminals of the integrated circuit according to the first aspect described above,
  As each waveform pattern in the input waveform file, “maintain logical value 0”, “maintain logical value 1”, “transition from logical value 0 → 1”, “logical value 1 → 0” for each input terminal. Any one of the four statesDefined,
  As the inter-terminal delay characteristics, “logical value 0 → 1 transition based on logical value 0 → 1 transition of input terminal”, “logical value 1 → 0 transition of output terminal based on logical value 0 → 1 transition of input terminal” ”,“ Logical value 0 → 1 transition of output terminal based on logical value 1 → 0 transition of input terminal ”,“ Logical value 1 → 0 transition of output terminal based on logical value 1 → 0 transition of input terminal ”CharacteristicsEach separatelyDefinedIt is what I did.
[0008]
  (3) According to a third aspect of the present invention, there is provided a method for measuring delay characteristics between terminals of an integrated circuit according to the first or second aspect described above.
  Parameters required for simulation include load capacity, input waveform rounding, or operating temperatureIs usedIt is what I did.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described based on the illustrated embodiments.
[0010]
§1. Conventional measurement method for delay characteristics between terminals
First, in order to facilitate the description of the present invention, the procedure of a conventional general method for measuring the delay characteristic between terminals will be described. FIG. 1 is a conceptual diagram showing a general procedure of this conventional measuring method. In this method, first, a circuit information file 1 and an input waveform file 2 are prepared, and a circuit simulation is executed in the circuit simulator unit 10. At this time, the analysis condition 3 is set, and the simulation is executed based on the parameter value indicated by the analysis condition 3. As a result of such circuit simulation, a delay characteristic 4 for each waveform is obtained. This delay characteristic indicates the delay characteristic of the output waveform for all the waveform patterns included in the input waveform file 2, and there can be a plurality of characteristics even if the delay characteristic is between the same terminals. The characteristic selection unit 20 executes a process of selecting any one characteristic according to the predetermined selection condition 5 for the inter-terminal delay characteristic having a plurality of characteristics as described above, and generates the inter-terminal delay characteristic 6. It has a function.
[0011]
Subsequently, the above procedure will be described in more detail based on a specific example. The circuit information file 1 prepared first is a file made up of data indicating each component constituting an integrated circuit to be measured and a connection relationship between these components. A general integrated circuit is composed of an enormous number of logic circuits, but here, for convenience, a very simple circuit composed of two logic circuits of an AND circuit 31 and a NOR circuit 32 as shown in FIG. The following description will be given by taking as an example a case where a simple circuit becomes an integrated circuit to be measured. In this case, the circuit information file 1 includes data indicating that the integrated circuit is configured by the AND circuit 31 and the NOR circuit 32 and these are connected as illustrated.
[0012]
On the other hand, the input waveform file 2 is a file in which the logic values given to all the input terminals A, B, and C of the integrated circuit shown in FIG. Here, the following four types are defined as logical values or transition states to be given to each input terminal.
[0013]
(1) Maintaining logical value 0 (hereinafter indicated by the symbol in FIG. 3 (a))
(2) Maintain logical value 1 (hereinafter indicated by the symbol in FIG. 3 (b))
(3) Transition from logical value 0 to 1 (hereinafter indicated by the symbol in FIG. 3 (c))
(4) Transition from logical value 1 to 0 (hereinafter indicated by the symbol in FIG. 3 (d))
Note that here, since the transition delay time of the logical value of the output terminal Y when any one of the three input terminals changes, the transition delay time of any one of the input terminals is described in (3) above. When the transition of ▼ and (4) occurs, the other two input terminals are prepared only with waveform patterns that are in the maintenance state of the above (1) and (2). Therefore, the input waveform file 2 is constituted by waveform patterns W1, W2, W3... W24 as shown in FIG.
[0014]
For example, in the waveform pattern W1, the input terminal A is in a state of “transition from logical value 0 to 1,” and the input terminals B and C are in a state of “maintaining logical value 0.” In the waveform pattern W2, The input terminal A is in a “transition from logical value 1 to 0” state, and the input terminals B and C are in a “maintain logical value 0” state. Here, a state in which the logical value of an arbitrary terminal X transitions from 0 to 1 is represented as “Xrise”, and a state in which the logical value of the terminal X transitions from 1 to 0 is represented as “Xfall”. The pattern W1 is Arise, and the waveform pattern W2 is a waveform pattern representing Afall. Similarly, the waveform patterns W3 to W8 are waveform patterns representing Arise or Afall, but the logical states of the input terminals B and C are different from each other. Eventually, eight waveform patterns W1 to W8 are prepared as waveform patterns in which the logic state of the input terminal A transitions, and a total of 24 waveform patterns indicating the transition of the logic states of all input terminals are prepared. A pattern will be prepared.
[0015]
The analysis condition 3 indicates parameters necessary for the simulation executed by the circuit simulator unit 10 and a plurality of measurement points for the parameters. As parameters, load capacity, input waveform rounding, temperature conditions, and the like are used. For example, in the case of the circuit shown in FIG. 2, the load capacitance indicates a capacitance value of a subsequent circuit connected to the output terminal Y. For example, in the case of the circuit shown in FIG. 2, the input waveform rounding is a parameter that quantitatively expresses distortion of a signal applied to the input terminals A, B, and C. The temperature condition is a parameter indicating the temperature during operation of this circuit. In addition to the above, various parameters can be used, but here, the following description will be given using an example in which a load capacity is used as a representative parameter. In this case, as analysis condition 3, information indicating a plurality of measurement points such as 10 pF, 15 pF, 20 pF, and 25 pF is prepared for the load capacitance.
[0016]
The circuit simulator unit 10 targets each integrated circuit specified in the circuit information file 1 and each measurement point set in the analysis condition 3 with respect to the operation when the individual waveform patterns included in the input waveform file 2 are given. A delay characteristic 4 for each waveform is obtained by executing a simulation under the above conditions. For example, when the waveform pattern W3 shown in FIG. 4 is given to the circuit shown in FIG. 2, the logic transition as shown in FIG. 5 occurs, and the logic value of the output terminal Y changes from 1 to 0. . That is, a logical change “Arise → Yfall” occurs. In the circuit simulator unit 10, an operation for simulating a physical phenomenon in the circuit at this time is executed, and a delay time d from the transition time corresponding to Arise to the transition time corresponding to Yfall is obtained. There are various methods for defining the delay time d. For example, as shown in FIG. 6, a reference potential level is defined at an intermediate position between a potential level of a logical value 0 and a potential level of a logical value 1. The time from when the logic signal at the input terminal A reaches the reference potential level to the time when the logic signal at the output terminal Y reaches the reference potential level may be defined as the delay time d.
[0017]
In addition, when the 24 waveform patterns included in the input waveform file 2 shown in FIG. 4 are given to the circuit, the logical value of the output terminal Y does not always change. When the logical value of the output terminal Y does not transition, the delay time d cannot be defined. Therefore, the transition to the logical value of the output terminal Y among the 24 waveform patterns included in the input waveform file 2 is made. The delay time d will be defined only for patterns that can be generated. In the case of the example shown here, after all, the logic value transition of the output terminal Y occurs only for the ten waveform patterns S1 to S10 shown in FIG. 7, and the delay times d1 to d10 are defined for each (for example, The waveform pattern S1 shown in FIG. 7 corresponds to the waveform pattern W3 shown in FIG.
[0018]
By the way, the simulation in the circuit simulator unit 10 is executed for a plurality of measurement points related to the parameter (in this example, load capacity) set in the analysis condition 3. For example, when four load capacitance values such as P1, P2, P3, and P4 are set as measurement points, the load capacitances P1, P2, P3, and P4 are connected to the subsequent stage of the circuit shown in FIG. In each case, separate simulations are executed, and four delay times are required. FIG. 8 is a graph in which measured values (calculated values by simulation) of four measurement points are plotted with the parameter value (load capacity value) on the horizontal axis and the delay time on the vertical axis. Here, such a change in the delay time relating to the predetermined parameter is referred to as a delay characteristic. The graph shown in FIG. 8 is, for example, a graph showing the delay characteristics of “Arise → Yfall” when the waveform pattern S1 is given. Similarly, the graphs showing the delay characteristics of the waveform patterns S2 to S10 are also shown. Will be obtained. After all, in FIG. 1, the delay characteristic 4 for each waveform obtained from the circuit simulator unit 10 is a graph as shown in FIG. 8 for each of the waveform patterns S1 to S10.
[0019]
In general, in designing an integrated circuit, the delay characteristic obtained for each terminal is more useful information than the delay characteristic obtained for each waveform pattern. Therefore, the delay characteristics between the terminals are usually subdivided taking into account the rise and fall of the signal waveform (so-called pin-to-pin characteristics) Is required. FIG. 9 is a correspondence table between the terminals finely classified as described above and the waveform patterns corresponding thereto. For example, “inter-terminal A → Y” composed of a combination of the input terminal A and the output terminal Y is further divided into 4 of “Arise → Yrise”, “Arise → Yfall”, “Afall → Yrise”, “Afall → Yfall”. Subdivided into two. Here, the waveform patterns corresponding to “Arise → Yrise” and “Afall → Yfall” do not logically exist in the circuit of FIG. 2 (indicating that “φ” in FIG. 9 does not exist), and “Arise → Yrise” “Yfall” corresponds to the waveform pattern S1 shown in FIG. 7, and “Afall → Yrise” corresponds to the waveform pattern S2 shown in FIG.
[0020]
Similarly, “between terminals B → Y”, which is a combination of the input terminal B and the output terminal Y, is “Brise → Yrise”, “Brise → Yfall”, “Bfall → Yrise”, “Bfall → Yfall”. There are no waveform patterns corresponding to “Brise → Yrise” and “Bfall → Yfall”, “Brise → Yfall” corresponds to the waveform pattern S3, and “Bfall → Yrise” corresponds to the waveform pattern S4. Corresponding to Further, “inter-terminal C → Y”, which is a combination of the input terminal C and the output terminal Y, is further changed to 4 of “Crise → Yrise”, “Crise → Yfall”, “Cfall → Yrise”, “Cfall → Yfall”. There is no waveform pattern corresponding to “Crise → Yrise” and “Cfall → Yfall”, “Crise → Yfall” corresponds to the waveform patterns S5, S7, S9, and “Cfall → Yrise” This corresponds to the waveform patterns S6, S8, and S10.
[0021]
In the case of this example, as shown in FIG. 10, three delay characteristics of waveform patterns S5, S7, and S9 are obtained between the terminals “Crise → Yfall”, and between the terminals “Cfall → Yrise”. As shown in FIG. 11, three delay characteristics of waveform patterns S6, S8, and S10 are obtained. For example, the graphs of the three types of delay characteristics shown in FIG. 10 are all the delays until the logical value of the output terminal Y transitions from 1 to 0 when the logical value of the input terminal C transitions from 0 to 1. It is the graph which plotted time using load capacity as a parameter. However, the logical states of the input terminals A and B are different in each graph. That is, as shown in FIG. 7, the delay characteristic for the waveform pattern S5 is in a state where both the input terminals A and B are maintained at the logical value 0, and the delay characteristic for the waveform pattern S7 is In the state where the input terminal A is maintained at the logical value 1 and the input terminal B is maintained at the logical value 0, the delay characteristic for the waveform pattern S9 is that the input terminal A is at the logical value 0 and the input terminal B is at the logical value 0. This is in a state where the logical value 1 is maintained.
[0022]
When a plurality of delay characteristics are obtained in this way, the characteristic selection unit 20 selects any one delay characteristic as a representative based on a predetermined selection condition 5. For example, when the selection condition “select the one having the longest delay time” is predetermined, the delay characteristic between the terminals “Crise → Yfall” is the characteristic of the waveform pattern S9 shown in FIG. 11 is selected, and the characteristic of the waveform pattern S10 shown in FIG. 11 is selected as the delay characteristic between the terminals “Cfall → Yrise”. Thus, as the terminal-to-terminal delay characteristic 6 finally obtained, the delay characteristic of the waveform pattern S1 is “Arise → Yfall”, the delay characteristic of the waveform pattern S2 is “Afall → Yrise”, and the waveform is “Brise → Yfall”. The delay characteristic of the pattern S3 is “Bfall → Yrise”, the delay characteristic of the waveform pattern S4 is “Crise → Yfall”, the delay characteristic of the waveform pattern S9 is “Cfall → Yrise”, and the delay characteristic of the waveform pattern S10 is “Cfall → Yrise”. Will be obtained.
[0023]
§2. Measuring method of delay characteristic between terminals according to the present invention
In the conventional measurement method described above, the waveform patterns S5, S6, S7, and S8 are selected and excluded by the characteristic selection unit 20, and are not used as the final inter-terminal delay characteristic 6. Therefore, the simulation calculation in the circuit simulator unit 10 includes useless calculations. In the above example, four measurement points P1, P2, P3, and P4 are set for the load capacity parameter, and the simulation is executed for the four measurement points. In practice, a more accurate delay characteristic is obtained. Therefore, a larger number of measurement points are set. If such a simulation for a large number of measurement points is executed for all waveform patterns, the calculation burden becomes very heavy and the efficiency becomes extremely low. The method according to the present invention described below is one method for reducing such a calculation burden.
[0024]
Hereinafter, a method for measuring the delay characteristic between terminals of an integrated circuit according to the present invention will be described with reference to the flowchart of FIG. First, in step 41, a circuit information file is prepared, in the subsequent step 42, an input waveform file is prepared, and in step 43, analysis conditions are set. The process so far is exactly the same as the conventional general method described above. That is, in step 41, a circuit information file 1 for identifying a circuit as shown in FIG. 2 is prepared. In step 42, an input waveform file 2 as shown in FIG. 4 is prepared. As a parameter, four measurement points P1 to P4 are set.
[0025]
Subsequently, in step 44, a fixed point is set. This fixed point indicates a specific parameter value for the parameter set in step 43. Here, a predetermined fixed point Pfix (Pfix = P4 is set in the illustrated example described later) is set. The following description will be given. In the subsequent step 45, simulation in the circuit simulator unit 10 is executed. That is, the circuit information file 1 prepared in step 41 and the input waveform file 2 prepared in step 42 are given to the circuit simulator unit 10 and simulation is executed. However, instead of executing the simulation for all the measurement points as in the conventional method, only the simulation with the parameter values fixed at the fixed point Pfix set in step 44 is executed. That is, although the simulation for all waveform patterns included in the input waveform file 2 shown in FIG. 4 is executed, the load capacitance value as a parameter is fixed to Pfix (= P4), and other measurement points P1 and P2 , P3 is not simulated.
[0026]
Thus, the delay time is obtained for each of the ten waveform patterns S1 to S10 as shown in FIG. 7, but since the load capacitance value is fixed at Pfix, for example, between the terminals “Crise → Yfall” Only three points (S5, S7, S9) as shown in FIG. 13 are obtained, and the delay time between terminals “Cfall → Yrise” is three points (S6, S6) as shown in FIG. Only S8, S10) are obtained. Subsequently, in step 46, only a necessary waveform pattern is selected, and a new input waveform file is created with the selected waveform pattern. That is, as for “Crise → Yfall” or “Cfall → Yrise”, a waveform pattern is selected based on a predetermined selection condition between terminals in which a plurality of delay times are defined. In the example shown here, based on the selection condition “select the one with the longest delay time”, only S9 is selected from the three points shown in FIG. 13, and only S10 is selected from the three points shown in FIG. Is selected. On the other hand, for terminals between which only one delay time is defined, such as “Arise → Yfall”, “Afall → Yrise”, “Brise → Yfall”, “Bfall → Yrise”, one corresponding waveform Select the pattern as it is. Eventually, among the 10 waveform patterns shown in FIG. 7, S1, S2, S3, S4, S9, and S10 are selected, and the remaining S5, S6, S7, and S8 are not selected. Accordingly, the new input waveform file includes only waveform patterns S1, S2, S3, S4, S9, and S10 as shown in FIG.
[0027]
Finally, in step 47, simulation is executed again using this new input waveform file, and a delay time is obtained for each waveform pattern as shown in FIG. At this time, simulation is performed for all the set measurement points P1, P2, P3, and P4, and six waveform patterns S1, S2, S3, S4, S9, and S10 included in the new input waveform file are performed. For each, a delay characteristic consisting of a graph in which the delay time for each measurement point is plotted is obtained. The six waveform patterns S1, S2, S3, S4, S9, and S10 are respectively “Arise → Yfall”, “Afall → Yrise”, “Brise → Yfall”, “Bfall → Yrise”, “Crise → Yfall”, This corresponds to the six terminals “Cfall → Yrise”, and the obtained six graphs show the delay characteristics between these terminals.
[0028]
The inter-terminal delay characteristic finally obtained by the measurement method according to the present invention described above is not different from the inter-terminal delay characteristic finally obtained by the conventional measurement method. However, in the conventional measurement method, a simulation has to be executed for all measurement points set as analysis condition 3 using an input waveform file composed of 24 waveform patterns shown in FIG. On the other hand, in the measurement method of the present invention, it is only necessary to execute simulation for the six waveform patterns shown in FIG. The above example is an example in which four measurement points are set for a very simple logic circuit having three inputs and one output. However, in reality, a larger number is obtained for an integrated circuit having a large number of inputs and outputs. The delay characteristic in which the measurement points are set is required, and the calculation load for the simulation is greatly reduced by applying the present invention.
[0029]
【The invention's effect】
As described above, according to the method for measuring delay characteristics between terminals of an integrated circuit according to the present invention, it is possible to reduce the calculation burden by increasing the efficiency of processing.
[Brief description of the drawings]
FIG. 1 is a conceptual diagram showing a general procedure of a conventional method for measuring delay characteristics between terminals.
FIG. 2 is a circuit diagram showing an example of a circuit for which a delay characteristic between terminals is obtained.
FIG. 3 is a diagram showing a form of a waveform pattern given as an input.
4 is a chart showing waveform patterns constituting an input waveform file 2 used in the procedure shown in FIG.
5 is a circuit diagram showing a logical operation when the waveform pattern W3 shown in FIG. 4 is given to the circuit shown in FIG. 2;
6 is a waveform diagram showing an example of a method for defining a delay time d from a transition of an input waveform A to a transition of an output waveform Y. FIG.
7 is a chart showing a list of delay characteristics obtained when the waveform pattern shown in FIG. 4 is given to the circuit shown in FIG. 2;
8 is a graph showing delay characteristics for the waveform pattern S1 shown in FIG.
FIG. 9 is a chart showing the correspondence between delay characteristics and waveform patterns between individual terminals.
FIG. 10 is a graph showing three types of delay characteristics defined between terminals “Crise → Yfall”;
FIG. 11 is a graph showing three types of delay characteristics defined between terminals “Cfall → Yrise”;
FIG. 12 is a flowchart showing the procedure of the inter-terminal delay characteristic measuring method according to the present invention.
FIG. 13 is a graph showing three types of delay times defined between terminals “Crise → Yfall” in a state where the load capacity is fixed at a fixed point Pfix.
FIG. 14 is a graph showing three types of delay times defined for terminals “Cfall → Yrise” in a state where the load capacity is fixed at a fixed point Pfix.
15 is a chart showing an example of a new input waveform file created by the process of step 46 in the flowchart shown in FIG. 12. FIG.
16 is a graph showing delay characteristics obtained when the waveform pattern shown in FIG. 15 is given to the circuit shown in FIG. 2;
[Explanation of symbols]
1 ... Circuit information file
2 ... Input waveform file
3. Analysis conditions
4 ... Delay characteristics for each waveform
5 ... Selection conditions
6 ... Delay characteristics between terminals
10 ... Circuit simulator
20 ... Characteristic selection section
31 ... AND circuit
32 ... NOR circuit
41-47 ... Flowchart steps
S1 to S10 ... Waveform pattern
W1-W24 ... Waveform pattern

Claims (3)

A delay characteristic indicating how the delay time from the transition point of the input-side logic value of the integrated circuit to the transition point of the output-side logic value changes based on a change in a predetermined parameter is expressed as a circuit simulator unit. A measurement method for obtaining each of the terminals between a specific input terminal and an output terminal by an operation simulation of an integrated circuit using an apparatus having a characteristic selection unit ,
The circuit simulator unit inputs each component constituting the integrated circuit to be measured and a circuit information file indicating a connection relationship between these components;
A step of inputting an input waveform file in which the circuit simulator unit collects a logic pattern to be given to all input terminals of the integrated circuit or a waveform pattern indicating a transition state thereof for a number of combinations;
The circuit simulator unit inputs parameters necessary for simulation and analysis conditions indicating a plurality of measurement points for the parameters;
The circuit simulator unit inputs a specific fixed point set for the parameter;
Based on the circuit information file and the input waveform file , the circuit simulator unit fixes each waveform pattern in the input waveform file to each input terminal of the integrated circuit in a state where the parameter value is fixed at the fixed point. To perform the operation simulation when given to the terminal, measure the delay time between each terminal,
A specific waveform satisfying a predetermined selection condition for a delay time between terminals in which a plurality of n delay times are defined based on a plurality of n waveform patterns based on the measurement result. Select a pattern, select a waveform pattern between terminals for which only one delay time is defined based on one waveform pattern, and exclude unnecessary waveform patterns that were not selected from the input waveform file. To create a new input waveform file,
The circuit simulator unit inputting the new input waveform file;
Said circuit simulator, based on said circuit information file and the new input waveform file, in a plurality of states that set the value of the parameter in each of the measuring points, each waveform patterns in said new input waveform file Performing an operation simulation when applied to each input terminal of the integrated circuit, measuring a delay time for each terminal for each measurement point, and obtaining a delay characteristic for each terminal;
A method of measuring delay characteristics between terminals of an integrated circuit, comprising: The measurement method according to claim 1,
As each waveform pattern in the input waveform file, “maintain logical value 0”, “maintain logical value 1”, “transition from logical value 0 → 1”, “logical value 1 → 0” for each input terminal. One of the four states of “transition of” is defined,
As the inter-terminal delay characteristics, “logical value 0 → 1 transition based on logical value 0 → 1 transition of input terminal”, “logical value 1 → 0 transition of output terminal based on logical value 0 → 1 transition of input terminal” ”,“ Logical value 0 → 1 transition of output terminal based on logical value 1 → 0 transition of input terminal ”,“ Logical value 1 → 0 transition of output terminal based on logical value 1 → 0 transition of input terminal ” A method for measuring delay characteristics between terminals of an integrated circuit, wherein the characteristics are defined separately. The measurement method according to claim 1 or 2,
A method for measuring delay characteristics between terminals of an integrated circuit, wherein load capacitance, input waveform rounding, or operating temperature is used as a parameter required for simulation.

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