JP3925854B2 - Programs in multiprocessor systems - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention, concerning a thread of a plurality of processes (or referred to as a program) to the program for dispatching a multi-processor system.
[0002]
[Prior art]
Conventionally, as an execution environment for a multi-thread program, a multi-processor system has been particularly successful in the application of a WEB server. In this case, the process executed in the system is a server program such as a proxy or a firewall. When performing distributed processing, one server program is often executed in one system.
[0003]
The multi-thread program of the WEB server repeatedly generates and deletes jobs in response to requests from a plurality of asynchronous clients. On the other hand, in a server application called a CPU (central processing unit) server or CPU Farm, a plurality of programs having different properties, for example, calculation and CAD (computer aided design) are executed.
[0004]
When one process including a multi-thread program is executed, assigning all the process threads to an assignable processor increases the execution speed of the process most. However, when there are a plurality of processes, it is necessary to assign threads by a method that optimizes the throughput of the system.
[0005]
For example, in a multi-processor system that can process eight processes simultaneously, when eight independent processes are executed, the throughput is higher than when executed by eight single processors that process one process. May be significantly inferior. This is considered to be the cause of the inefficiency caused by the competition resulting from the sharing of the user space.
[0006]
In a multi-thread program, thread switching is faster than program switching. Furthermore, since the same user space is shared between different threads, data can be passed between threads using pointers. Therefore, data transfer between threads is faster than data transfer between programs that require a copy operation. When executing a multi-thread program on a multi-processor system, the system preferably has a cache coherent shared memory. This is because, when data is transferred between threads running on different processors by pointer passing, no copy operation occurs at the hardware level.
[0007]
Multi-processor systems have been added to support hardware-level cache coherency as a result of being optimized for the execution of multi-threaded programs. Supporting cache coherency with hardware is suitable for data passing between threads that occurs frequently, that is, communication between threads.
[0008]
However, if data access using a cache coherency protocol is always used in preparation for data transfer between independent programs with low frequency of communication between threads, unnecessary processing increases in speed. In an example of a CC-NUMA (cache coherence-non uniform memory access) type multi-processor system, when an L2 (level 2) cache miss occurs, the home memory that manages the memory to which the data belongs without intervention of software The tag memory belonging to the node is accessed and the owner node holding the latest data is automatically queried. In addition, when a snoop cache is used, it is necessary to always broadcast addresses to all caches. Therefore, if there is only one address bus, a plurality of memory accesses requiring snoop cannot be generated simultaneously. The tag memory is a memory that manages a state in which data is cached. The snoop cache is a memory used for automatically managing coherency by hardware. The L2 cache miss means that the cache memory has a two-layer structure, and a cache miss is made in two layers after the first layer.
[0009]
Therefore, the hardware support for cache coherency is suitable for efficiently supporting a multi-thread program, but is an unnecessary support when a plurality of independent programs are executed.
[0010]
[Problems to be solved by the invention]
An object of the present invention, when executing a plurality of programs in a multi-processor system is to provide Hisage a program to control to maximize the throughput of the system.
[0011]
[Means for Solving the Problems]
The gist of the program of the present invention is a program for dispatching a thread of a process executed in a multi-processor system including a plurality of processors, wherein the multi-processor system is sent to each of the plurality of processors as a process thread. Means for comparing the length of processing time in the processor and the time waiting for I / O within the execution time of the process, and processing in the processor A program for causing a process to be executed by one processor or a plurality of processors depending on whether the time or I / O waiting time is long .
[0012]
How to dispatch threads of a process executed by the multi-processor system containing multiple processors, determining the processing efficiency of the process when assigning the threads of the process to the plurality of processors, said process Selecting whether to execute on one processor or a plurality of processors.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
It will be described with reference to the drawings programming implementation in the form of a ram of the present invention. In this specification and FIGS. 1, 2 and 4, reference numeral 38 generally indicates reference numerals 38a, 38b, P1, P2, and P3.
[0014]
The program of the present invention is a program for dispatching threads shown in FIG. In other words, the present invention is an invention of an operating system scheduler in a multi-processor system. First, a method for maximizing system throughput will be described.
[0015]
FIG. 2 represents the operating system 32 and the process 38. T0 to T4 indicate the threads of the process 38, and the positions of these threads T0, T1, T2, T3, and T4 indicate execution points in the multiprocessor system 40. In the example of FIG. 2, the thread T0 is a thread in the user space 36 that can be executed simultaneously with the threads T1, T2, T3, and T4. The thread T1 receives services from the system call to the threads T2 and T3, and then returns to the thread T4.
[0016]
In this specification, for example, if the threads T0, T2, and T3 in FIG. 2 are assigned to different processors, even the process 38 that can obtain a maximum of 3 parallelisms is assigned to one processor (single processor). This is called a single processor execution state.
[0017]
Conventionally, for example, when threads T0, T2, and T3 are executed in parallel by different processors, data is shared, and thus a cache coherency protocol is required. When the threads T0 to T4 are executed by a single processor, no cache coherency protocol is required. Therefore, the data in the user space 36 is marked as not requiring coherency in the corresponding page table. The page table is a table for managing the memory storage area in units of pages, and stores the correspondence between virtual addresses and physical addresses. This table can be used to manage cache control and cache coherency control. A page is each divided part when the program is divided into equal lengths.
[0018]
When marking that cache coherency is unnecessary, for example, in the page table 42 of FIG. 3, it is specified in the WIM bit field. With the function of an MMU (memory management unit) included in the multiprocessor system 40, the hardware 30 does not generate a cache coherency protocol for data access to this user space 36.
[0019]
However, there is a possibility that cache coherency may not be maintained when data is exchanged with a program executed by another processor. For example, when the thread T5 of FIG. 2 is executed by the processor uP2 of FIG. 4, when the user T36 having a process that does not require cache coherency is referred to, the thread coherency cannot be maintained. .
[0020]
In the above case, the dispatch to the processor is changed, and the thread T5 is added to the single processor execution state to maintain cache coherency. Use MMU assistance to generate events that change dispatches. In the page table 42, the user space 36 can be read / written only from the only processor that is executing, and cannot be read / written from other processors. An interrupt occurs before the thread T5 is referred to data that breaks cache coherency, and is dispatched to the same processor as the threads T0, T1, T2, T3, and T4.
[0021]
In the example of the page table 42 of FIG. 3, the read / write attribute for the page can be omitted by specifying the PP bit field in the cache coherency protocol.
[0022]
The contents of the read / write attribute recorded in the page table 42 look different depending on the processor. This is a technique that is also used when a software cache is implemented by DSM (distributed shared memory). In the DSM software cache, the page faulted page is moved between the nodes to obtain the cache effect, whereas in the present invention, the page faulted thread is moved between the nodes. Different. A page fault is an interrupt that occurs when a page that does not exist in memory is accessed.
[0023]
If all processes 38 are in a single processor execution state, the meaning of the multi-processor system 40 is lost. Therefore, the program of the present invention has the following configuration, and selects a process 38 to be in a single processor execution state.
[0024]
The program 10 of the present invention shown in FIG. 1 determines the processing efficiency of the processes 38a and 38b when the multiprocessor system 40 assigns threads of the processes 38a and 38b to a plurality of processors (multiprocessors) 28, respectively. This is a program for causing the determination means 12 and the selection means 14 to select whether the processes 38a and 38b are executed by the single processor 26 or the multi processor 28 based on the result of the determination means 12.
[0025]
The determination unit 12 includes an observation unit 16 that observes the execution states of the processes 38a and 38b, and a determination unit 18 that determines the processing efficiency of the processes 38a and 38b. The observation unit 16 includes a dividing unit (not shown) that divides the execution time of the processes 38a and 38b into processing time in the processors 26 and 28 and waiting time for I / O (input / output), and processing time. And a comparison means (not shown) for comparing the I / O waiting time. The determination unit 18 determines the processing efficiency of the processes 38a and 38b using the comparison result of the comparison unit.
[0026]
The selection unit 14 includes a memory management unit 20 and a task dispatcher 22. The memory management unit 20 turns on or off cache coherency for the processes 38 a and 38 b in the memory 24. The task dispatcher 22 selects multiprocessor execution or single processor execution.
[0027]
In the present invention, when the data processed by the process 38a executed by the single processor 26 is accessed from another processor by the determination unit 12 and the selection unit 14, the access is stopped and the access is stopped. Change to processor 26. That is, an interrupt is generated for an access from another processor, and the access is changed to the single processor 26.
[0028]
In the present invention, the single processor 26 reads / writes data for the data processed by the process 38a executed by the single processor 26 by the determination means 12 and the selection means 14, and the data is sent to other processors. Prohibits reading and writing.
[0029]
Next, a dispatch method by the program 10 will be described. The program 10 determines the processing efficiency when the threads of the processes 38a and 38b are assigned to the multiprocessor 28, respectively, and selects single processor execution or multiprocessor execution.
[0030]
When making a determination, (1) in the case of processing in which I / O bound occurs, even if the processes are processed in parallel in a short time consumed by the CPU, the effect is limited. Therefore, the execution time of the processes 38a and 38b is divided into the processing time in the processor 28 and the I / O waiting time, and the processing time and the I / O waiting time are compared. As a result of the comparison, if the I / O wait time is longer, a single processor is executed. In FIG. 1, the process 38a is executed by a single processor. I / O bound refers to using a virtual storage area on a hard disk in processing data, that is, generating a swap file.
[0031]
(2) A single processor execution candidate is also a case where an application program that runs on the operating system 42 including the program 10 is a single thread program. In this case, if the operating system 32 is a multi-thread program, the application program behaves like a multi-thread program. However, since an I / O bound is expected to occur, the operating system 32 is a candidate for single processor execution if the application program does not have concurrency of process processing. That is, in the program of the present invention, the selection means 14 selects the single processor execution in the above case.
[0032]
(3) Even if the process 38 is suitable for multiprocessor execution when executed alone, the processing efficiency may be poor when a plurality of processes 38 are executed. Such processing is also a candidate for single processor execution. That is, in the program 10 of the present invention, the determination unit 12 determines the processing efficiency of multiprocessor execution in the individual processes 38a and 38b, and when the determination result is as described above, the selection unit 14 executes the single processor execution. Select. For example, even if the process 38a in FIG. 1 is suitable for multiprocessor execution, the selection means 14 performs single processor execution.
[0033]
In a multi-processor system 40 having the program 10 of the present invention, a process 38 having a multi-thread program suitable for multi-processor execution is a multi-processor provided with hardware level cache coherency support. The processor 28 performs parallel processing.
[0034]
In FIG. 4, the process P3 is processed by two processors uP3 and uP4. Data accesses occurring in the processors uP3 and uP4 generate a cache coherency protocol.
[0035]
The process 38 that is not suitable for multiprocessor execution is executed by a single processor, and cache coherency with other processors is maintained only by a software control method using the assistance of the MMU. Data access to the user spaces 36a and 36b generated by the processors uP1 and uP2 respectively executing the processes P1 and P2 in FIG. 4 does not generate a cache coherency protocol. As a result, the bandwidth of the cache coherency protocol is relaxed and the throughput of the system 40 is improved.
[0036]
Since no cache coherency protocol is generated, when the process P1 is accessed from the processor uP2, the interrupt means generates an interrupt for the access. Then, after the occurrence of the interrupt, a thread is assigned from the processor uP2 to the processor uP1 to perform access.
[0037]
Further, the MMU controls the system 40 so that the processor reads / writes data processed by a process 38 executed by a processor and prohibits other processors from reading / writing data. .
[0038]
As mentioned above, although embodiment of this invention was described, this invention is not limited to said form. The above description is based on the assumption that the cache is an L1 (level 1) cache, and the single processor execution state is that a thread is executed by a single processor. The same idea can be applied to L2 cache. In this case, a single processor node execution state is set. The single processor node execution state refers to a state in which a plurality of processors belonging to the same node process a plurality of tasks belonging to one process.
[0039]
The space that omits the cache coherency protocol is a user space that is easy to implement and highly effective, but can be applied to a part of the system space. That is, the usage of the system space is classified and applied to a portion in which the cache coherency protocol can be omitted.
[0040]
In addition, the present invention can be implemented in a mode in which various improvements, modifications, and changes are made based on the knowledge of those skilled in the art without departing from the spirit of the present invention.
[0041]
【The invention's effect】
According to the present invention, in a multiprocessor system, process dispatching is optimally performed, so that all processes can be processed without reducing the system throughput.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a program according to the present invention and a state of dispatch.
FIG. 2 is a diagram showing an execution state of a thread of a process.
FIG. 3 is a diagram illustrating an example of a page table for maintaining cache coherency.
FIG. 4 illustrates an example of a multi-processor system.
[Explanation of symbols]
10: Program 12: Determination unit 14: Selection unit 16: Observation unit 18: Determination unit 20: Memory management unit 22: Task dispatcher 24: Memory 26: Single processor 28: Multiprocessor 30: Hardware 32: Operating System 34, 34a, 34b, 34c: System space 36, 36a, 36b, 36c: User space 38: Process 40: Multiprocessor system 42: Page table

Claims (3)

A program for dispatching threads of a process executing on a multi-processor system including a plurality of processors,
Said multi-processor system,
In order to determine the processing efficiency of each process when assigning process threads to each of the plurality of processors, the length of the processing time in the processor and the time waiting for I / O within the execution time of the process are compared. Means to
Means for selecting the process to be executed by one processor or a plurality of processors depending on whether processing time in the processor or I / O waiting time is long;
A page table for marking cache coherency unnecessary for data processed by a process executed by the one processor;
Data that is marked as not requiring cache coherency in the page table is being processed by a process running on the one processor, and the access is interrupted when the data is accessed from another processor Means for generating,
Means for assigning a process thread to the one processor executing the process from the other processor after the interrupt;
The one processor reads / writes the data to / from data processed by a process executed by the one processor, prohibits the other processor from reading / writing the data, and the cache coherency. MMU ( memory management unit ) to prevent cache coherency protocol from being generated due to unnecessary marks
Program to function as.   The program according to claim 1, wherein the selecting unit selects execution of a process in one processor when the I / O waiting time is long.   The program according to claim 1 or 2, wherein, when the process is a single thread process, the means for selecting selects execution of the process on one processor.

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