JP3922381B2 - LCD television receiver - Google Patents

Description

The present invention relates to a liquid crystal television receiver, and more particularly to a liquid crystal television receiver including a digital board connected to a gate driver and a source driver and including a timing controller, and an analog board connected to the digital circuit board.

Patent Document 1 discloses a timing generator that supplies a horizontal synchronization signal and a vertical synchronization signal to an LCD panel, and a signal that supplies an image signal to a data line made of transparent electrodes and a common voltage to a common voltage line made of transparent electrodes. A liquid crystal display device including a generator and an MPU that supplies a control signal to the timing generator and the signal generator for controlling the image signal to be supplied later than the common voltage is described. In this liquid crystal display device, an image signal that rises to a voltage greater than the common voltage is raised later than the rise of the common voltage, thereby suppressing a potential difference that occurs between the scanning line and the common voltage line when the power is turned on. It avoids stripe domains that are abnormal alignment of liquid crystals.

Patent Document 2 discloses a data / driver that supplies RGB signal voltages to an LCD panel, two low-voltage circuits that supply a common voltage to the LCD panel and the detector controller when the power is turned on, and common voltages from two constant-voltage circuits. A liquid crystal display device including a detector / controller that detects and supplies a power supply voltage to a data / driver and outputs RGB signal voltages is described. Even in this liquid crystal display device, the potential difference between the data line and the common voltage line is suppressed by controlling the RGB signal voltage to rise to a voltage higher than the common voltage after the common voltage is applied to the LCD panel. In addition, liquid crystal alignment anomalies that may occur when the power is turned on are suppressed.

  FIG. 1 is a general schematic diagram of a conventional liquid crystal television receiver.

As shown in the figure, the liquid crystal television receiver 1 includes an LCD panel 2 and an LCD panel 2.
Source driver 3 for supplying an image signal to the data line, a gate driver 4 for supplying a scanning voltage to the scanning line of the LCD panel 2 and a common voltage for the common line, and a synchronization signal for the source driver 3 and the gate driver 4 A digital circuit board 5 including a timing controller 6 that supplies a common voltage, a plurality of DC voltages for generating a scanning signal and an image signal to a source driver 3 and a gate driver 4; And an analog board 8 that is connected to the digital board 5 and processes a television signal received by the tuner circuit and outputs the processed television signal to the digital board 5. In such a general liquid crystal television receiver 1, a plurality of DC voltages for generating a common voltage, a scanning signal, and an image signal are connected to the output side of the DC-DC converter IC7 or the DC-DC converter IC7. The power-up sequence is executed so that a plurality of DC voltages rise in a predetermined order using a booster circuit, a polarity inversion circuit, and the like.
JP 2003-280612 A (page 3-4, FIG. 1-2) Japanese Patent Laid-Open No. 7-261716 (page 3-4, FIG. 1)

However, when the rising power sequence circuit is configured using the DC-DC converter IC7, the configuration of peripheral circuits such as the DC-DC converter IC, the booster circuit, and the polarity inversion circuit is complicated, and the sequence control is difficult. . In general, the DC-DC converter IC 7 is expensive, and the digital substrate 5 to be mounted is an expensive multi-layer substrate such as a four-layer substrate, so that cost reduction is necessary. Patent Documents 1 and 2 do not describe a means for supplying a common voltage, a scanning signal, and a DC voltage for generating an image signal, that is, a power supply sequence circuit.

An object of the present invention is to enable a liquid crystal television receiver to perform a rising sequence of a plurality of DC voltages supplied to a source driver and a gate driver with simple control.

Another object of the present invention is to reduce the cost of a circuit that executes a sequence and to reduce the cost of a liquid crystal television receiver.

A liquid crystal television receiver according to a first aspect of the present invention includes a liquid crystal display panel, a source driver connected to a data line of the liquid crystal display panel, a gate driver connected to a scanning line of the liquid crystal display panel, and the source driver And a digital substrate which is a multilayer substrate connected to the gate driver and including a timing controller, and an analog substrate which is connected to the digital circuit substrate and is a single layer substrate.

The analog board is provided with a power supply sequence circuit that outputs a plurality of DC voltages to the gate driver and the source driver in a preset order, and the digital board and the power supply sequence circuit are provided with the plurality of DC voltages. The DC-DC converter for generating is not included.

The power supply sequence circuit receives fifth to eighth voltages and outputs first to fourth voltages, the first voltage is commonly supplied to the gate driver as a common voltage, and the second voltage is is supplied to the gate driver, the third voltage is supplied to the source driver, wherein the fourth voltage is supplied to the gate driver.

The power supply sequence circuit includes a first circuit that outputs the input of the fifth voltage as the first voltage, and a circuit that generates and outputs the second voltage from the sixth voltage. A second circuit for receiving the input and outputting the second voltage with a first predetermined time delay from the output of the first voltage; and a circuit for generating and outputting the third voltage from the seventh voltage, A third circuit that receives the input of the second voltage and outputs the third voltage with a second predetermined time delay from the output of the second voltage; and a circuit that generates and outputs the fourth voltage from the eighth voltage. And a fourth circuit that receives the input of the third voltage and outputs the fourth voltage with a delay of a third predetermined time from the output of the third voltage.

The second circuit receives the input of the first voltage and conducts the sixth voltage to the output side, and adjusts the sixth voltage from the first transistor to the second voltage. Including a Zener diode. The third circuit includes a second transistor that conducts the seventh voltage to the output side by the input of the second voltage, and a voltage obtained by stepping down the seventh voltage that is conducted by the second transistor. A first shunt regulator for outputting, and first and second resistors for generating the third voltage from the constant voltage. The fourth circuit includes a third transistor that conducts the eighth voltage to an output side by the input of the third voltage, and a second Zener that steps down the eighth voltage conducted by the third transistor to a predetermined voltage. A diode, and a fourth transistor driven by a predetermined voltage by the second Zener diode and stepping down the eighth voltage to the fourth voltage.

In this liquid crystal television receiver, a power supply sequence circuit that outputs a plurality of DC voltages supplied to a gate driver and a source driver in a predetermined order is provided by configuring the analog circuit with discrete components, so that a simple circuit configuration is provided. Thus, a power supply sequence circuit can be configured, and sequence control becomes easy.

Further, since it is configured with discrete components, the DC-DC converter can be omitted, and the cost can be reduced. Also, a plurality of DC voltages (first voltage to fourth voltage)
Is provided in an analog circuit generally formed of a single-layer substrate, the mounting area of a digital circuit formed of an expensive multilayer substrate can be reduced, and the cost can be reduced. As a result, the cost of the liquid crystal television receiver can be reduced.

The first to fourth circuits output a plurality of voltages and the first to fourth voltages in a predetermined order to the source driver and the gate driver, for example, liquid crystal due to a potential difference between the common voltage and the image signal. It is possible to appropriately control the liquid crystal display panel by preventing alignment abnormality and the like.

In addition, the first circuit to the fourth circuit can be configured simply and inexpensively using discrete components such as transistors, capacitors, Zener diodes, shunt regulators, and the like. Further, it is easy to mount these circuits on an analog substrate having a relatively large area.

A liquid crystal television receiver according to a second invention includes a liquid crystal display panel, a source driver connected to a data line of the liquid crystal display panel, a gate driver connected to a scanning line of the liquid crystal display panel, and the gate driver. And a digital board connected to the source driver and including a timing controller, and an analog board connected to the digital circuit board, wherein the analog board is preliminarily supplied with a plurality of DC voltages to the gate driver and the source driver. A power supply sequence circuit for outputting in a set order is provided.

In this liquid crystal television receiver, a power supply sequence circuit that outputs a plurality of DC voltages supplied to a gate driver and a source driver in a predetermined order is provided by configuring the analog circuit with discrete components, so that a simple circuit configuration is provided. Thus, a power supply sequence circuit can be configured, and sequence control becomes easy.

Further, since it is configured with discrete components, the DC-DC converter can be omitted, and the cost can be reduced. Further, by providing a power supply sequence circuit in an analog circuit generally formed of a single layer substrate, the mounting area of a digital circuit formed of an expensive multilayer substrate can be reduced, and the cost can be reduced. As a result, the cost of the liquid crystal television receiver can be reduced.

Further , in the liquid crystal television receiver according to the second invention, the digital board and the power supply sequence circuit do not include a DC-DC converter.

Further , in the liquid crystal television receiver according to the second invention , the digital board is a multilayer board, and the analog board is a single-layer board.

Instead of mounting multiple DC voltage start-up power supply sequence circuits on a digital board consisting of a multilayer board, mounting on an analog board can reduce the area of an expensive multilayer board,
Cost can be reduced.

Furthermore , in the liquid crystal television receiver according to a second aspect of the invention , the power supply sequence circuit outputs first to fourth voltages, and the first voltage is commonly supplied to the gate drivers as a common voltage, and the second The voltage is supplied to the source driver, and the third voltage and the fourth voltage are supplied to the gate driver.

Thus, by outputting a plurality of voltages, the first to fourth voltages to the source driver and the gate driver in a predetermined order, for example, liquid crystal alignment abnormality due to a potential difference between the common voltage and the image signal can be prevented. The liquid crystal display panel can be appropriately controlled.

Further , in the liquid crystal television receiver according to a second aspect of the invention , the power supply sequence circuit receives a fifth to eighth voltage input, and outputs the fifth voltage input as the first voltage; A circuit that generates and outputs the second voltage from the sixth voltage, and that receives the input of the first voltage and outputs the second voltage with a delay of a first predetermined time from the output of the first voltage. Two circuits, and a circuit that generates and outputs the third voltage from the seventh voltage, and receives the input of the second voltage and delays the third voltage after a second predetermined time from the output of the second voltage. And a circuit that generates and outputs the fourth voltage from the eighth voltage, and receives the input of the third voltage and is delayed by a third predetermined time from the output of the third voltage. And a fourth circuit for outputting the fourth voltage. To.

In this case, the first to fourth circuits can be configured simply and inexpensively using discrete components such as transistors, capacitors, Zener diodes, shunt regulators, and the like. Further, it is easy to mount these circuits on an analog substrate having a relatively large area.

A liquid crystal television receiver according to a third aspect of the invention is the liquid crystal television receiver according to the second aspect of the invention , wherein the second circuit receives the input of the first voltage and conducts the sixth voltage to the output side. One transistor and a first Zener diode for adjusting the sixth voltage from the first transistor to the second voltage, and the third circuit outputs the seventh voltage according to the input of the second voltage. A second transistor that conducts to the first transistor, a first shunt regulator that receives a voltage obtained by stepping down the seventh voltage conducted by the second transistor and outputs a constant voltage, and a second transistor that generates the third voltage from the constant voltage. The fourth circuit includes a third transistor that conducts the eighth voltage to an output side by the input of the third voltage, and a third transistor. A second Zener diode that steps down the conducted eighth voltage to a predetermined voltage, and a third resistor and a fourth transistor that are driven by the predetermined voltage by the second Zener diode and step down the eighth voltage to the fourth voltage. It is characterized by including.

If the first circuit to the fourth circuit are configured as described above, the power supply sequence circuit can be configured easily and inexpensively. Further, it is easy to mount these circuits on an analog substrate having a relatively large area.

(1) Overall Configuration FIG. 2 is a schematic configuration diagram of a liquid crystal television receiver according to an embodiment of the present invention.

The liquid crystal television receiver 1 supplies an LCD panel 2, a source driver 3 that supplies an image signal to the data line of the LCD panel 2, a scanning signal to the scanning line of the LCD panel 2, and a common voltage to the common line. Gate driver 4 and source driver 3
And a digital board 5 having a timing controller 6 for supplying a synchronization signal to the gate driver 4, a tuner circuit for receiving a television broadcast signal, and an analog board 8 including a power supply sequence circuit 9.

The analog board 8 processes the television broadcast signal received by the tuner circuit and outputs it to the timing controller 6 as an image signal. The power supply sequence circuit 9 has a common voltage,
A plurality of DC voltages for generating scanning signals and image signals are supplied to the source driver 3 and the gate driver 4 through the digital board 5.

Here, the plurality of DC voltages include a common voltage VDDD, a gate voltage VEEG applied to the gate of the TFT via a gate line to turn off the TFT (Thin Film Transistor) of the LCD panel 2, and VDDG for gate voltage applied to the gate of the TFT via the gate line to turn on the TFT of the LCD panel 2, and VDDA for data signal applied to the source of the TFT of the LCD panel 2 via the data line including. As shown in FIG. 4, these VDDD, VEEG, VDDG, and VDDA are started up in the order of VDDD, VEEG, VDDA, and VDDG , and are output to the source driver 3 and the gate driver 4 through the data substrate 5. The

Note that the order of VEEG and VDDG may be switched. That is, the order in which a plurality of voltage rise is VDDD, VEEG, VDDA, VDDG forward or VDDD, VDDG, VDDA, must meet one of the order of VEEG.

In the following description, it is assumed that the order in which the plurality of voltages rise is the order of VDDD, VEEG, VDDA, and VDDG .

(2) Power Sequence Circuit Configuration FIG. 3 is an electric circuit diagram of the power sequence circuit 9.

The power supply sequence circuit 9 includes a first circuit 11, a second circuit 12, a third circuit 13, and a fourth circuit 14. In the following description, both the input terminal and the input voltage are Vin1 to Vin.
The output terminal and the output voltage are all referred to as VDDD, VEEG, VDDA, and VDDG.

The first circuit 11 includes an input terminal Vin1, an output terminal VDDD, and a capacitor C1 connected between a line connecting the input terminal Vin1 and the output terminal VDDD and the ground GND. When a DC voltage of 3.3 V is input to the input terminal Vin, the first circuit 11 outputs VDDD = 3.3 V as it is to the output terminal VDDD.

The second circuit 12 includes an input terminal Vin2, an output terminal VEEG, capacitors C2 to C5, resistors R1 to R5, and a Zener diode D1. In the second circuit 12, VD
When DD = 3.3V is output, the transistor Q1 is turned on, and the base current of the transistor Q2 flows due to the conduction of the transistor Q1, so that the transistor Q2 is turned on, and the input voltage Vin
2 = -8V is transmitted to the output side. Input voltage Vin2 = -8V is Zener diode D1
Thus, the voltage is stepped down to -6V and output to the output terminal VEEG as VEEG = -6V. VEEG
= −6V is the resistance R1, R2 and the capacitor C2, and the resistance R3, R4 and the capacitor C3
Starts rising after VDDD = 3.3V by a time constant determined by the following (first predetermined time).

The third circuit 13 includes an input terminal Vin3, an output terminal VDDA, capacitors C6 to C9, resistors R6 to R12, transistors Q3 and Q4, and a shunt regulator U1. In the third circuit 13, when VEEG = −6.0V is output, the transistor Q3 becomes conductive, and Vin3 = 12V is input to the base of the transistor Q4 and the terminal 3 of the shunt regulator U1 through the resistor R8, and the shunt regulator A constant voltage is output from the terminal 4. Further, the transistor Q4 becomes conductive, and the resistor R10 and the transistor Q4 are connected to Vin3.
= 12V is transmitted, but the constant voltage output from the terminal 4 of the shunt regulator U1 is fixed at a potential of 10.8V determined by the ratio of the resistor R11 and the resistor R12. The voltage is output to the terminal VDDA as VDDA = 10.8V. VDDA = 10
. 8V starts rising after VEEG = −6.0V by a time constant (second predetermined time) determined by the resistors R6, R7 and the capacitor C6, and the resistors R8, R9 and the capacitor C8.

The fourth circuit 14 includes an input terminal Vin4, an output terminal VDDG, and capacitors C10 to C1.
3, resistors R14 to R17, transistors Q5 to Q7, and a Zener diode D2. In the fourth circuit 14, when VDDA = 10.8V is output, the transistor Q
5 becomes conductive, the base current flows through the transistor Q6, and becomes conductive. Vin4 = 40 V is stepped down by the transistor Q6 and the resistor R16 and applied to the Zener diode D2. The cathode voltage of the Zener diode D2 is fixed to a predetermined value, a predetermined current flows through the base of the transistor Q7, Vin4 = 40V is stepped down by the resistor R17 and the transistor Q7, and output to the output terminal VDDG as VDDG = 25.0V Is done. VDDG = 25.0V is the resistance R
13, R14 and the capacitor C10, and start rising after VDDA = 10.8V by a time constant (third predetermined time) determined by the resistor R15 and the capacitor C11.

(3) Operational Effect According to the power supply sequence circuit 9, VDDD = 3.3V is output from the first circuit 11 using Vin1 to Vin4 input in random order from a power supply unit (not shown) of the analog substrate 8. After that, VEEG = −6.0V starts to be output from the second circuit 12 with a delay of the first predetermined time,
Since VDDA = 10.8V starts to be output from the third circuit 13 after a delay of the second predetermined time, and VDDG = 25.0V starts to be output from the fourth circuit 14 after a delay of the third predetermined time, a plurality of signals are output in a predetermined order. DC voltage (VDDD, VEEG, VDDA, VDDG) can be output to the source driver 3 and the gate driver 4 via the digital substrate 5.

In addition, when the DC-DC converter IC is used, the configuration of the DC-DC converter IC itself and peripheral circuits such as the booster circuit and the polarity inversion circuit are complicated, and the sequence control is difficult. In the power supply sequence circuit using discrete components such as the circuit 9, even if the input order of the input voltages Vin1 to Vin4 is out of order, the VDDD is surely VDDD.
, VEEG, VDDA, VDDG can be output in a predetermined order. In addition, it is possible to prevent the image quality from being deteriorated due to the influence of noise generated by the booster circuit and the polarity inversion circuit that are required when the DC-DC converter IC is used.

Further, since no DC-DC converter IC is used, the cost can be significantly reduced. Furthermore, in the conventional configuration in which the DC-DC converter IC is mounted on the digital board 5, the mounting area of the digital board 5 of an expensive multilayer board such as a four-layer board cannot be reduced by the mounting area of the DC-DC converter IC and peripheral circuits. However, if the simple power supply sequence circuit 9 is mounted on the analog substrate 8 which is an inexpensive single-layer substrate using discrete components as in the present embodiment, the area of the expensive multilayer substrate can be reduced, and the cost of the substrate can be reduced. Can be reduced. As a result, the cost of the liquid crystal television receiver 1 can be reduced.

It is a general schematic block diagram of the conventional liquid crystal television receiver. It is a schematic block diagram of the liquid crystal television receiver which concerns on one Embodiment of this invention. It is an electric circuit diagram of a power supply sequence circuit. Output sequence of power supply.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Gate driver 2 LCD panel 3 Source driver 4 Gate driver 5 Analog board 6 Timing controller 7 DC-DC converter 8 Analog board 9 Power supply sequence circuit

Claims (3)

A liquid crystal display panel; a source driver connected to a data line of the liquid crystal display panel; a gate driver connected to a scanning line of the liquid crystal display panel; and a timing controller connected to the source driver and the gate driver. A digital board that is a multilayer board, and an analog board that is connected to the digital circuit board and is a single-layer board,
The analog board is provided with a power supply sequence circuit that outputs a plurality of DC voltages to the gate driver and the source driver in a preset order, and the digital board and the power supply sequence circuit are provided with the plurality of DC voltages. Does not include a DC-DC converter for generating
The power supply sequence circuit receives fifth to eighth voltages and outputs first to fourth voltages, the first voltage is commonly supplied to the gate driver as a common voltage, and the second voltage is Supplied to the gate driver , the third voltage is supplied to the source driver, the fourth voltage is supplied to the gate driver,
A first circuit that outputs the input of the fifth voltage as the first voltage;
A circuit that generates and outputs the second voltage from the sixth voltage, and that receives the input of the first voltage and outputs the second voltage with a delay of a first predetermined time from the output of the first voltage. Two circuits,
A circuit that generates and outputs the third voltage from the seventh voltage, and that receives the input of the second voltage and outputs the third voltage with a second predetermined time delay from the output of the second voltage; 3 circuits,
A circuit that generates and outputs the fourth voltage from the eighth voltage, and that receives the input of the third voltage and outputs the fourth voltage with a delay of a third predetermined time from the output of the third voltage; 4 circuits,
Including
The second circuit receives the input of the first voltage and conducts the sixth voltage to the output side, and adjusts the sixth voltage from the first transistor to the second voltage. Including a Zener diode,
The third circuit includes a second transistor that conducts the seventh voltage to the output side by the input of the second voltage, and a voltage obtained by stepping down the seventh voltage that is conducted by the second transistor. A first shunt regulator for outputting, and first and second resistors for generating the third voltage from the constant voltage,
The fourth circuit includes a third transistor that conducts the eighth voltage to an output side by the input of the third voltage, and a second Zener that steps down the eighth voltage conducted by the third transistor to a predetermined voltage. A diode and a fourth transistor driven by a predetermined voltage by the second Zener diode and stepping down the eighth voltage to the fourth voltage;
A liquid crystal television receiver characterized by that. A liquid crystal display panel; a source driver connected to a data line of the liquid crystal display panel; a gate driver connected to a scanning line of the liquid crystal display panel; and a timing controller connected to the gate driver and the source driver. A digital board and an analog board connected to the digital circuit board;
The analog substrate is provided with a power supply sequence circuit that outputs a plurality of DC voltages to the gate driver and the source driver in a preset order ,
The digital board is a multilayer board, the analog board is a single-layer board, and the digital board and the power supply sequence circuit do not include a DC-DC converter,
The power supply sequence circuit outputs first to fourth voltages, the first voltage is commonly supplied to the gate driver as a common voltage, the second voltage is supplied to the gate driver, and the third voltage is Supplied to the source driver, and the fourth voltage is supplied to the gate driver;
The power supply sequence circuit receives a fifth to eighth voltage input, and outputs the fifth voltage input as the first voltage;
A circuit that generates and outputs the second voltage from the sixth voltage, and that receives the input of the first voltage and outputs the second voltage with a delay of a first predetermined time from the output of the first voltage. Two circuits,
A circuit that generates and outputs the third voltage from the seventh voltage, and that receives the input of the second voltage and outputs the third voltage with a second predetermined time delay from the output of the second voltage; 3 circuits,
A circuit that generates and outputs the fourth voltage from the eighth voltage, and that receives the input of the third voltage and outputs the fourth voltage with a delay of a third predetermined time from the output of the third voltage; A liquid crystal television receiver, comprising four circuits . The second circuit receives the input of the first voltage and conducts the sixth voltage to the output side, and adjusts the sixth voltage from the first transistor to the second voltage. Including a Zener diode,
The third circuit includes a second transistor that conducts the seventh voltage to the output side by the input of the second voltage, and a voltage obtained by stepping down the seventh voltage that is conducted by the second transistor. A first shunt regulator for outputting, and first and second resistors for generating the third voltage from the constant voltage,
The fourth circuit includes a third transistor that conducts the eighth voltage to an output side by the input of the third voltage, and a second Zener that steps down the eighth voltage conducted by the third transistor to a predetermined voltage. 3. The liquid crystal television according to claim 2 , further comprising: a diode; and a third resistor and a fourth transistor that are driven by a predetermined voltage by the second Zener diode and step down the eighth voltage to the fourth voltage. Receiver.

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