JP3920445B2 - Data line drive circuit for matrix display - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention drives a data line of a matrix type display device having a plurality of electrodes such as a liquid crystal display.circuitIt is about.
[0002]
[Prior art]
  FIG. 24 shows a data line driving circuit of a conventional TFT liquid crystal display disclosed in Japanese Patent Laid-Open No. 7-327185. As shown in the figure, the data line driving circuit 1 using the line sequential driving system includes a shift register 11, a plurality of buffer circuits (AMP in the figure) 12, a plurality of sample and hold switches (SS1 in the figure) 14, An R / W switch (SS2 in the figure) 15, a sampling capacitor 16, a hold capacitor 17, and an OP amplifier 18 are provided.
[0003]
  The sample hold switch 14 and the R / W switch 15 are configured in the same circuit and connected in series, and the sample switch 14 is configured by a p-channel MOS transistor 14b and an n-channel MOS transistor 14a as shown in FIG. This is a transfer gate switch. The sample hold switch 14 opens and closes in synchronization with the shift pulses N1 to Nm that have passed through the buffer circuit 12, and the R / W switch 15 opens and closes in synchronization with the control signal sent through the data transfer signal line TRF. It has become.
[0004]
  The sampling capacitor 16 is provided at the output stage of the sample and hold switch 14 and stores data (analog video signal) sampled by the sample and hold switch 14. The hold capacitor 17 is provided at the output stage of the R / W switch 15 and stores data (analog video signal) transferred from the sampling capacitor 16 by the R / W switch 15.
[0005]
  At this time, the capacitance value of the sampling capacitor 16 is Cs, the capacitance value of the hold capacitor 17 is Ch, and the sample hold switch 14 is set.ThereforeWhen the voltage value of the held data is V0, the voltage value of the data generated in the hold capacitor 17 is smaller than the input V0 and is reduced to V0Cs / (Cs + Ch). If Cs and Ch are approximately the same, it is necessary to input data twice as large as the desired value as can be seen from the above equation, and the power consumption of the video signal generation circuit portion increases. Therefore, it is designed so that Cs> 10 Ch.
[0006]
  In the data signal line drive circuit 1 configured as described above, the video signal input to the video signal line SIG is sampled by the sample hold switch 14 and then temporarily stored in the sampling capacitor 16 in a certain horizontal scanning period. . The stored video data (charge) is transferred to and held in the hold capacitor 17 via the R / W switch 15 in the next horizontal scanning period.
[0007]
  In the next horizontal scanning period, a signal having the same level as the voltage held in the hold capacitor 17 is output to the data signal lines SL1 to SLm via the OP amplifier 18. Since the hold capacitor 17 is smaller than the capacitors of the data signal lines SL1 to SLm, the signal level written to the data signal lines SL1 to SLm is reduced by the charge capacity division. For this reason, the signal is amplified by the OP amplifier 18.
[0008]
  FIG. 26 is a timing chart of a conventional control signal, and shows timing charts of N1, N2, N3, TRF, horizontal scanning first line, second line, and third line at that time.
[0009]
  Conventionally, the data line driving circuit for TFT liquid crystal display has been configured by combining ICs formed of transistors formed on a Si substrate. On the other hand, in recent years, it has been promoted to form the drive circuit on the same glass substrate as the liquid crystal panel by a low temperature process. By forming the drive circuit on the glass substrate, the liquid crystal panel and the drive circuit can be integrated, and the advantages of high reliability by downsizing the device and reducing the number of wirings can be obtained. Further, the cost is reduced by changing the substrate on which the driving circuit is formed from Si to glass.
[0010]
  In order to obtain a good image on a liquid crystal display, reduction of an output voltage error of a data line driving circuit is an important issue. As causes of the output voltage error, for example, 1. 1. Leakage current when the transistor is OFF 2. residual charge in the hold capacitor; There is a feedthrough phenomenon due to capacitive coupling in the transistor. These phenomena become prominent particularly when polycrystalline Si formed on a glass substrate by a low temperature process is used. Hereinafter, the problem which arises by each cause is demonstrated.
[0011]
  The capacitance value of the sampling capacitor 16 is determined by the time when the 0N resistance of the sample hold switch 14 and the gate of the sample hold switch 14 are open. The transistor performance of polycrystalline Si formed on a glass substrate by a low temperature process is inferior to that of a transistor formed on a Si substrate. FIG. 27 shows the Vg-Id characteristics of a polycrystalline Si n-channel MOS transistor. W / L = 10 μm / 5 μm. The n-channel MOS transistor ON current when Vg = 5V is 10^-FourSince it can be read as A, the p-channel MOS transistor is considered to have the same level, and the ON resistance of the sample-and-hold switch 14 composed of the transfer gate is 25 kΩ (set to R) when Vg = 5V. For example, considering that the data line driving circuit for an SVGA (800 × 600 pixels) TFT liquid crystal display is divided into 8 (the panel is divided by 8 and driven for each block), the clock frequency is about 5 MHz. The time during which the sample hold switch 14 is open is 200 nsec (denoted t). The capacitance value Cs of the sampling capacitor 16 at this time is V0 (1−e) assuming that the error from the desired value is 0.1%.^{-t / CsR}) = 0.999, Cs = 1.2 pF. Since the capacitance value Ch of the hold capacitor 17 is preferably about 1/10 of Cs, Ch = 120 fF.
[0012]
[Problems to be solved by the invention]
  In the conventional data line driving circuit as described above formed of low-temperature process polycrystalline Si on a glass substrate, the capacitance value Ch of the hold capacitor 17 cannot be increased so much, and the polycrystalline silicon MOS transistor is turned off. Since the current is large, the charge (video data) accumulated in the hold capacitor 17 leaks to the sampling capacitor 16 through the R / W switch 15 and causes an error from the set voltage value. It was.
[0013]
  For example, from the characteristics of the polycrystalline Si n-channel MOS transistor shown in FIG. 27, the OFF current is 1 × 10 5 when Vg = −1V.^-Ten A. If the transfer channel p-channel MOS transistor has the same performance, the leakage current of the R / W switch 15 is 2 × 10.^-Ten Become A. Assuming that the capacitance value Ch of the hold capacitor 17 is set to 120 fF and the scanning time for one line is 28 μsec (1/60 sec / 600 lines), the voltage accumulated in the sampling capacitor 16 is 5 V for the first 28 μsec. If the voltage generated in the hold capacitor 17 is 0V, the signal line SIG and the hold capacitor 17 leak, so that the maximum error voltage from the desired value is
ΔV1 = 28 × 10^-6・ 2 × 10^-Ten・ 2 / 1.2 × 10^-12= 9.3mV
Next, when the voltage generated in the sampling capacitor 16 is 0 V and the voltage accumulated in the hold capacitor 17 is 5 V, the maximum error voltage from the desired value is
ΔV2 = 28 × 10^-6・ 2 × 10^-Ten/ 120 × 10^-15= 47mV
become. Therefore, the maximum error voltage with the total desired value is
ΔV1 + ΔV2 = 56mV
become. When this voltage is controlled from 0 to 5 V at 256 levels, it becomes 20 mV per bit, so it will be nearly 3 bits.
[0014]
  The switch of the conventional data line driving circuit is a transfer gate. As described above, since the switches are connected in parallel, there is a problem that the leakage current is large. If the switch unit is configured by only one of the n-channel MOS transistor and the p-channel, the leakage current is halved and the output error of the data line driving circuit of the low-temperature polycrystalline Si TFT is reduced.
[0015]
  In addition, since the conventional data line driving circuit does not reset the charge (video data) of the hold capacitor 17 every horizontal scanning time, the amount of charge remaining in the hold capacitor 17 and then the R / W switch 15 are set. Thus, an error occurs in the data (charge) transferred from the sampling capacitor 16.
[0016]
  For example, if 5V is stored in the hold capacitor 17 during the previous horizontal scanning period, if 0V data is sent during the next horizontal scanning period, the voltage Vh generated in the hold capacitor 17 should be Vh = 0V. However,
Vh = (5Ch + 0) / (Cs + Ch) = 455 mV
Become. Of course, there is no problem as long as a constant residual charge remains before the data is transferred to the hold capacitor 17. For example, if the previous data is 0V instead of 5V, the voltage generated in the hold capacitor 17 when 0V data is sent is 0V. As can be seen from this, the input data of 0 V changes between 0 and 455 mV at the time of output depending on the previous data. This maximum error voltage 455 mV corresponds to 20 times or more of the hold voltage 20 mV per bit and is a very large error.
[0017]
  In addition, the performance of a MOS transistor composed of low-temperature process polycrystalline Si is poor at 1/10 to 1/5 of the mobility compared to a single-crystal Si MOS transistor. If the sample hold switch 14 and the R / W switch 15 are configured using this transistor, the charge of the sampling capacitor and the hold capacitor must be charged and discharged within several hundreds of nsec, so that the transistor size naturally increases. (Drain current increases depending on the gate width W.) As the transistor size increases, the gate-source capacitance, the gate-drain capacitance, and the ON gate capacitance increase. Compared with the capacity 17, it cannot be ignored. Since each switch has a transfer gate configuration, an error occurs between the final value of the video data and the input value although the change in the amount of charge caused by feedthrough due to capacitive coupling is small. Due to this error, the input value must be corrected. In order to determine the data to be input to the OP amplifier by turning off the R / W switch 15, the charge is extracted by the feed-through at the OFF time, and the final value is more than the input value. Becomes smaller. Since the capacitance value of the hold capacitor 17 is small as described above, the amount of change is large. Therefore, in order to correct this, data must be input with a certain bias value. This has the problem that the burden on the data line driving circuit is increased. Specifically, the gate signals of the switches 14 and 15 must be level-shifted, and the drive voltage of the shift register or the like must be increased in order to drive the level shifter, resulting in an increase in power consumption. . In addition, there is a problem that the circuit scale increases.
[0018]
  The present invention has been made to solve the above-mentioned problems of the prior art, and aims to improve the data accuracy of a video signal and reduce the circuit scale and power consumption.
[0019]
[Means for Solving the Problems]
  The data line driving circuit of the matrix display according to the first configuration of the present invention includes a signal amplifying means for outputting a signal to the data line, and a signal amplifying means which is turned on / off by the sampling signal and is supplied to the sampling capacitor provided in the output unit A sample hold switch for controlling capture, and an R / W switch which is turned on / off by an R / W signal and which controls signal transmission from the sampling capacitor to the input unit of the signal amplifying means. Two series circuits of a hold switch and the R / W switch are provided in parallel, and the series circuit of each groupThe sample hold switch and the R / W switch are alternately operated every horizontal scanning period, and the two sets of series circuits areA data line driving circuit for a matrix display that is alternately driven every horizontal scanning period, wherein the signal amplification means is configured such that the ON time of the R / W signal is set to be higher than the ON time of the sampling signal within one horizontal scanning period. The output is advanced by a time longer than ½ of the rise time of the output.
[0020]
In addition to the first configuration, the data line driving circuit of the matrix display according to the second configuration of the present invention includes:The R / W switch is kept on until one horizontal scanning period ends.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
  FIG. 1 shows an embodiment. In the figure, the first row of RGB is shown as a part included in the data line driving circuit. Rsig is a video signal line, 141 is an odd-numbered sample / hold switch, 142 is an even-numbered sample / hold switch, 151 is an odd-numbered R / W switch, 152 is an even-numbered R / W switch, 161 is for odd-numbered rows, and 162 is an even-numbered row 1Rout is connected to an OP amplifier. The hold capacitor 171 is configured using the input capacitor of the OP amplifier. Reference numeral 101 denotes a reset switch for resetting the voltage (video data) written in the input capacitor of the OP amplifier to the voltage Vdd. The voltage Vdd is a constant value. Control signal lines for controlling each switch are connected to 1S / HOd, 1S / HEv, R / WOd, R / WEv, and RSTo.
[0022]
  The odd-numbered and even-numbered sample-and-hold switches 141 and 142 have a configuration in which low-temperature polycrystalline Si n-type MOS transistors Qa are connected in series as shown in the figure. Similarly, the odd-numbered and even-numbered R / W switches 151 and 152 have a configuration in which n-type MOS transistors Qb are connected in series. Similarly, the reset switch 101 is configured by connecting n-type MOS transistors Qc in series.
[0023]
  Each switch of the present embodiment has n-type MOS transistors in series. This effect will be described. FIG. 2 shows the Id-Vg characteristics of a low-temperature polycrystalline Sin type MOS transistor (Single Gate) with W / L = 10 μm / 5 μm and the characteristics when two of them are connected in series (Dual Gate). When the ON current when Vg = 5V is seen, it is 10 when Single is selected.^-Four5 x 10 for A and Dual^-FiveA and the current in series are decreasing. However, it can be seen that the OFF current is even smaller than ½ and can be lowered by about one digit. This method is a very effective means for suppressing the leakage current. Further, the same effect can be obtained when three or more MOS transistors are connected in series.
[0024]
  FIG. 3 shows a configuration diagram of the MOS transistor. In the case of an n-type transistor, a p-type impurity is doped under the gate, and an n-type impurity is doped in the source and drain. A length Leff sandwiched between n-type high impurity concentration regions is referred to as an effective channel length, and an effective gate width is referred to as an effective channel width Weff. The thickness of the gate oxide film is represented by TOX. The following expression represents a drain current in a saturation region (Vds ≧ Vgs−Vth: Vds is a drain-source voltage, Vgs is a gate-source voltage, and Vth is a threshold voltage).
Id = βn / 2 · (Vgs−Vth)²                            (1)
βn = μn · Cox · Weff / Leff
Cox = εr · ε0 / TOX
μn: mobility
As can be seen from the equation (1), the ON current increases in proportion to the gate width W and decreases in inverse proportion to the gate length L.
[0025]
  The mobility μ of the low-temperature polycrystalline Si (low-temperature polycrystalline Si) MOS transistor formed on the glass substrate is 1/5 to 1/1 compared with the single-crystal Si MOS transistor formed on the Si wafer. The value is 10. As can be seen from this, for example, when designing a data line driving circuit of SVGA-TFTLCD divided by 8, the data sampling time is 200 nsec. In order to fully charge the sampling capacitor 161 within this time, the ON resistance of the transistor must be set to a value corresponding to the sampling capacitor, that is, the drain current Id must be adjusted. Since the low-temperature polycrystalline SiMOS transistor has a lower mobility than the single crystal Si, the gate width W must be made larger than that of the MOS transistor using the single crystal Si, and the leakage current is naturally increased. This is a problem of a data line driving circuit configured using a low-temperature process polycrystalline SiMOS transistor on a glass substrate.
[0026]
  The present embodiment solves the above problems. FIG. 4 is a timing chart of horizontal scanning input to the control signal and the row line. This is an example of designing a data line driving circuit of SVGA-TFTLCD. The drive circuit is controlled by dividing by 8. RGB video data is input to the drive circuit in parallel for each of the eight divided areas. FIG. 4 shows one of eight circuits. Of course, similar control signals are input to the other seven.
[0027]
  A horizontal scanning pulse is generated in order from the first line to the 600th line within 1/60 sec. The pulse width is about 25 μsec. (Because there is a blanking period.) First, in order to sample the data of the first row before the horizontal scanning pulse of the first row is generated (period of the 0th row), the odd-numbered sample hold switch of each column 141, 1S / HOd, 2S / HOd to 106S / HOd (the columns 101 to 106 are dummy, and no video signal is actually input) are input to each sample hold switch, and the video data is The data is sequentially written in each sampling capacity 161. At the beginning of the horizontal scanning period of the first row, the control signal RST0 is input to each reset switch 101..., And the charges (video data) accumulated in the input capacitors (hold capacitors) of the OP amplifiers in each line are connected to the lines 1Rout, 2Rout. ... 1Gout, 2Gout ..., 1Bout, 2Bout ... are charged to the voltage Vdd by each reset switch. The reset period is 400 nsec, and Vdd is 5V. After the reset, the control signal R / Wod is input to the R / W switch 151, and the charges (video data) held in the respective sampling capacitors 161 are connected to 1Rout, 2Rout, 1Gout, 2Gout, 1Bout, 2Bout,. To the input capacitance of each OP amplifier. After the data is written to the OP amplifier, the R / W switch is kept ON until the scanning period of the first row is completed. While the first row is writing data to the OP amplifier, in the first row horizontal scanning period, the second row data is even-numbered row samples of each column by the control signals 1S / HEv, 2S / HEv to 106S / HEv. Video signals are sequentially written into the sampling capacitors 162... Via the hold switch. The written data is written into each OP amplifier after resetting the charge (video data) remaining in the input capacitance of each OP amplifier in the second row horizontal scanning period. This operation is repeated up to the 600th line.
[0028]
  As described above, since two sets of sampling switches and R / W series circuits are provided in parallel for each data line and driven alternately, the degree of freedom in timing of sampling, R / W and reset signals is great. For this reason, even when a polycrystalline silicon transistor having a low mobility is used, it is possible to drive a video signal with a high degree of design freedom and high accuracy.
[0029]
  In this embodiment, the input capacitance of the OP amplifier is reset to Vdd, which is a constant voltage. Therefore, a voltage corresponding to only the latest input value is generated on the signal lines 1Rout, 2Rout... 1Gout, 2Gout... 1Bout, 2Bout. Therefore, the error of the driving voltage due to the data of the previous row which has occurred in the case of the conventional data line driving circuit without the reset operation is eliminated.
[0030]
  In this embodiment, since the period for writing data from the sampling capacitors 161..., 162... Into the input capacitance (hold capacitance) of the OP amplifier is sufficiently long until the horizontal scanning period of the row ends, the data Is generated in parallel with the sampling capacitor Cs and the input capacitor Ch of the OP amplifier, and is generated by a leakage current as compared with the case where data is held only by the hold capacitor Ch as in the conventional data line driving circuit. Data errors are very small.
[0031]
  As described above, in the prior art, the OFF current is a single gate transfer gate.^-Ten A, if the hold capacity is 120 fF (sampling capacity 1.2 pF) and the scanning time T for one line is 28 μsec (1/60 sec / 600 lines), the maximum error voltage from the desired value is
ΔV = 56mV
It is. For comparison, in this embodiment as well, the sample hold switches 141 and 142 and the R / W switches 151 and 152 have a single transfer gate configuration of W / L = 10 μm / 5 μm instead of a dual gate configuration of n-type MOS transistors. Consider the case. At this time, the reset switch has a dual gate configuration using only a small W and large L n-type MOS transistor, and leakage to Vdd is very small. The first 28 μsec is held at a sampling capacity of 1.2 pF, and the subsequent 28 μsec is held at a sum of 1.32 pF of the sampling capacity 1.2 pF and the hold capacity 120 fF. Leakage current is 2 × 10^-TenAssuming A, the maximum error voltage from the desired value is
ΔV '= 28 × 10^-6・ 2 × 10^-Ten・ 2 / 1.2 × 10^-12
                      + 28 × 10^-6・ 2 × 10^-Ten/1.32×10^-12= 14mV
become. It can be seen that the maximum error voltage is reduced to 14 mV / 56 mV × 100 = 25% compared to the conventional case.
[0032]
  In the present embodiment, the sample hold switches 141 and 142 and the R / W switches 151 and 152 are actually composed of dual gates using only n-type MOS transistors as shown in FIG. The MOS transistors Qa of the sample and hold switches 141 and 142 are W / L = 30 μm / 5 μm, the Qb of the R / W switches 151 and 152 are W / L = 12 μm / 5 μm, and the Qc of the reset switch 101 is W / L = 5 μm / 5 μm The capacitance values of the sampling capacitors 161 and 162 are designed to be 1.05 pF, and the input capacitance value (hold capacitance) of the OP amplifier is designed to be 105 fF. The maximum error voltage at this time is obtained as described above. As shown in FIG. 2, the OFF current is reduced to 1 × 10 −11 due to the dual gate. However, since W is increased to 3 times, 1.2 times, and 0.5 times such as 30 μm, 12 μm, and 5 μm, the OFF current is 3 × 10^-11 1.2 × 10^-11 0.5 × 10^-11 It is. Therefore, the maximum error voltage ΔV1 ″ with the desired value of the first 28 μsec is
ΔV1 ″ = 28 × 10^-6(3 × 10^-11+ 1.2 × 10^-11)
                                /1.05×10^-12= 1.1mV
become. The maximum error voltage ΔV2 ″ with the desired value for the next horizontal scanning period of 28 μsec is
ΔV2 ″ 28 × 10^-6(1.2 × 10^-11+ 0.5 × 10^-11)
                                /1.16×10^-12= 0.41mV
Thus, the total maximum error voltage is ΔV1 ″ + ΔV2 ″ = 1.5 mV. It can be seen that the accuracy is very high compared to the conventional 56 mV.
[0033]
  Each switch of the present embodiment is not a conventional transfer gate but a dual gate of only an n-type MOS transistor in order to suppress leakage current. Data (charge) written in the OP amplifier changes due to the feedthrough at the time of switching. In particular, the change is large in the case of a switch constituted by only one of n-type and p-type. (The transfer gate discharges part of the charge (video data) held in the sampling capacitor or hold capacitor through the gate when the gate voltage of the n-type MOS transistor falls. Because the gate voltage rises, the capacitance is charged through the gate, so there is little change.) This feedthrough phenomenon does not increase the error voltage described above, but (always the charge for that input voltage changes, so data input Sometimes it is necessary to consider the change.) The input voltage must be biased. For example, in order to obtain an output of 0 to 4V, it is necessary to input 1 to 5V. In this embodiment, since it is originally composed only of an n-type MOS transistor, for example, it must be sufficiently turned on even when the source voltage is 3.9 V and the drain voltage is 4 V. Therefore, the level shifter is used for the gate. A voltage pulse of 5 V or more is applied. However, when a bias is applied by feedthrough, a higher gate voltage must be applied, which is disadvantageous in terms of power or device reliability (the higher the applied voltage, the more the device deteriorates). It is. If the gate signal has a bias, there will be no problem, but the control signal is 5V or 3.3V, and the voltage applied to the gates of the switches 141, 142, 151, 152, 101 is biased. The provision of the control signal requires an increase in the voltage of the control signal, that is, the input voltage of the level shifter, which is also a problem in terms of power consumption.
[0034]
  In this embodiment, since the R / W switches 151 and 152 are turned on until the horizontal scanning period ends, a part of charges (video data) extracted when the sample hold switches 141 and 142 are turned off are changed to R By balancing the charge charged through the gate when the / W switch is turned on and the charge charged at the time of resetting, the DC bias component of the data input to the OP amplifier can be minimized.
[0035]
  Next, the design method used in this embodiment will be described. As the capacitance value of the n-type MOS transistor, there are three possible values of Cgg, Cgd, and Cgs as shown in FIG. Cgd and Cgs move the charge corresponding to the change in the gate voltage (Vg), while Cgg moves the charge corresponding to the voltage change of Vg−source voltage (Vin) −threshold voltage (Vth). The calculation formula is shown for each process. The voltage charged to the sampling capacitors (Cs) 161 and 162 by the sample and hold switches 141 and 142 is
Vs1 = Vin (2)
The voltage Vs2 after the sample hold switch is turned off is
Vs2 = Vin − {(Vg−Vin−Vth) / 2 · Cgs / (Cs + Cgs) + Vg / 2 · Cgs ′ / (Cs + Cgs ′)} (3)
Cgs: Cgg of the sample hold switch,
Cgs ′: Cgd + Cgs of the sample hold switch,
Cs: sampling capacity
The voltage Vs3 after the reset switch 101 is turned on is
Vs3 = Vdd (4)
The voltage generated in the input capacity (Cw) of the OP amplifier after the reset switch is turned off is
Vw = Vdd − {(Vg−Vdd−Vth) / 2 · Cgr / (Ch + Cgr) + Vg / 2 · Cgr ′ / (Ch + Cgr ′)} (5)
Cgr: Cgg of the reset switch,
Cgr ′: Cgd + Cgs of reset switch,
Ch: Hold capacity
The sampling capacity after turning on the R / W switch and the voltage generated in the input capacity of the OP amplifier are:
Vout = (ChVw + CsVs) / (Ch + Cs) + {(Vg- (ChVw + CsVs) / (Ch + Cs) -Vth) ・ Cgw / (Cs + Ch + Cgw) + Vg ・ Cgw '/ (Cs + Ch + Cgw')} (6)
Cgw: Cgg of the R / W switch,
Cgw ′: Cgd + Cgs of R / W switch
Since the gate length L is constant at 5 μm and two transistors are in series, Cgs, Cgr, Cgw are
Cgs = 2ε0εr · LWs / TOX = KWs (7)
Cgr = 2ε0εr · LWr / TOX = KWr (8)
Cgw = 2ε0εr · LWw / TOX = KWw (9)
Ws, Wr, and Ww represent the gate widths of the transistors Qa, Qc, and Qb of each switch. The gate-source and gate-drain capacitances depend only on the gate width W. Since two transistors are connected in series, Cgs ′, Cgr ′, and Cgw ′ are
Cgs ′ = 4αWs = K′Ws (10)
Cgr ′ = 4αWr = K′Wr (11)
Cgr ′ = 4αWw = K′Ww (12)
TOX: gate oxide film thickness,
α: CGDO (gate-drain capacitance),
CGSO (gate-source capacitance),
CGDO = CGSO.
[0036]
  In the present embodiment, L = 5 μm, TOX = 50 nm, α = 1.68 nF / m (measured value),
Cgs, Cgr, Cgw = 6.73 × 10^-9Ws, 6.73 × 10^-9Wr, 6.73 × 10^-9Ww
Cgs ′, Cgr ′, Cgw ′ = 6.72 × 10^-9Ws, 6.72 × 10^-9Wr, 6.72 × 10^-9Ww
And
Cgs = Cgs ′ = Kws (13)
Cgr = Cgr ′ = Kwr (14)
Cgw = Cgw ′ = KWw (15)
K = 6.73 × 10^-9
You can.
When Cs = nCh and solving with Vin = Vout,
Ww = A (n + 1) Ch / {K (1-A)} (16)
A = {Vin− (Va + nVs) / (n + 1)} / Vz
Vz = 2Vg- (Va + nVs) / (n + 1) -Vth
Vs = Vin−VyKWs / (Cs + KWs)
Va = Vdd−VxKWr / (Ch + KWr)
Vy = (2Vg−Vin−Vth) / 2
Vx = (2Vg-Vdd-Vth) / 2
become. This embodiment operates with Vg = 9 V, Vdd = 5 V, Vth = 1.4 V, Cw = 105 fF, and n = 10. Vin was set to 3V which is a midpoint of 1 to 5V. (Because the OFF characteristic of the n-type MOS transistor is closer to the negative side of 1V. FIG. 2) An R / W switch is formed which has Vin = Vout when the gate width Ws of Qa constituting the sample hold switch is changed. The value of the gate width Ww of Qb is shown in FIG. When the value of the gate width Ws of the transistor Qa = 30 μm, which is the design value of the present embodiment, is taken, it can be seen that the gate width Ww of Qb = 12 μm.
[0037]
  FIG. 7 shows the effect of this design method. The input voltage-output voltage characteristics when only the design value of the present embodiment and the gate width Ww of the R / W switches 151 and 152 are changed from 12 μm to 5 μm are shown. The solid line and the dotted line are the results obtained from the above formula (6), and the points are the results obtained by the SPICE system circuit simulation. A broken line indicates an ideal input / output characteristic where the output / input is 1. From the figure, it is understood that a bias voltage of almost 0.5 V is required to be applied to the input value in the design of 5 μm of the dotted line, although the bias voltage is hardly required in the design of the solid line R / W switch of 12 μm. Of course, in the type in which the R / W switches 151 and 152 are turned OFF and the data value is determined as in the conventional method, it goes without saying that the bias voltage becomes several volts.
[0038]
  It can also be seen that the charge decrease due to the feedthrough is compensated by setting the reset voltage to Vdd instead of the GND voltage. Due to this effect, the transistor size of the R / W switch can be designed to be small. (Because the amount of charge supplied from the gate by feedthrough when the R / W switch is ON can be small from the desired value even if it is small.)
[0039]
  FIG. 8 shows voltage changes V (Cs) and V (Ch) of the sampling capacitors Cs 161 and 162 and the input capacitor Ch of the OP amplifier, and the gate signals 1S / HOd, 2S / HOd... 1S / HEv of the sample hold switches 141 and 142. 2S / HEv (represented by Vgs), gate signals R / WOd of R / W switches 151 and 152, R / WEv (represented by Vgw), and gate signal RSTo (represented by Vgr) of the reset switch 101. Indicates timing. First, the sample hold switch is turned on, and charge (video data) is accumulated in the sampling capacitor Cs. The charge is partially extracted by feedthrough when it is OFF, and becomes a value smaller than the input value. Next, the reset switch is turned ON, and the voltage of the input capacitor Ch of the OP amplifier is reset to the voltage Vdd. This also reduces the voltage due to feedthrough when OFF. At this time, the amount of charge remaining in Ch is a constant value. Next, the R / W switch is turned on, and data (charge) is written to the input capacitance Ch of the OP amplifier. After writing, this state is maintained for the horizontal scanning period.
[0040]
  The sample hold switch and the R / W switch are configured only by the nMOS transistor, and the design method for minimizing the data shift due to the feedthrough has been described. Of course, the configuration in which each switch is configured by the transfer gate is similarly described above. Using the method, the feedthrough is achieved by optimizing the transistor size.InIt goes without saying that the data shift due to this can be minimized.
[0041]
  Here, the configuration of the entire liquid crystal display device and the data line driving circuit will be described. FIG. 9 shows the entire liquid crystal display device. The data line driving circuit 1 receives GND, Vdd, Vff, Vcc, and Vee as power sources, HCLK, ST, L / SW, R / W, and RST as control signals, and analog video signals Rsig, Gsig, and Bsig. Has been. As outputs, R1, G1, B1, R2, G2,... Are connected corresponding to each color column (source of pixel TFT). 102 is a pixel TFT and 103 is a liquid crystal. The gate of the pixel TFT corresponding to each row is connected to and controlled by the horizontal shift register 104 so as to be opened in the horizontal scanning period of each row. S1, S2, S3, S4,... Indicate the first row, the second row, the third row, the fourth row,.
[0042]
  Vdd is a power supply for operating a shift register or the like, and has a voltage of 5V. Vff is a power source for operating the sample hold switch, R / W switch, and reset switch, and has a voltage of 9V. Vcc and Vee are power supplies for operating the OP amplifier, and are set to voltages of 9V and -5V, respectively. The control signal HCLK is a clock for operating the shift register, ST is a start pulse, L / SW is a line switching signal, R / W is a signal for writing data to the input capacity of the OP amplifier, and RST is a reset signal.
[0043]
  FIG. 10 shows the entire data line driving circuit. The data line driving circuit 1 includes a shift register 105, a clock buffer 106, a start buffer 107, an L / SW controller 108, a sample hold signal generation unit 109, a level shifter 110, a sample hold unit 111, an R / W switch unit 112, and an R / W switch. The reset signal generator 113 and the OP amplifier 114 are included. One clock buffer 106 is provided for each of six columns R1 to B2, one L / SW controller 108 is provided for one drive circuit, one sample hold signal generator 109 and one level shifter 110 are provided for three columns R1, G1, and B1, One sample hold unit 111, one R / W switch unit, and one OP amplifier are provided in one column, and one R / W and reset signal generation unit is provided in six columns R1 to B2. The power input is not shown.
[0044]
  11 and 12 show the configuration of the clock buffer and start buffer. The clock buffer has two inverters in series, and the signal nCK is input from the first-stage inverter output and the signal pCK is input to the shift register 105 from the second-stage inverter output. The start buffer has a configuration in which two inverters are connected in series, and the output signal STo of the second-stage inverter is input to the shift register. Driven with voltage Vdd. FIG. 13 shows the configuration of the shift register. A transfer gate including an n-type MOS transistor Qx and a p-type MOS transistor Qy and an inverter are included. When driven by the voltage Vdd and inputted with signals STo, pCK, nCK, SRo1, SRo2,... Are output. The two stages shown in the figure are one set, and this is repeated and connected. SRo1, SRo2, SRo3, SRo4,... Are ANDed with pCK, nCK, pCK, nCK,..., And signals SR1, SR2, SR3, SR4,. FIG. 16 shows a timing chart of each control signal and each output signal. As can be seen from FIG. 16, it is possible to obtain shift signals SR1, SR2, SR3, SR4,. That is, the shift register can be driven at a clock frequency that is ½ of the shift signal frequency. Since the drive limit frequency of the shift register composed of the low-temperature polycrystalline SiMOS transistor, which is inferior to that of single crystal Si, is lower than that of single crystal Si, it is driven by dividing by 8 as in this embodiment. Even so, it is difficult to drive high-definition LCD panels such as SVGA and XGA. However, if the shift register configuration used in this embodiment is used, it can be driven at a clock frequency that is ½ of the desired shift signal frequency, so that the general clock frequency matches the shift signal frequency. Compared with, it is possible to increase the drive limit frequency. In this embodiment, the SVGA LCD panel can be driven by using the shift register.
[0045]
  The shift signals SR1, SR2,... Are input to the respective sample hold signal generators 109. Control signals pL / SW and nL / SW generated from the L / SW controller 108 are input to each sample and hold signal generator 109. The configuration of the L / SW controller 108 is as shown in FIG. 17, and generates an inverted signal nL / SW and a non-inverted signal pL / SW of the signal L / SW. The signals SR1, pL / SW, nl / SW input to the sample hold signal generation unit 109 become an odd row sample hold control signal 1S / HOd and an even row sample hold control signal 1S / HEv by the AND circuit shown in FIG. . The timing chart of these signals 1S / HOd, 2S / HOd,..., 1S / HEv, 2S / HEv,.
[0046]
  The level shifter 110 is a circuit for level-shifting the voltages of the control signals 1S / HOd and 1S / HEv sent with the drive voltage Vdd (5V) to Vff (9V). The voltage level shift is realized using the circuit shown in FIG. Qx and Qz are n-type MOS transistors, and Qy is a p-type MOS transistor.
[0047]
  In FIG. 10, the sample hold unit 111 and the R / W switch unit 112 surrounded by a dotted line are the parts already shown and described in FIG. Video data Rsig, Gsig, Bsig, and control signals 1S / HOd, 1S / HEv are input to the sample hold unit 111, and the R / W switch unit includes R / W and a control signal formed by the reset signal generator 113. R / WOd, R / WEv, and RSTo are input.
[0048]
  The R / W and reset signal generator 113 shifts the level of the signal RST of the voltage Vdd (5V) to generate the signal RSTo of the voltage Vff (9V), and the inverted signal, non-inverted signal of the signal L / SW and the signal R / W A control signal is generated by level-shifting the signals R / WOd and R / WEv formed by AND with Vff to Vff.
[0049]
  The video data signal 1Rout output from the R / W switch unit 112 is connected to the input of the operational amplifier OPA1R, and the data amplifies the current through the operational amplifier and transmits the video data to the liquid crystal cell.
[0050]
  In FIG. 4, the timing of the control signal of this embodiment has been briefly described before. Here, the timing of the sample hold signals 1S / HOd and R / WEv, 1S / HEv and R / WOd in the first column. State. 20 shows horizontal scanning pulses (output signals S1, S2, S3... Of the horizontal shift register 104), sample hold signals 1S / HOd, 2S / HOd,..., 1S / HEv, 2S / HEv,. The timings of the / W signals R / WOd and R / WEv, the voltage V (R1) generated in the column data line R1, and the current I (R1) are shown. When the OP amplifier operates, current flows and charges the LCD panel. The LCD panel has a heavy load and is 60 to 80 pF. It takes some time to complete charging to this large capacitive load and transfer data to the liquid crystal cell. It is about 5 μsec. At this time, a large current flows through the GND line, the potential becomes unstable, and the circuit operation is affected. In order to avoid this, in this embodiment, the ON timing of the sample hold signals 1S / HEv and 1S / HOd is delayed by the time Td from the ON timing of R / WOd and R / WEv. (The ON timing of the start signal STo is delayed.) The value of Td is 1 of the rising and falling time Tr (time required from Low to High and from High to Low) of the output voltage V (R1) of the OP amplifier. It is larger than / 2. That is, Td> Tr / 2 is set. As described above, by performing the sample and hold operation while avoiding the timing of the current peak, a highly accurate sample and hold operation is enabled.
[0051]
Embodiment 2. FIG.
  Another embodiment of the sample hold unit and the R / W switch unit will be described. This is shown in FIG. As can be seen from a comparison with the embodiment of FIG. 1, the difference is the configuration of the sample and hold switches 115 and 116. Of course, the sample hold switch 115 is for odd lines and 116 is for even lines. In the sample and hold switches 115 and 116, n-type MOS transistors Qa are connected in series as in the first embodiment. A feature is that auxiliary capacitors (Cf) 117 and 118 are connected to a connection point between the transistors Qa.
[0052]
  The effect of this will be described. FIG. 22 shows the relationship between the drain-source voltage and the drain current when a gate voltage of −1 V is applied to a low-temperature polycrystalline Sin type MOS transistor having a gate length of L 5 μm and a gate width W of 10 μm. That is, it can be seen what value the leakage current at the OFF time has in the drain-source voltage. When the drain-source voltage of the transistor decreases by 1 V, the leakage current can be suppressed to about 1/5.
[0053]
  The second embodiment uses this characteristic and has an effect of further reducing the error from a desired value due to leakage of data (charge) held in the sampling capacitor Cs as compared with the first embodiment. The operation will be described. When analog video data (charge) is sampled in the sampling capacitor Cs during sample hold, the auxiliary capacitor Cf is simultaneously charged to the same potential. The charge stored in the auxiliary capacitor Cf leaks to the signal line Rsig side and decreases in voltage during the period when the data of each line is sampled and during the period when the data is written to the OP amplifier. 1V or less. For example, if the capacitance value of the auxiliary capacitor Cf is 500 fF, the voltage Vf after the 5 V charge leaks during the two-line scanning time 56 μsec (SVGA-LCD panel is driven by dividing by 8) is the transistor size of Qa, Since W / L = 30 μm / 5 μm from the first embodiment, the drain current in FIG.
Vf = (5 V × 500 fF−3 × 10^-TenA × 56μs)
                                  /500fF=4.966V
become. As can be seen from this, the current at which the charge stored in the sampling capacitor Cs leaks to the Rsig side is 10 from FIG.^-13 It becomes A order. Therefore, the leak to the Rsig side is negligibly small, the error from the desired value of the data is reduced, and the accuracy of the analog data output value is increased.
[0054]
  FIG. 23 shows another configuration of the sampling switches 115 and 116. As described above, the leakage current of the transistor Qa can be reduced by lowering the drain-source voltage of Qa. In the figure, an inverted signal of the S / HOd signal is input to the transistor 210, and the potential at the connection point between Qa and Qb is fixed to Vx when Qa and Qb are OFF. For example, assuming that Rsig changes from Vmin to Vmax, when Vx is fixed to (Vmin + Vmax) / 2, the maximum value of the drain-source voltage of Qa decreases to about half. For example, if Vmin = 1V and Vmax = 5V, Vx is 3.5V, and the leakage current is 1 × 10 in FIG.^-TenFrom (A) to 8 × 10^-12It decreases to (A). Therefore, the leakage to the Rsig side becomes so small that it can be ignored, the error from the desired value of the data is reduced, and the data accuracy is improved.
[0055]
  The LCD data line driving device composed of low-temperature process polycrystalline Si MOS transistors has been described, but this technology can also be applied to a data line driving circuit composed of single-crystal Si or high-temperature polycrystalline Si MOS transistors. Needless to say.
[0056]
【The invention's effect】
  According to the data line driving circuit of the matrix display according to the first configuration of the present invention, the signal amplifying means for outputting a signal to the data line and the sampling capacitor which is turned on / off by the sampling signal and provided in the output unit A sample-and-hold switch that controls data signal capture, and an R / W switch that is turned on / off by an R / W signal and that controls signal transmission from the sampling capacitor to the input of the signal amplifying means. Two series circuits of the sample hold switch and the R / W switch are provided in parallel, and the series circuit of each group is provided.The sample hold switch and the R / W switch are alternately operated every horizontal scanning period, and the two sets of series circuits areA data line driving circuit for a matrix display that is alternately driven every horizontal scanning period, wherein the signal amplification means is configured such that the ON time of the R / W signal is set to be higher than the ON time of the sampling signal within one horizontal scanning period. Since the output time is faster than 1/2 of the output rise time, the sample and hold operation can be performed while avoiding the unstable period of the GND line voltage immediately after the R / W pulse is turned on. Operation is possible.
[0057]
Further, in addition to the first configuration, if the R / W switch is kept on until one horizontal scanning period ends,During the hold period of the video signal, the hold capacitor and the sampling capacitor act in parallel to increase the capacitance value, so that the error voltage of the video signal due to the leakage current of the switch circuit decreases.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a sample hold unit and an R / W switch unit according to the present embodiment.
FIG. 2 is a diagram showing Id-Vg characteristics of a single gate and dual gate configuration of a low-temperature polycrystalline Sin type MOS transistor with W / L = 10 μm / 5 μm.
FIG. 3 is a configuration diagram of a MOS transistor.
FIG. 4 is a drive sequence diagram of the present embodiment.
FIG. 5 is a diagram showing parasitic capacitance of a MOS transistor.
FIG. 6 shows a sample hold switch gate width Ws and an R / W switch gate width where output / input = 1 when a sample hold, R / W, and reset switch are configured in a dual gate configuration of an n-type MOS transistor. It is a graph which shows the relationship of Wr.
FIG. 7 is a graph showing the relationship between input and output when the transistor sizes of the sample hold switch, R / W switch, and reset switch are optimized.
FIG. 8 is a diagram illustrating gate signal timing of the sample hold switch, the R / W switch, and the reset switch, and voltage change of the sampling capacitor Cs and the hold capacitor (OP amplifier input capacitor) Ch.
FIG. 9 is a diagram showing an entire liquid crystal display.
FIG. 10 is a diagram showing an entire data line driving circuit.
FIG. 11 is a diagram illustrating a configuration of a clock buffer circuit.
FIG. 12 is a diagram showing a configuration of a start pulse buffer.
FIG. 13 illustrates a structure of a shift register circuit.
FIG. 14 is a diagram illustrating a configuration of an odd-numbered output circuit of a shift register circuit.
FIG. 15 is a diagram showing a configuration of an even-numbered output circuit of a shift register circuit;
FIG. 16 is a timing chart of an input signal and an output signal of the shift register circuit.
FIG. 17 is a diagram showing a circuit configuration of an L / SW controller.
FIG. 18 is a diagram illustrating a configuration of a circuit that generates a 1S / HOd signal and a 1S / HEv signal.
FIG. 19 is a diagram showing a configuration of a level shift circuit.
FIG. 20 is a diagram illustrating the timing of the output voltage waveform, current waveform, and control signal of the OP amplifier.
FIG. 21 is a circuit diagram showing configurations of a sample hold unit and an R / W switch unit according to another embodiment.
FIG. 22 is a graph showing the relationship between drain-source voltage and leakage current of a low-temperature polycrystalline Sin type MOS transistor with W / L = 10 μm / 5 μm.
FIG. 23 is a diagram showing another configuration of the sampling switch.
FIG. 24 is a diagram showing a conventional data line driving circuit.
FIG. 25 is a diagram showing a conventional switch configuration.
FIG. 26 is a timing chart of a conventional control signal.
FIG. 27 is a diagram showing Id-Vg characteristics of a single gate configuration of a low-temperature polycrystalline Sin type MOS transistor with W / L = 10 μm / 5 μm.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Data line drive circuit, 11 Shift register, 12 Buffer circuit, 14 Sample hold switch, 15 R / W switch, 16 Sampling capacity, 17 Hold capacity, 18 OP amplifier, 101 Reset switch, 102 Pixel TFT, 103 Liquid crystal, 104 Horizontal Shift register, 105 Shift register, 106 Clock buffer, 107 Start buffer, 108 L / SW controller, 109 Sample hold signal generator, 110 Level shifter, 111 Sample hold, 112 R / W switch, 113 R / W, Reset signal Generator, 114 OP amplifier, 115, 116 Auxiliary capacitor, 141 Odd row sample / hold switch, 142 Even row sample / hold switch, 151 Odd row R / W switch, 1 52 even row R / W switch, 161 odd row sampling capacity, 162 even row sampling capacity.

Claims (2)

A signal amplifying means for outputting a signal to the data line;
A sample-and-hold switch that is turned on and off by the sampling signal and that controls the capture of the data signal into the sampling capacitor provided in the output unit;
An R / W switch that is turned on / off by an R / W signal and controls signal transmission from the sampling capacitor to the input of the signal amplification means;
With
Two series circuits of the sample hold switch and the R / W switch are provided in parallel for each data line, and the sample hold switch and the R / W switch of the series circuit of each set are provided in one horizontal scanning period. A matrix display data line driving circuit that operates alternately every time and drives the two series circuits alternately every horizontal scanning period,
A matrix characterized in that the ON time of the R / W signal is advanced by a time greater than ½ of the rise time of the output of the signal amplifying means from the ON time of the sampling signal within one horizontal scanning period. Display data line drive circuit.   2. The data line driving circuit for a matrix display according to claim 1, wherein the R / W switch is held in an on state until one horizontal scanning period ends.

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