JP3911386B2 - DMA communication control method, transfer data processing method, DMA communication control device, and engine control device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a DMA (Direct Memory Access) communication control method, a transfer data processing method,DMA communication control device,And, more specifically, the DMA control method in the case where data exchange with the A / D conversion means is performed by serial communication using the DMA control means, and is transferred using the DMA communication control method. Data processing method for processing received data, and the DMAA DMA communication control apparatus comprising main control means for performing control using the control means;The present invention relates to an engine control device.
[0002]
[Prior art]
The engine control is centered on the fuel injection control, and the ignition timing control, knock control, idle speed control, diagnosis, etc. are comprehensively controlled by a microcomputer (hereinafter simply referred to as a microcomputer) to optimize the engine. By operating it, it has the effects of improving power performance, purifying exhaust gas, and improving fuel efficiency.
[0003]
FIG. 10 is a block diagram schematically showing a main part of an engine control ECU (Electronic Control Unit) which is the center of a system for electronic control of the engine. In the figure, reference numeral 1 denotes an ECU. The ECU 1 includes a microcomputer 2, an A / D conversion IC 7, an input processing circuit 8, and an output processing circuit 9. The microcomputer 2 includes a CPU 3, a RAM 4, and a ROM 5. And a DMAC (Direct Memory Access Controller) 6.
[0004]
Analog signals output from the water temperature sensor, intake air amount sensor, oil temperature sensor, air flow meter, throttle opening sensor, knock sensor, etc. are A / D converted by the A / D conversion IC 7, and the crank angle sensor, engine rotation sensor The digital signal output from the above is input to the microcomputer 2 via the input processing circuit 8.
[0005]
Further, the microcomputer 2 calculates an optimal control value based on these input signals, and drives various actuators such as solenoids and motors, lights lamps, and other ECUs via the output processing circuit 9. Is to control. Data exchange between the microcomputer 2 and the A / D conversion IC 7 is serial communication via the serial communication line L, and DMA communication is performed to reduce the load on the CPU 3.
[0006]
The sensor signal subjected to A / D conversion processing is periodically A / D converted every predetermined time (for example, 4 milliseconds), such as water temperature, intake air amount, oil temperature (for example, 20 ch in total). Some are processed, and some are A / D converted in synchronization with engine rotation, such as a knock signal. In other words, the A / D conversion processing here includes time synchronization A / D conversion processing and non-time synchronization A / D conversion processing such as engine rotation synchronization A / D conversion processing.
[0007]
As described above, when there are two types of A / D conversion processes having different activation timings, as shown in FIG. 11, while the time synchronous A / D conversion process is being executed (that is, the time synchronous A / D conversion). While the processing request is being generated, a request for engine rotation synchronization A / D conversion processing may occur. Conversely, a time-synchronized A / D conversion process request is generated while the engine rotation-synchronized A / D conversion process is being executed (that is, while an engine rotation-synchronized A / D conversion process request is being generated). There are things to do.
[0008]
When processing requests overlap, a request generated later is awaited until the DMA communication at that time ends. This is because when DMA communication is started once, communication is automatically performed by the hardware function of the microcomputer 2, and the serial communication line L is occupied, and other requests are interrupted in the middle. It is because it is not possible. That is, if the CPU 3 activates the DMAC 6 once, the DMAC 6 occupies the serial communication line L.
[0009]
Accordingly, since the engine rotation synchronization A / D conversion process cannot be executed during the period in which the time synchronization A / D conversion process is being performed (for example, 1.6 milliseconds), the time synchronization A / D conversion process ends. You have to wait until you do it, and it may be delayed up to 1.6 ms. This is a case where data for A / D conversion processing is synchronized with time for 20 channels and processing for 1 channel takes 80 μs.
[0010]
[Problems to be solved by the invention]
However, if the A / D conversion process of the knock signal is delayed by 1 ms or more, a problem may occur. Therefore, at present, the time synchronous A / D conversion process is divided into two (first half: 10 ch, second half: 10 ch), As shown in FIG. 12, the A / D conversion process is alternately performed every 2 milliseconds to prevent a delay in the engine rotation synchronization A / D conversion process.
[0011]
Next, the sensor signals output from the water temperature sensor, the intake air amount sensor, the oil temperature sensor (20 ch in total) are A / D converted by the A / D conversion IC 7, and the 20 A / D converted processing signals are A case where data is written to the RAM 4 will be described with reference to a flowchart shown in FIG. 13 and a timing chart shown in FIG.
[0012]
First, the CPU 3 determines the address Da of the RAM 4.₀ ~ Da_TenIn addition, transmission data to be transmitted from the DMAC 6 to the A / D conversion IC 7 via the serial communication line L is used as a transmission table Ta (see FIG. 15A) or a transmission table Tb (see FIG. 15B). Set (steps A1, a1).
[0013]
When the setting is completed, the start address Da of the memory in which the transmission table Ta (, Tb) is set₀ Are written in the address register inside the DMAC 6 and the number of data 10 is written in the counter inside the DMAC 6 (steps A 2 and a 2).
[0014]
Further, A / D conversion processing is performed by the A / D conversion IC 7, and the data subjected to the A / D conversion processing is transmitted to the DMAC 6. When this data is received by the DMAC 6, the data is transferred to a predetermined memory. Since it is necessary, the start address Db of the transfer destination table Tw (RAM4)₀ Are written in the address register inside the DMAC 6, and the number of data 10 is written in the counter inside the DMAC 6 (steps A3 and a3). When the writing is completed, an operation start command is transmitted to the DMAC 6 (steps A4 and a4).
[0015]
When the DMAC 6 receives the operation start command from the CPU 3, the address Da₀ The data stored in order (ie, data in the transmission table Ta or transmission table Tb) is transmitted to the A / D conversion IC 7 via the serial communication line L (step B1).
[0016]
When the A / D conversion IC 7 receives the data from the DMAC 6 (that is, the data including the A / D conversion processing start command and the channel of the signal to be A / D converted), the A / D conversion IC 7 receives the A / D of the corresponding sensor signal. D conversion processing is performed (step C1), and the A / D conversion processing data is transmitted to the DMAC 6 via the serial communication line L (step C2).
[0017]
When the DMAC 6 receives the A / D converted data transmitted from the A / D conversion IC 7, the DMAC 6 sends the data to the address Db.₀ Are sequentially written in the transfer destination table Tw (step B2). When these processes are completed once, the address signal is incremented by 1 and continues as shown in FIG. 16 until the reception of 10 data is completed. When the reception of 10 data is completed, the process is completed. Is notified to the CPU 3 (step B3).
[0018]
When the CPU 3 receives a notification of completion of processing from the DMAC 6, the CPU 3 performs predetermined processing using the data written in the transfer destination table Tw (steps A5 and a5).
[0019]
Further, steps D1 to D3 shown in FIG. 14 are processes performed in synchronization with the engine rotation, and the CPU 3 sends the serial communication line from the DMAC 6 to the address Dc of the RAM 4 in order to perform the A / D conversion process on the knock signal. Transmission data to be transmitted to the A / D conversion IC 7 via L is set (step D1). When the setting is completed, the address Dc is stored in the internal address register of the DMAC 6, and the number of data 1 is stored in the internal counter of the DMAC 6. (Step D2).
[0020]
Further, A / D conversion processing is performed by the A / D conversion IC 7, and the data subjected to the A / D conversion processing is transmitted to the DMAC 6. When this data is received by the DMAC 6, the data is transferred to a predetermined memory. Since there is a need, the address Dd of the transfer destination table Tx (RAM4) is written to the address register inside the DMAC6, and the number of data 1 is written to the counter inside the DMAC6 (step D3). A command is transmitted (step D4).
[0021]
When the DMAC 6 receives the operation start command from the CPU 3, the DMAC 6 transmits the data stored in the address Dc to the A / D conversion IC 7 via the serial communication line L (step B4).
[0022]
When the A / D conversion IC 7 receives data from the DMAC 6 (that is, data including the A / D conversion processing start command and the channel of the knock signal to be A / D converted), the corresponding sensor signal (knock) is received. Signal) is A / D converted (step C3), and the A / D converted data is transmitted to the DMAC 6 via the serial communication line L (step C4).
[0023]
When the DMAC 6 receives the A / D converted data transmitted from the A / D conversion IC 7, the DMAC 6 writes the data to the address Dd of the transfer destination table Tx (step B 5). Therefore, the CPU 3 is interrupted to notify the CPU 3 that the processing has been completed (step B6).
[0024]
When the CPU 3 receives notification of the completion of processing from the DMAC 6, the CPU 3 performs predetermined processing using the data written in the transfer destination table Tx (step D5).
[0025]
As described above, by performing the time-synchronized A / D conversion process in two, the maximum delay time of the knock signal A / D conversion process can be reduced to 0.8 milliseconds.
[0026]
However, the time synchronization A / D conversion process is divided into two parts, so that the A / D conversion process is performed and the process using the time synchronization data transferred to the transfer destination table Tw, the setting of the transmission table, etc. Before the division, only the step A5 and the steps A1 to A4 may be sufficient. However, the division requires the step a5 and the steps a1 to a4, which increases the processing load on the CPU 3.
[0027]
  The present invention has been made in view of the above problems, and can prevent a delay in processing performed without synchronizing with time, such as engine rotation synchronization A / D conversion processing, and reduce the processing load on the CPU. DMA communication control method that can be performed, transfer data processing method for processing data transferred using the DMA communication control method,DMA communication control device, andAn object of the present invention is to provide an engine control device.
[0028]
[Means for solving the problems and effects thereof]
  In order to achieve the above object, in the DMA communication control method (1) according to the present invention, there are at least two types of time synchronization data that need to be processed in synchronization with time, and without synchronizing with time, There is at least one type of non-time-synchronous data that needs to be processed at a predetermined timing, and these processes are performed using the DMA control means, and the A / D conversion is performed on the processing performed by the DMA control means. In the DMA communication control method in the case of including transmission of data for A / D conversion processing request to the means and reception of data A / D converted by the A / D conversion means, the time synchronization data , N (≧ 2) groups, the first data requesting the DMA control means to process the time synchronization data belonging to the first group in synchronization with time When the processing request step and the processing of the time synchronization data belonging to the kth (1 ≦ k ≦ n−1) th group are completed, the DMA control means sends the processing of the time synchronization data belonging to the k + 1th group. A second data processing requesting step for requesting non-time synchronous data processing to request the DMA control means to process the non-time synchronous data in synchronization with a predetermined timing instead of time, and IncludingWhen the DMA control means is processing the time synchronization data belonging to the kth group, if it is not time to request the processing of the non-time synchronization data, the kth group When the processing of the time synchronization data belonging to the kth group is completed in order to continuously perform the processing of the time synchronization data belonging to the k + 1th group and the processing of the time synchronization data belonging to the k + 1th group, Without requesting the DMA control means to process the time synchronization data belonging to the (k + 1) th group, while the DMA control means processes the time synchronization data belonging to the kth group. If it is time to request processing of the non-time-synchronized data, the time-synchronized data belonging to the kth group If management is completed, the on DMA control unit, rather than requiring the time processing of the synchronous data belonging to the (k + 1) th group, and requests the non-time processing of synchronous data,The first non-time synchronous data processing request step is prioritized over the second data processing request step.
[0029]
  According to the above-described DMA communication control method (1), the time synchronization data is divided into n (≧ 2) groups, and processing of the time synchronization data is requested for each group. Since a period during which the DMA control means does not occupy the serial communication line L (see FIG. 1) can be created between the processing of the time synchronization data to which it belongs, the processing of non-time synchronization data is interrupted during this period. It becomes possible to make it.
  Further, the first non-time synchronous data processing request step is prioritized over the second data processing request step.Therefore, it is possible to prevent a delay in processing performed without synchronizing with time, such as engine rotation synchronization A / D conversion processing.
[0030]
Furthermore, although the time synchronization data is divided into n groups, when the processing of the time synchronization data belonging to the kth (1 ≦ k ≦ n−1) th group is finished, the DMA control means , A second data processing requesting step for requesting processing of the time synchronization data belonging to the (k + 1) th group, for example, when processing of the time synchronization data belonging to the first group is completed, The DMA control means is requested to process the time synchronization data belonging to the second group.
[0031]
  According to the DMA communication control method (1), when the DMA control means is processing the time synchronization data belonging to the kth group, it requests processing of the non-time synchronization data. If the timing is not reached, the k-th group is processed in order to continuously process the time-synchronized data belonging to the k-th group and the time-synchronized data belonging to the k + 1-th group. Instead of requesting the DMA control means to process the time-synchronized data belonging to the (k + 1) -th group without stopping after the processing of the time-synchronized data belonging to the group is completed, the non-time synchronization Request data processing.
  for that reason,For example, even if the time synchronization data is divided into a first half group (first group) and a second half group (second group and also the final nth group),If it is not necessary to interrupt the processing of the non-time synchronized data,The processing of the time synchronization data belonging to the first half group and the processing of the time synchronization data belonging to the second half group are continuously performed.ShowTherefore, when the predetermined processing is performed using the data after the processing, the first half group and the second half group can be performed at a time. Therefore, the processing load on the CPU can be reduced.
[0033]
  Also, a DMA communication control method (2) Is the DMA communication control method (1), After the processing of the time synchronization data belonging to the k-th group is finished, if the DMA control means is not requested to process the time synchronization data belonging to the k + 1-th group, When the processing of the time synchronization data is completed, the DMA control means includes a third data processing requesting step for requesting the processing of the time synchronization data belonging to the (k + 1) th group.
[0035]
  Further, as described above, the processing of the non-time synchronization data is interrupted between the processing of the time synchronization data belonging to the k-th group and the processing of the time synchronization data belonging to the k + 1-th group. Even if the above-mentioned DMA communication control method (2) Includes the third data processing requesting step for requesting the DMA control means to process the time synchronous data belonging to the (k + 1) th group when the processing of the non-time synchronous data is completed. Therefore, the time synchronization data belonging to the (k + 1) th and subsequent groups can be reliably processed.
[0036]
  Also, a DMA communication control method (3) Is the DMA communication control method (1)Or (2)When the DMA control means is processing the time synchronization data belonging to the nth group, and when it is time to request the processing of the non-time synchronization data, the nth When the processing of the time synchronization data belonging to the group is completed, the DMA control means is requested to process the non-time synchronization data.2The non-time synchronous data processing requesting step is included.
[0037]
  The above-mentioned DMA communication control method (3), When the DMA control means is processing the time-synchronized data belonging to the n-th group (that is, the last group), at the timing of requesting the processing of the non-time-synchronized data. In this case, when the processing of the time synchronization data belonging to the nth group is completed, the DMA control means is requested to process the non-time synchronization data.2Since the non-time synchronous data processing request step is included, it is possible to prevent a delay of processing performed without synchronizing with time, such as engine rotation synchronization A / D conversion processing.
[0038]
  Also, a DMA communication control method (4) Is the DMA communication control method (1) to (3), When the DMA control means is processing the non-time-synchronized data, and when it is time to request processing of the time-synchronized data belonging to the first group, When the processing of the non-time-synchronized data is completed, the DMA control means includes a fourth data processing request step for requesting the processing of the time-synchronized data belonging to the first group.
[0039]
  The above-mentioned DMA communication control method (4), When the DMA control means is processing the non-time-synchronized data, and when it is time to request processing of the time-synchronized data belonging to the first group, When the processing of the non-time synchronization data is completed, the DMA control means includes the fourth data processing request step for requesting the processing of the time synchronization data belonging to the first group. It is possible to ensure that the process is performed.
[0040]
  Also, a DMA communication control method (5) Is the DMA communication control method (1) to (4), At least one group of transmission data for transmission from the DMA control means to the other party that performs serial communication with the DMA control means is collected and stored in a predetermined location. A first transmission data storing step is included.
[0041]
  Also, a DMA communication control method (6) Is the DMA communication control method (1) to (5), At least two groups of transmission data for transmission from the DMA control means to the other party that performs serial communication with the DMA control means are collected into a transmission table and stored in a predetermined location. A second transmission data storage step is included.
[0042]
  Also, a DMA communication control method (7) Is the DMA communication control method (5Or (6), The transmission table is configured based on the priority of the time synchronization data.
[0043]
As described in the section “Problems to be Solved by the Invention”, the CPU 3 sends the DMAC 6 to the A / D conversion IC 7 which is a counterpart to perform serial communication with the DMAC 6 before issuing an instruction to the DMAC 6. Transmission data for this purpose is stored in the RAM 4. Incidentally, in FIG. 13 and FIG. 14, this processing is shown as processing of steps A1 and a1.
[0044]
  The above-mentioned DMA communication control method (5) ~ (7), The transmission data is not stored in a predetermined place for each transmission, but is stored as a transmission table in a group for at least one group, so that the processing load on the CPU can be reduced. it can.
[0045]
  Further, the above-described DMA communication control method (6), At least two groups are collectively stored as a transmission table, so that the processing load on the CPU can be further reduced.
[0046]
  Also, the above-described DMA communication control method (7Since the transmission table configured based on the priority of the time synchronization data can be used, it is possible to avoid performing communication control more than necessary.
[0047]
For example, in the past, the 20 types of time-synchronized data used for engine control were all treated equally by performing A / D conversion processing every 4 milliseconds, but these 20 types of data are not at the same level. In other cases, one A / D conversion process is required once every 4 milliseconds, and another A / D conversion process is sufficient once in 64 milliseconds. Therefore, efficient communication can be performed by using the transmission table configured based on the priority of the time synchronization data.
[0049]
  DMA communication control method (1) to (7), The time synchronization data is divided into n groups so that the time synchronization data belongs substantially equally, so that balanced communication control can be performed, and communication with less waste can be realized.
[0050]
  Further, the transfer data processing method (1) according to the present invention comprises the DMA communication control methods (1) to (7A transfer data processing method for processing data transferred using any one of the above), including a transfer data processing step for performing predetermined processing using the transferred data for at least two groups collectively It is characterized by being.
[0051]
As described in the section “Problems to be Solved by the Invention”, when the CPU 3 receives a notification of the completion of processing from the DMAC 6, conventionally, the CPU 3 uses the data written in the transfer destination table Tw to perform predetermined processing. The process is to be performed. Incidentally, in FIG. 13 and FIG. 14, this processing is shown as processing of steps A5 and a5.
[0052]
As described above, conventionally, by dividing the time-synchronized A / D conversion process into two, the process using the time-synchronized data that has been A / D converted and transferred to the transfer destination table Tw is performed before the division. Step A5 was sufficient, but by dividing, step a5 was necessary, and the processing load on the CPU 3 increased.
[0053]
According to the transfer data processing method (1) described above, since the transfer data processing step for performing predetermined processing using the transferred data collectively for at least two groups is included, the processing load on the CPU increases. Can be avoided.
[0054]
  The DMA communication control apparatus (1) according to the present invention includes a transmission process for transmitting processing request data for A / D conversion processing to the A / D conversion processing means, and A / D conversion by the A / D conversion processing means. In the DMA communication control apparatus having the main control means for performing the reception of the processed A / D conversion data using the DMA control means, the data to be subjected to the A / D conversion processing is synchronized with time. Including at least two types of time-synchronized data that needs to be processed and at least one type of non-time-synchronized data that needs to be processed in synchronization with the rotational speed of the engine. When receiving a command from the main control means to transmit the processing request data of the A / D conversion process, the main control means performs the transmission process and the reception process. A first command that divides the data into two groups is used to instruct the DMA control means to transmit the processing request data for requesting A / D conversion processing in synchronization with time. When the first data processing requesting unit and the transmission processing and the reception processing for the first group are completed, A / D conversion is performed on a second group different from the first group in the time synchronization data. A second data processing requesting means for instructing the DMA control means to transmit the processing request data for requesting processing, and A / D conversion for the non-time synchronized data in synchronization with the engine speed Non-time synchronous data processing requesting means for instructing the DMA control means to transmit processing request data for requesting processing;When the DMA control means is processing the time synchronization data belonging to the first group and the timing for requesting the processing of the non-time synchronization data is not reached, the first group When the processing of the time synchronization data belonging to the first group is completed, the processing of the time synchronization data belonging to the second group and the processing of the time synchronization data belonging to the second group are continuously performed. Without transmission, the DMA control unit is instructed to transmit processing request data for requesting A / D conversion processing to the second group, while the DMA control unit is in the first group. When it is time to request processing of the non-time-synchronized data when processing of the time-synchronized data to which it belongs, the time belonging to the first group When the processing in the period data is completed, the relative non-time synchronous data, the transmission of the processing request data for a request for A / D conversion processing is commanded to the DMA controller,The processing by the non-time synchronous data processing requesting unit is prioritized over the processing by the second data processing requesting unit.
  The engine control apparatus (1) according to the present invention includes a transmission process for transmitting processing request data for A / D conversion processing to the A / D conversion processing means, and an A / D conversion processing by the A / D conversion processing means. Main control means for performing reception processing for receiving received A / D conversion data using DMA control meansengineIn the control device, at least two types of time-synchronized data that needs to be processed in synchronization with time and data that is subjected to A / D conversion processing, and non-time that needs to be processed in synchronization with the engine speed When at least one type of synchronization data is included, and the DMA control unit receives an instruction from the main control unit to transmit the processing request data for A / D conversion processing, the transmission processing and the reception processing The main control means makes a request for A / D conversion processing in synchronization with time for the first group of the time synchronization data divided into two groups. When the first data processing requesting unit for instructing the DMA control unit to transmit the processing request data and the transmission processing and the receiving processing for the first group are completed, the time Second data processing request means for instructing the DMA control means to transmit the processing request data for requesting A / D conversion processing to a second group different from the first group in the period data And non-time synchronous data processing requesting means for instructing the DMA control means to transmit processing request data for requesting A / D conversion processing in synchronization with the engine speed with respect to the non-time synchronous data. WithWhen the DMA control means is processing the time synchronization data belonging to the first group and the timing for requesting the processing of the non-time synchronization data is not reached, the first group When the processing of the time synchronization data belonging to the first group is completed, the processing of the time synchronization data belonging to the second group and the processing of the time synchronization data belonging to the second group are continuously performed. Without transmission, the DMA control unit is instructed to transmit processing request data for requesting A / D conversion processing to the second group, while the DMA control unit is in the first group. When it is time to request processing of the non-time-synchronized data when processing of the time-synchronized data to which it belongs, the time belonging to the first group When the processing in the period data is completed, the relative non-time synchronous data, the transmission of the processing request data for a request for A / D conversion processing is commanded to the DMA controller,The processing by the non-time synchronous data processing requesting unit is prioritized over the processing by the second data processing requesting unit.
[0055]
  DMA communication control device (1)According to the engine control device (1) described above, it is possible to prevent a delay in processing performed without synchronizing with time, such as engine rotation synchronization A / D conversion processing.
[0056]
  further,According to the above-described DMA communication control device (1) and the above-described engine control device (1), the main control meansIt is practical because it is designed to reduce the processing load ofDMA communication control device,An engine control device can be realized.
[0057]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, a DMA communication control method, a transfer data processing method according to the present invention,DMA communication control device,An embodiment of the engine control device will be described with reference to the drawings.
[0058]
FIG. 1 is a block diagram schematically showing a main part of an engine control ECU in which the engine control apparatus according to the embodiment (1) is employed. Components similar to those of the engine control ECU shown in FIG. 10 are denoted by the same reference numerals, and description thereof is omitted here. In the figure, reference numeral 11 denotes an ECU. The ECU 11 includes a microcomputer 12, an A / D conversion IC 7, an input processing circuit 8, and an output processing circuit 9. The microcomputer 12 includes a CPU 13, a RAM 14, and a ROM 15. And the DMAC 16.
[0059]
Analog signals output from the water temperature sensor, intake air amount sensor, oil temperature sensor, air flow meter, throttle opening sensor, knock sensor, etc. are A / D converted by the A / D conversion IC 7, and the crank angle sensor, engine rotation sensor The digital signal output from the above is input to the microcomputer 12 via the input processing circuit 8.
[0060]
Further, the microcomputer 12 calculates an optimum control value based on these input signals, drives various actuators such as a solenoid and a motor, turns on a lamp, The ECU is controlled. Data exchange between the microcomputer 12 and the A / D conversion IC 7 is serial communication via the serial communication line L, and DMA communication is performed to reduce the load on the CPU 13.
[0061]
The sensor signal that performs A / D conversion processing is periodically A / D conversion processed every predetermined time (for example, 4 milliseconds), such as water temperature, intake air amount, oil temperature (for example, 20 ch in total). There are those in which A / D conversion processing is performed in synchronization with engine rotation, such as a knock signal. In other words, the A / D conversion processing here includes time synchronization A / D conversion processing and non-time synchronization A / D conversion processing such as engine rotation synchronization A / D conversion processing.
[0062]
Next, regarding the processing operations performed by the CPU 13, the DMAC 16, and the A / D conversion IC 7 in the engine control ECU 11 in which the engine control apparatus according to the embodiment (1) is adopted, the flowcharts shown in FIGS. It demonstrates based on the timing chart shown in FIGS. Here, a case will be described in which A / D conversion processing is performed every predetermined time and a signal consisting of 20 channels in total is divided into two groups, a first half group and a second half group.
[0063]
FIG. 5 shows a case where processing requests do not overlap, and FIG. 6 shows a case where it is time to request processing of non-time synchronization data when processing time synchronization data belonging to the first half group. Show. FIG. 7 shows a case where it is time to request processing of non-time synchronized data while processing time synchronized data belonging to the latter half group. FIG. 8 shows processing of non-time synchronized data. It shows a case where it is time to request processing of time synchronization data.
[0064]
First, processing operations relating to time synchronization data performed in synchronization with time will be described with reference to the flowchart shown in FIG. Every 4 milliseconds, the address De of the RAM 14₀ ~ De_{twenty one}Then, transmission data to be transmitted from the DMAC 16 to the A / D conversion IC 7 via the serial communication line L is set as a transmission table Tc (see FIG. 9) (step S1).
[0065]
When the setting is completed, a flag F1 indicating that processing of time synchronization data belonging to the first half group has been requested._EXE , A flag F2 indicating that processing of time synchronization data belonging to the latter half group has been requested_EXE , And a flag F3 indicating that processing of non-time synchronous data is requested_EXE Are both 0, that is, whether the DMAC 16 is not processing time-synchronized data or non-time-synchronized data (step S2).
[0066]
Flag F1_EXE , F2_EXE , F3_EXE Are both 0, that is, if the DMAC 16 determines that neither the time synchronization data nor the non-time synchronization data is being processed, the DMAC 16 can be requested to process the time synchronization data. , The start address De of the memory in which the transmission table Tc is set₀ Are written in the address register in the DMAC 16 and the number of data 10 is written in the counter in the DMAC 16 (step S3).
[0067]
Further, A / D conversion processing is performed by the A / D conversion IC 7, and the data subjected to the A / D conversion processing is transmitted to the DMAC 16. When this data is received by the DMAC 16, the data is transferred to a predetermined memory. Since it is necessary, the start address Df of the transfer destination table Ty (RAM 14)₀ Are written into the address register inside the DMAC 16 and the number of data 10 is written into the counter inside the DMAC 16 (step S4).
[0068]
When these writings are completed, an operation start command is transmitted to the DMAC 16 (step S5), and then a flag F1 indicating that processing of time synchronization data belonging to the first half group is requested._EXE 1 (step S6), and a flag F2 indicating that the processing request for the time synchronization data belonging to the latter half group is in a standby state_req Is set to 1 (step S8).
[0069]
By the way, when the DMAC 16 receives the operation start command from the CPU 13, the address De₀ The data stored in order (ie, data in the transmission table Tc) is transmitted to the A / D conversion IC 7 via the serial communication line L (step J1).
[0070]
When the A / D conversion IC 7 receives the data from the DMAC 16 (that is, the data including the A / D conversion processing start command and the channel of the signal to be A / D converted), the A / D conversion IC 7 receives the A / D of the corresponding sensor signal. D conversion processing is performed (step K1), and the A / D conversion processing data is transmitted to the DMAC 16 via the serial communication line L (step K2).
[0071]
When the DMAC 16 receives the data subjected to the A / D conversion processing transmitted from the A / D conversion IC 7, the DMAC 16 stores the data in the address Df.₀ Are sequentially written in the transfer destination table Ty (step J2). When these processes are completed once, the address signal is incremented by 1 and continues until reception of 10 data is completed. When reception of 10 data is completed, an interruption is made to notify the CPU 13 that the process has been completed. (Step J3).
[0072]
On the other hand, in the determination process in step S2, the CPU 13 determines the flag F1._EXE , F2_EXE , F3_EXE Is one, that is, if the DMAC 16 determines that time-synchronized data or non-time-synchronized data is being processed, the DMAC 16 cannot be requested to process time-synchronized data at this time. Therefore, the flag F1 indicating that the processing request for the time synchronization data belonging to the first half group is in a standby state._req 1 (step S7), and a flag F2 indicating that the processing request for the time synchronization data belonging to the latter half group is in a standby state_req Is set to 1 (step S8).
[0073]
Next, processing operations relating to non-time synchronization data (knock signal) performed in synchronization with engine rotation will be described based on the flowchart shown in FIG. In synchronization with the engine rotation, transmission data to be transmitted from the DMAC 16 to the A / D conversion IC 7 via the serial communication line L is set in the address Dg of the RAM 14 (step S11).
[0074]
When the setting is completed, a flag F1 indicating that processing of time synchronization data belonging to the first half group has been requested._EXE , A flag F2 indicating that processing of time synchronization data belonging to the latter half group has been requested_EXE , And a flag F3 indicating that processing of non-time synchronous data is requested_EXE Are both 0, that is, whether the DMAC 16 is not processing time-synchronized data or non-time-synchronized data (step S12).
[0075]
Flag F1_EXE , F2_EXE , F3_EXE Are both 0, that is, if the DMAC 16 determines that neither the time synchronization data nor the non-time synchronization data is being processed, the DMAC 16 can be requested to process the time synchronization data. Then, the address Dg of the memory in which the transmission data is set is written into the address register inside the DMAC 16 and the number of data 1 is written into the counter inside the DMAC 16 (step S13).
[0076]
Further, A / D conversion processing is performed by the A / D conversion IC 7, and the data subjected to the A / D conversion processing is transmitted to the DMAC 16. When this data is received by the DMAC 16, the data is transferred to a predetermined memory. Since it is necessary, the address Dh of the transfer destination table Tz (RAM 14) is written into the address register inside the DMAC 16, and the number of data 1 is written into the counter inside the DMAC 16 (step S14).
[0077]
When these writings are completed, an operation start command is transmitted to the DMAC 16 (step S15), and then a flag F3 indicating that processing of non-time synchronous data is requested._EXE Is set to 1 (step S16).
[0078]
By the way, when the DMAC 16 receives the operation start command from the CPU 13, the DMAC 16 transmits the data stored in the address Dg to the A / D conversion IC 7 via the serial communication line L (step J7).
[0079]
When the A / D conversion IC 7 receives data from the DMAC 16 (that is, data including the A / D conversion processing start command and the channel of the knock signal to be A / D converted), the corresponding sensor signal (knock) is received. Signal) is A / D converted (step K5), and the A / D converted data is transmitted to the DMAC 16 via the serial communication line L (step K6).
[0080]
When the DMAC 16 receives the data subjected to A / D conversion processing transmitted from the A / D conversion IC 7, the DMAC 16 writes the data to the address Dh of the transfer destination table Tz (step J 8). Therefore, the CPU 13 is interrupted to notify the CPU 13 that the processing has been completed (step J9).
[0081]
On the other hand, in the determination process in step S12, the CPU 13 determines that the flag F1_EXE , F2_EXE , F3_EXE Is determined to be 1, that is, if the DMAC 16 determines that the time synchronization data or the non-time synchronization data is being processed, the DMAC 16 may be requested to process the non-time synchronization data at this time. Flag F3 indicating that the non-time synchronous data processing request is in a standby state._req Is set to 1 (step S17).
[0082]
Next, the processing operation of the CPU 13 performed in synchronization with the interrupt processing upon completion of communication of the DMAC 16 will be described based on the flowchart shown in FIG. If there is an interrupt process from the DMAC 16, the flag F3_EXE Is determined to be 1 (step S21), flag F3_EXE 1 is completed, the completion of the communication of the DMAC 16 means the completion of the processing of the non-time synchronous data, and the non-time synchronous data (for example, a knock signal) transferred to the address Dh and subjected to the A / D conversion process. ) Can be performed, this process is set to the ready state (the process is in a process executable state and executed according to the processing priority in the CPU 13) (step S24), and then the flag F3_EXE Is set to 0 (step S25), and the process proceeds to step S29.
[0083]
In the determination process in step S21, the flag F3_EXE If it is determined that is not 1, the flag F2_EXE Is determined to be 1 (step S22), the flag F2_EXE If it is determined that 1 is 1, the completion of communication of the DMAC 16 means the completion of the processing of the time synchronization data belonging to the latter half group, and the address Df₀ ~ Df₁₉It is possible to perform a predetermined process using the A / D conversion-processed time synchronization data transferred to, so that this process is set to a ready state (a process executable state, and depending on the processing priority in the CPU 13 (Step S26), and then the flag F2_EXE Is set to 0 (step S27), and the process proceeds to step S29.
[0084]
In the determination process in step S22, the flag F2_EXE If it is determined that is not 1, the flag F1_EXE Is determined to be 1 (step S23), the flag F1_EXE If it is determined that 1 is 1, the completion of communication of the DMAC 16 means the completion of the processing of the time synchronization data belonging to the first half group, so the flag F1_EXE Is set to 0 (step S28), and the process proceeds to step S29. On the other hand, flag F1_EXE If it is determined that is not 1, the process proceeds to step S29.
[0085]
In step S29, a flag F1 indicating that the processing request for the time synchronization data belonging to the first half group is in a standby state._req The flag F2 indicating that the processing request for the time synchronization data belonging to the latter half group is in a standby state_req , And a flag F3 indicating that the non-time synchronous data processing request is in a standby state_req Is determined to be 0 or not.
[0086]
Flag F1_req , F2_req , F3_req Is 0, that is, if it is determined that neither the time-synchronized data processing request nor the non-time-synchronized data processing request is in the standby state, there is no need to perform any processing on the DMAC 16. The processing operation is finished as it is.
[0087]
On the other hand, flag F1_req , F2_req , F3_req Is determined to be 1, first, the flag F3_req Is determined to be 1 (step S30), and the flag F3_req If it is determined that the non-time synchronous data processing request is in a standby state, the memory address Dg in which the transmission data is set is transferred to the internal address register of the DMAC 16 and the number of data 1 is set. Write to the internal counter of the DMAC 16 (step S33).
[0088]
Further, A / D conversion processing is performed by the A / D conversion IC 7, and the data subjected to the A / D conversion processing is transmitted to the DMAC 16. When this data is received by the DMAC 16, the data is transferred to a predetermined memory. Since it is necessary, the address Dh of the transfer destination table Tz (RAM 14) is written into the address register inside the DMAC 16, and the number of data 1 is written into the counter inside the DMAC 16 (step S34).
[0089]
When these writings are completed, an operation start command is transmitted to the DMAC 16 (step S35), and then a flag F3 indicating that processing of non-time synchronous data is requested._EXE Is set to 1 (step S36), and the flag F3 is set._req Is set to 0 (step S37).
[0090]
By the way, when the DMAC 16 receives the operation start command from the CPU 13, the DMAC 16 transmits the data stored in the address Dg to the A / D conversion IC 7 via the serial communication line L (step J7).
[0091]
When the A / D conversion IC 7 receives data from the DMAC 16 (that is, data including the A / D conversion processing start command and the channel of the knock signal to be A / D converted), the corresponding sensor signal (knock) is received. Signal) is A / D converted (step K5), and the A / D converted data is transmitted to the DMAC 16 via the serial communication line L (step K6).
[0092]
When the DMAC 16 receives the data subjected to A / D conversion processing transmitted from the A / D conversion IC 7, the DMAC 16 writes the data to the address Dh of the transfer destination table Tz (step J 8). Therefore, the CPU 13 is interrupted to notify the CPU 13 that the processing has been completed (step J9).
[0093]
On the other hand, in the determination process in step S30, the CPU 13 determines that the flag F3_req If it is determined that is not 1, the flag F1_req Is determined to be 1 (step S31), and the flag F1_req If it is determined that 1 is 1, the processing request for the time synchronization data belonging to the first half group is in a standby state, and therefore the start address De of the memory in which the transmission table Tc is set₀ Are written in the address register in the DMAC 16 and the data number 10 is written in the counter in the DMAC 16 (step S38).
[0094]
Further, A / D conversion processing is performed by the A / D conversion IC 7, and the data subjected to the A / D conversion processing is transmitted to the DMAC 16. When this data is received by the DMAC 16, the data is transferred to a predetermined memory. Since it is necessary, the start address Df of the transfer destination table Ty (RAM 14)₀ Are written in the address register in the DMAC 16 and the number of data 10 is written in the counter in the DMAC 16 (step S39).
[0095]
When these writings are completed, an operation start command is transmitted to the DMAC 16 (step S40), and then a flag F1 indicating that processing of time synchronization data belonging to the first half group is requested._EXE 1 (step S41) and flag F1_req Is set to 0 (step S42).
[0096]
By the way, when the DMAC 16 receives the operation start command from the CPU 13, the address De₀ The data stored in order (ie, data in the transmission table Tc) is transmitted to the A / D conversion IC 7 via the serial communication line L (step J1).
[0097]
When the A / D conversion IC 7 receives the data from the DMAC 16 (that is, the data including the A / D conversion processing start command and the channel of the signal to be A / D converted), the A / D conversion IC 7 receives the A / D of the corresponding sensor signal. D conversion processing is performed (step K1), and the A / D conversion processing data is transmitted to the DMAC 16 via the serial communication line L (step K2).
[0098]
When the DMAC 16 receives the data subjected to the A / D conversion processing transmitted from the A / D conversion IC 7, the DMAC 16 stores the data in the address Df.₀ Are sequentially written in the transfer destination table Ty (step J2). When these processes are completed once, the address signal is incremented by 1 and continues until reception of 10 data is completed. When reception of 10 data is completed, an interruption is made to notify the CPU 13 that the process has been completed. (Step J3).
[0099]
On the other hand, in the determination process in step S31, the CPU 13 determines the flag F1._req If it is determined that is not 1, the flag F2_req Is determined to be 1 (step S32), the flag F2_req If it is determined that 1 is 1, the processing request for the time synchronization data belonging to the latter half group is in a standby state, and therefore the start address De of the memory in which the transmission table Tc is set.₀ Address De advanced 11 from₁₁Are written into the address register inside the DMAC 16 and the number of data 10 is written into the counter inside the DMAC 16 (step S43).
[0100]
Further, A / D conversion processing is performed by the A / D conversion IC 7, and the data subjected to the A / D conversion processing is transmitted to the DMAC 16. When this data is received by the DMAC 16, the data is transferred to a predetermined memory. Since it is necessary, the start address Df of the transfer destination table Ty (RAM 14)₀ Address Df advanced 10 from_TenAre written in the address register in the DMAC 16 and the data number 10 is written in the counter in the DMAC 16 (step S44).
[0101]
When these writings are completed, an operation start command is transmitted to the DMAC 16 (step S45), and then a flag F2 indicating that processing of time synchronization data belonging to the latter half group is requested._EXE 1 (step S46) and flag F2_req Is set to 0 (step S47).
[0102]
By the way, when the DMAC 16 receives the operation start command from the CPU 13, the address De₁₁The data stored in order (ie, data in the transmission table Tc) is transmitted to the A / D conversion IC 7 via the serial communication line L (step J4).
[0103]
When the A / D conversion IC 7 receives the data from the DMAC 16 (that is, the data including the A / D conversion processing start command and the channel of the signal to be A / D converted), the A / D conversion IC 7 receives the A / D of the corresponding sensor signal. D conversion processing is performed (step K3), and the A / D conversion processing data is transmitted to the DMAC 16 via the serial communication line L (step K4).
[0104]
When the DMAC 16 receives the data subjected to the A / D conversion processing transmitted from the A / D conversion IC 7, the DMAC 16 stores the data in the address Df._TenAre sequentially written in the transfer destination table Ty (step J5). When these processes are completed once, the address signal is incremented by 1 and continues until reception of 10 data is completed. When reception of 10 data is completed, an interruption is made to notify the CPU 13 that the process has been completed. (Step J6).
[0105]
According to the engine control apparatus according to the embodiment (1), the time synchronization data is divided into two groups, and processing of the time synchronization data is requested for each group. Since a period during which the DMA control means does not occupy the serial communication line L can be created between the processes of the time synchronization data, it is possible to interrupt the processing of non-time synchronization data during this period. . Therefore, it is possible to prevent a delay in processing performed without synchronizing with time, such as engine rotation synchronization A / D conversion processing.
[0106]
Further, when performing predetermined processing using these data after the A / D conversion processing, the first half group and the second half group are combined at a time as shown in FIG. 4 (see step S26). ), The processing load on the CPU can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram schematically showing a main part of an engine control ECU in which an engine control apparatus according to an embodiment (1) of the present invention is employed.
[Figure 2]
FIG. 4 is a flowchart showing processing operations performed by a CPU in an engine control ECU employing the engine control apparatus according to the embodiment (1).
[Figure 5]
FIG. 8 is a timing chart showing processing operations performed by a CPU, a DMAC, and an A / D conversion IC in an engine control ECU employing the engine control apparatus according to the embodiment (1).
FIG. 9 is a diagram showing a transmission table that summarizes transmission data written in a RAM and transmitted from the DMAC to the A / D conversion IC via the serial communication line.
FIG. 10 is a block diagram schematically showing a main part of an engine control ECU in which a conventional engine control device is employed.
FIG.
FIG. 12 is an explanatory diagram for explaining that the start timings of the time-synchronized A / D conversion process and the non-time-synchronized A / D conversion process overlap.
FIG. 13 is a flowchart showing processing operations performed by a CPU, a DMAC, and an A / D conversion IC in an engine control ECU employing a conventional engine control device.
FIG. 14 is a timing chart showing processing operations performed by a CPU, a DMAC, and an A / D conversion IC in an engine control ECU employing a conventional engine control device.
FIGS. 15A and 15B are diagrams showing a transmission table in which transmission data written in a RAM and transmitted from the DMAC to the A / D conversion IC via the serial communication line is collected. .
FIG. 16 is an explanatory diagram for explaining data exchange between a DMAC and an A / D conversion IC;
[Explanation of symbols]
7 A / D conversion IC
11 ECU
12 Microcomputer
13 CPU
14 RAM
15 ROM
16 DMAC

Claims (10)

There are at least two types of time synchronization data that need to be processed in synchronization with time,
There is at least one type of non-time synchronization data that needs to be processed at a predetermined timing without being synchronized with time,
These processes are performed using the DMA control means.
When the processing performed by the DMA control means includes transmission of data requesting A / D conversion processing to the A / D conversion means and reception of data A / D converted by the A / D conversion means In the DMA communication control method of
The time synchronization data is divided into n (≧ 2) groups,
A first data processing requesting step for requesting the DMA control means to process the time synchronous data belonging to the first group in synchronization with time;
When the processing of the time synchronization data belonging to the kth (1 ≦ k ≦ n−1) th group is completed, the second requesting the DMA control means to process the time synchronization data belonging to the k + 1th group. Data processing request steps of
A first non-time-synchronized data processing requesting step for requesting the DMA control means to process the non-time-synchronized data in synchronization with a predetermined timing instead of time,
When the DMA control means is processing the time synchronization data belonging to the k-th group, if it is not time to request the processing of the non-time synchronization data,
In order to continuously perform the processing of the time synchronization data belonging to the kth group and the processing of the time synchronization data belonging to the k + 1th group,
Without completing the processing of the time synchronization data belonging to the kth group,
Request the DMA control means to process the time synchronization data belonging to the (k + 1) th group;
On the other hand, when the DMA control means is processing the time-synchronized data belonging to the kth group, and when it is time to request the non-time-synchronized data,
When the processing of the time synchronization data belonging to the kth group is finished,
Rather than requesting the DMA control means to process the time-synchronized data belonging to the (k + 1) th group, it requests the non-time-synchronized data to be processed,
A DMA communication control method characterized in that the first non-time synchronous data processing request step is prioritized over the second data processing request step. If the DMA control means is not requested to process the time synchronization data belonging to the (k + 1) th group after completion of the processing of the time synchronization data belonging to the kth group,
When the processing of the non-time synchronized data ends,
Wherein the DMA controller, the 3 DMA communication control method according to claim 1, characterized in that it comprises a data processing requesting step of requesting the time processing of the synchronous data belonging to the (k + 1) th group. When the DMA control means is processing the time synchronization data belonging to the nth group, and when it is time to request the processing of the non-time synchronization data,
When the processing of the time synchronization data belonging to the nth group is finished,
3. The DMA communication control method according to claim 1, further comprising a second non-time synchronous data processing requesting step for requesting the DMA control means to process the non-time synchronous data. When it is time to request the processing of the time synchronization data belonging to the first group when the DMA control means is processing the non-time synchronization data,
When the processing of the non-time synchronized data ends,
It said DMA control means, according to any one of claims 1-3, characterized in that it contains a fourth data processing request step of requesting processing of the time alignment data belonging to the first group DMA communication control method. First transmission data storage for storing transmission data to be transmitted from the DMA control means to the other party that performs serial communication with the DMA control means for at least one group as a transmission table and stored in a predetermined location DMA communication control method according to any one of claims 1-4, characterized in that it contains the step. Second transmission data storage for storing transmission data to be transmitted from the DMA control means to the other party that performs serial communication with the DMA control means for at least two groups as a transmission table and stored in a predetermined location DMA communication control method according to any one of claims 1-5, characterized in that it contains the step. The transmission table, according to claim 5 or claim 6 DMA communication control method wherein a said those constructed in accordance with the priority of the time synchronization data. A transfer data processing method for processing data transferred using the DMA communication control method according to any one of claims 1 to 7 ,
A transfer data processing method comprising a transfer data processing step for performing predetermined processing using the transferred data collectively for at least two groups. Transmission processing for transmitting processing request data for A / D conversion processing to the A / D conversion processing means, and reception processing for receiving A / D conversion data subjected to A / D conversion processing by the A / D conversion processing means In the DMA communication control device having the main control means for performing the above using the DMA control means,
At least two types of time-synchronized data that needs to be processed in synchronization with time and at least non-time-synchronized data that needs to be processed in synchronization with the engine speed are included in data to be A / D converted. 1 type is included,
The DMA control means comprises:
When receiving a command from the main control means to transmit the processing request data of the A / D conversion processing, the transmission processing and the reception processing are performed.
The main control means is
The DMA control means transmits the processing request data for requesting A / D conversion processing in synchronization with the time to the first group of the time-synchronized data divided into two groups. First data processing requesting means for commanding;
When the transmission process and the reception process for the first group are completed, the A / D conversion process request is made to the second group different from the first group in the time synchronization data. Second data processing request means for instructing the DMA control means to transmit processing request data;
Non-time synchronous data processing requesting means for instructing the DMA control means to transmit processing request data for requesting A / D conversion processing in synchronization with the engine speed for the non-time synchronous data. ,
When the DMA control means is processing the time synchronization data belonging to the first group, and the timing for requesting the processing of the non-time synchronization data is not reached,
In order to continuously perform the processing of the time synchronization data belonging to the first group and the processing of the time synchronization data belonging to the second group,
Without stopping after processing of the time synchronization data belonging to the first group,
The DMA control means is instructed to transmit processing request data for requesting A / D conversion processing to the second group,
On the other hand, when the DMA control means is processing the time synchronization data belonging to the first group, and when it is time to request the processing of the non-time synchronization data,
When the processing of the time synchronization data belonging to the first group is finished,
The DMA control means is instructed to transmit processing request data for requesting A / D conversion processing for the non-time synchronous data,
A DMA communication control apparatus configured to give priority to the processing by the non-time synchronous data processing request means over the processing by the second data processing request means. Transmission processing for transmitting processing request data for A / D conversion processing to the A / D conversion processing means, and reception processing for receiving A / D conversion data subjected to A / D conversion processing by the A / D conversion processing means In an engine control device provided with main control means for performing the above using DMA control means,
At least two types of time-synchronized data that needs to be processed in synchronization with time and at least non-time-synchronized data that needs to be processed in synchronization with the engine speed are included in data to be A / D converted. 1 type is included,
The DMA control means comprises:
When receiving a command from the main control means to transmit the processing request data of the A / D conversion processing, the transmission processing and the reception processing are performed.
The main control means is
The DMA control means transmits the processing request data for requesting A / D conversion processing in synchronization with the time to the first group of the time-synchronized data divided into two groups. First data processing requesting means for commanding;
When the transmission process and the reception process for the first group are completed, the A / D conversion process request is made to the second group different from the first group in the time synchronization data. Second data processing request means for instructing the DMA control means to transmit processing request data;
Non-time synchronous data processing requesting means for instructing the DMA control means to transmit processing request data for requesting A / D conversion processing in synchronization with the engine speed for the non-time synchronous data. ,
When the DMA control means is processing the time synchronization data belonging to the first group, and the timing for requesting the processing of the non-time synchronization data is not reached,
In order to continuously perform the processing of the time synchronization data belonging to the first group and the processing of the time synchronization data belonging to the second group,
Without stopping after processing of the time synchronization data belonging to the first group,
The DMA control means is instructed to transmit processing request data for requesting A / D conversion processing to the second group,
On the other hand, when the DMA control means is processing the time synchronization data belonging to the first group, and when it is time to request the processing of the non-time synchronization data,
When the processing of the time synchronization data belonging to the first group is finished,
The DMA control means is instructed to transmit processing request data for requesting A / D conversion processing for the non-time synchronous data,
An engine control device configured to prioritize processing by the non-time-synchronized data processing requesting unit over processing by the second data processing requesting unit.

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