JP3906438B2

JP3906438B2 - Overcurrent overvoltage protection circuit

Info

Publication number: JP3906438B2
Application number: JP15158697A
Authority: JP
Inventors: 昌也圓尾
Original assignee: 昌也圓尾
Priority date: 1997-05-26
Filing date: 1997-05-26
Publication date: 2007-04-18
Anticipated expiration: 2017-05-26
Also published as: JPH10336888A

Description

【０００１】
【産業上の利用分野】
本発明は、負荷である回路を、雷等のサージの過電流、過電圧から保護する過電流過電圧保護回路に関する。
【０００２】
【従来の技術】
従来のサージ保護は、電気の入力線とアースの間（プラス線とマイナス線の間）に、サージアブソーバを接続して、過電流、過電圧をアースに逃がすようにしている。
【０００３】
【発明が解決しようとする課題】
サージアブソーバが、通電（機能）して、サージの過電流、過電圧をアースに逃がすためには、電気の入力線の電圧が、定格電圧の２倍、あるいは、それ以上の電圧にならなければならない。そのために、負荷回路には、サージが流れる間、定格電圧の２倍以上の過電圧が印加され、定格電流の２倍以上の過電流が流れる。従って、負荷回路は、定格の２倍以上の過電圧、過電流によって、壊れるか、または、大きなダメージを受けるという問題点があった。
【０００４】
また、本発明者は、以前、エンハンスメント形絶縁ゲート形半導体（ＭＯＳ）のドレインとゲートの間に過電流遮断回路を接続し、そのＭＯＳのソースにコイルを接続し、そのコイルのソースと接続していない側の端とそのＭＯＳのゲートを抵抗で接続することによって、ラッシュカレントを定常電流の１．５倍程度に抑えて流し、ラッシュカレント状態が終わった後、定常電流を流す過電流保護装置を提出しているが、その保護装置は、過電流を抑えることは出来るが、過電圧を遮断することが出来ないという問題点があった。
【０００５】
本発明は、電気の入力線に、過電流、過電圧が発生すると、その過電流、過電圧を感知して、その過電流、過電圧が、負荷回路に流れる前に、その過電流、過電圧を遮断して、負荷回路を保護する過電流過電圧保護回路を提供することを目的とする。
【０００６】
【課題を解決するための手段】
上記の目的を達成するために、本発明の過電流過電圧保護回路は、第１のＰ型エンハンスメント形絶縁ゲート形半導体（ＭＯＳ）のソースに第１のインダクタ（コイル）を接続し、ゲートに第２のＰ型ＭＯＳのドレインを接続し、第２のＰ型ＭＯＳのソースを、第１のインダクタの第１のＰ型ＭＯＳのソースと接続していない側の端に接続し、その第１のインダクタと磁気相互結合した第２のインダクタと第１の抵抗を直列に、第２のＰ型ＭＯＳのゲートとソースの間に接続し、そして、第１のＰ型ＭＯＳのゲートは、第１のゲート電圧供給箇所に第２の抵抗で接続し、第２のＰ型ＭＯＳのゲートは、第２のゲート電圧供給箇所に第３の抵抗で接続したものである。
【０００７】
【作用】
上記のように構成された過電流過電圧保護回路は、雷等によるサージによって、急に過電流が流れようとすると、第１のインダクタの両端に電圧が発生し、同時に、磁気相互結合（磁気誘導）により、第２のインダクタの両端にも電圧が発生する。その第２のインダクタに発生する電圧により、第２のＰ型ＭＯＳのゲート電圧が、そのＭＯＳのシュレッショルド電圧より大きくなると、第２のＰ型ＭＯＳは導通し、第１のＭＯＳのゲートとソースを短絡し、第１のＰ型ＭＯＳのゲートは、そのソース電圧と同じになり、第１のＰ型ＭＯＳは不導通になり、過電流、過電圧が流れる前に、過電流、過電圧を遮断する。
【０００８】
【実施例】
本発明の過電流過電圧保護回路の実施例について、図１により説明する。
Ｐ型ＭＯＳ１のソースは、コイル３に接続し、コイル３のソースと接続していない側の端を端子Ａとし、Ｐ型ＭＯＳ１のドレインは、負荷回路に接続し、負荷回路のドレインと接続していない側の端を端子Ｂとし、Ｐ型ＭＯＳ１のゲートは、抵抗４に接続し、抵抗４のゲートと接続していない側の端をゲート端子Ｇとする。そして、Ｐ型ＭＯＳ２のソースは、端子Ａに接続し、ドレインは、Ｐ型ＭＯＳ１のゲートに接続し、Ｐ型ＭＯＳ２のソースとゲートの間に、コイル５と抵抗６を直列に接続し、コイル５と並列に抵抗８を接続する。コイル５は、コイル３と磁気相互結合している。また、Ｐ型ＭＯＳ２のゲートは、抵抗７に接続し、抵抗７のゲートと接続していない側の端を端子Ｂに接続する。
そして、端子Ａをプラス側、端子Ｂをマイナス側とする過電流過電圧保護回路である。
【０００９】
通常、磁気相互結合した２個のコイルは、図２のコイル23、25のように、２個のコイルを近づけて回路図に描くが、図１においては、回路図全体が分かり易いように、コイル３、５を離して描いているが、図２に示すコイル23、25と同じ意味を持つものである。
【００１０】
各部のはたらきを説明する。
端子Ａがプラス、端子Ｂがマイナスの定常電圧がかかり、そして、ゲート端子Ｇには、Ｐ型ＭＯＳ１のソースに対して、つまり、端子Ａに対してシュレッショルド電圧以上のゲート電圧がかかり、Ｐ型ＭＯＳ１が導通して定常電流が流れている時、急に、端子Ａがプラス、端子Ｂがマイナスの過電圧がかかり、過電流が流れようとすると、コイル３のインダクタンスが急激な電流変化を阻止して、コイル３の両端に一瞬ある大きさの電圧が発生する。端子ＡとＰ型ＭＯＳ１のゲートの間の電位差は同じであるが、Ｐ型ＭＯＳ１のソースとゲートの間の電位差（ゲート電圧）は、コイル３に発生した電圧により、その電圧の大きさだけ小さくなり、Ｐ型ＭＯＳ１は、過電流が流れようとするのを抑える。また、コイル３に電圧が発生すると同時に、磁気相互結合したコイル５には、磁気誘導によって巻き線数比に比例して大きな電圧を発生させることが出来る。そして、コイル５に発生したその大きな電圧によって、一瞬に、Ｐ型ＭＯＳ２のゲート電圧は、そのスレッショルド電圧以上になって、Ｐ型ＭＯＳ２は導通状態になる。それによって、Ｐ型ＭＯＳ１のゲート電圧は、端子Ａの電圧とほぼ同じになって、Ｐ型ＭＯＳ１は、不導通状態になり、過電圧、過電流を遮断することができる。
【００１１】
Ｐ型ＭＯＳ１が遮断した後、過電圧は、Ｐ型ＭＯＳ１の両端にかかると共に、直列に接続した抵抗６，７の両端にかかる。定格（正常）電圧の時、抵抗６における電圧降下が、Ｐ型ＭＯＳ２のスレッショルド電圧未満になるように、そして、定格電圧より少し大きい電圧の時、Ｐ型ＭＯＳ２のスレッショルド電圧以上になるように、抵抗６と抵抗７の抵抗値の割合（比）を選べば、コイル５に発生した電圧によって、Ｐ型ＭＯＳ２が導通し、Ｐ型ＭＯＳ１が遮断した後、コイル５に発生した電圧が減少しても、過電圧により抵抗６における電圧降下が大きくなって、Ｐ型ＭＯＳ２のゲート電圧は、そのスレッショルド電圧以上になるために、Ｐ型ＭＯＳ２は導通状態にある。そして、過電圧が正常電圧近くに下がって、抵抗６における電圧降下が、Ｐ型ＭＯＳ２のスレッショルド電圧未満になるまで、Ｐ型ＭＯＳ２は導通状態を続ける。
【００１２】
これにより、Ｐ型ＭＯＳ１は、過電圧がかかり始める時から、過電圧が終わる時まで、不導通状態を続け、過電圧を完全に遮断することができ、そして、過電圧が終わった後、自動的に導通状態に復帰し、再び、定常電流を流すことができる。
【００１３】
また、図１の実施例のＰ型ＭＯＳ２をＰＮＰ形バイポーラトランジスタ（ＢｉＴＲ）に置き換えた実施例を、図３によって説明する。
図１の回路のＰ型ＭＯＳ２を取り除いて、ＢｉＴＲ22を接続する。図１の回路と同じで、重複する部分の説明は省きます。ＢｉＴＲ22のエミッタを端子Ａに接続し、抵抗６と抵抗７の接続箇所にベースを接続し、コレクタをＰ型ＭＯＳ１のゲートに接続する。そして、定格（正常）電圧の時、抵抗６における電圧降下が、ＢｉＴＲ22が導通する電圧より小さくなるように、そして、定格電圧より少し大きい電圧の時、ＢｉＴＲ22が導通する電圧より大きくなるように、抵抗６と抵抗７の抵抗値の割合（比）を選べば、図１の実施例の回路と同じように、コイル５に発生した電圧によって、Ｐ型ＭＯＳ１が遮断した後、コイル５に発生した電圧が減少しても、過電圧により抵抗６における電圧降下が大きくなって、ＢｉＴＲ22は導通状態にある。そして、過電圧が正常電圧近くに下がって、抵抗６における電圧降下が、ＢｉＴＲ22が導通する電圧より小さくなるまで、ＢｉＴＲ22は導通状態を続ける。
これにより、Ｐ型ＭＯＳ１は、過電圧がかかり始める時から、過電圧が終わる時まで、不導通状態を続け、過電圧を完全に遮断することができ、そして、過電圧が終わった後、自動的に導通状態に復帰し、再び、定常電流を流すことができる。
【００１４】
次に、図１の実施例にホトカプラを加えた実施例を、図４によって説明する。図１の回路と同じで、重複する部分の説明は省きます。Ｐ型ＭＯＳ２のドレインは、ホトカプラ15の発光ダイオード（ＬＥＤ）のアノードに接続し、そのＬＥＤのカソードは、抵抗16に接続し、抵抗16のカソードと接続していない側の端は、端子Ｂに接続する。ホトカプラ15の受光トランジスタのコレクターは、端子Ａに接続し、エミッタは、Ｐ型ＭＯＳ１のゲートに接続する。
【００１５】
この接続により、図１の回路と同じように、過電流が流れようとすると、コイル３に電圧が発生し、そして、コイル５に発生した電圧により、Ｐ型ＭＯＳ２は導通状態になり、Ｐ型ＭＯＳ２のドレイン電流が、ホトカプラ15のＬＥＤと抵抗16を流れ、端子Ｂに流れる。このドレイン電流により、ホトカプラ15のＬＥＤは発光し、受光トランシスタは導通状態になる。それによって、Ｐ型ＭＯＳ１のゲート電圧は、ほぼ端子Ａの電圧になって、Ｐ型ＭＯＳ１は、不導通状態になり、過電圧、過電流を遮断することができる。
【００１６】
その後、過電圧が正常電圧の近くまで下がって、Ｐ型ＭＯＳ２が不導通状態になると、ＬＥＤを流れる電流が止まり、受光トランジスタも不導通状態になり、そして、Ｐ型ＭＯＳ１は導通状態に戻り、再び、定常電流を流す。
これにより、Ｐ型ＭＯＳ１は、過電圧がかかり始める時から、過電圧が終わる時まで、不導通状態を続け、過電圧を完全に遮断することができ、そして、過電圧が終わった後、自動的に導通状態に復帰し、再び、定常電流を流すことができる。
【００１７】
次に、図１の実施例の端子ＡＢ間（負荷に並列）に、抵抗とコンデンサーを接続した実施例を、図５によって説明する。
図１の回路のＰ型ＭＯＳ１のソースに、抵抗９の一方の端を接続し、他方の端をコンデンサー10に接続し、コンデンサー10の抵抗９と接続していない側の端を端子Ｂに接続する。この実施例の回路の他の部分は、図１の回路と同じであるので、説明を省きます。
【００１８】
この回路に過電圧がかかり、過電流が流れようとすると、図１の実施例と同じように、コイル３に電圧が発生し、その発生した電圧の大きさだけＰ型ＭＯＳ１のゲート電圧が小さくなり、Ｐ型ＭＯＳ１は過電流を抑えるが、Ｐ型ＭＯＳ１のソースと端子Ｂの間に接続した抵抗９とコンデンサー10に電流が流れるために、コンデンサー10が飽和するまで、つまり、過電圧が最大の大きさになるまで、コイル３に過電流が流れ続ける。それによって、コイル３に、過電流が流れ始めた時の大きさ程ではないが、ある大きさの電圧が発生し続ける。そして、同時に、コイル５に巻き線数比に比例した大きさの電圧が発生し続ける。それにより、Ｐ型ＭＯＳ２のゲート電圧は、抵抗６における電圧降下にコイル５の電圧を加えた大きさになるために、Ｐ型ＭＯＳ２のゲート電圧が、抵抗６における電圧降下だけの大きさの場合に較べて、Ｐ型ＭＯＳ２は、より低抵抗の導通状態になり、Ｐ型ＭＯＳ１のゲート電圧を、端子Ａの電圧により速く近づけることができ、Ｐ型ＭＯＳ１をより速く不導通状態にして、過電流、過電圧をより速く遮断することができる。
【００１９】
次に、別の実施例を図６により説明する。図６の回路の部品で、図１の回路と同じ部品は、同じ番号を付ける。
Ｐ型ＭＯＳ１のソースは、コイル３に接続し、コイル３のソースと接続していない側の端を端子Ａとし、Ｐ型ＭＯＳ１のドレインは、負荷回路に接続し、負荷回路のドレインと接続していない側の端を端子Ｂとし、Ｐ型ＭＯＳ１のゲートは、抵抗24に接続し、抵抗24のゲートと接続していない側の端を端子Ｂに接続し、また、Ｐ型ＭＯＳ１のゲートは、ツェナーダイオードのアノードに接続し、ツェナーダイオードのカソードは、端子Ａに接続する。そして、Ｐ型ＭＯＳ２のソースは、端子Ａに接続し、ドレインは、Ｐ型ＭＯＳ１のゲートに接続し、Ｐ型ＭＯＳ２のソースとゲートの間に、コイル５と抵抗６を直列に接続し、ダイオード28のアノードを、コイル５と抵抗６の接続箇所に接続し、カソードを端子Ａに接続する。また、Ｐ型ＭＯＳ２のゲートは、抵抗７に接続し、抵抗７のゲートと接続していない側の端を端子Ｂに接続する。端子ＡＢ間に、コイル11と抵抗12とコンデンサー13を直列に接続する。コイル３、５、11は、同時に磁気相互結合しているコイルである。そして、端子Ａをプラス側、端子Ｂをマイナス側とする過電流過電圧保護回路である。
【００２０】
各部のはたらきを説明する。
ツェナーダイオード14のツェナー電圧をＰ型ＭＯＳ１のスレッショルド電圧より大きく設定すると、端子Ａがプラス、端子Ｂがマイナスの定常電圧がかかる時、Ｐ型ＭＯＳ１のゲート電圧が、スレッショルド電圧より大きくなり、Ｐ型ＭＯＳ１が導通して定常電流が流れる。
この接続により、図１の回路と同じように、過電圧がかかり、過電流が流れようとすると、コイル３に電圧が発生し、その発生した電圧の大きさだけＰ型ＭＯＳ１のゲート電圧が小さくなり、Ｐ型ＭＯＳ１は過電流を抑えるが、端子ＡＢ間に接続したコイル11と抵抗12とコンデンサー13に電流が流れるために、コンデンサー13が飽和するまで、つまり、過電圧が最大の大きさになるまで、コイル11に過電流が流れ続ける。それによって、コイル11に、ある大きさの電圧が発生し続ける。そして、同時に、コイル５に巻き線数比に比例した大きさの電圧が発生し続ける。それにより、Ｐ型ＭＯＳ２のゲート電圧は、抵抗６における電圧降下にコイル５の電圧を加えた大きさになるために、Ｐ型ＭＯＳ２のゲート電圧が、抵抗６における電圧降下だけの大きさの場合に較べて、Ｐ型ＭＯＳ２は、より低抵抗の導通状態になり、Ｐ型ＭＯＳ１のゲート電圧を、端子Ａの電圧により速く近づけることができ、Ｐ型ＭＯＳ１をより速く不導通状態にして、過電流、過電圧をより速く遮断することができる。
【００２１】
コイル３、５、11に、電流トランスを用いることもできる。
【００２２】
【発明の効果】
本発明は、以上に説明したように構成されているので、以下に記載するような効果を示す。コイル３とコイル５を磁気相互結合させることによって、主電流が流れるコイル３のインダクタンスを小さくして、発生する電圧を小さくしても、コイル５に巻き線数比に比例して大きな電圧を発生させて、Ｐ型ＭＯＳ２を導通させ、Ｐ型ＭＯＳ１を不導通状態にすることができ、また、コンデンサー10やコイル３、５と磁気相互結合したコイル11を接続することにより、主電流が流れるコイル３のインダクタンス、インピーダンスをさらに小さくしても、Ｐ型ＭＯＳ１を確実に不導通状態にすることができるので、小型のコイル３で過電流過電圧を遮断することができ、そして、定常電流が流れる時のコイル３における電圧降下（損失）も小さくすることができる。
【図面の簡単な説明】
【図１】本発明の過電流過電圧保護回路の実施例を示す回路図である。
【図２】磁気相互結合した２個のコイルの通常の描き方を示す図である。
【図３】本発明の過電流過電圧保護回路にバイポーラトランジスタを用いた実施例を示す回路図である。
【図４】本発明の過電流過電圧保護回路にホトカプラを用いた実施例を示す回路図である。
【図５】本発明の過電流過電圧保護回路に、負荷に並列に抵抗とコンデンサーを接続した実施例を示す回路図である。
【図６】本発明の過電流過電圧保護回路の３個のコイルを用いた実施例を示す回路図である。[0001]
[Industrial application fields]
The present invention relates to an overcurrent overvoltage protection circuit for protecting a circuit as a load from surge overcurrent and overvoltage such as lightning.
[0002]
[Prior art]
In the conventional surge protection, a surge absorber is connected between the electric input line and the ground (between the plus line and the minus line) so that overcurrent and overvoltage are released to the ground.
[0003]
[Problems to be solved by the invention]
In order for the surge absorber to energize (function) and release the surge overcurrent and overvoltage to ground, the voltage of the electrical input line must be twice or more than the rated voltage. . Therefore, an overvoltage more than twice the rated voltage is applied to the load circuit while a surge flows, and an overcurrent more than twice the rated current flows. Therefore, there is a problem that the load circuit is broken or is seriously damaged by overvoltage and overcurrent more than twice the rating.
[0004]
In addition, the present inventor previously connected an overcurrent cutoff circuit between the drain and gate of an enhancement type insulated gate semiconductor (MOS), connected a coil to the source of the MOS, and connected to the source of the coil. An overcurrent protection device that flows the rush current to about 1.5 times the steady current by connecting the non-side end and the MOS gate with a resistor, and flows the steady current after the rush current state ends However, the protection device has a problem that it can suppress the overcurrent but cannot cut off the overvoltage.
[0005]
In the present invention, when an overcurrent or overvoltage occurs in an electric input line, the overcurrent or overvoltage is sensed, and the overcurrent or overvoltage is cut off before the overcurrent or overvoltage flows into the load circuit. An object of the present invention is to provide an overcurrent overvoltage protection circuit for protecting a load circuit.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, an overcurrent overvoltage protection circuit according to the present invention has a first inductor (coil) connected to a source of a first P-type enhancement type insulated gate semiconductor (MOS), and a first to a gate. The drain of the second P-type MOS is connected, the source of the second P-type MOS is connected to the end of the first inductor that is not connected to the source of the first P-type MOS, and the first A second inductor magnetically coupled to the inductor and a first resistor are connected in series between the gate and source of the second P-type MOS, and the gate of the first P-type MOS is A gate resistor is connected to the gate voltage supply location with a second resistor, and the gate of the second P-type MOS is connected to the second gate voltage supply location with a third resistor.
[0007]
[Action]
In the overcurrent overvoltage protection circuit configured as described above, when an overcurrent suddenly flows due to a surge caused by lightning or the like, a voltage is generated at both ends of the first inductor, and at the same time, magnetic mutual coupling (magnetic induction) ) Also generates a voltage across the second inductor. When the gate voltage of the second P-type MOS becomes larger than the threshold voltage of the MOS due to the voltage generated in the second inductor, the second P-type MOS becomes conductive, and the gate and source of the first MOS , The gate of the first P-type MOS becomes the same as its source voltage, the first P-type MOS becomes non-conductive, and the overcurrent and overvoltage are cut off before the overcurrent and overvoltage flow. .
[0008]
【Example】
An embodiment of the overcurrent overvoltage protection circuit of the present invention will be described with reference to FIG.
The source of the P-type MOS 1 is connected to the coil 3 and the end of the side not connected to the source of the coil 3 is a terminal A. The drain of the P-type MOS 1 is connected to the load circuit and is connected to the drain of the load circuit. The end of the side not connected is a terminal B, the gate of the P-type MOS 1 is connected to the resistor 4, and the end not connected to the gate of the resistor 4 is a gate terminal G. The source of the P-type MOS 2 is connected to the terminal A, the drain is connected to the gate of the P-type MOS 1, the coil 5 and the resistor 6 are connected in series between the source and the gate of the P-type MOS 2, and the coil A resistor 8 is connected in parallel with 5. The coil 5 is magnetically coupled to the coil 3. The gate of the P-type MOS 2 is connected to the resistor 7 and the end of the resistor 7 not connected to the gate is connected to the terminal B.
And it is an overcurrent overvoltage protection circuit with terminal A as the positive side and terminal B as the negative side.
[0009]
Normally, two magnetically coupled coils are drawn on a circuit diagram by bringing the two coils close to each other like the coils 23 and 25 in FIG. 2, but in FIG. 1, the entire circuit diagram is easy to understand. Although the coils 3 and 5 are drawn apart from each other, they have the same meaning as the coils 23 and 25 shown in FIG.
[0010]
The function of each part is explained.
The terminal A is positive and the terminal B is negative, and the gate terminal G is applied to the source of the P-type MOS 1, that is, the gate voltage higher than the threshold voltage to the terminal A, P When the type MOS1 is conducting and a steady current is flowing, suddenly an overvoltage is applied to the terminal A and the terminal B is negative, and if the overcurrent is about to flow, the inductance of the coil 3 prevents an abrupt current change. Thus, a voltage of a certain magnitude is generated at both ends of the coil 3 for a moment. Although the potential difference between the terminal A and the gate of the P-type MOS 1 is the same, the potential difference (gate voltage) between the source and the gate of the P-type MOS 1 is reduced by the magnitude of the voltage due to the voltage generated in the coil 3. Thus, the P-type MOS 1 suppresses an overcurrent from flowing. Further, at the same time as the voltage is generated in the coil 3, the magnetically coupled coil 5 can generate a large voltage in proportion to the winding number ratio by magnetic induction. Due to the large voltage generated in the coil 5, the gate voltage of the P-type MOS 2 instantaneously becomes equal to or higher than the threshold voltage, and the P-type MOS 2 becomes conductive. As a result, the gate voltage of the P-type MOS 1 becomes substantially the same as the voltage at the terminal A, and the P-type MOS 1 becomes non-conductive and can block overvoltage and overcurrent.
[0011]
After the P-type MOS 1 is cut off, the overvoltage is applied to both ends of the P-type MOS 1 and to both ends of the resistors 6 and 7 connected in series. When the rated (normal) voltage is reached, the voltage drop across the resistor 6 is less than the threshold voltage of the P-type MOS 2, and when the voltage is slightly higher than the rated voltage, it is greater than or equal to the threshold voltage of the P-type MOS 2. If the ratio (ratio) of the resistance values of the resistors 6 and 7 is selected, the voltage generated in the coil 5 decreases after the P-type MOS 2 is turned on and the P-type MOS 1 is cut off by the voltage generated in the coil 5. However, since the voltage drop in the resistor 6 becomes large due to the overvoltage, and the gate voltage of the P-type MOS 2 becomes equal to or higher than the threshold voltage, the P-type MOS 2 is in a conductive state. Then, the P-type MOS 2 continues to be in a conductive state until the overvoltage drops near the normal voltage and the voltage drop across the resistor 6 becomes less than the threshold voltage of the P-type MOS 2.
[0012]
As a result, the P-type MOS 1 can continue to be in a non-conductive state from when the overvoltage starts to be applied until the overvoltage ends, and can completely shut off the overvoltage. The steady current can be flowed again.
[0013]
An embodiment in which the P-type MOS 2 in the embodiment of FIG. 1 is replaced with a PNP-type bipolar transistor (BiTR) will be described with reference to FIG.
The P-type MOS 2 in the circuit of FIG. 1 is removed and the BiTR 22 is connected. It is the same as the circuit in Fig. 1, and the explanation of the overlapping part is omitted. The emitter of BiTR22 is connected to terminal A, the base is connected to the connection point of resistors 6 and 7, and the collector is connected to the gate of P-type MOS1. When the voltage is rated (normal), the voltage drop across the resistor 6 is smaller than the voltage at which BiTR22 is conducted, and when the voltage is slightly higher than the rated voltage, the voltage drop is larger than the voltage at which BiTR22 is conducted. If the ratio (ratio) of the resistance values of the resistors 6 and 7 is selected, the P-type MOS 1 is cut off by the voltage generated in the coil 5 and then generated in the coil 5 as in the circuit of the embodiment of FIG. Even if the voltage decreases, the voltage drop across the resistor 6 increases due to overvoltage, and BiTR22 is in a conducting state. Then, BiTR22 continues to be in a conductive state until the overvoltage drops near the normal voltage and the voltage drop across resistor 6 becomes smaller than the voltage at which BiTR22 conducts.
As a result, the P-type MOS 1 can continue to be in a non-conductive state from when the overvoltage starts to be applied until the overvoltage ends, and can completely shut off the overvoltage. The steady current can be flowed again.
[0014]
Next, an embodiment in which a photocoupler is added to the embodiment of FIG. 1 will be described with reference to FIG. It is the same as the circuit in Fig. 1, and the explanation of the overlapping part is omitted. The drain of the P-type MOS 2 is connected to the anode of the light-emitting diode (LED) of the photocoupler 15, the cathode of the LED is connected to the resistor 16, and the end not connected to the cathode of the resistor 16 is connected to the terminal B Connecting. The collector of the light receiving transistor of the photocoupler 15 is connected to the terminal A, and the emitter is connected to the gate of the P-type MOS 1.
[0015]
With this connection, as in the circuit of FIG. 1, when an overcurrent is about to flow, a voltage is generated in the coil 3, and the voltage generated in the coil 5 causes the P-type MOS 2 to be in a conductive state. The drain current of the MOS 2 flows through the LED of the photocoupler 15 and the resistor 16 and flows to the terminal B. Due to this drain current, the LED of the photocoupler 15 emits light, and the light receiving transistor becomes conductive. As a result, the gate voltage of the P-type MOS 1 becomes almost the voltage at the terminal A, and the P-type MOS 1 is in a non-conducting state, so that overvoltage and overcurrent can be cut off.
[0016]
After that, when the overvoltage drops to near the normal voltage and the P-type MOS 2 becomes non-conductive, the current flowing through the LED stops, the light receiving transistor also becomes non-conductive, and the P-type MOS 1 returns to the conductive state, and again A steady current is passed.
As a result, the P-type MOS 1 can continue to be in a non-conductive state from when the overvoltage starts to be applied until the overvoltage ends, and can completely shut off the overvoltage. The steady current can be flowed again.
[0017]
Next, an embodiment in which a resistor and a capacitor are connected between the terminals AB (parallel to the load) in the embodiment of FIG. 1 will be described with reference to FIG.
Connect one end of the resistor 9 to the source of the P-type MOS 1 in the circuit of FIG. 1, connect the other end to the capacitor 10, and connect the end of the capacitor 10 not connected to the resistor 9 to the terminal B To do. The other parts of the circuit of this embodiment are the same as the circuit of FIG.
[0018]
When an overvoltage is applied to this circuit and an overcurrent flows, a voltage is generated in the coil 3 as in the embodiment of FIG. 1, and the gate voltage of the P-type MOS 1 is reduced by the magnitude of the generated voltage. The P-type MOS 1 suppresses overcurrent, but since the current flows through the resistor 9 and the capacitor 10 connected between the source of the P-type MOS 1 and the terminal B, the overvoltage is maximum until the capacitor 10 is saturated. Until this time, overcurrent continues to flow through the coil 3. As a result, a voltage of a certain magnitude continues to be generated in the coil 3, although not as large as when the overcurrent starts to flow. At the same time, a voltage having a magnitude proportional to the winding ratio is continuously generated in the coil 5. As a result, the gate voltage of the P-type MOS 2 becomes a magnitude obtained by adding the voltage of the coil 5 to the voltage drop at the resistor 6, so that the gate voltage of the P-type MOS 2 is as large as the voltage drop at the resistor 6. In comparison, the P-type MOS 2 is in a conductive state having a lower resistance, the gate voltage of the P-type MOS 1 can be brought closer to the voltage at the terminal A, and the P-type MOS 1 is brought into a non-conductive state more quickly. Current and overvoltage can be cut off faster.
[0019]
Next, another embodiment will be described with reference to FIG. 6 that are the same as the circuit of FIG. 1 are numbered the same.
The source of the P-type MOS 1 is connected to the coil 3 and the end of the side not connected to the source of the coil 3 is a terminal A. The drain of the P-type MOS 1 is connected to the load circuit and is connected to the drain of the load circuit. The end of the P-type MOS 1 is connected to the resistor 24, the end of the P-type MOS 1 connected to the resistor 24, the end not connected to the gate of the resistor 24 is connected to the terminal B, and the gate of the P-type MOS 1 is The Zener diode is connected to the anode, and the Zener diode cathode is connected to the terminal A. The source of the P-type MOS 2 is connected to the terminal A, the drain is connected to the gate of the P-type MOS 1, the coil 5 and the resistor 6 are connected in series between the source and the gate of the P-type MOS 2, and the diode The anode of 28 is connected to the connection point of the coil 5 and the resistor 6, and the cathode is connected to the terminal A. The gate of the P-type MOS 2 is connected to the resistor 7 and the end of the resistor 7 not connected to the gate is connected to the terminal B. A coil 11, a resistor 12 and a capacitor 13 are connected in series between the terminals AB. Coils 3, 5, and 11 are coils that are magnetically coupled simultaneously. And it is an overcurrent overvoltage protection circuit with terminal A as the positive side and terminal B as the negative side.
[0020]
The function of each part is explained.
When the Zener voltage of the Zener diode 14 is set larger than the threshold voltage of the P-type MOS 1, when the terminal A is applied with a positive voltage and the terminal B is applied with a negative voltage, the gate voltage of the P-type MOS 1 becomes larger than the threshold voltage. MOS1 conducts and a steady current flows.
With this connection, as in the circuit of FIG. 1, when an overvoltage is applied and an overcurrent flows, a voltage is generated in the coil 3, and the gate voltage of the P-type MOS 1 is reduced by the magnitude of the generated voltage. The P-type MOS 1 suppresses overcurrent, but current flows through the coil 11, the resistor 12 and the capacitor 13 connected between the terminals AB, so that the capacitor 13 is saturated, that is, until the overvoltage reaches the maximum level. The overcurrent continues to flow through the coil 11. As a result, a certain voltage is continuously generated in the coil 11. At the same time, a voltage having a magnitude proportional to the winding ratio is continuously generated in the coil 5. As a result, the gate voltage of the P-type MOS 2 becomes a magnitude obtained by adding the voltage of the coil 5 to the voltage drop at the resistor 6, so that the gate voltage of the P-type MOS 2 is as large as the voltage drop at the resistor 6. In comparison, the P-type MOS 2 is in a conductive state having a lower resistance, the gate voltage of the P-type MOS 1 can be brought closer to the voltage at the terminal A, and the P-type MOS 1 is brought into a non-conductive state more quickly. Current and overvoltage can be cut off faster.
[0021]
A current transformer can also be used for the coils 3, 5, and 11.
[0022]
【The invention's effect】
Since the present invention is configured as described above, the following effects are exhibited. By magnetically coupling the coil 3 and the coil 5, even if the inductance of the coil 3 through which the main current flows is reduced and the generated voltage is reduced, a large voltage is generated in the coil 5 in proportion to the winding ratio. Thus, the P-type MOS 2 can be made conductive and the P-type MOS 1 can be made non-conductive, and the coil 11 through which the main current flows can be obtained by connecting the coil 10 magnetically coupled to the capacitor 10 and the coils 3 and 5. Even if the inductance and impedance of 3 are further reduced, the P-type MOS 1 can be surely turned off, so that the overcurrent overvoltage can be cut off by the small coil 3 and a steady current flows. The voltage drop (loss) in the coil 3 can also be reduced.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an embodiment of an overcurrent overvoltage protection circuit of the present invention.
FIG. 2 is a diagram showing a normal way of drawing two coils mutually magnetically coupled.
FIG. 3 is a circuit diagram showing an embodiment in which a bipolar transistor is used in the overcurrent overvoltage protection circuit of the present invention.
FIG. 4 is a circuit diagram showing an embodiment in which a photocoupler is used in the overcurrent overvoltage protection circuit of the present invention.
FIG. 5 is a circuit diagram showing an embodiment in which a resistor and a capacitor are connected in parallel to a load in the overcurrent overvoltage protection circuit of the present invention.
FIG. 6 is a circuit diagram showing an embodiment using three coils of the overcurrent overvoltage protection circuit of the present invention.

Claims

The source of the P-type MOS (1) is connected to the coil (3), the end not connected to the source of the coil (3) is a terminal A, and the drain of the P-type MOS (1) is connected to the load circuit. The end of the load circuit that is not connected to the drain of the load circuit is the terminal (B), and the gate of the P-type MOS (1) is connected to the resistor (4) and is connected to the gate of the resistor (4). The end of the P-type MOS (2) is connected to the terminal (A), the drain is connected to the gate of the P-type MOS (1), and the P-type MOS (2) ), The coil (5) and the resistor (6) are connected in series between the source and the gate, the resistor (8) is connected in parallel with the coil (5), and the coil (5) is connected to the coil (3). Magnetically coupled, and the gate of the P-type MOS (2) is connected to the resistor (7) and connected to the gate of the resistor (7). Not connect the ends of the side to the terminal (B), the overcurrent overvoltage protection circuit terminals (A) to the positive side, the terminals (B) and the negative side.

The P-type MOS (2) is replaced with a PNP-type bipolar transistor (22), the emitter of the bipolar transistor (22) is connected to the terminal (A), and the base is connected to the connection point of the resistor (6) and the resistor (7) The overcurrent overvoltage protection circuit according to claim 1, wherein the collector is connected to the gate of the P-type MOS (1).

The source of the P-type MOS (1) is connected to the coil (3), the end not connected to the source of the coil (3) is a terminal A, and the drain of the P-type MOS (1) is connected to the load circuit. The end of the load circuit that is not connected to the drain of the load circuit is the terminal (B), and the gate of the P-type MOS (1) is connected to the resistor (4) and is connected to the gate of the resistor (4). The end of the P-type MOS (2) is connected to the terminal (A), and the drain is connected to the anode of the light emitting diode of the photocoupler (15). The cathode is connected to the resistor (16), the end of the resistor (16) not connected to the cathode is connected to the terminal B, the collector of the light receiving transistor of the photocoupler (15) is connected to the terminal (A), the emitter Is connected to the gate of the P-type MOS (1) and P Between the source and gate of the MOS (2), a coil (5) and a resistor (6) are connected in series, a resistor (8) is connected in parallel with the coil (5), and the coil (5) 3) Magnetically coupled with each other, and the gate of the P-type MOS (2) is connected to the resistor (7), and the end of the resistor (7) not connected to the gate is connected to the terminal (B). The overcurrent overvoltage protection circuit with the terminal (A) on the positive side and the terminal (B) on the negative side.

One end of the resistor (9) is connected to the source of the P-type MOS (1), the other end is connected to the capacitor (10), and the end of the capacitor (10) on the side not connected to the resistor (9) The overcurrent overvoltage protection circuit according to claim 1, wherein the terminal is connected to the terminal (B).

The source of the P-type MOS (1) is connected to the coil (3), the end not connected to the source of the coil (3) is the terminal (A), and the drain of the P-type MOS (1) is the load The end of the load circuit that is not connected to the drain of the load circuit is the terminal (B), and the gate of the P-type MOS (1) is connected to the resistor (24) and connected to the gate of the resistor (24). The end of the P-type MOS (1) is connected to the anode of the Zener diode, the cathode of the Zener diode is connected to the terminal (A), P The source of the type MOS (2) is connected to the terminal (A), the drain is connected to the gate of the P type MOS (1), and the coil (5) is connected between the source and gate of the P type MOS (2). And the resistor (6) are connected in series, and the anode of the diode (28) is connected to the coil 5) and the resistor (6) are connected to each other, the cathode is connected to the terminal (A), the gate of the P-type MOS (2) is connected to the resistor (7), and the resistor (7) is connected to the gate. The end on the side that is not connected is connected to the terminal (B), the coil (11), the resistor (12), and the capacitor (13) are connected in series between the terminals (A) and (B), and the coil (3 ), (5), and (11) are overcurrent overvoltage protection circuits that are magnetically coupled at the same time, with the terminal (A) on the positive side and the terminal (B) on the negative side.