JP3906112B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a redundancy system for repairing a defect.
[0002]
[Prior art]
Semiconductor memory redundancy systems include a row redundancy system for repairing defective rows (rows including defective cells) and a column redundancy system for repairing defective columns (columns including defective cells). Is installed at the same time. In the row redundancy system, when a row address corresponding to a defective row in the memory array is input, a spare row is accessed instead of accessing the defective row.
[0003]
More specifically, when a row address for selecting a word line including a defective cell is input, replacement control is performed to activate a spare word line instead of activating the word line. A column redundancy system is a state in which a row corresponding to an input row address in a memory array is accessed (for example, a state in which a word line is activated), and a column address corresponding to a defective column in the memory array is input. Instead, the spare column is accessed instead of accessing the defective column.
[0004]
For example, in a column redundancy system in which a bit line or a column selection line is replaced with a spare bit line or a spare column selection line, instead of activating a bit line or column selection line for selecting a defective column, an access row is accessed. Replacement control for activating a spare bit line or a spare column selection line for reading and writing to a spare cell is performed. Here, the column selection line includes a data line in a column redundancy system in which a defective data line is replaced with another data line, in addition to a signal line for controlling a column switch that connects the bit line to the data line.
[0005]
Thus, in general, in a redundancy system, in order to replace a defective cell, instead of replacing each cell with a spare cell, a plurality of cells in the row or column direction including the defective cell are replaced with a plurality of cells in the spare row or spare column. Replace with a spare cell. Hereinafter, in this specification, a set of a plurality of cells in the row direction to be subjected to defective cell replacement and a signal line for selecting the cells are referred to as “normal row elements” or simply “row elements”. A set of a plurality of cells in the column direction to be subjected to defective cell replacement and a signal line for selecting them are called “normal column elements” or simply “column elements”. A set of spare cells, which are defective row and column replacement units, and a signal line for selecting them are called “redundant elements”. In a system that performs defect replacement for both rows and columns, a “redundant row element” and a “redundant column element” are prepared. Furthermore, an “element” is not limited to a set of physically continuous cells selected by a single signal line, but is a set of two-dimensional cells and a bundle of a plurality of signal lines that are selected together. Including some cases.
[0006]
FIG. 18 shows a redundancy system in a conventional semiconductor memory. The memory array is divided into two upper and lower memory blocks with a sense amplifier (S / A) bank in between. Redundant row element RELEMENT <0> is arranged in the lower half memory block, and this is assigned to the replacement of the defective row element in the lower half memory block. Another redundant row element RELEMENT <1> is arranged in the upper half memory block, and this is assigned to the replacement of the defective row element in the upper half memory block.
[0007]
As shown by a broken line, the memory array is also divided into two parts on the left and right. Redundant column element CELEMENT <0> is arranged in the left half area, and this is assigned to the replacement of the column element in the left half area. Another redundant column element CELEMENT <1> is arranged in the right half area, which is assigned to replace the defective column element in the right half area.
[0008]
In this specification, a set of normal elements that are allowed to be replaced by a certain redundant element in the memory array is called a “relief area” by the redundant element. A relief area is assigned to each redundant element. In the example of FIG. 18, the “row relief areas” assigned to the redundant row elements RELEMENT <0> and <1> are the RRA <0> and <1> in the upper and lower halves of the memory array, respectively. “Column relief areas” assigned to CELEMENT <0> and <1> are CRA <0> and <1>, respectively, of the left and right halves of the memory array.
[0009]
Defective cells on the memory array can be replaced using either redundant row elements or redundant column elements. This means that, as shown in FIG. 18, one row relief region always has an “overlap region” that at least partially overlaps one or more other color relief regions.
[0010]
FIG. 19 shows the relationship between redundant row elements and redundant column elements, focusing on one “overlapping region”. Replacement by redundancy is to replace a defective element with a redundant element as described above. When the defective element includes a cell in the overlap region of interest, a portion included in the overlap region of the defect element is referred to as a partial defect element. A part of the redundant element for replacing the partial defective element is called a partial redundant element. In FIG. 19, there is shown a case where there is a defective cell indicated by an X in each of the partial defect row element and the partial defect column element in the overlapping region. It may be outside the overlap area.
[0011]
In a conventional redundancy system, when attention is paid to a certain overlap area, a redundant row element assigned to a row relief area including the overlap area and a redundant column element assigned to a column relief area including the same overlap area intersect each other. As described above, the relationship between the redundant element and the relief area is set. As described above, the redundant elements of the row and column intersect each other in the overlapping area, so that the cells on the redundant column element assigned to the same overlapping area can be selected by the redundant row element assigned to the overlapping area. Similarly, it means that a cell on a redundant row element assigned to the same overlapping area can be selected by the redundant column element assigned to the overlapping area.
[0012]
Further, when expressing the characteristics of the conventional redundancy system in another way, a plurality of redundant row elements and redundant column elements in the memory chip, and a relief area to which they are assigned, so as to satisfy the following conditions: The relationship is set. That is, all normal row elements (normal row elements including partial normal row elements included in the overlap region or normal row elements are completely selected) for selecting cells in the overlap region to be replaced by a certain redundant row element Are included in the overlapping area, and the partial normal row element may coincide with the normal row element) always intersects the redundant column element assigned to the column replacement in the overlapping area. Similarly, all normal column elements (normal column elements including partial normal column elements included in the overlapping area, or normal column elements are selected for selecting cells in the overlapping area to be replaced by a certain redundant column element) (Although it is possible that the partial normal column element is completely included in the overlapping region and the partial normal column element matches the normal column element), the redundant row element assigned to the row replacement in the overlapping region always intersects.
[0013]
Therefore, since it is possible to select a cell on a redundant column element with a certain normal row element for a certain overlapping region, when the normal row element is replaced by a certain redundant row element, even on the redundant column element, The cell corresponding to the row address of the replaced normal row element is also replaced. Similarly, since it is possible to select a cell on a redundant row element with a normal column element for a certain overlapping region, when the normal column element is replaced with a redundant column element, the redundant column element also has The cell corresponding to the column address of the replaced normal column element is also replaced.
[0014]
In addition, the redundant row element and the redundant column element corresponding to the overlapping region intersect each other means that there is a spare cell at the intersection point. For example, when a spare word line that is a redundant row element and a spare column selection line that is a redundant column element intersect, there is a spare cell that these spare word line and spare column selection line select together. means. As shown in FIG. 19, this spare cell is commonly called a Limbo Cell. In such a system, the cell at the intersection of the partially defective row element and the partially defective column element in the overlap region is replaced by this limbo cell.
[0015]
[Problems to be solved by the invention]
Problems of such a conventional redundancy system will be described with reference to FIG. As shown in FIG. 20, the semiconductor memory chip is composed of a plurality of memory arrays MA <0>, MA <1>,. In the example of FIG. 20, two redundant row elements RELEMEMT and redundant column element CELEMENT are arranged in each memory array, and two row relief areas and column relief areas are set respectively. As described above, a large number of redundant row elements and redundant column elements exist in the memory chip, and there are many combinations of these redundant row elements and redundant column elements. However, combinations of redundant row elements and redundant column elements that intersect each other are limited.
[0016]
Therefore, when determining redundant elements to be assigned to each relief area, it is redundant to design so that the redundant row elements and the redundant column elements assigned to the so-called overlapping areas where the row relief area and the column relief area overlap each other. This is an obstacle to restricting the selection range of elements, reducing the degree of freedom in redundancy design, and increasing replacement efficiency or relief efficiency. In other words, setting the repair area by the redundant column element and the redundant row element so that the redundant row and the redundant column element assigned to the overlapping area have a limbo cell as shown by a circle in FIG. The selection range is narrowed, and as a result, high relief efficiency is limited. In addition, since the design of the redundancy circuit section is closely related to the configuration of the memory array and the design of other peripheral circuits, if the degree of freedom of redundancy design is restricted, the degree of freedom of design of the entire chip is also restricted. In other words, it leads to an increase in chip size and a decrease in performance.
[0017]
An object of the present invention is to provide a semiconductor memory device adopting a redundancy system with high repair efficiency.
[0018]
[Means for Solving the Problems]
A semiconductor memory device according to the present invention includes a plurality of first cells including a cell array having a plurality of memory cells, a set of memory cells in a first direction defined in the cell array, and a first selection line for selecting the set. A first normal element, a set of memory cells in the second direction defined in the cell array, and a second selection line for selecting the memory cell, and corresponding first normal elements respectively. Collaboration A plurality of second normal elements for selecting memory cells, a plurality of first redundant elements arranged to replace the defective first normal element in the cell array, and a defect first in the cell array. A plurality of second redundant elements arranged to replace two normal elements, and a first normal element set that is allowed to be replaced by each first redundant element in the cell array. One relief region and a second relief region defined as a set of second normal elements that are allowed to be replaced by each second redundant element in the cell array, the plurality of first regions At least two normal elements are activated simultaneously, and at least two first normal elements activated simultaneously Whether or not the element is replaced by the first redundant element is controlled independently of each other and has a defect in the first relief region including one of the first normal elements that are simultaneously activated. At least one of the second redundant elements replacing two normal elements does not intersect with one of the first normal elements activated simultaneously.
[0019]
According to the present invention, as at least one second redundant element that replaces the second normal element having a defect in the first relief area including one of the first normal elements that are simultaneously activated, By selecting one that does not intersect with one of the first normal elements to be activated, the relief range is substantially expanded, and high relief efficiency can be obtained.
[0020]
In the present invention, it is preferable that the second normal element having a defect in the first relief area including one of at least two first normal elements activated simultaneously is the plurality of second redundant elements. The second redundant element that intersects the one of the at least two first normal elements that are simultaneously activated is also replaced.
In the present invention, for example, the first relief region including one of at least two first normal elements that are simultaneously activated and the first relief region including the other one are arranged adjacent to each other. One of the second redundant elements intersects with the other one of the at least two first normal elements to be simultaneously activated, and the at least two first normal elements to be simultaneously activated. The second normal element having a defect in the first relief area including one is replaced.
[0021]
In the present invention, at least three first relief regions each including one of at least three first normal elements that are simultaneously activated may be successively arranged. In this case, at least two second redundancy elements capable of replacing the second normal element having a defect in one of the first relief areas including one of at least three first normal elements that are simultaneously activated. The element intersects any remaining one of the at least three first normal elements that are simultaneously activated.
[0022]
A selection circuit for selecting the first normal element is arranged between the first relief regions arranged adjacently or successively.
[0023]
In the present invention, the cell array specifically includes first and second memory arrays adjacent to each other across the row decoder, and the first normal element of the first and second memory arrays responds to the row address. At least one of the first and second memory arrays is simultaneously activated by the row decoder, and at least one of the plurality of first redundant elements is arranged corresponding to the first and second memory arrays. Independently of each other, the plurality of second redundant elements are used in the first and second memory arrays at least one of the first and second memory arrays. One at a time, intersecting the first redundant element in each memory array, and independently of each other, the second normal element of the defect in the first and second memory arrays. Used for the replacement of cement.
[0024]
Further, in order to perform such replacement control, a column decoder for selecting the second normal element of each of the first and second memory arrays, and a row replacement control signal generated in response to the defective row address Activated by the redundant row decoder for selecting the first redundant element and the column redundant control signal generated in response to the defective column address to select the second redundant element, respectively. A redundant column decoder for outputting a row replacement control signal and a column replacement control signal in accordance with the defective address, and defined in one of the first and second memory arrays, wherein the first normal element is A first relief region replaceable by a first redundant element disposed corresponding to one of the memory arrays; In it A replacement control circuit configured so that the second normal element has an overlapping region at least partially overlapping with a second relief region replaceable by a second redundant element arranged corresponding to the other of the memory array With.
[0025]
The first relief areas to which the first redundant elements are assigned are set in the first and second memory arrays, respectively. The second relief areas to which the second redundant elements are assigned are the first and second memory areas. Set across memory arrays.
[0026]
The cell array may include three or more memory arrays that are continuous with a row decoder that simultaneously selects at least one first normal element in response to a row address. In this case, the plurality of first redundant elements are arranged so as to be used for the replacement of the first normal element of the defect in each memory array, independently of each other, at least one corresponding to each memory array. Each of the second redundant elements intersects with the first redundant element in the corresponding memory array, at least one in each memory array, independently of each other, and the second redundant element in the selected at least one memory array. Arranged to be used for replacement of two normal elements.
[0027]
Specifically, in the present invention, each first normal element has one or more word lines as a first selection line, and each first redundant element has one or more spare word lines. And each second normal element is One or more bit lines or parts thereof And each second redundant element has One or more spare bit lines, or part of them Have
[0028]
In the present invention, when the cell array has two adjacent memory arrays, for example, the first relief area defined by the first redundant element is set as a row relief area covering the entire memory array, The relief area has N (N is an integer equal to or greater than 2) N cells, where C is the total cell capacity of each memory array. Redundant A first column relief area including a column element and having a capacity of 2 C / M (M is an integer of 3 or more) and (M−1) / 2 is set in each memory array, and the remaining capacity C of each memory array It is assumed that two areas of / M each are combined to have a second column relief area with a capacity of 2C / M set including N redundant column elements. At this time, for example, the first column relief area is used as a normal data part, and the second column relief area is used as a parity data part for storing inspection data for error detection / correction of data in the normal data part. It is done.
[0029]
Two memory arrays arranged adjacent to each other may be divided into a plurality of subarrays that are assigned the same row address and are simultaneously activated by a predetermined number. At this time, one spare column selection line continuously formed across a plurality of subarrays is assigned with a different row address and used as a plurality of second redundant elements.
[0030]
In the present invention, the cell array further includes a plurality of memory arrays, a plurality of main word lines arranged across the memory arrays, and a plurality of main word lines arranged in each memory array and selected by the main word lines. A sub word line, at least one spare main word line arranged across a plurality of memory arrays, and at least one spare main word line arranged in each memory array, one of which is arranged in each memory array by the spare main word line And a spare sub word line to be selected. in this case, One or more The sub-word line is the first normal element One or more A spare sub word line is used as the first redundant element.
[0031]
The semiconductor memory device according to the present invention also includes a plurality of memory cells, a plurality of normal row elements defined as a set of memory cells in the row direction in the memory array, and memory cells in the column direction in the memory array. A plurality of normal column elements defined as a set, and the first and second memory arrays that are simultaneously activated, and at least one corresponding to each of the first and second memory arrays and arranged to each other; At least one redundant row element used independently for replacement of a defective normal row element and at least one corresponding to the first and second memory arrays are arranged so as to cross the redundant row element in the corresponding memory array. Redundant column elements that are used independently to replace defective normal column elements. The row relief area defined as a set of normal row elements that are allowed to be replaced by the redundant row element arranged in one of the first and second memory arrays, and the redundant column element arranged in the other It is characterized in that it is set so as to have an overlapping area at least partially overlapping with a column relief area defined as a set of normal column elements that are allowed to be replaced.
[0032]
In this case, preferably, the redundant column element in the memory array to which the overlapping region belongs is also used for replacement of the defective normal column element in the overlapping region.
[0034]
The semiconductor memory device according to the present invention further includes a plurality of memory cells, a plurality of normal row elements defined as a set of memory cells in the row direction, and a plurality of normal column elements defined as a set of memory cells in the column direction. A plurality of redundant row elements used for replacement of defective normal row elements of the cell array, and a plurality of redundant column elements used for replacement of defective normal column elements of the cell array. At least two first and second row relief areas having different cell capacities defined as a set of normal row elements that are allowed to be replaced by the redundant row elements are set, and are replaced by the plurality of redundant column elements. No is allowed Wherein the repair efficiency in each column repair region which is defined as a set of gel column element is set to be equal in the cell array.
[0035]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[Embodiment 1]
The semiconductor memory of the first embodiment includes a cell array, a plurality of normal row elements defined as a set of memory cells in the row direction in the cell array and including selection lines for selecting the memory cells, and a memory in the column direction in the cell array. A plurality of normal column elements for selecting a memory cell in the column direction are provided, which are defined as a set of cells, include a selection line for selecting the cell, and cooperate with the normal row element. A plurality of redundant row elements for replacing defective normal row elements in the cell array and a plurality of redundant column elements for replacing defective normal column elements are arranged. Within the cell array, a row relief area is defined as a set of normal row elements that are allowed to be replaced by each redundant row element, and a column relief area is defined as a set of normal column elements that are allowed to be replaced by each redundant column element. Is done.
[0036]
In this basic configuration, in the first embodiment, at least two of the plurality of normal row elements are activated simultaneously, and whether or not these normal row elements are replaced by redundant row elements is controlled independently of each other. In addition, a defective normal column element in a row relief region including one of at least two normal row elements that are simultaneously activated is replaced by a redundant column element that cooperates with the other of the normal row elements to select a memory cell. . Further, in the first embodiment, the relationship between the row and column relief areas of the cell array and the redundant elements is that the redundant row elements assigned to the overlapping area where the row and column relief areas overlap and the redundant column elements corresponding to the same overlapping area are It is chosen not to cross each other.
[0037]
FIG. 1 is a diagram for explaining the first embodiment, in which two memory arrays MA <0>, MA <adjacent to each other across a row decoder / word line driver (RD & WD) in a cell array of a semiconductor memory chip. 1> is shown. Although not shown in the drawing, a plurality of normal row elements and a plurality of normal column elements are arranged independently in each of the memory arrays MA <0> and <1>.
[0038]
The memory array MA <0> includes redundant row elements RELEMENT <0>, <1> used for replacement of defective row elements and redundant column elements CELEMT <0>, <1> used for replacement of defective column elements. Is arranged. Similarly, redundant row elements RELEMENT <2>, <3> and redundant column elements CELEMENT <2>, <3> are also arranged in the area of the memory array MA <1>.
[0039]
Redundant column elements CELEMENT <0>, <1> arranged in memory array MA <0> share row elements, and redundant row elements RELEMENT <0>, <1 arranged in memory array MA <0>. > Share column elements. Redundant column elements CELEMENT <0>, <1> and redundant row elements RELEMENT <0>, <1> on the memory array MA <0> side cross each other and have so-called limbo cells. The above relationship is the same for the memory array MA <1>.
[0040]
In this embodiment, when a certain row address is input, as illustrated in FIG. 1, the row elements NREi <0>, <1> corresponding to the input row address are changed to the left and right memory arrays MA <0>, <1. 1> are activated simultaneously one by one.
[0041]
Although only two memory arrays are shown in FIG. 1, in fact, row elements may be simultaneously activated in a plurality of memory arrays other than only the two memory arrays. Specifically, for example, the memory arrays MA <0> and MA <1> are ranges in which row elements (word lines) are continuously arranged, but when a certain row address is input, two memories are stored. A row decoder / word line driver (RD & WD) arranged between the arrays MA <0> and MA <1> simultaneously activates word lines in the memory arrays MA <0> and MA <1>. . As will be described later, this is a condition required in the redundancy system in this embodiment.
[0042]
Memory array MA <0> is divided into two in the vertical direction (column direction), and each row repair area RRA <0>, <R is a set of row elements that can be replaced by redundant row elements RELEMENT <0>, <1>. 1>. Similarly, the memory array MA <1> is also divided into two vertically, and row relief areas RRA <2>, <3, each of which is a set of row elements that can be replaced by redundant row elements RELEMENT <2>, <3>. Is defined as>.
Therefore, the two normal row elements simultaneously activated in the left and right memory arrays MA <0> and <1> belong to different row relief areas, and it is possible to decide whether or not to rescue each redundant row element independently. .
[0043]
On the other hand, in this embodiment, the redundant column element for replacement of the defective column element in the memory array MA <0> is separated from the memory array MA <0> (specifically, the word line is shared with the defective column element). Not), those arranged on the memory array MA <1> side are used. As the redundant column element for replacement of the defective column in the memory array MA <1>, those arranged on the memory array MA <0> side are used. In order to perform such column redundancy, it is necessary to simultaneously activate the two memory arrays MA <0> and MA <1> as described above.
[0044]
Specifically, the relationship between the redundant column elements and the memory arrays MA <0>, <1> will be described as follows. Memory array MA <0> is divided into two left and right (in the row direction), and each column repair area CRA <2> is formed by redundant column elements CELEMENT <2>, <3> arranged on the memory array MA <1> side. , <3>. Similarly, the memory array MA <1> is also divided into two parts on the left and right, and each column repair area CRA <0>, <1> is formed by redundant column elements CELEMENT <0>, <1> arranged on the memory array MA <0> side. 1> is set.
[0045]
When attention is paid to the overlapping area where the column repair area CRA <2> and the row repair area RRA <1> in the left half of the memory array MA <0> overlap, the redundant row elements allocated to the overlapping area are the same memory array MA. RELEMENT <1> arranged in <0>, and the redundant column element is SELEMENT <2> arranged in the adjacent memory array MA <1> (or may be SELEMENT <3>). That is, the redundant row element and the redundant column element assigned to the overlapping region of the row and column relief regions do not intersect each other. In other words, the redundant row element and the redundant column element corresponding to the overlap region do not have a limbo cell that is a cell at the intersection point of each other.
[0046]
Similarly, for the column relief area CRA <3> in the right half of the memory array MA <0>, the redundant column element CELEMT <3> (or CELEMENT <2>) on the memory array MA <1> side is selected. Similarly, with respect to the right side memory array MA <1>, the redundant column element CELEMENT <disposed in the left side memory array MA <0> with respect to the column relief areas CRA <0>, <1> of the left and right halves. 0> and <1> are assigned.
[0047]
In many cases, there are not only two memory arrays in a memory chip, but a larger number of memory arrays are arranged, for example, as shown in FIG. Then, when paying attention to a certain redundant row element, the number of redundant column elements that do not intersect with each other is larger than the number of redundant column elements that intersect with this. If the overlap of the column repair areas by the plurality of redundant column elements is allowed, the number of redundancy elements for the repair area can be increased. In other words, compared to the conventional method, the range in which one redundant column element can be repaired is widened, and a redundancy system with high repair efficiency can be constructed. Specifically, in the conventional method, when defective columns are concentrated in a certain area, the number of redundant column elements that use the defective column as a relief area is limited, and thus there are cases where the relief cannot be made. On the other hand, in this embodiment, even if there is a concentration of defective columns, it is possible to replace any defective column in any region within the range of the memory array in which all redundant column elements are activated simultaneously. If the total number of defects is in the range of the total number of redundant column elements, it can be relieved. Therefore, a redundancy system with higher relief efficiency can be constructed.
[0048]
In FIG. 1, a case where a plurality of normal elements that are remedied independently by redundant elements and are simultaneously activated is a row element. However, by reversing the relationship between a row and a column, The present invention can also be applied to the case where they are activated simultaneously and are repaired separately by redundant column elements. Each redundant element in FIG. 1 may be considered as a plurality of spare signal lines in addition to a single spare signal line. A plurality of spare signal lines constituting one redundant element may be arranged together or distributedly arranged. Further, each redundant element need not necessarily be a continuous set of spare cells. Furthermore, a configuration in which redundant elements are arranged in a separate array dedicated to redundant elements may be employed. These modifications are possible not only in this embodiment but also in the following embodiments.
[0049]
FIG. 2 shows the relationship between a set of column relief areas CRA and row relief areas RRA defining the overlapping areas in FIG. 1 in an easy-to-understand manner. When attention is paid to a pair of the row relief area RRA and the column relief area CRA that are diagonally opposite to each other and its overlapping area, there exists an area other than the overlapping area in the row relief area RRA. There are areas other than the overlapping areas. This corresponds to a case where the row and column relief areas RRA and CRA intersect and a part of each area is an overlapping area.
[0050]
FIG. 3 shows an aspect different from FIG. That is, in this example, the entire memory array MA <0> is one column relief area CRA, and the row relief area RRA is an upper and lower half of the memory array MA <0>. The entire memory array MA <0> becomes one column relief area CRA. In other words, the redundant column elements CELEMENT <2>, <3> arranged in the right memory array MA <1> are both This means that the entire memory array MA <0> is used as a relief area. In this case, the row relief area RRA is completely included in the column relief area CRA, and the row relief area RRA becomes an overlapping area as it is. The redundant row element assigned to the overlapping area (row relief area) is RELEMENT <0> or RELEMENT <1>.
[0051]
Also in this case, the redundant row element and the redundant column element assigned to the overlapping area where the row and column redundancy relief areas overlap do not intersect each other.
[0052]
FIG. 4 shows an example in which the entire memory array MA <0> is one row relief area RRA and the column relief area CRA is a half of the memory array MA <0> that is divided into the left and right, contrary to FIG. That the entire memory array MA <0> becomes one row relief area RRA means that both redundant row elements RELEMENT <0>, <1> arranged in the memory array MA <0> are memory array MA <0. > Means that the entire area is a relief area. In this case, the column relief area CRA is completely included in the row relief area RRA, and the column relief area CRA is an overlapping area as it is. The redundant column element corresponding to the overlapping area (column relief area) is the redundant column element CLEMENT <2> or CELEMENT <3> on the memory array MA <1> side. Also in this case, the redundant row element and the redundant column element corresponding to the overlapping region where the row and column redundancy relief regions overlap do not intersect each other.
[0053]
FIG. 5 is an example in which a set of row relief area RRA and column relief area CRA completely match. Here, a case where one memory array as a whole is one row relief area RRA and at the same time one column relief area CRA, and therefore, these row relief area RRA and column relief area CRA are directly overlapped areas is shown. ing. That is, redundant row elements RELEMENT <0> and <1> are used together for row relief on the memory array MA <0> side, and adjacent memory array MA <1> is used for column relief of the memory array MA <0>. Both side redundant column elements CLEMENT <2> and CELEMENT <3> are used. Also in this case, the redundant row element and the redundant column element corresponding to the overlapping region where the row and column redundancy relief regions overlap do not intersect each other.
It goes without saying that these modifications regarding the relationship between a set of row relief areas and column relief areas and their overlapping areas are possible not only in the first embodiment but also in the following embodiments.
[0054]
In the first embodiment, when attention is paid to an overlapping area of a set of row and column relief areas RRA and CRA, a normal row element including a partial normal row element for selecting a cell in the overlapping area is included in the overlapping area. A normal column element that does not intersect with a redundant column element that replaces a normal column element that includes a partial normal column element for selecting a cell in the overlapping area, but that includes a partial normal column element for selecting a cell in the overlapping region It intersects with a redundant row element that replaces a normal row element including a partial normal row element for selecting a cell in the region.
[0055]
Here, that the normal row element does not intersect with the redundant column element means that a cell on the redundant column element is not selected by the normal row element. In other words, even when the normal row element is replaced by the redundant row element, the cell corresponding to the row address of the normal row element to be replaced on the redundant column element is not necessarily replaced. Here, the phrase “necessarily” is used unless another normal row element that selects a cell corresponding to the row address of the replaced normal row element on the redundant column element is also replaced.
[0056]
Further, since the normal column element for selecting a cell in the overlapping region intersects with the redundant row element, it is possible to select a cell on the redundant row element with the normal column element. Therefore, when the normal column element is replaced with the redundant column element, the cell corresponding to the column address of the normal column element to be replaced on the redundant row element is also replaced.
[0057]
Also, it should be noted that the redundant column element assigned to the overlap area does not intersect the normal row element for selecting the cell in the overlap area, even if the cell in the overlap area is not crossed. It must cross another normal row element that is activated simultaneously with the normal row element to be selected or a redundant row element in which the other normal row element is replaced. This is because when a column address corresponding to a defect in the memory array is input in a state where a row corresponding to the input row address in the memory array is activated, the column redundancy system Instead of accessing the cell corresponding to the address, a spare cell on the row corresponding to the input row address is accessed. Accordingly, if a normal row element (or a redundant row element replaced in place of the normal row element) for selecting a spare cell on the redundant column element used for replacement is not activated, the spare cell is accessed. Because you can't. Therefore, not all of the redundant column elements that do not intersect with the normal row element for selecting cells in the overlapping area can be used as redundant column elements assigned to the overlapping area, but from the range of simultaneously activated memory arrays. Need to be selected.
[0058]
In view of this, the first embodiment has another normal row (column) element that is activated simultaneously with a normal row (column) element that selects selection of a cell in the overlapping region of the row and column redundancy relief regions. The redundant column (row) element to be applied to the overlapping region is selected from the redundant column (row) elements that intersect with. The plurality of normal row (column) elements that are activated at the same time are independently replaced by redundant row (column) elements. Therefore, the row (column) elements activated simultaneously may be all normal elements or some may be replaced with redundant elements. The simultaneous activation means that the same row (column) address corresponds to the plurality of normal row (column) elements.
[0059]
In addition, the redundant column (row) element selected for the overlapping region intersects with another normal row (column) element selected at the same time. ) A cell on an element can be selected, so that if another normal row (column) element is replaced by a redundant row (column) element, then on the selected redundant column (row) element That is, the cell corresponding to the row address of the other normal row element to be replaced is also replaced.
[0060]
Here, when one row (column) element has a plurality of selection lines, the activation of the row (column) element means that any of the plurality of selection lines constituting the row (column) is activated. An activated state. Further, in order to simultaneously activate a plurality of rows (columns), they need to be driven by separate selection circuits (drivers).
[0061]
The above situation can be explained more specifically as follows. Redundant column elements CELEMENT <0>, <1> arranged in the region of memory array MA <0> in FIG. 1 intersect with the word lines in the normal element region of memory array MA <0>. That is, in the memory array MA <0>, the word lines are arranged so as to be continuous with the normal column element region and the redundant column elements CELEMENT <0>, <1> region. Similarly, redundant column elements CELEMENT <2>, <3> arranged in the region of memory array MA <1> intersect with the word lines in the normal element region of memory array MA <1>. However, the word lines are independent from each other between the memory arrays MA <0> and <1> and are not continuous. Therefore, when the defective column in the memory array MA <0> is replaced by the redundant column element CELEMENT <2>, <3> on the memory array MA <1> side, the word line for selecting a cell on the defective column to be replaced Since the word line for selecting the spare cell on the redundant column element is not common, in the case of this embodiment for performing such column relief, the word lines in the memory arrays MA <0> and <1> are simultaneously activated. It is necessary to make it.
[0062]
On the other hand, redundant row elements RELEMENT <0>, <1> arranged in the region of memory array MA <0> in FIG. 1 are a plurality of rows arranged in the column direction of the normal row element region of memory array MA <0>. Crosses a column selection line that selects a cell. That is, in the memory array MA <0>, the column selection line is arranged so that the normal row element region and the redundant row element RELEMENT <0>, <1> region are continuous. Therefore, replacement of defective word lines in the memory array MA <0> by these redundant row elements RELEMENT <0>, <1> is performed in the same manner as in the prior art.
[0063]
Next, a specific defect row / column replacement control system in the first embodiment will be described with reference to FIG. In FIG. 6, for the sake of simplicity, an example in which one redundant column element CELEMENTA, CELEMENTb and one redundant row element RELEMENTA, RELEMENTb are arranged in two adjacent memory arrays MA <0>, <1>, respectively. Is shown. Specifically, the redundant row elements RELEMENTA and RELEMENTb of the memory arrays MA <0> and <1> are allocated as the entire row array where the respective memory arrays are arranged. On the other hand, the redundant column element CELEMENTa on the memory array MA <0> side uses the entire memory array MA <1> as the column relief area, and the redundant column element CELEMTb on the memory array MA <1> side is the entire memory array MA <0>. Are assigned as column relief areas.
[0064]
The row decoder / word line driver 11 is shared by the two memory arrays MA <0> and <1>, and at least one normal row element (word line) of each of the memory arrays MA <0> and <1>. Are activated simultaneously. However, if the normal row element to be activated in either one of the memory arrays MA <0> and <1> includes a defect, the other normal row element is replaced with the redundant row element. Can be independently deactivated. More specifically, the decoding unit 12 of the row decoder 11 is shared by the two memory arrays MA <0> and <1>, but the word line driver units 13a and 13b are connected to the memory arrays MA <0>, It is prepared for each <1> and can be activated and deactivated independently. The row element may be a single word line or a plurality of word lines.
[0065]
A redundant row decoder 14 is prepared to select a redundant row element RELEMENT instead of a defective row normal element when a defective row address is input. In the redundant row decoder 14, the decoding unit 15 is shared by the two memory arrays MA <0> and <1>, and the word line driver units 16a and 16b are prepared for the memory arrays MA <0> and <1>, respectively. Active and inactive can be controlled independently. However, the decoding unit 15 may be provided separately for the memory arrays MA <0> and <1>.
[0066]
The column decoders 17a and 17b select the normal column elements (column selection lines) of the memory arrays MA <0> and <1> according to the column address. Redundant column decoders 18a and 18b are prepared to select a redundant column element CELEMENT instead of a defective normal column element when a defective column address is input.
[0067]
In general, one column selection line simultaneously selects a plurality of bit line pairs and controls parallel transfer of a plurality of data. However, it is not limited to this. In addition, since the word lines of the two memory arrays MA <0> and <1> are simultaneously activated, it is possible to perform data transfer of a plurality of bits simultaneously in both memory arrays MA <0> and <1>. It is. In some cases, the normal column element is not a column selection line but a bit line or a data line to which the bit line is selectively connected. One column element may include a plurality of column selection lines and a plurality of data lines.
[0068]
Row replacement control circuits 31a and 31b and column replacement control circuits 32a and 32b are arranged as replacement control circuits for performing row and column replacement control. These replacement control circuits include a defective address storage circuit in which a defective address is programmed, an address comparison circuit for detecting a match between a defective address held in the defective address storage circuit and a row and column address supplied from the outside, Consists of Specifically, the defective address storage circuit includes a fuse set using fuses corresponding to a plurality of addresses, and a fuse data latch circuit that reads and holds the fuse data when the power is turned on.
[0069]
In order to perform such an address comparison, the row address data RA <0: n> is transferred to the row address signal line 21 and supplied to the row decoder 11 and to the row replacement control circuits 31a and 31b. The Similarly, the column address data CA <0: m> is transferred through the column address signal line 22 and supplied to the column decoders 17a and 17b and simultaneously supplied to the column replacement control circuits 32a and 32b. When a defective row address is input, the row replacement control circuits 31a and 31b output row replacement control signals 19a and 19b. The row replacement control signals 19a and 19b activate the redundant row decoder 14 and deactivate the row decoder 11 corresponding to the input row address.
[0070]
In this embodiment, one normal row element is selected at a time in memory arrays MA <0> and <1>. However, for defective row replacement, two normal row elements selected at the same time are independent of each other. It is important that the replacement is controlled. That is, as illustrated in FIG. 6, among the row normal elements (word lines WLa and WLb indicated by broken lines) simultaneously selected in the memory arrays MA <0> and <1>, for example, on the memory array MA <1> side When the word line WLb is defective, replacement control is performed instead of activating only the redundant row element RELEMENTb (spare word line) in the same memory array MA <1>.
[0071]
As described above, the control for replacing only one of the word lines WLa and WLb simultaneously selected in the memory arrays MA <0> and <1> is performed by performing row replacement control on the two row replacement control circuits 31a and 31b with different row addresses. This is possible by programming to output signals 19a, 19b.
[0072]
When a defective column address is input, the column replacement control circuits 32a and 32b output column replacement control signals 20a and 20b. The column replacement control signals 20a and 20b activate the redundant column decoders 18a and 18b, respectively, and deactivate the column decoders 17a and 17b corresponding to the input defective column address. In this embodiment, as described above, the defective normal column element in the memory array MA <0> is replaced with the redundant column element CELMENTb in the memory array MA <1>, and the defective normal column element in the memory array MA <1> is replaced. The column element is replaced with a redundant column element CEMENTa in the memory array MA <0>.
[0073]
Therefore, the column replacement control signal 20a output from one of the column replacement control circuits 32a is supplied as an activation signal to the redundant column decoder 18a of the memory array MA <0>, and at the same time, the column decoder on the memory array MA <1> side. The disable signal 20ab is supplied to the 17b side. The column replacement control signal 20b output from the other column replacement control circuit 32b is supplied as an activation signal to the redundant column decoder 18b of the memory array MA <1>, and at the same time the column decoder 17a side of the memory array MA <0> side. Is supplied as a disable signal 20bb. FIG. 6 shows an example in which a defective normal column element (column selection line CSL indicated by a broken line) on the memory array MA <0> side is replaced with a redundant column element CELEMENTb on the memory array MA <1> side.
[0074]
A plurality of redundant row elements can be arranged in each of memory arrays MA <0> and <1>. Also in this case, a redundant row decoder is arranged for each redundant row element, and a row replacement control circuit is prepared. Each row replacement control circuit may be programmed with defective row address information in a range defined as a row relief region by each redundant row element. As a result, similar to the above example, a necessary row replacement control signal can be generated in accordance with the defective row address.
[0075]
FIG. 7 shows a specific configuration example of the replacement control circuits 31a, 31b, 32a, and 32b in FIG. As shown in the figure, the replacement control circuit is held by a fuse set 41 in which a plurality of fuses FSi programmed with defective addresses are arranged, and a fuse data latch circuit 42 including a latch LATi that reads and holds data of each fuse FSi. The address comparison circuit 42 compares the fuse data with the address Ai. The address comparison circuit 42 is constituted by an exclusive OR gate G1i. The comparison output FOUTi between each fuse data and the address bit is detected by the match detection circuit 44 including the NAND gate G2. Thereby, when the input address matches the stored defective address, the hit signal bHIT is output. The hit signal bHIT corresponds to the row and column replacement control signals 19a, 19b, 20a, and 20b described above with reference to FIG.
[0076]
In the fuse set 41, a master fuse (enable fuse) FSM is prepared in addition to a fuse FSi for storing a defective address. The master fuse FSM is for setting the fuse set 41 to an enable state for the first time when the fuse set 41 is programmed so that the unprogrammed fuse set 41 does not output the hit signal bHIT. . Data of the master fuse FSM is also read and held in the latch LATM, and its output is supplied to the coincidence detection circuit 44 as an enable signal FOUTM.
[0077]
FIG. 8 is a configuration example of one latch LAT of the fuse data latch circuit 42. The fuse FS is connected in series between the power supply terminal Vcc and the ground terminal Vss for both the read NMOS transistor QN and the precharge PMOS transistor QP. When the power is turned on, the precharge signal PRE is kept at the “L” level for a certain time and then becomes “H”. Meanwhile, the NMOS transistor QN is kept off, and the node N is precharged to “H” by the PMOS transistor QP. After the PMOS transistor QP is turned off, the read signal INIT becomes “H” and the NMOS transistor QN is turned on. If the fuse FS is cut, the node N holds “H”. If the fuse FS is not cut, the charge of the node N is discharged through the fuse FS and becomes “L”. As a result, fuse data is read and latched.
[0078]
[Embodiment 2]
In the second embodiment, the first embodiment is extended to allow a row and redundant column element assigned to a row having an overlapping region and a column relief region to cross each other. This can be said to be a combination of the redundancy method of the first embodiment and the conventional redundancy method.
[0079]
In other words, in the second embodiment, a plurality of row (or column) redundancy elements are prepared for one overlapping region as row (or column) redundancy elements assigned to the overlapping region of the row and column relief regions. A part of the plurality of row (or column) redundancy elements intersects with the column (or row) redundancy element assigned to the overlapping area, but the rest do not intersect.
[0080]
This will be specifically described with reference to FIG. It is assumed that the redundant row element RELEMENT <1> is assigned to the upper half row relief area RRA <1> of the left memory array MA <0>. At this time, the redundant column elements assigned to the left half column relief area CRA <2> of the left memory array MA <0> are not limited to the CELEENT <2> or the CELEMENT <3> on the memory array MA <1> side. The CELEMENT <0> or <1> on the memory array MA <0> side is also used.
[0081]
At this time, the redundant row element RELEMENT <1> corresponding to the overlapping area of the row and column relief areas RRA <1>, CRA <2> and the redundant column elements CELEMT <2>, CELEMENT <3> do not cross each other. , RELEMENT <1> and redundant column elements CELEMENT <0>, <1> cross each other. That is, the redundant row element RELEMENT <1> and the redundant column element CELEMENT <0>, <1> have cells (limbo cells) that are simultaneously selected by, for example, successive spare word lines.
[0082]
According to this embodiment, the number of redundancy elements for a certain relief area can be further increased as compared with the first embodiment. The replacement control method is basically the same as FIG. 6 described in the previous embodiment. That is, for the normal row elements activated simultaneously in the two memory arrays MA <0> and <1>, the replacement control of the defective row is performed independently in the memory arrays MA <0> and <1>. However, FIG. 6 shows an example in which the redundant column element arranged in one memory array uses the other memory array as the column relief area. Therefore, the signal lines of the disable signals 20ab and 20bb from the column replacement control circuits 32a and 32b are provided only on one memory array side.
[0083]
On the other hand, in the second embodiment, the redundant column element arranged in one memory array uses the other memory array as a column relief region in addition to the memory array in which the redundant column element is arranged. Therefore, in this embodiment, the signal lines of the disable signals 20ab and 20bb output from the column replacement control circuits 32a and 32b shown in FIG. 6 are arranged across both memory arrays MA <0> and <1>. It is necessary to install.
[0084]
[Embodiment 3]
In the third embodiment, the redundant column (or row) element that does not intersect with the redundant row (or column) element assigned to a certain overlapping area in the first and second embodiments is used together with the column (or row) relief area. The row (or column) relief region that forms the overlapping region intersects with a redundant row (or column) element (or normal row (or column) element) assigned to another row (or column) relief region adjacent thereto. A thing shall be selected.
[0085]
FIG. 9 is an example for explaining the third embodiment. Here, four memory arrays MA <0> to <3> are arranged. Two memory arrays MA <0> and <1> are adjacent to each other with a row decoder / word line driver (RD & WD) sandwiched therebetween, and similarly, the remaining two memory arrays MA <2> and <3> Adjacent to each other with a shared row decoder / word line driver (RD & WD) interposed therebetween. It is assumed that the two memory arrays MA <0> and <1> are activated simultaneously, and that the two memory arrays MA <2> and <3> are also activated simultaneously.
[0086]
In each of the memory arrays MA <0> to <3>, redundant row elements RELEMENT <0> to <3> and redundant column elements CELEMENT <0> to <3> are arranged. Each of memory arrays MA <0> to <3> is one row relief area and at the same time one column relief area. In other words, this is an example in which the row relief area and the column relief area have overlapping areas where they completely coincide.
[0087]
Focusing on the memory array MA <0>, the redundant row element RELEMENT <0> arranged in the area of the memory array MA <0> is used to repair the defective row of the memory array MA <0>, and the defective column For the repair, redundant column element CELEMENT <1> arranged in adjacent memory array MA <1> is used. Therefore, the redundant row element and the redundant column element corresponding to the memory array MA <0>, which is an overlapping area of the row relief area and the column relief area, do not intersect each other.
[0088]
Similarly, paying attention to the memory array MA <1>, the redundant row element RELEMENT <1> arranged in the area of the memory array MA <1> is used for the defective row relief, and the defective column relief is adjacent. Redundant column element CELEMENT <0> arranged in memory array MA <0> is used. Therefore, also in this case, the redundant row element and the redundant column element corresponding to the memory array MA <1> which is the overlapping region do not intersect each other.
Also between the memory arrays MA <2> and <3>, the redundancy element and its relief area are set in the same relationship.
[0089]
Regarding the defective column repair of the memory array MA <0>, the redundant column elements that do not intersect the redundant row element RELEMENT <0> used for the defective row repair of the memory array MA <0> include CELEMENT <1>, <2>, <3>. Of these, the redundant column element CELEMENT <1> arranged in the nearest adjacent memory array MA <1> is used for the memory array MA <0> to be replaced. This is a feature of this embodiment. By performing such replacement control, the control signal wiring from the replacement control circuit can be shortened.
[0090]
This point will be specifically described. For each redundant column element, a replacement control circuit RCTR is provided as shown in FIG. As described with reference to FIG. 6, the replacement control circuit RCTR includes an address storage circuit such as a fuse circuit that stores a defective address, and an address comparison that detects coincidence between an externally supplied address and a defective address stored in the address storage circuit Circuit. When a defective address is accessed by this replacement control circuit RCTR, a replacement control signal is output that deactivates the decoding unit corresponding to the defective address and activates the spare decoding unit corresponding to the redundancy element instead. Is done.
[0091]
Specifically, as shown in FIG. 9, when a defective column of memory array MA <0> is accessed, replacement control circuit RCTR in the vicinity of memory array MA <1> activates redundant column element CELEMENT <1>. And a disable signal DIS for inactivating the defective column of the memory array MA <0> is output. According to this embodiment, the wiring length of the disable signal DIS can be minimized. Accordingly, a high-speed redundancy system can be constructed, and further, the wiring area of the disable signal can be minimized, so that the area of the redundancy circuit can be minimized and the chip area can be reduced.
[0092]
In the above-described example of repairing a defective column of the memory array MA <0>, the CELEMENT <2> and <3> arranged in the memory arrays MA <2> and <3> located at separate positions are selected as redundant column elements. Then, the disable signal must be supplied via the wiring from the control circuit RCTR for activating them to the area of the memory array MA <0>. Therefore, the operation of disabling the defective normal column element is delayed due to the influence of the wiring delay. Further, when the wiring length of the disable signal is increased, as a result, the area occupied by the wiring in the chip increases, so that the area of the replacement control circuit portion increases and the chip size also increases.
[0093]
As a modification of the third embodiment, as a redundant row element corresponding to the memory array MA <0> that is the overlapping area, in addition to the CELMENT <1> of the adjacent memory array MA <1>, a memory array that is continuous therewith CELEMENT <2> and <3> of MA <2> and <3> can also be used. Of course, in this case, in order to use the redundant column elements CELEMENT <2> and <3> of the memory arrays MA <2> and <3> for the relief of the memory array MA <0>, the normal row elements or It is necessary to simultaneously activate the redundant row element that replaces it.
[0094]
That is, as a redundant column (or row) element that does not intersect with a redundant row (or column) element corresponding to a certain overlap region, a plurality of row (or column) repairs that are continuous with a row (or column) repair region that includes the overlap region. Any of a plurality of redundant column (or row) elements that intersect the redundant row (or column) element (or normal element) corresponding to each region can be selected.
[0095]
Also in this case, since the plurality of row (or column) relief areas are not physically separated from each other, the wiring length of the disable signal that deactivates the defective normal element can be suppressed, and a high-speed redundancy system can be obtained. .
[0096]
Also in this embodiment, for the normal row elements activated simultaneously in the memory arrays MA <0> and <1>, the replacement control of the defective row is performed independently in the memory arrays MA <0> and <1>. Is called. Similarly, for normal row elements that are simultaneously activated in memory arrays MA <2> and <3>, replacement control of defective rows is performed independently of each other in memory arrays MA <2> and <3>. These replacement control methods are the same as in the first and second embodiments.
[0097]
In this embodiment, a plurality of row relief regions adjacent to or continuing to a row relief region forming an overlapping region are adjacent to each other with a row decoder / word line driver interposed therebetween as shown in FIG. In many cases, when the word line has a hierarchical structure of the main word line and the sub word line, the sub word line driver is interposed. Similarly, the column relief area adjacent to or continuing to the column relief area forming the overlapping area sandwiches the column decoder / column selection line driver, and in the case of a hierarchical column selection line structure, the sub column selection line driver is sandwiched between them. In many cases, it becomes an adjacent form.
[0098]
[Embodiment 4]
In the fourth embodiment of the present invention, the redundant column elements corresponding to the same overlapping area as the redundant row elements corresponding to the overlapping area include those that do not cross each other, and the column (or row) relief area forming the overlapping area is a memory. It is a part of the chip, and the redundancy efficiency in the column (or row) relief region is equal to the relief efficiency in the other column (or row) relief region.
[0099]
In the semiconductor memory, each relief area and the number of redundant elements corresponding thereto are determined based on the defect distribution prediction in the chip. As shown in FIG. 10, it is assumed that each memory chip is composed of a plurality of memory arrays each having a capacity C [Mbit] (only two MA <0> and <1> are shown in the figure). Assume that the row relief areas by the redundant row elements RLEMENT <0> and RLEMENT <1> provided in each memory array are the memory arrays MA <0> and <1>, respectively.
[0100]
Now, it is assumed that four redundant column elements are required for the column relief area of capacity (2/3) C [Mbit] as the column relief efficiency from the defect distribution prediction. In the case of FIG. 10, the column relief area CRA <A>, which is a 2/3 area of the memory array MA <0>, includes four redundant column elements CELEMENT <0: 1>, <2: 3>, and similarly memory The column relief area CRA <C>, which is a 2/3 area of the array MA <1>, includes four redundant column elements CELEMENT <8: 9>, <10:11>. At this time, it becomes a problem how many redundancy elements are provided in the remaining 1/3 of the memory arrays MA <0> and <1>.
[0101]
If the remaining capacity (1/3) C [Mbit] is used as each column repair area and two redundant column elements are arranged for each, the repair efficiency for this column repair area is (2/3) C It is lower than that for column repair areas CRA <A> and <C> having four redundant column elements for [Mbit]. This is because if the number of redundancy elements per unit capacity is the same, the greater the relief area, the higher the relief efficiency. If the relief efficiency of only a part of the relief area of the chip is lower than that of the other relief areas in this way, the yield of the whole chip will be lowered accordingly.
[0102]
On the other hand, if three or more redundant column elements are provided for the column relief region of capacity (1/3) C [Mbit], the relief efficiency can be increased. However, in this case, only the column relief area of the capacity (1/3) C [Mbit] has an unnecessarily high relief efficiency, or the number of redundancy elements per unit capacity is increased, leading to an increase in the chip area. In general, a memory array is configured by repeatedly arranging a plurality of sub-arrays having the same capacity. In many cases, the same number of redundancy elements are arranged in each sub-memory array, so that the number of redundancy elements is increased only for some sub-arrays. This complicates the array configuration in terms of layout and circuit, leading to performance degradation and chip area increase.
[0103]
Therefore, in the fourth embodiment, as shown in FIG. 10, two redundant column elements are provided for the remaining 1/3 of each memory array, and adjacent memory arrays MA <0>, <1> are provided. The two capacity (1/3) C [Mbit] areas are collectively referred to as one column relief area CRA <B>. Redundant column elements for the column relief area CRA <B> of the capacity (2/3) C [Mbit] collected in this way are four elements of CELEMENT <4: 7>.
[0104]
In this case, paying attention to the overlapping area of the memory array MA <0>, which is one row relief area, and the column relief area CRA <B>, the same overlap as the redundant row element RLEMENT <0> corresponding to this overlapping area Looking at the relationship with the redundant column element CELEMENT <4: 7> corresponding to the region, CELEMENT <4: 5>, which is a part of the redundant column element CELEMENT <4: 7>, intersects with the redundant row element RLEMENT <0>. However, the other part of CELEMENT <6: 7> does not cross the redundant row element RLEMENT <0>. Therefore, in this embodiment, a case where redundant row elements and redundant column elements that do not intersect with each other in a certain overlap region and a case where redundant row elements and redundant column elements that intersect each other are used are mixed. It can be seen that this is a modification of Form 2.
[0105]
In addition, the row relief area MA <0> by the redundant row element RELEMENT <0> in the memory array MA <0> and the column relief area by the redundant column element CEREMENT <6: 7> in the memory array MA <1> are: The redundant column element CELEMENT <6: 7> has an overlapping area and does not intersect with the redundant row element RELEMENT <0> on the memory array MA <0> side, and the redundant row element on the adjacent memory array MA <1> side. Crosses RELEMENT <1>. That is, the relief area MA <0> to which RELEMENT <0> is assigned and the relief area MA <1> to which RELEMENT <1> is assigned are adjacent to each other. This aspect is also a modification of the third embodiment.
[0106]
In FIG. 10, when attention is paid to the overlapping area between the row relief area MA <0> and the column relief area CRA <B>, there exists an area other than the overlap area in the row relief area MA <0>. Since there is an area other than the overlapping area in CRA <B>, this is the form described in the first embodiment, in which the row and column relief areas intersect so as to partially overlap.
[0107]
In this way, in the embodiment of FIG. 10, the redundant column element CELEMENT <4: 7> corresponding to the overlapping area does not intersect the redundant row element RELEMENT <0> corresponding to the same overlapping area. It can be seen that the column relief area CRA <B> that forms the overlapping area is a part of the memory chip. Since four redundancy elements are prepared for the capacity (2/3) C [Mbit] for the repair of the column defect in the column repair area CRA <B>, the repair efficiency of the other column repair area It can be seen that it is the same as in CRA <A>, <C>.
[0108]
Therefore, according to this embodiment, the repair efficiency in all the repair regions in the chip can be uniformly set to a necessary and sufficient value, and a memory chip with a high yield and a minimized area can be realized. Become.
[0109]
[Embodiment 5]
Next, in the fifth embodiment, with respect to a plurality of row (or column) relief areas existing in a memory chip, the relief areas in the column relief area (or row relief area) are mixed by mixing those having different capacity of the relief areas. It is configured so that the efficiency is uniform over the entire chip.
[0110]
An example of the memory array configuration is shown in FIG. This is the result of moving the area on the memory array MA <1> side of the column relief area CRA <B> in FIG. 10 (1/3 capacity portion of the memory array) to the memory array MA <0> side. As a result, two column relief areas A and B are set in one memory array MA <0>, and one column relief area C is set in the other memory array MA <1>. Therefore, the capacity of the memory array MA <0> is (4/3) C [Mbit], and the capacity of the memory array MA <1> is (2/3) C [Mbit]. Redundant row elements RELEMENT <0> and <1> are provided for each. That is, row relief regions having different capacities are mixed in the memory chip.
[0111]
Also in this method, the column redundancy in all the column relief regions in the memory chip is 4 elements with respect to the capacity (2/3) C [Mbit]. Therefore, the repair efficiency in all the column repair regions in the memory chip can be made to a necessary and sufficient value, and a chip with a high yield and a minimized area can be realized.
[0112]
However, in this embodiment, the wiring length of the word line and the wiring length of the sense amplifier control signal or the like running in the word line direction in the sense amplifier region are different between the memory arrays MA <0> and <1>. For this reason, it is necessary to pay sufficient attention to the row system circuit design. Further, since the capacity of the row relief area is different between the memory array MA <0> and the memory array MA <1>, the relief efficiency in the row relief area is also different as a result. Therefore, it is preferable to apply when the difference does not affect the relief efficiency of the entire chip.
[0113]
[Embodiment 6]
The sixth embodiment shown in FIG. 12 is an example in which the fourth embodiment is applied to a 32 Mbit DRAM. In this embodiment, a redundant column element corresponding to the same overlapping area as a redundant row element corresponding to an overlapping area of the row and column relief areas includes a non-crossing redundant column element and a part of the memory chip forming the overlapping area. A column (or row) relief area is used as a memory cell portion for check bits (parity bits) for error detection / correction. Specifically, each of the memory arrays MA <0> and <1> has a parity data portion for storing parity bits for error detection / correction for 2 Mbits in the normal data portion of 16 Mbits. It has a capacity of 36 Mbit.
[0114]
In the left memory array MA <0>, a redundant row array including a plurality of redundant row elements RELEMENTA <0: n> (n is a natural number) is arranged as an array different from the normal cell array. Each of the redundant row elements RELEMENTA <0: n> is allowed to replace any normal row element in the 18 Mbit memory array MA <0>. Therefore, the row relief area by each of the redundant row elements RELEMENTA <0: n> is the entire left 18 Mbit memory array MA <0>.
[0115]
Similarly, a redundant row array is also arranged in the right memory array MA <1>, and there are a plurality of redundant row elements RELEMENTB <0: n> (n is a natural number). The row relief area by the redundant row element RELEMENTB <0: n> is also the entire 18 Mbit memory array MA <1> on the right.
As described above, the system having the separate array for redundancy can increase the repair area by the redundant element, and thus can increase the replacement efficiency.
[0116]
Each memory array MA <0>, <1> is divided into 16 submemory arrays in the column direction by sense amplifier banks (regions in which a plurality of sense amplifiers S / A are continuously arranged). When a certain row address is input, as illustrated by hatching in FIG. 12, two subarrays in each memory array are activated simultaneously, and one normal row element in each subarray, and therefore four in the entire chip. These normal row elements are activated simultaneously. These four normal row elements correspond to the same row address, and the left and right normal row elements can be independently replaced by redundant row elements.
[0117]
The 16 Mbit normal data portion and 2 Mbit parity data portion of each of the memory arrays MA <0> and <1> are each composed of 16 1 Mbit segments and 2 1 Mbit segments. Each segment has one redundancy spare column selection line SCSL for redundancy. In the normal data part, 4 segments are grouped together to form a 4 Mbit quadruple segment QSEG. Therefore, each memory array MA <0>, <1> has four quadruple segments QSEG <0> to <3> and QSEG <4> to <7>. In the parity data section, two segments are gathered to form a 2 Mbit double segment (DSEG) DSEG. The memory array MA <0>, <1> includes two double segments Parity DSEG <0>, There is <1>.
[0118]
When reading data from this chip, a total of 8 (one in each of the left and right memory arrays) is used, one from each quadruple segment QSEG, with four (two in the left and right memory arrays) normal row elements activated. 4 column select lines CSL (not shown) are simultaneously activated. As a result, data of 16 m [bits] (m: natural number) is read from the entire chip, and one column selection line in two parity double segments DSEG (Parity DESG <0>, Parity DSEG <1>). CSL is activated to read 2m [bits] parity data. That is, data is read out by m [bits] from the intersection of the row element activated simultaneously and the column selection line CSL. In addition, it is possible to simultaneously read / write data from each memory array MA <0>, <1> in this way because the row elements are simultaneously activated in each memory array MA <0>, <1>. It has become.
[0119]
Also, when a defect in the quadruple segment QSEG of the normal data portion is remedied by a redundant column element, four spare column selection lines SCSL in the quadruple segment QSEG are used to provide two parity double segment DSEG (Parity DESG <0>, Parity DSEG <1>) When repairing a defect in the whole with a redundant column element, four spare CSLs among them are used.
[0120]
It should be noted that in this embodiment, the spare column selection line SCSL continuous in the memory array is divided into eight by the 3-bit input row address AR <0: 2>, and each of them is independent. This is used as a redundant column element. As described above, the spare column selection line is divided by the row address in consideration of the following circumstances. If a row element is activated and a column selection line is activated, whether it is a normal column selection line CSL or a spare column selection line SCSL, an activated row element and an activated column selection The cell specified by the line is read or written. Here, a plurality of row elements corresponding to a row address are simultaneously activated in the same memory array, and a column address corresponding to a normal column selection line CSL including a defect is input, and a spare is used instead of the normal column selection line CSL. When the column selection line SCSL is activated, spare cells are not read or written to a plurality of cells that should have been selected by the normal column selection line CSL on a plurality of row elements activated simultaneously in the same memory array. A plurality of cells selected by the column selection line SCSL are read or written.
[0121]
Thus, cells on a plurality of row elements that are simultaneously activated in the same memory array are always replaced together when they are replaced with spare column selection lines. Therefore, spare cells on a plurality of simultaneously activated row elements (for example, word lines) that are simultaneously selected and read / written simultaneously using the same spare column selection line must belong to the same redundant column element. However, spare cells on row elements (word lines) that are not read or written at the same time may not belong to the same redundant column element.
[0122]
FIG. 13 shows a state in which a plurality of redundant column elements are formed by one spare column selection line by assigning a row address to the spare column selection line SCSL, and two adjacent subarrays (memory blocks) MB0 sharing a sense amplifier. , MB1. The subarrays MB0 and MB1 are divided into four areas A, B, C, and D determined by row addresses AR0 and AR1. In the shared sense amplifier system, adjacent subarrays sharing the sense amplifier cannot be activated at the same time. Now, if a row address is input and only one word line is activated in the range of this subarray, the activated word line is in one of the regions A, B, C, and D.
[0123]
Since spare cells on a plurality of row elements (word lines) that are not simultaneously read and written because they are not activated simultaneously do not have to belong to the same redundant column element, spare cells on spare column selection line SCSL are assigned row addresses AR0 and AR1. Thus, it is possible to classify the spare cell sets into independent redundant column elements. In this way, one spare column selection line SCSL is constituted by four redundant column elements CELEMENT <0: 3> determined by the row addresses AR0 and AR1. Since this method can increase the number of redundant elements without increasing the number of spare cells, it is an area efficient redundancy system.
[0124]
Each redundant column element of CELEMENT <0: 3> has a different column address if the fuse set corresponds to each redundant column element CELEMENT <0: 3> (although it does not necessarily correspond one-to-one). Can be programmed to replace If the addresses of all the columns of this memory array can be programmed into each fuse set, CELEMENT <0: 3> can replace all defective cells in regions A, B, C, and D, respectively. That is, the column relief areas by CLEMENT <0: 3> are A, B, C, and D, respectively.
[0125]
In addition, since spare cells on a plurality of row elements (word lines) that are simultaneously read and written using the same spare column selection line and are simultaneously activated in the same weight array belong to the same redundant element, the same memory The row elements (word lines) that are simultaneously activated and simultaneously read and written in the array must be in the same row relief area.
[0126]
As described above, in order to substantially increase the number of redundant column elements by assigning row addresses without physically increasing spare column selection lines, for example, the method disclosed in US Pat. Any suitable method can be used. An example in which one spare column selection line is used as substantially four redundant column elements with 2-bit row addresses AR0 and AR1 will be specifically described.
[0127]
In this case, as shown in FIG. 14, four fuse sets selected by row addresses AR0 and AR1 are used for one spare column selection line. FIG. 14 shows one fuse FSn <0: 3> corresponding to one address An in four fuse sets, and a data latch LATn <0: 3> for holding each fuse data. These fuse data are selected by a fuse set selection circuit 51 into which a fuse set selection signal FSEL <0: 3> is input, and transferred to an EXOR gate 52 which is an address comparison circuit.
[0128]
The selection signals FSEL <0: 3> are generated by a decoding circuit 53 that decodes the row addresses AR0 and AR1, as shown in FIG. This selection signal FSEL <0: 3> is generated before the column address is input and is supplied to the fuse set selection circuit 51. Accordingly, a fuse set that has a possibility of hitting corresponding to the redundant column element assigned to the column relief area corresponding to the activated row element is selected by the row address, and a plurality of fuse sets are selected as shown in FIG. Circuits after the address comparison circuit can be shared.
[0129]
As a result, a portion obtained by dividing one spare column selection line into four parts can be used as independent redundant column elements, and column replacement control can be performed for defective column relief areas assigned to the respective redundant column elements.
[0130]
In the 32 Mbit DRAM of FIG. 12, the spare column selection line SCSL is divided into eight by the 3-bit input row address (AR <0: 2>) in this manner to form eight redundant column elements. Therefore, each of the quadruple segment QSEG <0: 7> in the normal data portion and the entire two double segment parityDSEG <0: 1> in the parity data portion are each divided into eight column repair areas. Two simultaneously activated areas (shaded areas) in each QSEG <0: 7> and in the entire two Parity DSEG <0: 1> in FIG. 12 correspond to the same set of row addresses AR <0: 2>. Therefore, it belongs to the relief area of the same redundant column element and is called a linked partial relief area.
[0131]
For example, the left memory array MA <0>, which is a row relief area by redundant row elements RELEMENTA <0: n>, and a column relief area, which is 1/8 of the entire two Parity DSEG <0: 1>. The overlapping overlapping areas are two hatched areas of Parity DSEG <0>. The redundant row element RLEMENTA <0: n> corresponding to this overlapping region intersects with the redundant column element corresponding to this overlapping region belonging to the spare column selection line SCSL in the Parity DSEG <0>, but is adjacent to the memory array. It does not intersect with the redundant column elements corresponding to the same overlapping region belonging to the spare column selection line SCSL in the Parity DSEG <1> of MA <1>.
[0132]
That is, a cell on the redundant row element RLEMENTA <0: n> can be selected by the spare column selection line SCSL in the Parity DSEG <0>, but the RLEMENTA <0 by the spare column selection line SCSL in the Parity DSEG <1>. : The cell above n> cannot be selected. Therefore, it can be seen that this embodiment is an aspect of the second embodiment.
[0133]
In addition, the redundant column elements corresponding to the two overlapping regions belonging to the spare column selection line SCSL in the Parity DSEG <1> are row relief regions (the left memory array MA <0>) that form the two overlapping regions. And redundant row element RLEMENTB <0: n> corresponding to the adjacent row relief area (the memory array MA <1> on the right side). This is also an aspect of Embodiment 3.
[0134]
Looking at column redundancy, there are four parity cell data parts for the column repair area (512 Kbit), which is 1/8 of the 4 Mbit part composed of two double segments DSEG (Parity DSEG <0: 1>). There are redundant column elements. Since this is the same as the column redundancy efficiency in the column relief area of the normal data portion, it can be seen that this is also an aspect of the fourth embodiment.
[0135]
Since the parity data portion has a halfway capacity with respect to the normal data portion, it is generally difficult to align the repair efficiency of the parity data portion with that of the normal data portion. However, if the parity data section that spans multiple memory arrays (for example, two as in this embodiment) is used as one column repair area, the repair efficiency of the parity data section can be aligned with that of the normal data section. It becomes. As a result, the repair efficiency in all the repair areas in the memory chip including the parity data portion can be made equal to a necessary and sufficient value, so that a chip with a high yield and a minimized area can be realized. .
[0136]
By the way, in the sixth embodiment, the normal row element for selecting the cell in the overlapping area of the memory array MA <0>, which is the row relief area, and the column relief area in the parity data portion is the cell in the overlap area. Replace the 1/8 portion of the normal column selection line CSL for selection, but do not intersect with the redundant column element which is the 1/8 portion of the spare column selection line SCSL in the memory array MA <1>, but its overlapping region It can be said that the normal column element for selecting the cell in the intersection intersects the redundant row element in another array that replaces the normal row element for selecting the cell in the overlapping region.
[0137]
Here, the normal row element does not intersect with the redundant column element means that the cell on the redundant column element is not selected when selecting the normal row element, that is, even when the normal row element is replaced by the redundant row element. That is, the cell corresponding to the row address of the normal row element to be replaced on the redundant column element is not necessarily replaced. Here, “not necessarily” is not limited to the case where another normal row element that selects a cell corresponding to the row address of the normal row element to be replaced on the redundant column element is also replaced by another redundant row element. Because.
[0138]
In addition, it can be said that the normal column element for selecting the cell in the overlapping region intersects the redundant row element in another array is the normal column element which is 1/8 of the normal column selection line CSL. This is because a cell on a redundant row element can be selected by selecting a normal column selection line CSL that includes it. When the normal column element is replaced with a redundant column element, the cell corresponding to the column address of the normal column element to be replaced on the redundant row element is also replaced.
[0139]
In the example of FIG. 10, the total capacity 2C of the two memory arrays MA <0> and <1> is divided into three to set the normal data area and the parity data area. Also, in the example of FIG. 12, the normal data area and the parity data area are set by dividing the total capacity 2C of the two memory arrays MA <0> and <1> into nine. To generalize these embodiments, the normal data area and the parity data area are set by dividing the total capacity 2C of the two memory arrays MA <0> and <1> into M (integer of 3 or more). can do.
[0140]
At this time, as the normal data area, first (M−1) / 2 first column relief areas each having a capacity of 2C / M each including N (integer greater than or equal to 2) redundant column elements are memory arrays MA <0. >, <1>. As the parity data area, a second column relief area having a capacity of 2 C / M is set so as to span the two memory arrays MA <0> and <1>. Thereby, the column relief efficiency of the normal data area and the parity data area is the same.
[0141]
[Embodiment 7]
16A and 16B show an embodiment in which the present invention is applied to a semiconductor memory having hierarchical word lines. In the hierarchical word line system, as shown in FIG. 16A, a plurality of sub word lines SWL are arranged for one low resistance main word line MWL. The sub word line SWL is driven by a sub word line driver SWLDRV connected to a plurality of locations of the main word line MWL. Here, one main word line MWL corresponds to a plurality of row addresses, and a plurality of sub word line drivers SWLDRV may be connected at several locations of the main word line MWL (separately for each driven sub word line SWL). Row address corresponds), or one main word line MWL corresponds to one row address, and one sub word line driver SWLDRV is connected to the main word line MWL at each of several connection points of the main word line MWL. It may be.
[0142]
As described above, in the hierarchical word line system, one logical word line (corresponding to one row address) is logically composed of a plurality of sub word lines. Then, as indicated by broken lines in FIG. 16B, a plurality of sub word lines SWL are activated simultaneously. As a result, the length of the sub-word line can be shortened. As a result, the word line delay is reduced and high-speed operation is possible. In addition, by activating only a part of the sub word line drivers connected to the main word line, it is possible to limit the array area to be activated, thereby reducing the number of sense amplifiers that are simultaneously operated and reducing power consumption. There are advantages that the sense amplifier can be operated at a high speed by suppressing it to a low level or suppressing internal power supply noise during the operation of the sense amplifier.
[0143]
In such a hierarchical word line system, in order to increase row redundancy relief efficiency, replacement is not performed in units of one or more main word lines, but in units of one sub word line or main word lines. It is performed in units of a plurality of sub word lines arranged in a direction orthogonal to each other, or a plurality of sub word lines or one sub word line arranged in a direction orthogonal to the main word line are collectively replaced in the longitudinal direction of the word lines. It can be considered as a unit. Correspondingly, the redundant row element is configured by a plurality of or one spare sub word line arranged in a direction orthogonal to the word line, or some of these redundant elements are redundantly arranged in the longitudinal direction of the word line. It can be a low element. Here, the plurality of spare sub-word lines arranged in the direction orthogonal to the word lines constituting the redundant row element are not necessarily arranged continuously. Further, even when one or a plurality of spare sub word lines are grouped together in the longitudinal direction of the word line to form a redundant row element, it is not always necessary to group consecutive ones.
[0144]
In such a row redundancy system, if the length of the sub word line is shortened, the relative ratio of the width of the row relief region in the word line direction to the width of the column relief region in the word line direction is considered to be small. . At the same time, if the number of redundant column elements is constant, it is considered that the number of redundant column elements intersecting with the redundant row element is reduced. Further, when the length of the sub word line is shortened, there may be a redundant row element that does not intersect the redundant column element at all.
[0145]
FIG. 16B shows the redundancy system together with the layout of the memory array, focusing on the sub word line SWL layer. Here, a row relief region, which is a set of row elements that can be rescued by a certain redundant row element RELEMENT, is a plurality of sub word lines SWL driven by a plurality of sub word line drivers SWLDRV arranged in a line in a direction orthogonal to the word lines. Consists of. The row relief region and the row relief region adjacent thereto in the word line direction are configured such that the sub word lines SWL constituting each row relief region are physically (spatially) nested. . The redundant row element RELEMENT is formed by one spare sub word line SSWL or a plurality of spare sub word lines SSWL arranged in a direction perpendicular to the word line, or a plurality of one to a plurality of spare sub word lines SSWL. Consists of several shapes in the line direction. At this time, when the redundant row element is constituted by a plurality of spare sub-sub word lines SSWL, the plurality may be continuously arranged or may not necessarily be consecutive.
[0146]
FIG. 16B shows one redundant column element CELEMENT composed of one or a plurality of spare column selection lines and one column repair area CRA repaired by this, but in this column repair area CRA, The relief areas RRA <a>, <b>, <c> are included, and the two row relief areas RRA <d>, <e> intersect.
[0147]
Among the redundant row elements, RELEMENT <A> corresponding to the overlapping region of the row repairing region RRA <a> and the column repairing region CRA intersects with the redundant column element CELEMENT corresponding to the overlapping region, but another row repairing region. RELEMENT <B> corresponding to the overlapping area of RRA <c> and the column repair area does not cross the redundant column element CELEMENT corresponding to the overlapping area.
[0148]
With reference to FIG. 17, the row redundancy system in the hierarchical word line system of this embodiment will be specifically described. Although column redundancy is not described here, any of the systems described in the previous embodiments can be applied. As shown in FIG. 17, the cell array has a plurality of memory arrays MA <0>, <1>, <2>,. A main word line MWL (representatively, only one) is provided across these memory arrays, and a sub word line SWL simultaneously selected by the main word line MWL is provided for each memory array. . These sub word lines SWL are used to select a plurality of memory cells arranged in the direction of the word lines in the memory array. Each sub word line SWL becomes a normal row element which is a unit for defective row replacement.
[0149]
The row decoder includes a main word line decoder 61 for selecting the main word line MWL and a sub word line decoder 62 for driving the sub word line SWL provided for each memory array. In each sub word line decoder 62, there is a sub word line driver 63 for driving the sub word line SWL corresponding to the selected main word line MWL.
[0150]
Corresponding to main word line MWL, at least one spare main word line SMWL is arranged across the memory array. Spare sub word lines SSWL simultaneously selected by spare main word line SMWL are arranged as redundant row elements in each memory array. These spare sub word lines SSWL are selected by a spare main word line SMWL and are driven by a spare sub word line triber 64 in a spare word line decoder 62 to select a spare cell.
[0151]
A row replacement control circuit 65 is prepared for each spare word line decoder 62. The row replacement control circuit 65 includes a defective address storage circuit and an address comparison circuit, similarly to the row replacement control circuits 31a and 31b described above with reference to FIG. The row address data RA transferred to the row address signal line 67 is supplied to the main word line decoder 61 and the sub word line decoders 62 and simultaneously to the row replacement control circuits 65.
[0152]
The row replacement control circuit 65 has a first activation signal 68 for activating the spare main word line SMWL and a second activation for activating the spare sub word line SSWL when a defective address is input. The signal 69 is output. The first activation signal 68 is sent to the main word line decoder 61 to activate the spare main word line SMWL. However, at this time, the selected normal main word line MWL is kept in an active state without being inactivated. This is a necessary condition for replacing only a part of the plurality of sub word lines SWL selected simultaneously by the main word line MWL.
[0153]
A second activation signal 69 output from a certain row replacement control circuit 65 deactivates a defective sub word line SWL among a plurality of sub word lines SWL selected by the main word line MWL, and is selected by a spare word line. The corresponding spare sub word line SSWL is activated. By such control, in the example shown in FIG. 17, the defective sub word line SWL in the memory array MA <2> is replaced with the spare sub word line SSWL in the same memory array MA <2>.
[0154]
In FIG. 17, the main word line MWL and the spare main word line SMWL may be configured by one signal line or may be two complementary signal lines. In addition, a plurality of sub word lines SWL selected by one main word line MWL in each memory array may be arranged in a direction orthogonal to the main word line. In this case, a plurality of spare sub word lines SSWL are similarly arranged for one spare main word line SMWL in each memory array.
[0155]
In this case, a bundle of a plurality of sub word lines SWL arranged in a direction orthogonal to the main word line can be replaced with one row element, and a bundle of a plurality of spare sub word lines SSWL can be replaced with one redundant row element. . In this case, the state in which the row elements are simultaneously activated means a state in which any sub word line is activated in each row element.
[0156]
Alternatively, each of the plurality of sub word lines SWL arranged in a direction orthogonal to the main word line can be replaced with one row element, and each of the plurality of spare sub word lines SSWL can be replaced with one redundant row element. In order to perform the latter replacement control, a separate row address or a dedicated row address for redundancy is assigned to each sub word line and each spare sub word line. Accordingly, the row replacement control circuit 65 also programs the address storage circuit to generate the activation signal 69 reflecting the row address information. The generated activation signal 69 has row address information dedicated to the redundancy. Further, when there are a plurality of spare word lines, the first activation signal 68 may include redundancy dedicated address information for selectively selecting each spare main word line.
[0157]
Although the hierarchical word line system has been described above, a similar redundancy system can be configured also in the hierarchical column selection line system. In this case, a plurality of sub column selection lines are arranged for one main column selection line, and the sub column selection lines are driven by sub column selection line drivers connected to a plurality of locations of the main column selection lines. The redundant column element is configured by a single spare sub-column selection line arranged in parallel with the column selection line, or a plurality of redundant column elements arranged in the column selection line direction. At this time, when the redundant column element is composed of a plurality of spare sub-column selection lines, the plurality of redundant column elements may be continuously arranged or may not necessarily be continuous.
[0158]
In addition to the case where the redundant column element is constituted by one spare column selection line or a part obtained by dividing this by a row address as described above, one or a plurality of pairs of spare bit lines (or a part thereof) is used. ) Can also be used.
[0159]
【The invention's effect】
As described above, according to the present invention, a redundancy system with high relief efficiency can be obtained.
[Brief description of the drawings]
FIG. 1 is a diagram showing a semiconductor memory redundancy system according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating an example in which a column relief area and a row relief area partially overlap.
FIG. 3 is a diagram illustrating an example in which a row relief area is included in a column relief area.
FIG. 4 is a diagram illustrating an example in which a column relief area is included in a row relief area.
FIG. 5 is a diagram illustrating an example in which a row relief area and a column relief area completely match.
FIG. 6 is a diagram illustrating a configuration of a replacement control circuit unit.
FIG. 7 is a diagram showing a specific example of the replacement control circuit.
FIG. 8 is a diagram showing a configuration of one fuse data latch circuit of the replacement control circuit;
FIG. 9 is a diagram showing a redundancy system for a semiconductor memory according to another embodiment of the present invention.
FIG. 10 is a diagram showing a redundancy system for a semiconductor memory according to another embodiment of the present invention.
FIG. 11 is a diagram showing a redundancy system for a semiconductor memory according to another embodiment of the present invention.
FIG. 12 is a diagram showing a redundancy system for a semiconductor memory according to another embodiment of the present invention.
FIG. 13 is a diagram for explaining a redundant column element setting method according to the embodiment;
FIG. 14 is a diagram showing a configuration of a fuse setting circuit when a spare column selection line is used in four divisions.
FIG. 15 is a diagram showing a configuration of a fuse set selection signal generation circuit based on row addresses.
FIG. 16A is a diagram showing a hierarchical word line configuration of a semiconductor memory according to another embodiment of the present invention;
FIG. 16B is a diagram showing a layout of a sub word line layer having the same hierarchical word line configuration;
FIG. 17 is a diagram illustrating a configuration example of a row replacement control circuit unit according to the same embodiment;
FIG. 18 is a diagram showing a conventional semiconductor memory redundancy system;
FIG. 19 is a diagram showing a state of defect replacement in an overlapping area of a row relief area and a column relief area of the conventional example.
FIG. 20 is a diagram showing a memory chip configuration for explaining a problem of the prior art.
[Explanation of symbols]
MA <0: 1>... Memory array, RELEMENT <0: 1>... Redundant row element CELEMENT <0: 1>.

Claims (22)

A cell array having a plurality of memory cells;
A plurality of first normal elements including a set of memory cells in the first direction defined in the cell array and a first selection line for selecting the memory cells;
A plurality of memory cells are selected in cooperation with the corresponding first normal elements including a set of memory cells in the second direction defined in the cell array and a second selection line for selecting the memory cells. A second normal element;
A plurality of first redundant elements arranged to replace a defective first normal element in the cell array;
A plurality of second redundant elements arranged to replace a defective second normal element in the cell array;
A first relief region defined as a set of first normal elements that are allowed to be replaced by each first redundant element in the cell array;
A second relief region defined as a set of second normal elements allowed to be replaced by each second redundant element in the cell array;
At least two of the plurality of first normal elements are simultaneously activated,
Whether at least two first normal elements that are simultaneously activated are replaced by the first redundant element is controlled independently of each other, and is one of the first normal elements that are simultaneously activated. At least one of the second redundant elements that replaces the second normal element having a defect in the first relief region including the first normal element does not intersect with the one of the first normal elements that are simultaneously activated A semiconductor memory device. A second normal element having a defect in the first relief region including one of at least two first normal elements that are simultaneously activated is the simultaneous activation of the plurality of second redundant elements. 2. The semiconductor memory device according to claim 1, wherein said semiconductor memory device is also replaced by a second redundant element that intersects said one of said at least two first normal elements. The first relief region including one of at least two first normal elements that are simultaneously activated and the first relief region including the other one are disposed adjacent to each other,
One of the second redundant elements intersects the other one of the at least two first normal elements to be simultaneously activated, and the at least two first normal elements to be simultaneously activated. 3. The semiconductor memory device according to claim 1, wherein a second normal element having a defect in a first relief region including one is replaced. At least three first relief regions each including one of at least three first normal elements that are simultaneously activated are sequentially arranged, and at least three first activation regions that are simultaneously activated At least two second redundant elements that can replace a second normal element having a defect in one of the first relief areas including one of the normal elements are at least three first active elements that are activated simultaneously. 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device intersects with any of the remaining normal elements. 4. The semiconductor memory device according to claim 3, wherein a selection circuit for selecting a first normal element is arranged between the first relief regions arranged adjacently or successively. The cell array has first and second memory arrays adjacent to each other across a row decoder,
At least one of the first normal elements of the first and second memory arrays is simultaneously activated by the row decoder in response to a row address from the first and second memory arrays,
The plurality of first redundant elements are arranged at least one corresponding to the first and second memory arrays, and independently of each other, a first defect in each of the first and second memory arrays. Used to replace the normal element of
The plurality of second redundant elements are arranged at least one in each of the first and second memory arrays so as to intersect the first redundant elements in each memory array, and are independent of each other. 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is used for replacement of a second normal element of a defect in the second memory array. A column decoder for selecting a second normal element of each of the first and second memory arrays;
A redundant row decoder which is activated by a row replacement control signal generated in response to a defective row address to select each of the first redundant elements;
A redundant column decoder for selecting each of the second redundant elements, activated by a column replacement control signal generated in response to a defective column address;
The row replacement control signal and the column replacement control signal are output in accordance with a defective address, and are defined in one of the first and second memory arrays, and a first normal element in the first and second memory arrays is provided in one of the memory arrays. The first redundancy area replaceable by the first redundant element arranged correspondingly, and the second redundancy element in which the second normal element therein is arranged corresponding to the other of the memory array 7. The semiconductor memory device according to claim 6, further comprising a replacement control circuit configured to have an overlapping region at least partially overlapping with a second relief region that can be replaced by an element. First relief areas to which the first redundant elements are assigned are set in the first and second memory arrays, respectively;
8. The semiconductor memory device according to claim 6, wherein the second relief area to which the second redundant element is allocated is set across the first and second memory arrays. The cell array includes three or more memory arrays that are continuous with a row decoder that simultaneously selects at least one first normal element in response to a row address,
The plurality of first redundant elements are arranged to be used for replacement of the first normal element of a defect in each memory array, independently of each other, at least one corresponding to each memory array,
The plurality of second redundant elements intersect with the first redundant element in the corresponding memory array at least one in each of the memory arrays, and in the at least one selected memory array independently of each other 5. The semiconductor memory device according to claim 4, wherein the semiconductor memory device is arranged so as to be used for replacement of the second normal element of the defect. Each of the first normal elements has one or more word lines as the first selection line,
Each of the first redundant elements has one or more spare word lines,
Each of the second normal elements has one or a plurality of bit lines or a part thereof,
10. The semiconductor memory device according to claim 1, wherein each of the second redundant elements has one or a plurality of spare bit lines or a part thereof. The first relief area defined by the first redundant element is a row relief area covering the entire memory array,
The second relief area includes N (N is an integer of 2 or more) redundant column elements, where C is the total cell capacity of each memory array, and has a capacity of 2 C / M (M is an integer of 3 or more). ) And the first column relief area set to (M−1) / 2 in each memory array and the two areas of the remaining capacity C / M of each memory array are combined into N redundant 9. The semiconductor memory device according to claim 8, further comprising a second column relief region having a capacity of 2 C / M set including the column element. The first column relief area is a normal data portion, and the second column relief area is a parity data portion for storing inspection data for error detection / correction of data in the normal data portion. The semiconductor memory device according to claim 11. Each of the memory arrays is divided into a plurality of sub-arrays that are assigned the same row address and are simultaneously activated by a predetermined number, and one spare column selection line continuously formed across the plurality of sub-arrays is: 13. The semiconductor memory device according to claim 6, wherein different row addresses are allocated and used as the plurality of second redundant elements. The cell array includes a plurality of memory arrays, a plurality of main word lines arranged across these memory arrays, a plurality of sub word lines arranged in each memory array and selected by each main word line, At least one spare main word line arranged across the plurality of memory arrays and at least one spare main word line arranged in each memory array, one of which is selected in each memory array by the spare main word line A spare sub-word line,
6. One or more of the sub word lines are used as the first normal element, and one or more of the spare sub word lines are used as the first redundant element. A semiconductor memory device according to item. Each of a plurality of memory cells, a plurality of normal row elements defined as a set of memory cells in the row direction in the memory array, and a plurality of normal column elements defined as a set of memory cells in the column direction in the memory array And first and second memory arrays activated simultaneously,
A redundant row element disposed at least one corresponding to each of the first and second memory arrays and used to replace a defective normal row element independently of each other;
At least one redundant column element corresponding to the first and second memory arrays is arranged to intersect with the redundant row element in the corresponding memory array and is used for replacing defective normal column elements independently of each other. And
A row repair area defined as a set of normal row elements that are allowed to be replaced by the redundant row element arranged in one of the first and second memory arrays, and a replacement by the redundant column element arranged in the other A semiconductor memory device, characterized in that it is set so as to have an overlapping region that at least partially overlaps a column relief region defined as a set of normal column elements that are allowed. 16. The semiconductor memory device according to claim 15, wherein the redundant column element in the memory array to which the overlapping region belongs is also used for replacement of a defective normal column element in the overlapping region. The first and second memory arrays are disposed adjacent to each other with a row decoder shared therebetween,
17. The semiconductor memory device according to claim 15, wherein the row decoder is configured to simultaneously select one normal row element of each of the first and second memory arrays. Each normal row element has one or more word lines,
Each redundant row element has one or more spare word lines,
Each normal column element has one or a plurality of bit lines, or a part thereof,
18. The semiconductor memory device according to claim 15, wherein each redundant column element has one or a plurality of spare bit lines or a part thereof. The row relief area defined by at least one redundant row element arranged corresponding to each memory array covers the entire memory array,
The column relief area has a capacity of 2 C / M (M is an integer of 3 or more) including N (N is an integer of 2 or more) redundant column elements, where C [bit] is the total cell capacity of each memory array. N redundant column elements are gathered by combining two areas of (M−1) / 2 set for each memory array and the remaining capacity C / M of each memory array. The semiconductor memory device according to claim 15, further comprising a second column relief region having a capacity of 2 C / M set including The first column relief area is a normal data part, and the second column relief area is a parity data part for storing inspection data for error detection / correction of data in the normal data part. The semiconductor memory device according to claim 19. Each of the memory arrays is divided into a plurality of sub-arrays that are assigned the same row address and are simultaneously activated by a predetermined number, and one spare column selection line continuously formed across the plurality of sub-arrays is: 21. The semiconductor memory device according to claim 15, wherein different row addresses are assigned and used as a plurality of redundant column elements. A cell array having a plurality of memory cells, a plurality of normal row elements defined as a set of memory cells in the row direction, and a plurality of normal column elements defined as a set of memory cells in the column direction;
A plurality of redundant row elements used to replace defective normal row elements of the cell array;
A plurality of redundant column elements used to replace defective normal column elements of the cell array,
In the cell array, at least two first and second row relief regions having different cell capacities defined as a set of normal row elements that are allowed to be replaced by the redundant row elements are set, and the plurality of redundant rows A semiconductor memory device, wherein repair efficiency in each column repair area defined as a set of normal column elements that are allowed to be replaced by column elements is set to be equal in the cell array.

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