JP3903861B2 - Information processing apparatus and diagnostic program - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having an output buffer having an automatic output impedance adjustment function, and a diagnostic program thereof. Regarding the program.
[0002]
[Prior art]
In semiconductor integrated circuits, it is known that signal reflection occurs when the output impedance of the output buffer does not match the impedance of the transmission line. Since the impedance of the transmission line is usually fixed, signal reflection can be suppressed by changing the impedance of the output buffer.
As shown in FIG. 6, the conventional output impedance matching circuit has a constant output potential of the replica buffer 4 connected to the external reference resistor 1 set so as to match the impedance of the transmission line when a normal system is started up. The output potential of the potential circuit 2 is compared with the voltage comparison circuit 3.
[0003]
Then, by inputting a count up / down signal to the adjustment counter 5 according to the comparison result, the adjustment counter 5 performs a count up / down operation, and a plurality of units connected in parallel in the replica buffer 4 by the adjustment counter output signal. Are selectively turned ON / OFF, and the value of the adjustment counter 5 converges when the output impedance of the replica buffer 4 matches the impedance of the external reference resistor 1.
[0004]
By setting the value of the adjustment counter 5 at this time to the main buffer 8 via the selection circuit 6 and the pre-buffer 7, the main buffer 8 composed of a plurality of MOSFETs connected in parallel as in the replica buffer 14. The MOSFET inside is selectively turned on / off.
[0005]
As a result, the output impedance of the main buffer 8 matches the impedance of the external reference resistor 1, and the output impedance of the logic signal from the main logic 9 matches the impedance of the transmission line.
[0006]
[Problems to be solved by the invention]
However, in the output impedance matching circuit, the adjustment counter 5 is not incorporated with the adjustment value HOLD (Up / Down suppression) function and the Read / Write function. There was no effective means of knowing the impedance adjustment value.
[0007]
For this reason, when any malfunction occurs during the evaluation of the system, there is a problem that it is difficult to determine whether the cause is due to the impedance adjustment circuit system.
[0008]
[Means for Solving the Problems]
According to a first information processing apparatus of the present invention, an output buffer having a plurality of transistors connected in parallel that can be selectively turned on / off and having an impedance adjustment function is counted according to a comparison result between an output potential and a reference potential. An information processing apparatus including an information processing apparatus main body including an impedance adjustment unit having an adjustment counter that is turned up / down to control on / off of the plurality of transistors, and a diagnosis processor that diagnoses or monitors the information processing apparatus main body, A read path from the diagnostic processor connected to the adjustment unit; and a selection circuit that selects the adjustment counter according to an address from the diagnostic processor and sends the adjustment counter to the read path, and reads the value of the adjustment counter from the diagnostic processor And
[0009]
A second information processing apparatus according to the present invention includes an output buffer having a plurality of transistors connected in parallel that can be selectively turned on / off and having an impedance adjustment function, and a plurality of transistors connected in parallel like the output buffer. Compare the output voltage of the replica buffer with the output of the replica buffer and the reference potential and output the result as an adjustment value up / down instruction. A circuit, an adjustment counter that counts up / down in response to the up / down instruction and converges to a value that matches the transmission line impedance, and means for controlling on / off of the plurality of transistors by the converged adjustment counter value Information processing apparatus main body including an impedance adjustment unit and a diagnostic processor for diagnosing or monitoring the information processing apparatus main body An information processing apparatus comprising: a read path from a diagnostic processor connected to the adjustment unit; and a selection circuit that selects the adjustment counter according to an address from the diagnostic processor and sends the adjustment counter to the read path. The status value is read from the diagnostic processor.
[0010]
A third information processing apparatus of the present invention is the first or second information processing apparatus, wherein a read path from a diagnostic processor connected to the adjustment unit, the read selection circuit, and an adjustment unit A write path from a diagnostic processor connected to the circuit, and a circuit that writes the data from the write path to the adjustment counter when the address from the diagnostic processor designates the adjustment counter and is instructed to write. Reading and writing from the diagnostic processor of the counter is performed.
[0011]
A fourth information processing apparatus according to the present invention is the third information processing apparatus, wherein the adjustment unit suppresses count-up / down of an adjustment counter based on a comparison result between an output potential and a reference potential, and A count-up / down-inhibiting flag that validates writing to the adjustment counter from the diagnostic processor and means for writing to the count-up / down-inhibiting flag according to an instruction from the diagnostic processor 300 are also provided.
[0012]
A fifth information processing apparatus according to the present invention is any one of the first to fourth information processing apparatuses, wherein the diagnostic processor stores a prescribed range of the adjustment counter value; and the information processing apparatus After performing the address designation in anticipation of a lapse of a predetermined time from the startup of the main body, the value of the adjustment counter is read and output through the read path, and it is determined whether the read value is within a specified range. And a means for outputting.
[0013]
The sixth information processing apparatus of the present invention is the third or fourth information processing apparatus, wherein the diagnostic processor stores a specified range of the adjustment counter value and an increase / decrease value of the adjustment; In anticipation of the elapse of a predetermined time from the startup of the information processing apparatus body, the count up / down suppression flag is set, the address is designated, and then the value of the adjustment counter is read and output through a read path. The means for determining whether the read value is within the specified range and outputting the determination contents, the presence / absence of trial adjustment designation is acquired, and if specified, the increase / decrease value is added to or subtracted from the read value Means for instructing writing of the adjusted value to the adjustment counter, reading out the adjustment counter value, determining whether the specified value has been set, and outputting the determination content.
[0014]
A first diagnostic program of the present invention is a program mounted on a diagnostic processor of any one of the first to fourth information processing apparatuses, and a predetermined range of the adjustment counter value is previously stored in a predetermined area of a storage unit. A procedure for storing and reading the value of the adjustment counter through a read path and outputting the value after performing the addressing in anticipation that a predetermined time or more has elapsed since the start of the information processing apparatus main body, and the read value is within the specified range And a procedure for outputting the determination content.
[0015]
A second diagnostic program of the present invention is a program installed in a diagnostic processor of the third or fourth information processing device, and stores a predetermined range of the adjustment counter value and an adjustment increase / decrease value in a storage unit in advance. Set the count-up / down-inhibit flag, specify the address, specify the address and then make the adjustment through the read path in anticipation of the procedure for storing in a predetermined area and that a predetermined time or more has elapsed since the startup of the information processing apparatus body The procedure reads out and outputs the counter value, determines whether the read value is within the specified range and outputs the determination contents, and obtains the presence or absence of trial adjustment designation. Instructs to write the value obtained by adding or subtracting the increment / decrement value to the adjustment counter, reads the adjustment counter value, determines whether it is set to the specified value, and outputs the determination contents And having a that procedure.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment of an information processing apparatus according to the present invention.
[0017]
Referring to this figure, the main body of the information processing apparatus of the present invention is connected in parallel with an external reference resistor 10 and a constant potential circuit 11 which are set to match the impedance of the transmission line as an impedance adjustment unit. The replica buffer 14 composed of a plurality of MOSFETs, the voltage comparison circuit 13 that compares the output potential 50 of the replica buffer 14 and the output potential 51 of the constant potential circuit 11, and a count that is a comparison result signal from the voltage comparison circuit 13 It includes an adjustment counter 15 that counts up / down by an up / down signal 52, and a selection circuit 16 that receives an adjustment counter output signal 53 and a logic signal 54 from the main logic 19.
[0018]
The buffer unit includes a pre-buffer 17 that receives a selection circuit output signal 55 and a main buffer 18 that receives a pre-buffer output signal 56.
[0019]
Also, the card / LSI is selected at the time of read / write and the read path 34 and the adjustment counter 15 for reading the value of the adjustment counter 15 around the adjustment counter and the write path 31 for writing to the up / down suppression flag of the adjustment counter 15 A bit address signal 33 for selecting a target bit, and a write instruction signal 30.
[0020]
The information processing apparatus includes a diagnostic processor 300. The diagnostic processor 300 controls the card / LSI selection signal 32, the bit address signal 33, and the write instruction signal 30, and sets the Up / Down suppression flag, and then the adjustment counter 15 The internal state value is read, and an edited value or a specified value is written to the adjustment counter 15.
[0021]
The predetermined area of the storage unit 301 of the diagnostic processor 300 holds the specified range value of the adjustment counter 15 and the adjustment increase / decrease value when performing the trial adjustment.
[0022]
FIG. 2 is a block diagram illustrating a detailed configuration of the impedance adjustment unit and the buffer unit of FIG. Referring to this figure, each main buffer 18 includes four FETs connected in parallel, and each FET is weighted for impedance when ON. The replica buffer 14 has the same configuration.
[0023]
The adjustment counter 15 is, for example, a 4-bit Up / down counter, and each bit output controls the gate of the corresponding FET of the replica buffer 14. When the logic signal 54 is ON, the corresponding FET gate of the main buffer is controlled.
[0024]
The bit address signal 33 received from the diagnostic processor 300 is decoded by the decoder 20 and becomes a suppression flag selection signal 33-1 and a counter bit i selection signal 33-2. This output is selected by the card / LSI selection signal 32 by the LSI 80. If it is, it will be activated.
[0025]
FIG. 3 is a block diagram showing a detailed configuration of the adjustment counter 15 of FIG. If the Up / Down suppression flag 152 is OFF, the count value of the adjustment counter 15 is incremented or decremented by a count-up / count-down signal 52 that is a comparison result signal from the voltage comparison circuit 13.
[0026]
That is, the input data obtained by incrementing / decrementing the value of the counter body 151 by the U / D signal is strobed to each bit F / F of the counter body 151.
[0027]
If the Up / Down suppression flag 152 is ON, the write instruction signal 30 is ON and the value of the write path 31 is strobed to the F / F of the counter body 151 specified by the counter bit i selection signal 33-2.
[0028]
That is, the logical product outputs 60-1,..., 60-4 of the CTWT signal and the counter bit i selection signal 33-2 (i: 0 to 3) in FIG. Strobe to the corresponding F / F. Note that the values of each F / F are held when any of the above strobes is OFF.
[0029]
Further, the Up / Down suppression flag 152 is reset by an initial reset at power-on, and the suppression flag selection signal 33-1 is turned ON (the bit address signal specifies the Up / Down suppression flag 152) under the control of the diagnostic processor 300. The value of the write path 31 is written in the same manner as described above by the write instruction 30. The written value is retained unless the power is turned off and on again.
[0030]
Next, the operation of the embodiment of the present invention will be described with reference to the drawings. First, the automatic adjustment operation performed by the impedance adjustment unit will be described with reference to FIG.
[0031]
In FIG. 2, the voltage comparison circuit 13 compares the output potential 50 of the replica buffer 14 connected to the external reference resistor 10 set so as to match the impedance of the transmission line with the output potential 51 of the constant potential circuit 11. ing.
[0032]
Since the count up / down signal 52 is input to the adjustment counter 15 according to the comparison result, the adjustment counter 15 counts up / down, and as a result, the adjustment counter output signal 53 is output. A plurality of MOSFETs connected in parallel are selectively turned ON / OFF.
[0033]
For example, when the initial value of the adjustment counter 15 is “0010”, the MOSFET corresponding to “0” among the plurality of MOSFETs connected in parallel in the replica buffer 14 is in the OFF state, and the MOSFET in the OFF state is infinite. Large resistance and no current flows.
[0034]
Further, the MOSFET corresponding to “1” among the plurality of MOSFETs connected in parallel in the replica buffer 14 is turned ON, the MOSFET in the ON state becomes a resistance and a current flows, and the output potential 50 of the replica buffer 14 is The voltage comparison circuit 13 compares the output potential 51 of the constant potential circuit 11 with the count up / down signal 52 as a comparison signal, and the adjustment counter 15 counts up / down. As a result, the ON / OFF state of each MOSFET in the replica buffer 14 is corrected.
[0035]
In this way, the value of the adjustment counter 15 converges when the output impedance of the replica buffer 14 matches the impedance of the external reference resistor 10. The value of the adjustment counter 15 at this time is set in the main buffer 18 via the selection circuit 16 and the pre-buffer 17.
[0036]
As a result, the MOSFET in the main buffer 18 composed of a plurality of MOSFETs connected in parallel as in the replica buffer 14 is selectively turned ON / OFF, and the output impedance of the main buffer 18 is the impedance of the external reference resistor 10. And the output impedance of the logic signal 54 from the main logic 19 matches the impedance of the transmission line.
Next, the reading and writing operations of the adjustment counter 15 by the diagnostic processor 300 will be described with reference to FIGS.
[0037]
After the Up / down suppression flag 152 is specified by the bit address signal 33 from the diagnostic processor 300, the Write path 31 is set to a valid value (eg, logic “1”), the Write instruction 30 is turned on, and this flag is set.
[0038]
As a result, the adjustment counter 15 shifts to the Up / Down inhibition state, and the internal state value of the adjustment counter 15 is held.
[0039]
Next, when each bit of the adjustment counter 15 is sequentially designated from the diagnostic processor 300 by the bit address signal 33, the selection of the counter bit i is sequentially turned on, and the internal state value of the adjustment counter 15 is read to the diagnostic processor 300 by the Read path 34. .
[0040]
Similarly, by designating each F / F of the adjustment counter 15 with the bit address signal 33 and then performing a Write instruction, writing is performed from the diagnostic processor 300 to the corresponding F / F of the adjustment counter 15 using the Write path 31.
When the diagnostic processor 300 makes a trial correction of the impedance adjustment value, an offset value (offset value) obtained by adding or subtracting a preset increase / decrease value to the read internal state value of the adjustment counter 15 is used as a write path. The output impedance of the main buffer 18 is changed by writing to the adjustment counter 15 from the diagnostic processor 300 using 31.
[0041]
For example, when the adjustment value of the adjustment counter 15 is “0110”, this value is stored, and the read value from the read path 34 is “0110”. When performing a trial correction of the impedance adjustment value, in the diagnostic processor 300, for example, “0001” is added to the read internal state value “0110” of the adjustment counter 15, and an offset value “0111” is added to the write path. The output impedance of the main buffer 18 is changed by writing to the adjustment counter 15 using the diagnostic processor 300 (see FIG. 1).
Next, the overall operation of the embodiment of the present invention will be described including the processing means or procedure of the diagnostic processor 300. 4 and 5 are flowcharts explaining the operation of the information processing apparatus according to the present invention from the diagnostic processor side, and are the processing procedure of the diagnostic program installed in the diagnostic processor 300. FIG.
[0042]
Referring to FIG. 4, impedance adjustment is automatically started when the apparatus is turned on (step 1), and a sufficient time until impedance adjustment is completed is monitored on the diagnostic processor side using a preset timer or the like ( Step 2, 3).
[0043]
When the time elapses (step 2), an impedance adjustment target CARD, such as CARD 100, is selected, and then an impedance adjustment target LSI, such as LSI 80, is selected (step 4).
[0044]
Next, the Up / Down suppression flag 152 is designated by the bit address signal 33, the Write path 31 is turned on (logic "1"), the Write instruction 30 is issued, and the Up / Down suppression flag 152 is set. As a result, the adjustment counter 15 is shifted to the Up / Down inhibition state, and the internal state value of the adjustment counter 15 is held (step 5).
[0045]
Next, each bit of the adjustment counter 15 is sequentially specified by the bit address signal 33, and the internal state value of the adjustment counter 15 is read by the Read path 34 and output to the display device or the like (step 6). It is determined whether or not the read internal state value of the adjustment counter 15 is within a specified range (step 7).
[0046]
The specified range of the adjustment counter value is, for example, a slight fluctuation (temperature fluctuation, etc.) with respect to the automatic adjustment value read when the transmission operation between the LSI 80 and the LSI on the receiving CARD 200 is normally performed. Is stored in a predetermined area of the storage unit of the diagnostic processor 300 for each CARD.
[0047]
If the internal state value of the adjustment counter 15 is within the specified range, it is judged OK (within range) and the specified range is output to a display device or the like (step 8).
[0048]
Next, an inquiry is made as to whether or not to adjust the impedance, and if not specified is specified (step 9), the Up / Down suppression flag 152 is reset through the write path (step 10), and the process ends. If adjustment is specified, the process proceeds to the offset value setting in step 13.
[0049]
On the other hand, when the internal state value of the adjustment counter 15 is not within the specified range, the fact that it is out of the range and the specified range is output to a display device or the like, indicating that a failure of the adjustment counter 15 or a failure of the impedance adjustment circuit system is suspected. A message is also output (step 11).
[0050]
An inquiry is made as to whether or not to proceed to failure investigation, and if not specified is specified (step 12), the Up / Down suppression flag 152 is reset and the process ends. If it is designated to proceed to failure investigation, the process proceeds to the setting of the offset value in step 13.
[0051]
Moving to FIG. 5, when impedance adjustment is performed, a value that is offset from the internal state value of the read adjustment counter 15 by the increment / decrement value is set, and in the failure investigation, a predetermined value within a specified range is set (step 13). An instruction to write the set value to the adjustment counter 15 is given (step 14).
[0052]
Next, the internal state value of the adjustment counter 15 is read by the Read path 34 (step 15), and it is checked whether or not the read internal state value of the adjustment counter 15 matches the expected value (step 16).
[0053]
If the internal state value of the adjustment counter 15 matches the expected value, a write success is output (step 17) and the process ends. If the internal state value of the adjustment counter 15 is not as expected, a write failure is output (step 18) and an inquiry is made as to whether or not the counter value is to be re-corrected (step 19). When re-correcting the counter value, the offset value is corrected (step 20), and writing to the adjustment counter 15 is performed using the write path 31 (step 14). This re-correction of the counter set value is repeated several times until it can be written.
[0054]
When a failure investigation is performed in this way, a value within a prescribed range assumed as a normal adjustment counter 15 is set as an offset value. In this state, it can be determined that the adjustment circuit system has failed by executing a transmission test program or the like to check whether the transmission operation between the LSI 80 and the LSI on the receiving side is normally restored.
Further, when the transmission value becomes normal in the state where the adjustment value is within the specified range but is set to be offset, it is possible to collect the failure of the impedance characteristic of the transmission line cable or the like as the cause of the transmission operation failure.
[0055]
In addition, the automatic adjustment value of the adjustment counter is read and determined whether it is within a specified range in the initial diagnosis at the time of starting up the information processing apparatus, and if it is out of the range, that fact is output. A predetermined value within the specified range may be set.
[0056]
In the above description, the replica buffer 14 is provided in the adjustment unit of the information processing apparatus main body, and the convergence value of the adjustment for this is applied to the main buffer. However, the replica buffer 14 is not provided and the adjustment is directly performed by the output of the main buffer 18. You may do it.
[0057]
Further, the writing from the diagnostic processor 300 to the Up / Down suppression flag 152 is not limited to the method of performing address designation and writing of write path data, but may be performed by a dedicated set signal or the like.
[0058]
The write path 31 and the read path 34 are 1-bit serial buses, but may be a multi-bit parallel bus.
[0059]
【The invention's effect】
As described above, according to the present invention, the value of the adjustment counter can be easily read, so that if any malfunction occurs during system evaluation, it is easy to determine whether the cause is due to a failure of the impedance adjustment circuit system. It can be judged (conventionally, a special measuring instrument is necessary for the measurement, and it took time to solve the problem). It also enables data collection for improving reliability.
According to the present invention, the diagnostic processor can write to the adjustment counter, and the information processing apparatus can be operated in that state. Therefore, when investigating whether the cause of the malfunction at the time of system evaluation is due to the failure of the impedance adjustment circuit system , Experimental impedance adjustment is possible.
Furthermore, the automatic adjustment value of the adjustment counter can be read for initial diagnosis at the time of starting up the information processing apparatus to check whether it is within a specified range, and intermittent failures in transmission operation can be prevented in advance.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an embodiment of an information processing apparatus of the present invention.
FIG. 2 is a block diagram showing a detailed configuration of an impedance adjustment unit and a buffer unit in FIG.
3 is a block diagram showing a detailed configuration of an adjustment counter 15 in FIG.
FIG. 4 is a flowchart illustrating the operation of the information processing apparatus according to the present invention from the diagnostic processor side.
FIG. 5 is a flowchart for explaining the operation of the information processing apparatus according to the present invention from the diagnosis processor side.
FIG. 6 is a diagram for explaining a conventional output impedance matching circuit;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 External reference resistance 11 Constant potential circuit 13 Voltage comparison circuit 14 Replica buffer 15 Adjustment counter 151 Counter main body 152 Up / Down suppression flag 16 Selection circuit 17 Prebuffer 18 Main buffer 19 Main logic 20 Decoder 30 Write instruction signal 31 Write path 32 Card LSI selection signal 33 bit address signal 33-1 inhibition flag selection signal 33-2 counter bit i selection signal 34 Read path 80 LSI
100, 200 CARD
300 diagnostic processor

Claims (4)

An output buffer having a plurality of transistors connected in parallel that can be selectively turned on / off and having an impedance adjustment function, and a plurality of transistors connected in parallel in the same manner as the output buffer. A replica buffer to which an external resistor matching the impedance is connected, a voltage comparison circuit that compares the output potential of the replica buffer with a reference potential, and outputs the result as an up / down instruction for the adjustment value, and receives and counts the up / down instruction. and adjustment counter that converges to a value up / down to match the transmission line impedance, an impedance adjusting section and a means for controlling the pre SL on / off of the double number of transistors in the output buffer converged adjusted counter value Information processing apparatus main body including information processing including diagnosis processor for diagnosing or monitoring the information processing apparatus main body A location,
Wherein the read path from the connected diagnosis processor to the adjustment unit, the adjustment circuitry that counter selects each bit of the data be sent to the read-out path, diagnosis connected to the adjustment unit according to the address from the diagnostic processor If a write path from the processor and an address from the diagnostic processor specify an arbitrary bit of the adjustment counter, a write instruction is given, and a flag to enable writing to the adjustment counter by the diagnostic processor is set A circuit for writing data from the write path to the designated bit of the adjustment counter; and an adjustment counter by the diagnostic processor that suppresses count-up / down of the adjustment counter due to a comparison result between the output potential and a reference potential Count-up / down-suppression flag that enables writing to the memory and instructions from the diagnostic processor And means to perform more writes to count up / down inhibition flag, the diagnostic processor state values of the adjustment counter is read out, characterized that you diagnostic processor writing to the adjustment counter is performed Information processing device. The diagnostic processor stores the specified range of the adjustment counter value and, after performing the addressing in anticipation that a predetermined time or more has elapsed since the startup of the information processing apparatus body, the adjustment counter through the read path 2. The information processing apparatus according to claim 1, further comprising: means for reading out and outputting the value of the first output, determining whether the read value is within a specified range, and outputting the determination content. The diagnosis processor is configured to store a specified range of the adjustment counter value and an increase / decrease width value of the adjustment, and to set the count-up / down-suppression flag in anticipation that a predetermined time or more has elapsed since startup of the information processing apparatus main body. After setting and addressing, means for reading out and outputting the value of the adjustment counter through a read path, determining whether the read value is within the specified range and outputting the determination content, and test adjustment designation Whether or not the specified value is added to or subtracted from the read value, and if it is specified, the value written to the adjustment counter is instructed, and the adjustment counter value is read and set to the indicated value. claim 1 Symbol placement of the information processing apparatus characterized by having a means for outputting a determination determined contents. A program installed in the diagnostic processor of the information processing apparatus according to claim 1 , wherein a predetermined range of the adjustment counter value and an adjustment increase / decrease value are stored in a predetermined area of a storage unit in advance, and the information processing apparatus In anticipation of the elapse of a predetermined time since the start-up of the main body, the count up / down suppression flag is set, the address is designated, the value of the adjustment counter is read and output through a read path, and the read value is The procedure for judging whether it is within the specified range and outputting the contents of judgment and the presence / absence of trial adjustment designation are obtained, and if designated, adjustment of the value obtained by adding or subtracting the increase / decrease value to the read value A procedure for instructing writing to the counter, reading out the adjustment counter value, determining whether it has been set to the instructed value, and outputting the determination contents. Program.

Images