JP3897356B2 - Arithmetic processing device and self-diagnosis method thereof - Google Patents

Description

The present invention relates to a processor with a built-in self-diagnosis function, and more particularly to an arithmetic processing unit such as a processor that enables self-diagnosis of an adder / subtractor without requiring expected value data for evaluating a diagnosis result, and a self-diagnosis method thereof.

  Conventionally, in the manufacturing process of an integrated circuit such as a processor with a built-in self-diagnosis function, a TAP controller (Test Access Port Controller) is built in the integrated circuit as a self-diagnosis circuit. By performing a self-diagnosis test on the RAM and the built-in arithmetic unit, an integrated circuit causing a manufacturing defect is found and removed, and by using the integrated circuit that has passed the self-diagnosis test, an LSI package assembly or processor・ The module assembly is prevented from being wasted, and the yield in the process after wafer manufacture is improved.

  FIG. 22 shows the basic hardware configuration of the processor. In FIG. 22, the instruction memory management unit (IMMU) performs conversion between a logical address and a percentage address using an instruction TLB (Instruction Translation Lookup Buffer), and the prefetch unit 104 performs an instruction field based on a branch prediction 108. In 106, prefetch is performed from the instruction cache 110. A secondary cache 112 is further provided between the instruction cache 110 and the processor local tantalator connector 114, and is connected to an external unit via the processor local tantalator connector 114.

  The instruction fetched from the instruction cache 110 is predecoded by the predecode unit 116 and then stored in the instruction buffer 118, and the branch unit 122, integer arithmetic unit register file (IEU register file) 124, floating point by the dispatch unit 120. This is distributed to the arithmetic unit register file (FPU register file) 128.

  Subsequent to the IEU register file 124, integer arithmetic units (IE ALU) 130-1 and 130-2 are provided, execute integer arithmetic instructions, output them to the completion unit 134, and load or store in accordance with instructions from the load / store unit 126. Store is done.

  The floating point arithmetic unit register file 128 is followed by floating point arithmetic units (FP ALU) 132-1 and 132-2, which execute floating point arithmetic instructions and output them to the completion unit 136. Loading or storing is performed in accordance with instructions from.

  FIG. 23 shows a basic configuration of an integer arithmetic unit including an instruction decoder in the processor of FIG. An integer operation instruction from the dispatch unit 138 is latched by the staging latch 144 and decoded by the decoder 150. The source register 140 stores the first operand of the instruction, the source register 142 stores the second operand, is latched by the respective staging latches 146 and 148, and is input to the arithmetic unit (ALU) 152.

  The arithmetic unit 152 receives the operation instruction of the addition instruction ADD or the subtraction instruction SUB decoded by the decoder 150, performs addition or subtraction of two input data, and causes the staging latch 156 to latch. The operation result of the staging latch 156 is stored in the destination register 168 from the multiplexer 164 via the staging latch 166.

  The addition instruction ADD and the subtraction name decoded by the decoder 150 are operated by the logical instruction unit 162 after being latched by the staging latch 154 after being latched by the staging latch 154. At this time, via the staging latches 158 and 160 An AND, OR, NAND, NPR, XOR, or XNOR logical operation is performed on the two input data, and the operation result is stored in the destination register 168 via the multiplexer 164 and the staging latch 166.

  A processor incorporating such an arithmetic unit, for example, mounts a self-diagnosis circuit for the adder / subtracter provided in the arithmetic unit 152 of FIG. 24, and performs a self-diagnosis test on the internal arithmetic unit at the wafer manufacturing stage or package manufacturing stage. To implement.

  FIG. 24 shows a configuration of a conventional addition / subtraction circuit in which a self-diagnosis circuit is mounted. In FIG. 24, for example, a two-input adder / subtracter 202 with a carry input Cin is mounted on the test target unit 200.

  A general-purpose register file 204, selectors 210 and 212, and source registers 214 and 215 are provided on the input side of the adder / subtracter 202. The output of the source register 215 is branched into two and directly input to one of the selectors 218, and inverted by the inverter 216 and input to the other of the selectors 218. The selector 218 switches between addition input and subtraction input to the adder / subtracter 202. The calculation result of the adder / subtracter 200 is stored in the destination register 220.

  Addition and subtraction by the adder / subtractor 202 are performed based on the addition instruction ADD or the subtraction instruction SUB of the decoder 230 that has decoded the operation code 232. Assuming that the data in the source registers 214 and 216 are A and B, respectively, when the add instruction ADD is issued from the decoder 230, the selector 218 selects the value B of the source register 215 and inputs it to the adder / subtractor 202, and at the same time add / subtract The carry input of the unit 202 is set to Cin = 0, so that the adder / subtracter 202 executes addition of C = A + B.

  When the subtract instruction SUB is issued from the decoder 230, the selector 218 selects the output of the inverter 216 obtained by inverting the value B of the source register 215 and inputs it to the adder / subtractor 202. At the same time, the carry input of the adder / subtractor 202 is set to Cin = As a result, the adder / subtracter 202 executes subtraction of C = A−B. The subtraction of C = A−B by the adder / subtractor 202 is performed by adding the carry input Cin = 1 to the adder / subtractor 202 in the complement of B1 ′s of B by the inverter 216. The two's complement B2's is obtained and added to A, thereby subtracting C = AB-A + B1's + 1 = A + B2's.

  As a self-diagnosis circuit for such an addition / subtraction circuit, a self-diagnosis controller 228 including a TAP controller (Test Access Port controller) 226 and a comparator 234 is provided.

  In a processor equipped with this self-diagnosis circuit, before starting the self-diagnosis, the TAP controller 226 calculates a large amount of input data for self-diagnosis from an external RAM or the like and self-diagnosis using the input data. A huge amount of expected value data obtained when the device operates normally is read into the general register file 204 and prepared.

  Next, the TAP controller 226 activates the self-diagnosis controller 228, reads the source data 206 as the first operand, the source data 208 as the first operand, and the expected value 225 from the general register file 204 in the first cycle. Data 206 and 208 are stored in source registers 214 and 215 via selectors 210 and 212. The expected value 225 is set to one input of the comparator 234 of the self-diagnosis controller 228.

  In the next cycle, for example, two source data are added by the addition instruction ADD and stored in the destination register 220, and the addition result 224 is compared with the expected value 225 already read by the comparator 234 of the self-diagnosis controller 228. To do.

  If the two match in the comparison 234, the arithmetic unit 202 is normal. If the two do not match, it is determined that the arithmetic unit 202 is abnormal, an error is output to the outside, and the processor causing the error is removed from the manufacturing process.

  If such a self-diagnosis process is executed for all input data and expected values prepared in the general-purpose register file 204 and there is no abnormality, the processor passes the test and is sent to the next step.

  24 includes linear feedback registers (LFSR) 236 and 238 that operate as pseudo-random number generators, and the data X and Y read from the general-purpose register file 204 are stored in the source registers 214 and 238, respectively. After being set as an initial value via 215, a self-diagnosis can be performed by generating pseudo-random numbers under the control of the self-diagnosis controller 228.

Even in this self-diagnosis that generates pseudo-random numbers, it is necessary to prepare in advance an expected value corresponding to the random number generated at the time of diagnosis and read it into the general-purpose register file 204, and preparation and reading of input data can be made unnecessary. However, the expected value is required.
Japanese Patent Application Laid-Open No. 62-206643 Japanese Patent Laid-Open No. 01-180043

  However, in an integrated circuit such as a processor incorporating such an arithmetic unit, when the self-diagnosis function of the arithmetic unit is mounted on the integrated circuit, a large amount of self-test is performed from an external RAM or the like when the self-diagnosis test is performed. The signature register that stores the input data for diagnosis and the huge amount of expected value data obtained when the arithmetic unit operates normally by self-diagnosis using the input data, and stores the calculation result based on the input data. The process of comparing the value with the expected value is repeated, and a large-scale and complicated self-diagnosis circuit is required.

  For this reason, when the self-diagnosis function of an arithmetic unit is mounted on an integrated circuit, it is attempted to improve the yield by reducing the size of the silicon semiconductor portion that is the main body of the integrated circuit and increasing the number of chips that can be manufactured from the wafer. However, the die size cannot be reduced by mounting a large-scale and complicated self-diagnosis circuit, resulting in a decrease in yield.

  Also, even if trying to reduce the power consumption of the processor by reducing the die size, the self-diagnostic circuit becomes large and complicated, so the die size cannot be reduced and the power consumption cannot be sufficiently realized. There was a problem.

  Furthermore, in the manufacture of an integrated circuit such as a processor, the time that can be allocated to the self-diagnosis test per processor is determined by the number of units produced in the month, and the input data used for self-diagnosis is determined according to the allocated time. The expected value data was recreated, and there was a problem that it took time and effort to prepare.

It is an object of the present invention to provide an arithmetic processing apparatus such as a processor and a method thereof that can perform self-diagnosis of an arithmetic unit using only input data without requiring expected value data.

  FIG. 1 is a diagram illustrating the principle of the present invention. The present invention is directed to an integrated circuit having a self-diagnosis function, and includes an arithmetic circuit 10-1 including an adder / subtractor 12 to be diagnosed, a data storage unit 14 for storing self-diagnosis data, and self-diagnosis data. And a self-diagnosis processing unit 10-2 for executing a diagnosis process so that all bits of the operation result are all 0 (is all 1) by the operation circuit 10-1.

  According to the present invention, an arithmetic circuit and a self-diagnosis processing unit are configured so that all bits that can be easily inspected as an operation result are obtained with all 0 (or all 1) as input for arbitrary self-diagnosis input data. This eliminates the need for the expected value and the comparison circuit for the expected value, reduces the circuit scale required to realize self-diagnosis, thereby reducing the die size, improving processor yield and reducing power consumption. An integrated circuit such as a processor that implements a self-diagnosis function that contributes is realized.

Here, when the two input data are X and Y, the self-diagnosis processing unit performs self-diagnosis with the calculation result being all 0 by the next addition / subtraction.
(1) Subtraction with X as a subtracted number and Y as a subtracted number Z = XY
(2) Subtraction with Y as a subtracted number and X as a subtracted number Z ′ = Y−X
(3) Addition of two subtraction results Z ″ = Z ′ + Z
(4) The result of addition is normal if all 0s, abnormal if not all 0s

  As a specific example, first, as the arithmetic circuit 10-1, as shown in FIG. 1B, a first source register 24 for storing the first operand A and a second source register 26 for storing the second operand B are used. And a complement circuit (inverter) 30 that inverts the second operand B and outputs a one's complement B1's, and the first operand A is input as a subordinate, and the output value B1's of the complement circuit 30 is carried as a subtraction. A test object which is input together with Cin and executes subtraction C = (A−B) by internally generating 2's complement B2 ′s obtained by adding 1 to 1's complement B1 ′s and adding it to the first operand A A first adder / subtracter 12 with a carry input, and a second adder / subtractor 36 provided at the next stage of the first adder / subtractor 12.

For such an arithmetic circuit 10-1, the self-diagnosis processing unit 10-2 uses arbitrary self-diagnosis data X, Y having a predetermined bit length stored in the first and second source registers 24, 26. Perform the following diagnostic process.
(1) In the first cycle, the subtraction Z = (X−Y) is executed as Z = (X + Y2 ′s) = (X + Y1 ′s + 1) using the complement circuit 30 and the first adder / subtractor 12.
(2) Substituting the subtracted number X and the reduction number Y in the second cycle and subtracting Z ′ = (Y−X) using the complement circuit 30 and the first adder / subtractor Z = (Y + X2 ′s) = (Y + X1 ′s + 1) Run as.
(3) In the third cycle, the second adder / subtractor 36 is used to perform the addition Z ″ = (Z + Z ′) = (X + X1 ′s + 1 + Y + Y1 ′s + 1) of the subtraction results Z and Z ′ in the first and second cycles.
(4) If the addition result is all bits 0, it is determined to be normal, and if it is not all bits 0, it is determined to be abnormal.

Further, as another form, when the two input data are X and Y, the self-diagnosis processing unit 10-2 performs self-diagnosis by the following subtraction, conversion, and comparison determination.
(1) Subtraction with X as a subtracted number and Y as a subtracted number Z = XY
(2) Subtraction with Y as a subtracted number and X as a subtracted number Z ′ = Y−X
(3) Calculate 2's complement Z2's for subtraction result Z '
Z'2's = Z1's + 1
(3) Comparison Z = Z'2's
(4) Normal when matched, abnormal when mismatched

  As a specific example in this case, first, the arithmetic circuit first inverts the first source register storing the first operand A, the second source register storing the second operand B, and the second operand B to 1 The first complement circuit for outputting the complement B1's of the first and second operands A are input as the attenuator, and the output value B1's of the inverting circuit is input as a subtract together with the carry Cin = 1 to the one's complement B1's An adder / subtracter with a carry input to be tested to execute subtraction C = (A−B) by internally generating a 2's complement B2 ′s obtained by adding 1 and adding it to the first operand A; A second complement circuit that outputs the 2's complement C2's by inverting the subtraction value C and adding 1 and a comparator that compares the outputs of the adder / subtractor and the second complement circuit are provided.

For such an arithmetic circuit, the self-diagnosis circuit executes the following processing using arbitrary self-diagnosis data X and Y having a predetermined bit length stored in the first and second source registers.
(1) In the first cycle, the subtraction Z = (X−Y) is executed as Z = (X + Y2 ′s) = (X + Y1 ′s + 1) using the first complement circuit and the adder / subtracter.
(2) In the second cycle, the subtracted number X and the number Y are exchanged and the subtraction Z ′ = (Y−X) is executed as Z = (Y + X2 ′s) = (Y + X1 ′s + 1) using the first complement circuit and the adder / subtracter. Then, the complement Z′2 ′ = (Z1 ′s + 1) of the subtraction result Z ′ is output from the second complement circuit and compared with the subtraction result Z in the first cycle, and the two match (Z′2 ′s = Y2 ′). s−X2 ′s = X + Y2 ′s = Z), it is determined to be normal, and if they do not match, it is determined to be abnormal.

Here, Z′2 ′s = Y2′s−X2 ′s = X + Y2 ′s = Z determined by the comparator (1)
Proving the establishment of is as follows.
Z = X−Y = X + Y1 ′s + 1 = X + Y2 ′s (2)
Z ′ = Y−X = Y + X1 ′s + 1 = Y + X2 ′s (3)
From (2) Y2's = -Y (4)
From (3), X2's = -X (5)
Therefore, if (4) and (5) are substituted into (1) and transformed,
Z′2 ′s = Y2′s−X2 ′s
= -Y-(-X)
= -Y + X
= XY
It becomes. Here, substituting equation (2) for -Y in the second term on the right side,
Z'2's = X + Y2's
= Z
Thus, the relationship of Z′2 ′s = Z in (1) is established.

There are various variations in the configuration of the specific arithmetic circuit and the self-diagnosis processing for making all of the self-diagnosis calculation results equal to zero or two calculation results.

  According to the present invention, with respect to arbitrary input data for self-diagnosis, the arithmetic circuit and the self-diagnosis processing unit are configured so that all bits that can be easily inspected as an operation result are obtained as all zeros or all ones. This eliminates the need for the expected value and the comparison circuit for the expected value for self-diagnosis, thereby reducing the necessary circuit scale for realizing the self-diagnosis, resulting in a smaller size, improved processor yield, and lower consumption. A processor such as a processor having a self-diagnosis function that contributes to electric power can be realized.

Also, when reading test data from outside, the expected value is not required, so external data can be read in a short time, and the time required for self-diagnosis per unit varies depending on the production plan of the processor such as a processor. Even in such a case, it is possible to flexibly and easily cope with the fact that preparation of the expected value is not required.

  FIG. 2 is a circuit block diagram showing the basic configuration of the processor according to the present invention.

  In FIG. 2, a processor with a self-diagnosis function according to the present invention includes an arithmetic circuit 10-1 having an adder / subtractor 12 to be diagnosed, a general-purpose register file 14 as a data storage unit for storing self-diagnosis data, and an operation code. A decoder 50 is provided that outputs an addition instruction ADD or a subtraction instruction SUB by inputting and decoding.

  A self-diagnosis processing unit 10-2 is provided for the arithmetic circuit 10-1 including the adder / subtractor 12 as the test target. The self-diagnosis processing unit 10-2 is provided with a TAP controller (Test Access Port Controller) 42 and a self-diagnosis controller 44. The TAP controller 42 performs a self-diagnosis test on the RAM and the built-in arithmetic unit built in the LSI under the control of the self-diagnosis controller 44 in the wafer manufacturing stage and the package manufacturing stage in the LSI manufacturing process.

In other words, the arithmetic circuit 10-1 including the adder / subtractor 12 to be self-diagnosis is configured to generate a two's complement for the input test data X and Y. (1) Subtraction Z = X−Y, where X is a reduced number and Y is a reduced number.
(2) Subtraction Z ′ = Y−X where Y is a subtracted number and X is a subtracted number
(3) Addition of two subtraction results Z ″ = Z + Z ′ = 0
, And the self-diagnosis process of the arithmetic circuit 10-1 that does not require comparison between the operation result and the expected value by confirming that all bits of the final operation result ZZ are 0 is executed.

In another form of the self-diagnosis process of the present invention, the following subtraction, conversion, and comparison determination are performed for the two input test data X and Y.
(1) Subtraction Z = X−Y, where X is a subtracted number and Y is a subtracted number
(2) Subtraction Z ′ = Y−X where Y is a subtracted number and X is a subtracted number
(3) A two's complement Z2 ′s is calculated for the subtraction result Z ′. Z2's = Z1's + 1
(4) Comparison of subtraction result and conversion result Z = Z2's
Then, the self-diagnosis is executed such that the comparison between the calculation result and the expected value is unnecessary by confirming the coincidence of the comparison result.

  FIG. 3 shows a first embodiment of a processor with a self-diagnosis function according to the present invention. In this first embodiment, an arithmetic circuit is operated so that the operation result is all 0 for all bits. It is characterized in that the calculation result is confirmed.

  In FIG. 3, the processor according to the first embodiment includes an arithmetic circuit unit 10-1 and a self-diagnosis processing unit 10-2. The self-diagnosis processing unit 10-2 is provided with a TAP controller 42 and a self-diagnosis controller 44. The TAP controller 42 controls a self-diagnosis test for the adder / subtractor 12 as the test object 11 incorporated in the arithmetic circuit 10-1 in the wafer manufacturing stage and the package manufacturing stage in the LSI manufacturing process. Specifically, the activation is confirmed by the BIST START signal for the self-diagnosis controller 44, and the diagnosis end is received by the BIST DONE signal.

  The self-diagnosis controller 44 operates in response to the BIST START signal from the TAP controller 42, and controls the arithmetic circuit 10-1 side to execute a self-diagnosis test. The self-diagnosis controller 44 is provided with an all-zero detector 48, which receives the calculation result 40 from the self-diagnosis test from the calculation circuit 10-1, and if all bits of the calculation result 40 are all zero, the test object 11 is selected. When all the bits are not all zero, it is determined that the adder / subtracter 12 as the test object 11 is abnormal, and an error signal E4 is output to the outside to detect an error. Make a notification.

  Next, the side of the arithmetic circuit 10-1 to be subjected to the self-diagnosis test will be described. The arithmetic circuit 10-1 includes a general-purpose register file 14, multiplexers 20 and 22, a first source register 24, a second source register 26, and an inverter 30 as a complement circuit that generates the complement of the first source register 26, a multiplexer 28, and a test object 11. A 2-input adder / subtractor 12 with a carry Cin, a destination register 32, 34, 38, a 2-input adder / subtractor 36 having no carry input, and a decoder 50 are provided.

  The decoder 50 receives the operation code 52 of the program and decodes the addition instruction ADD or the subtraction instruction SUB as an instruction for the arithmetic unit. The general-purpose register file 14 is a set of registers that hold data such as integer data and addresses used inside the processor. In the self-diagnosis test of the present invention, test data prepared in advance for use in self-diagnosis is stored. It is read in advance from an external RAM or the like through the write port WR.

  Data stored in the general-purpose register file 14 is read from the read port RD as first source data 16 and second source data 18 and is stored in the first source register 24 and the second source register 26 via the multiplexers 20 and 22. The In the self-diagnosis test, the first test data X and the second test data Y are read from the general-purpose register file 14 and stored in the first source register 24 and the second source register 26, respectively. Here, the data handled in this embodiment is, for example, 32-bit width data.

  The multiplexer 20 selects and outputs the value of the first source data 16 and the value of the first source register 24 by the control signal E2 from the self-diagnosis controller 44. Similarly, the multiplexer 22 selects and outputs the value of the second source data 18 and the value of the second source register 26 by the control signal E2 from the self-diagnosis controller 44.

  Here, the first source register 24 holds the value of the first operand of the adder / subtractor, and the second source register 26 holds the value of the second operand of the adder / subtracter.

  The inverter 30 functions as a complement circuit that inverts the value held in the second source register 26 and generates a one's complement. The multiplexer 28 selects and outputs the value of the second source register 26 and the value of the inverter 30 according to the operation instruction from the decoder 50. In the self-diagnosis test of the present invention, the subtraction instruction SUB is output from the decoder 50, the multiplexer 28 selects the output from the inverter 30, and outputs the one's complement obtained by inverting the value of the second source register 26.

  The adder / subtractor 12 to be tested 11 of the first embodiment is a two-input adder / subtracter with a carry input in which the output of the decoder 50 is the carry input Cin. In the case of the addition instruction ADD, the carry input is Cin = On the other hand, in the case of the subtraction instruction SUB, the carry input is Cin = 1.

  Therefore, in the normal addition instruction ADD, if the first operand of the adder / subtracter 12 is A, the second operand is B, and the addition output is C, addition of C = A + B is performed. The adder / subtractor 12 receives the subtraction instruction SUB from the decoder 50 during the self-diagnosis test, so that the value of the first source register 24 is the first operand A and the value of the second source register 26 is the second operand B. The multiplexer 28 generates the 1's complement B1's obtained by inverting the second operand B. Further, the carry input Cin = 1 to the adder / subtractor 12 generates the 2's complement B2's (= B1's + 1) of the second operand B. As a result, the subtract instruction of C ′ = A + B2 ′s = AB is executed.

  Specifically, the 2-input adder / subtractor 12 with the carry input Cin in FIG. 3 has the circuit configuration of FIG. The arithmetic unit 10 includes an adder / subtractor 12-1 and an adder / subtractor 12-2. The first operand A of the instruction is input to one of the adder / subtractor 12-1, and the addition result of the adder / subtractor 12-2 is input to the other. is doing. The adder / subtracter 12-2 adds the second operand B of the instruction and the carry input Cin and outputs the result. Therefore, the addition output C of the adder / subtracter 12 is C = A + B + Cin, and the carry input Cin is Cin = 0 by the addition instruction ADD from the decoder 50 and Cin = 1 by the subtraction instruction SUB.

  Referring to FIG. 3 again, the destination register 32 provided on the output side of the adder / subtractor 12 holds the calculation result of the adder / subtractor 12 in normal calculation processing, and stores the value of the held calculation result as a data forward. -Output to the pass path 35 and finally reflect the operation result in the general-purpose register file 14.

  In the self-diagnosis test according to the present invention, the value of the subtraction result Z ′ = Y−X (= Y + X2 ′s = Y + X1 ′s + 1), which is the operation result of the second cycle, is held. The next destination register 34 holds a value of Z = X−Y (= X + Y2 ′s = X + Y1 ′s + 1), which is a subtraction result of the first cycle in the self-diagnosis test.

  The two-input adder / subtractor 36 is effective only during the self-diagnosis test, receives the control signal E3 from the self-diagnosis controller 44, and obtains the subtraction result Z of the destination register 34 obtained by subtraction twice by the subtractor 12. And Z ″ = Z + Z ′ = (X−Y) + (Y−X) = X + Y2 ′s + Y + X2 ′s is calculated by adding the subtraction result Z ′ of the destination register 32.

  The destination register 38 at the output stage of the adder / subtracter 36 holds the final calculation result Z ″ = Z + Z ′ of the self-diagnosis test. The calculation result 40 is supplied to the all-zero detector 48 of the self-diagnosis controller 44. An error occurs and all zeros are checked.

  Next, the operation for C = A + B by the addition instruction ADD and the C '= AB by the subtraction instruction SUB, which are normal operation instructions in the first embodiment of FIG. 3, will be described.

  First, the first operand A and the second operand B of the operation instruction are read from the read port of the general-purpose register file 14 as the first source data 16 and the second source data 18, respectively, and are sent through the multiplexers 20 and 22 to the first source register. 24 and the second source register 26.

  On the other hand, the opcode 52 of the operation instruction is decoded by the decoder 50, and if it is an addition instruction ADD, the multiplexer 28 selects the second operand B of the first source register 26 as it is. The second operand B and the carry input Cin = 0 are input, and C = A + B is calculated.

  In the case of the subtraction instruction SUB, the multiplexer 28 selects the output of the inverter 30, so that the adder / subtractor 12 has the 1's complement B1's obtained by inverting the first operand A and the second operand B, and the carry input Cin = 1. Then, C ′ = A−B = A + B2 ′s = A + B1 ′s + 1 is calculated.

  The values of C and C ′ that are the calculation results of the adder / subtracter 12 are held in the destination register 32, output to the data forward path 35, and finally reflected in the general-purpose register file 14 from the write port.

  Next, the operation by the self-diagnosis test of the present invention will be described. In the self-diagnosis test, the TAP controller 42 asserts the BIST START signal for the self-diagnosis controller 44, and the operation of the self-diagnosis test is started. By the start of this self-diagnosis test, the first operand X and the second operand Y, which are test data already stored in the general-purpose register file 14, are read from the read port, selected by the multiplexers 20 and 22, 1 source register 24 and second source register 26 hold.

  On the other hand, the self-diagnosis controller 44 controls the decoder 50 by the control signal E1, and outputs a subtraction instruction SUB by decoding the operation code 52. In response to the subtraction instruction SUB from the decoder 50, the multiplexer 28 selects the output of the inverter 30, so that the adder / subtractor 12 has the first operand X, the one's complement Y1's obtained by inverting the second operand Y, and the carry input Cin = 1 is input.

As a result, in the first cycle of the self-diagnosis process, the adder / subtractor 12 sets Z = X−Y = X + Y2 ′s = X + Y1 ′s + 1 as the subtraction result Z.
And the operation result Z is held in the destination register 32.

  Next, in the second cycle of the self-diagnosis test after one clock, the self-diagnosis controller 44 controls the multiplexers 20 and 22 to exchange the values X and Y of the first source register 24 and the second source register 26. Thus, the first operand Y is held in the first source register 24, and the second operand X is held in the second source register 26, replacing the values in the first cycle.

Further, the multiplexer 28 continuously selects the output of the inverter 30 by the subtraction instruction SUB of the decoder 50. Therefore, the adder / subtractor 12 receives the first operand Y, the second operand X, and the carry input Cin = 1.
Z ′ = Y−X = Y + X2 ′s = Y + X1 ′s + 1
Is calculated. At this time, the value of Z = X−Y, which is the previous calculation result, is held in the destination register 34 since one clock has elapsed, and the value of Z ′ = Y−X, which is the current subtraction result, is It is held in the nation register 32.

  The subtraction results Z ′ and Z held in the destination registers 32 and 34 in this way are input to the 2-input adder 36 as the first operand Z ′ and the second operand Z, and Z ″ = Z + Z ′ is calculated. Is done. The calculation result Z ″ is held in the destination register 38 and is output as the calculation result 40 to the all-zero detector 48 of the self-diagnosis controller 44.

Here, when the adder / subtractor 12 as the test object 11 is normal, the subtraction result Z ″ has the following relationship.
Z ″ = Z + Z ′ = (X−Y) + (Y−X)
= X + Y2's + Y + X2's
= (X + X2's) + (Y + Y2's)
= 0 + 0
= 0

  Therefore, the all-zero detector 48 of the self-diagnosis controller 44 has only to check that all bits of the operation result 40 are all 0, and prepares the expected value as the operation result of the test data X and Y as in the prior art. There is no need to compare with the operation result of. For this reason, the all-zero detector 48 may have, for example, a circuit configuration that takes OR logic of all bits, and an error signal is generated if all bits are not all 0 by the OR output of the logic circuit of such all-bit OR input. E4 can be output to notify the abnormality of the arithmetic unit 12 to the outside.

  Such a self-diagnosis test is repeated a plurality of times for the remaining two sets of input data stored in advance in the general-purpose register file 14, thereby completing the self-diagnosis.

  FIG. 5 is a circuit block diagram of a second embodiment of the processor with a self-diagnostic function according to the present invention, in which the comparison between the calculation result and the expected value is unnecessary. In the second embodiment, after subtracting the subtraction Z = X−Y and Z ′ = Y−X for the two input test data X and Y, the first calculation result Z and the second calculation result Z The two's complement Z'2's is compared, and a self-diagnosis test that does not require comparison with the expected values of the input data X and Y is performed based on the comparison result.

  In FIG. 5, the configuration from the general-purpose register file 14 to the destination register 34 on the arithmetic circuit 10-1 side is the same as that of the first embodiment of FIG. For this reason, in the self-diagnosis test, two test data X and Y are read from the general-purpose register file 14 and held in the first source register 24 and the second source register 26, and then subtracted Z in the first cycle. = X−Y = X + Y2 ′s = (X + Y1 ′s + 1) is executed, and the first cycle process held in the destination register 32 is performed.

  In the next second cycle, the subtraction Z ′ = (Y−X) = (Y + X2 ′s) = (Y + X1 ′s + 1) is performed by switching the input data X and Y, and the calculation result in the first cycle is one clock later. Therefore, it is held in the destination register 34, and the second calculation result is held in the destination register 32.

  Following the destination registers 32 and 34, a comparator 54 is provided in the second embodiment. The first subtraction result Z held in the destination register 34 is input to one input of the comparator 54. An inverter 56 and a +1 increment circuit 58 are provided at the other input of the comparator 54.

  Therefore, the second subtraction result Z ′ held in the destination register 32 is inverted by the inverter 56 to become a one's complement Z1 ′s, and then by adding 1 by the +1 increment circuit 58, the two's complement of Z ′. Z′2 ′s = Z′1 ′s + 1 is converted and input to the comparator 54.

  Therefore, the comparator 54 compares the first operand Z, which is the value of the destination register 34, with the second operand Z′2 ′s converted by the inverter 56 and the +1 increment circuit 58, and compares the comparison result 40. -1 is output.

  On the other hand, a TAP controller 42 and a self-diagnosis controller 44-1 are provided on the self-diagnosis processing unit 10-2 side, and an error detector 60 is provided in the self-diagnosis controller 44-1. The error detector 60 inputs the comparison result 40-1 from the comparator 54 of the arithmetic circuit unit 10-1. If the first operand Z and the first operand Z′2 ′s in the comparator 54 match, the test is performed. The adder / subtracter 12 of the target 10 is determined to be normal. On the other hand, if the comparison results do not match, an error is detected and an error signal E4 indicating an abnormality of the adder / subtractor 12 is output to the outside.

  Here, it is proved that the coincidence relationship between the first operand Z and the second operand Z′2 ′s in the comparator 54 is established as follows.

First, the final calculation result is as follows.
Z′2 ′s = Y2′S−X2 ′S = X + Y2 ′S = Z (6)
Proving this is as follows. Here, Z = X−Y = X + Y1 ′s + 1 = X + Y2 ′S (7)
Z ′ = Y−X = Y + X1 ′s + 1 = Y + X2 ′S (8)
It is. Therefore, Y2's = -Y from (7) (9)
From (8), X2 ′s = −X (10)
It becomes. Therefore, when (9) and (10) are substituted into (6) and transformed,
Z'2's = X + Y2's
= -Y-(-X)
= -Y + X
= XY
It becomes. Here, substituting equation (7) for -Y in the second term on the right side,
Z'2's = X + Y2's
= Z
Thus, the relationship of Z′2 ′s = Z in (5) is established.

  Further, as the comparator 54, when the arithmetic operation of the arithmetic unit 12 is correct, the first operand Z ′ and the second operand Z′2 ′s coincide with each other. Therefore, the first operand Z and the second operand Z′2 It is only necessary to take the OROR of the EXOR output of all bits after taking the EXOR logic of all bits for each of 's, and the comparator 54 itself can also be configured with simple logic data.

  FIG. 6 is a circuit block diagram of a third embodiment of a processor having a self-diagnosis function of the present invention. The third embodiment is characterized in that a 2-input adder / subtracter having no carry input is provided as a test target.

  In FIG. 6, the self-diagnosis processing unit 10-2 includes a TAP controller 42 and a self-diagnosis controller 44, as in the first embodiment of FIG. 3, and the self-diagnosis controller 44 is provided with an all-zero detector 48. .

  The arithmetic circuit 10-1 includes a two-input adder / subtracter 65 having no carry input as the test object 10. A register file 14, multiplexers 20 and 22, a first source register 24 and a second source register 26, an inverter 30 and a multiplexer 28 are provided on the input side of the adder / subtractor 65 as in the first embodiment of FIG. Although the same, the +1 increment circuit 61 is provided after the inverter 30 in accordance with the addition / subtraction of the adder / subtractor 65 without carry input.

  The inverter 30 and the +1 increment circuit 61 invert the second operand B of the second source register 26 by the inverter 30 and convert it to a one's complement B1's. The data is converted into B2's and output to the adder / subtractor 65.

  Therefore, in the adder / subtracter 65, the first operand A is input as an output by the selection of the second operand B2's of the multiplexer 28 by the subtraction instruction SUB from the decoder 50, and C = A + B2's = AB. Subtraction will be performed.

  At the output stage of the adder / subtractor 65, there are provided destination registers 32 and 34, a two-input adder / subtractor 36 and a destination register 38, which are the same as those in the first embodiment of FIG.

  Next, the operation of the self-diagnosis test will be described for the third embodiment of FIG. When the TAP controller 42 asserts the BIST START signal, the self-diagnosis controller 44 operates and starts a self-diagnosis test. First, operands X and Y as test data are read from the general-purpose register file 14 and are held in the first source register 24 and the second source register 26 via the multiplexers 20 and 22.

At this time, since the subtraction instruction SUB is output under the control of the decoder 50, the multiplexer 28 selects the output of the +1 increment circuit 61. Therefore, the first operand X and the second operand B2 ′s are input to the adder / subtractor 65 as the test object 10,
Z = X + Y2 ′s = X + Y1 ′s + 1 = X−Y
Is calculated and held in the destination register 32.

  In the next second cycle, the multiplexer 20 selects and outputs the test data X of the second source register 26 by the control signal E2 of the self-diagnosis controller 44, and at the same time, the multiplexer 22 outputs the test data X of the first source register 24. Select and output, thereby switching the values of the source registers 24 and 26.

At this time, the multiplexer 28 continuously receives the subtraction instruction SUB from the decoder 50. Therefore, the first operand Y and the second operand X2's converted by the inverter 30 and the +1 increment circuit 61 are input to the adder / subtractor 65,
Z ′ = Y + X2 ′s = Y + X1 ′s + 1 = Y−X
Execute. Since the second subtraction result is one clock later, it is held in the destination register 32, and the previous subtraction result Z is held in the next destination register 34.

For this reason, the first and second operands Z ′ and Z are input to the adder / subtractor 36, and the operation of Z ″ = Z + Z ′ is executed and held in the destination register 38. If the adder / subtracter 65 is normal, the calculation result Z ″ in the adder / subtractor 36 is
Z ″ = Z + Z ′ = (X−Y) + (Y−X)
= X + Y2's + Y2's + Y + X2's
= (X + X2's) + (Y + Y2's)
= 0 + 0
= 0
It becomes.

  The addition result 40 of the adder / subtractor 36 is given to the all-zero detector 48 of the self-diagnosis controller 44, and if all bits are all zero, the adder / subtractor 65 determines that it is normal, and if it is not all zero, it determines that the adder / subtractor 65 is abnormal. An error signal E4 is output to the outside.

  In the third embodiment of FIG. 6, an adder / subtracter having no carry input is used as an adder / subtracter to be tested instead of the two-input adder / subtractor 12 with a carry input as in the first embodiment of FIG. It can correspond to the self-diagnosis test when it is used.

  FIG. 7 is a circuit block diagram of a fourth embodiment of a processor with a self-diagnosis function according to the present invention. In the fourth embodiment, the adder / subtracter 36 provided in the output stage in the first embodiment of FIG. 3 is abolished, and the second calculation by the adder / subtractor 36 is provided as the test target 10. The two-input adder / subtractor 12 is used to perform the operation. In this way, the configuration of the arithmetic circuit can be simplified because no dedicated adder / subtracter is required for the second calculation.

  In FIG. 7, a general-purpose register file 14, multiplexers 20 and 22, a first source register 24, a second source register 26, an inverter 30, A multiplexer 28 is provided, and subsequently, multiplexers 64 and 66 are newly provided.

  The multiplexers 64 and 66 select the outputs of the first source register 24 and the multiplexer 28 in the first cycle by the control signal E5 from the self-diagnosis controller 44, but the outputs of the adder / subtractor 12 in the second cycle. The values of the destination registers 34 and 32 on the side are selected and output. In addition to the carry input Cin, a control signal E3 for controlling the first calculation and the second calculation is also input to the adder / subtractor 12.

  Next, the operation of the self-diagnosis test in the fourth embodiment of FIG. 7 will be described. When the self-diagnosis controller 44 operates when the TAP controller 42 asserts the BIST START signal, first, arbitrary test data X and Y are read from the general-purpose register file 14, and the first source register 24 is read via the multiplexers 20 and 22. One operand X is held, and at the same time, the second operand Y is held in the second source register 26.

At this time, the multiplexer 28 selects the output of the inverter 30, and the multiplexers 64 and 66 select the output of the first source register 24 and the output of the multiplexer 28. Of course, the decoder 50 outputs the subtraction instruction SUB. Therefore, the first operand X, the second operand Y2's and the carry input Cin = 1 are input to the adder / subtractor 12 of the test object 10,
Z = X + Y2 ′s = X + Y1 ′s + 1 = X−Y
And the subtraction result Z is held in the destination register 32.

In the second cycle, the self-diagnosis controller 44 controls the multiplexers 20 and 22 while maintaining the subtraction instruction SUB of the decoder 50 to exchange the operands X and Y of the first source register 24 and the second source register 26. Since the control of the multiplexer 28 and the multiplexers 64 and 66 is the same as in the first cycle, the first operand Y, the second operand X2's, and the carry input Cin = 1 are input to the adder / subtractor 12. ,
Z ′ = Y + X2 ′s = Y + X1 ′s + 1 = Y−X
Perform subtraction.

  The second subtraction result Z ′ is held in the destination register 32, and the first subtraction result Z is held in the next destination register 34 because it is one clock later.

  In the next third cycle, the self-diagnosis controller 44 controls the decoder 50 to output the addition instruction ADD, and controls the multiplexers 64 and 66 by the control signal E5 to select the output side of the adder / subtractor 12. Let

  Therefore, the first operand Z held in the destination register 34, the second operand Z ′ held in the destination register 32, and the carry input Cin = 0 are input to the adder / subtractor 12, and Z ″. = Add Z + Z '.

The addition result Z ″ in the third cycle is held in the destination register 32 and is output as an operation result 40 to the all-zero detector 48 of the self-diagnosis controller 44. If the adder / subtractor 12 is normal, the finally obtained calculation result Z ″ is
Z ″ = Z + Z ′ = (X−Y) + (Y−X)
= X + Y2's + Y + X2's
= (X + X2's) + (Y + Y2's)
= 0 + 0
= 0
It becomes.

  For this reason, the all-zero detector 48 of the self-diagnosis controller 44 determines that the adder / subtractor 12 is normal if the addition result 40 is all-zero, and determines that the adder / subtractor 12 is abnormal if it is not all-zero, and sends the error signal E4 to the outside. Output.

  In the fourth embodiment of FIG. 7, the circuit configuration of the arithmetic circuit 10-1 is simpler than that of the first embodiment of FIG. 3 because another adder / subtracter is not required at the output stage of the adder / subtractor 12. it can. On the other hand, in the first embodiment of FIG. 3, although the circuit configuration becomes complicated by the provision of the adder / subtractor 36, the self-diagnosis operation can be performed at a high speed because only two cycles are required. In the fourth embodiment, since the self-diagnosis operation is performed in three cycles, it takes much time. Therefore, the first embodiment shown in FIG. 3 and the fourth embodiment shown in FIG. 7 may be used in accordance with a request for either simplifying the circuit configuration or increasing the speed of the self-diagnosis operation.

  FIG. 8 is a circuit block diagram of a fifth embodiment of a processor with a self-diagnosis function according to the present invention. In the fifth embodiment, the adder / subtracter 36 provided on the output side in the third embodiment of FIG. 6 is omitted, and the adder / subtracter provided in the test object 10 as in the fourth embodiment of FIG. 65 is used for the second addition.

  In FIG. 8, the arithmetic circuit 10-1 has a general-purpose register file 14, multiplexers 20 and 22, a first source register 24, a second source register 26, and an inverter 30 on the input side of a two-input adder / subtractor 65 to be tested 10. , The +1 increment circuit 61 and the multiplexer 28 are the same as in the third embodiment of FIG. 6, but in addition to this, the multiplexer 64 is provided on the input side of the adder / subtractor 65 as in the fourth embodiment of FIG. , 66 are newly provided.

  The multiplexers 64 and 66 select and output the first operand of the first source register 24 and the second operand of the multiplexer 28 during the subtraction operations of the first and second cycles of the self-diagnosis test. In the addition operation in the third cycle, the output side of the adder / subtractor 65 is controlled to be selected.

  Further, the self-diagnosis processing unit 10-2 side is configured by a self-diagnosis controller 44 including a TAP controller 42 and an all-zero detector 48, as in the third embodiment of FIG.

  Next, the operation of the self-diagnosis test of the fifth embodiment in FIG. 8 will be described. When the BIST START signal from the TAP controller 42 is asserted and the self-diagnosis controller 44 starts a self-diagnosis operation, arbitrary test data X and Y are first read from the general-purpose register file 14 and selected by the multiplexers 20 and 22. They are stored in the first source register 24 and the second source register 26.

  At this time, the decoder 50 outputs a subtraction instruction SUB under the control of the self-diagnosis controller 44, and the multiplexer 28 inverts the test data Y held in the second source register 26 by the inverter 30 to make a one's complement Y1's. Thereafter, by adding 1 by the +1 increment circuit 61, the output of 2's complement Y2's is selected.

The multiplexers 64 and 66 select the outputs of the first source register 24 and the multiplexer 28 based on the control signal E5. Therefore, in the first cycle, the first operand X and the second operand Y2's are input to the adder / subtractor 65 of the test object 10,
Z = X + Y2 ′s = X + Y1 ′s + 1 = X−Y
The operation result Z is executed, and the operation result Z is held in the destination register 32.

  In the next second cycle, the multiplexer 20 selects and outputs the value Y of the second source register 26 by the control signal E2 of the self-diagnosis controller 44, and the multiplexer 22 simultaneously outputs the value X of the first source register 24. Is selected and output, and the input data X and Y are switched.

The selection states of the multiplexer 28 and the multiplexers 64 and 66 are the same. For this reason, the first operand Y and the second operand X2's are input to the adder / subtractor 65 of the test object 10,
Z ″ = Y + X2 ′s = Y + X1 ′s + 1 = Y−X
Perform subtraction. This second subtraction result Z ″ is held in the destination register 32, and after one clock, the first subtraction result Z is held in the destination register 34.

  In the next third cycle, the decoder 50 outputs the addition instruction ADD under the control of the self-diagnosis controller 44, and the multiplexer 64 selects and outputs the value Z held in the destination register 34 by the control signal E5. At the same time, the multiplexer 66 selects and outputs the value Z ′ held in the destination register 32.

  Therefore, for the third time, the adder / subtractor 65 inputs the first operand Z and the second operand Z ′, executes the calculation of Z ″ = Z + Z ′, and holds the calculation result Z ″ in the destination register 32. The calculation result 40 in the third cycle is given to the all-zero detector 48 of the self-diagnosis controller 44, and the presence or absence of all-zero is checked.

If the final calculation result Z '' by the self-diagnosis at this time is normal, the adder / subtractor 65 is
Z ″ = Z + Z ′ = (X−Y) + (Y−X)
= X + Y2's + Y + X2's
= (X + X2's) + (Y + Y2's)
= 0 + 0
= 0
It becomes. For this reason, when the all-zero detector 48 detects all bits of all zeros from the calculation result 40, the adder / subtractor 45 determines that it is normal. On the other hand, if it is not all zero, it determines that the adder / subtractor 65 is abnormal and sends the error signal E4 to the external. Output to.

  In the fifth embodiment of FIG. 8, in contrast to the third embodiment of FIG. 6, the third embodiment requires three cycles, whereas the self-diagnosis test operation is completed in two cycles. However, there is an advantage that the circuit configuration of the arithmetic circuit 10-1 can be simplified correspondingly without requiring another adder / subtracter at the output stage of the adder / subtractor 65 to be tested 10.

  FIG. 9 is a circuit block diagram of a sixth embodiment of a processor with a self-diagnosis function according to the present invention. In the sixth embodiment, two subtractions Z = X−Y of two test data and subtraction Z ′ = Y−X in which the test data are exchanged are simultaneously executed in one cycle of the self-diagnosis test. The addition result Z ″ = Z + Z ′ is executed.

  In the sixth embodiment of FIG. 9, the first source register 24 and the second source register 26 are directly connected to the input side of the two-input adder / subtractor 12 with a carry input to be tested 10 immediately after the general-purpose register file 14. The multiplexers 20 and 22 in the first embodiment of FIG. 3 are omitted.

  The value of the first source register 24 is input as the first operand of the adder / subtractor 12 to be tested 10, and the value of the second source register 26 or the value inverted by the inverter 30 is input to the multiplexer 28 as the second operand. Is selected. The output of the adder / subtractor 12 is provided with a destination register 32, and the value of the destination register 32 is input to the next adder / subtractor 36.

  Subtraction Z = X−Y is executed by the system of the first source registers 24 and 26, the inverter 30, the multiplexer 28, the adder / subtractor 12, and the destination register 32. On the other hand, an inverter 70, a multiplexer 68, an adder / subtractor 72, and a destination register 34 are provided in parallel with the operation system of the operation Z.

  The multiplexer 68 selects and outputs the value of the first source register 24 or the value inverted by the inverter 70. The adder / subtractor 72 receives the value of the second source register 26 as the first operand, the value selected by the multiplexer 68 as the second operand, and the input from the carry input Cin. Store in the nation register 74.

  The adder / subtractor 36 inputs the operation results Z and Z ′ stored in parallel in each of the destination registers 32 and 74 as operands, performs addition of Z ″ = Z + Z ′, and stores it in the destination register 38. Store.

  On the other hand, the self-diagnosis processing unit 10-2 side is constituted by a self-diagnosis controller 44 having a TAP controller 42 and an all-zero detector 48.

  Next, the operation of the self-diagnosis test of the sixth embodiment in FIG. 9 will be described. When the TAP controller 42 asserts the BIST START signal, the self-diagnosis controller 44 operates and starts a self-diagnosis test. First, arbitrary test data X and Y stored in the general-purpose register file 14 are read from the read port and held in the first source register 24 and the second source register 26, respectively.

  At this time, the decoder 50 outputs the subtraction instruction SUB by the control signal E1 of the self-diagnosis controller 44. For this reason, the multiplexers 68 and 28 select the outputs of the inverters 70 and 30. The carry input Cin to the adders / subtracters 12 and 72 is Cin = 1.

  Therefore, the first operand X, the second operand Y1's, and the carry input Cin = 1 are input to the adder / subtracter 12, and the operation of Z = X + Y1's + 1 is executed and held in the destination register 32. At the same time, the adder / subtracter 72 receives the first operand Y, the second operand X1's, and the carry input Cin = 1, performs the operation of Z '= Y + X1's + 1, and holds it in the destination register 74.

  As a result, the adder / subtracter 36 executes addition Z ″ = Z ′ + Z with the value Z ′ of the destination register 74 as the first operand and the value Z of the destination register 732 as the second operand, and adds it to the destination register 38. Hold the result Z ″.

Therefore, the calculation result 40 obtained in the first cycle of the self-diagnosis process is given to the all-zero detector 48 of the self-diagnosis controller 44. Here, the calculation result 40Z ″ from the adder / subtracter 36 is obtained when the adder / subtractor 12 to be tested 10 is normal.
Z ″ = Z + Z ′
= (X−Y) + (Y−X)
= X + Y2's + Y + X2's
= (X + X2's) + (Y + Y2's)
= 0 + 0
= 0
It has become.

  For this reason, when the all-zero detector 48 of the self-diagnosis controller 44 detects all bits zero of the calculation result 40, the adder / subtracter 12 of the test object 10 is determined to be normal, while when it is determined that it is not all zero, the adder / subtractor 12 is determined to be abnormal. Then, error execution E4 is output to the outside.

  In the sixth embodiment of FIG. 9, the subtraction of the two test data X and Y and the subtraction obtained by exchanging the test data are performed simultaneously, and the self-diagnosis operation is completed in one cycle by adding the subtraction results. And higher-speed self-diagnosis processing can be executed.

  FIG. 10 is a circuit block diagram of a seventh embodiment of a processor having a self-diagnosis processing function according to the present invention. The seventh embodiment is characterized in that the two-cycle self-diagnosis test process in the second embodiment of FIG. 4 is speeded up in one cycle.

  In FIG. 10, in the arithmetic circuit unit 10-1 of the seventh embodiment, a first source register 24 and a second source register 26 are provided directly after the general-purpose register file 14, and the second embodiment of FIG. The form of multiplexers 20, 22 is omitted. The first and second source registers 24 and 26, the inverter 30, the multiplexer 28, the adder / subtracter 12 with carry input as the test object 10, and the destination register 32 constitute an arithmetic system of Z = XY.

  On the other hand, the first and second source registers 24 and 26, the inverter 70, the multiplexer 68, the adder / subtractor 72 with the carry input Cin, and the destination register 74 are used to calculate Z ′ = Y−X by exchanging the test data X and Y. The system is configured. It can be seen that this is the same as the sixth embodiment of FIG.

  Since the seventh embodiment corresponds to the second embodiment of FIG. 5, the comparator 54 is provided following the two systems of subtraction results Z and Z ′. The subtraction result Z of the destination register 32 is input to one side of the comparator 54. The other input of the comparator 54 is obtained by inverting the subtraction result Z ′ held in the destination register 74 by the inverter 56 to obtain one's complement Z′1 ′s, and then adding 1 by the +1 increment circuit 58. It is converted to 2's complement Z'2's and input.

  For this reason, the comparator 54 compares the subtraction result Z and the two's complement Z'2's of the subtraction result Z ', and inputs the comparison result 40-1 to the error detector 60 of the self-diagnosis controller 44-1. If the calculation result Z in the comparator 54 and the two's complement Z′2 ′s of the calculation result Z ′ match, the adder / subtracter 12 to be tested 10 is normal, and if not, the adder / subtractor 12 is abnormal. Yes, this is detected by the error detector 60, and an error signal E4 indicating an abnormality of the adder / subtractor 12 is output to the outside.

  The self-diagnosis processing unit 10-2 includes a TAP controller 42 and a self-diagnosis controller 44-1. The difference from the first embodiment in FIG. 5 is that the multiplexers 20 and 22 on the first and second source registers 24 and 26 side are different. There is no control signal.

  Next, the operation of the self-diagnosis test in the seventh embodiment of FIG. 10 will be described. When the TAP controller 42 asserts the BIST START signal, the self-diagnosis controller 44-1 is activated and a self-diagnosis test of the arithmetic circuit 10-1 is started. First, arbitrary test data X and Y are read from the general-purpose register file 14 from the read port, and the test data X is held in the first source register 24 and the test data Y is held in the second source register 26.

  At this time, the decoder 50 decodes the operation code 52 by the control signal E1 of the self-diagnosis controller 44-1, and outputs a subtraction instruction SUB. As a result, the multiplexers 68 and 28 select the outputs of the inverters 70 and 30.

  At this time, when looking at the adder / subtracter 12 as the test object 10, the first operand X, the second operand Y2's and the carry input Cin = 1 are input, and Z = X + Y1's and the carry input Cin = 1 are input. Then, the subtraction of Z = X + Y1 ′s + 1 is executed, and the subtraction result Z is held in the destination register 32.

  At the same time, the adder / subtracter 72 receives the first operand Y, the second operand X1's and the carry input Cin = 1, executes the operation of Z '= Y + X1's + 1, and holds the operation result in the destination register 74.

  Further, the comparator 54 inputs the operation result Z held in the destination register 32, and the operation result Z ′ held in the destination register 34 is inverted by the inverter 56 to be a one's complement Z′1 ′s. By adding 1 by the +1 increment circuit 58, it is converted into 2's complement Z'2's and inputted, and the two are compared.

  At this time, if the adder / subtracter 12 of the test object 10 is normal, Z and Z′2 ′s input to the comparator 54 coincide with each other, and this comparison coincidence is detected by the error detector 60 of the self-diagnosis controller. Recognize that the vessel 12 is normal. On the other hand, if Z and Z'2's do not match in the comparator 54, the error detector 60 determines that the adder / subtractor 12 of the test object 10 is abnormal, and outputs an error signal E4 to the outside.

  In the seventh embodiment of FIG. 10, as compared with the second embodiment of FIG. 5, the two's complement Z′2 of the subtraction Z = X−Y and the subtraction Z ′ = Y−X necessary for the comparison processing is provided. The comparison result can be obtained by calculating 's in one cycle of the self-diagnosis test, and a higher-speed self-diagnosis operation can be performed.

  FIG. 11 is a circuit block diagram of an eighth embodiment of a processor with a self-diagnosis function according to the present invention. In the eighth embodiment, with respect to the adder / subtracter 65 having no carry input Cin of the test object 10 in the third embodiment of FIG. 6, the subtraction of the test data X and Y and the same as in the sixth embodiment of FIG. The replacement is performed in parallel and the operation is completed in one cycle.

  In FIG. 11, the arithmetic circuit unit 10-1 is provided with a first source register 24 and a second source register 26 directly after the general-purpose register file 14. The first source register 24 and the second source register 26, the inverter 30, the +1 increment circuit 61, the multiplexer 28, the adder / subtractor 65 and the destination register 32 of the test object 10 constitute an arithmetic system of subtraction Z = XY. Yes.

  Further, the subtraction Z ′ = Y−X in which the test data X and Y are exchanged by the first and second source registers 24 and 26, the inverter 76, the +1 increment circuit 78, the multiplexer 68, the adder / subtractor 72, and the destination register 74. The system is configured.

  The subtraction results Z and Z ′ held in the destination registers 32 and 74 performed in parallel are input to the adder / subtracter 36, and Z ″ = Z + Z ′ is added and held in the destination register 38. The calculation result 40 is output to the all-zero detector 48 of the self-diagnosis controller 44. Of course, the TAP controller 42 and the self-diagnosis controller 44 are provided on the self-diagnosis processing unit 10-2 side.

  Next, the operation of the self-diagnosis test in the embodiment of FIG. 11 will be described. When the TAP controller 42 asserts the BIST START signal, the self-diagnosis controller 44 is activated. First, arbitrary test data X and Y are read from the general-purpose register file 14 from the read port, and the first source register 24 and the second source register 26 are read. Hold on each. At this time, the decoder 54 outputs the subtraction instruction SUB by the control signal E1 of the self-diagnosis controller 44.

  As a result, the multiplexers 68 and 61 select the outputs of the +1 increment circuits 78 and 61. First, looking at the operation on the adder / subtractor 12 side, the adder / subtractor 12 inverts the first operand X of the first source register 24 and the test data Y of the first source register 26 by the inverter 30 to a 1's complement Y1's. After the conversion, the second operand converted to 2's complement Y2's by adding 1 by the +1 increment circuit 61 is input.

  For this reason, the adder / subtractor 12 performs the operation of Z = X + Y2 ′s = X + Y1 ′s + 1 = XY, and holds the operation result Z in the destination register 32. At the same time, the adder / subtracter 72 inverts the operand Y of the second source register 26 and the input data Y of the first source register 24 by the inverter 76 to convert it into a one's complement Y1's, and then adds 1 by the +1 increment circuit 78. The second operand converted to 5's 2's complement X2's is input, Z '= Y + X2's = Y + X1's + 1 = Y-X is executed, and the operation result Z' is held in the destination register 74. .

  Therefore, the adder / subtractor 36 inputs the first operand Z ′ of the destination register 74 and the second operand Z of the destination register 32 and executes addition of Z ″ = Z ′ + Z. Is stored in the destination register 38 and output to the all-zero detector 48 of the self-diagnosis controller 44 as the operation result 40.

Z ″ as the calculation result 40 is Z ″ = Z + Z ′ = (X−Y) + (Y−X) when the adder / subtracter 12 of the test object 10 is normal.
= X + Y2's + Y + X2's
= (X + X2's) + (Y + Y2's)
= 0 + 0
= 0 (11)
It becomes. Therefore, the all-zero detector 48 of the self-diagnosis controller 44 determines that the adder / subtractor 12 is normal if Z ″ of the calculation result 40 is all zero, and determines that the adder / subtractor 12 is abnormal if the calculation result 40 is not all zero. Is output to the outside.

  FIG. 12 is a circuit block diagram of a ninth embodiment of a processor having a self-diagnosis function according to the present invention. The ninth embodiment is characterized in that the adder / subtracter 36 in the sixth embodiment of FIG. 9 is omitted, and this addition is performed by the adder / subtractor 12 of the test object 10.

  That is, in the sixth embodiment shown in FIG. 9, all calculations are completed in the first cycle, but in the ninth embodiment shown in FIG. 12, two cycles are required. The circuit configuration is simplified by eliminating the adder / subtractor 36.

  In FIG. 12, the subtraction Z = X−Y for any two test data X and Y read from the register file 14 by the arithmetic circuit 10-1 is the first source register 24, the second source register 26, the inverter 30, This is performed by the system of the multiplexer 28, the adder / subtractor 12 as the test object 10, and the destination register 32. In this system, multiplexers 80 and 82 are newly provided at the input stage of the adder / subtractor 12.

  Further, subtraction Z ′ = Y−X in which arbitrary test data X and Y read out from the general-purpose register file 14 are replaced with the first source register 24, the second source register 26, the inverter 70, the multiplexer 68, the adder / subtractor 72, and the destination. An operation is executed in the system of the register 34.

  The multiplexers 80 and 82 are switched by the addition instruction ADD and the subtraction instruction SUB from the decoder 50. When the subtraction instruction SUB is output, the outputs of the multiplexers 68 and 28 are selected. On the other hand, in the case of the addition instruction ADD, the values of the destination registers 74 and 32 are selected and output. The self-diagnosis processing unit 10-2 side includes a TAP controller 42 and a self-diagnosis controller 44 having an all-zero detector 48.

  Next, the operation of the self-diagnosis test of the ninth embodiment in FIG. 12 will be described. When the TAP controller 42 asserts the BIST START signal, the self-diagnosis controller 44 starts a self-diagnosis test. First, arbitrary test data X and Y are read from the general-purpose register file 14, held in the first source register 24 as the first operand X, and held in the second source register 26 as the second operand Y.

  At this time, the decoder 50 decodes the operation code 52 by the control signal E1 from the self-diagnosis controller 44 and outputs a subtraction instruction SUB. Therefore, the multiplexers 68 and 28 select the outputs of the inverters 70 and 30, respectively. Further, the output of the first source register 24 of the multiplexers 80 and 82 and the output of the multiplexer 28 are selected.

  As a result, the adder / subtractor 12 to be tested 11 receives the first operand X, the 1's complement Y1's obtained by inverting the test data Y by the inverter 30 as the second operand, and the carry input Cin = 1. As a result, the adder / subtractor 12 performs the operation of Z = X + Y1 ′s + 1 and holds the operation result Z in the destination register 32.

  At the same time, the adder / subtracter 72 receives the 1's complement X1's obtained by inverting the test data X of the first source register 24 by the inverter 70 as the first operand X and the second operand, and the carry input Cin = 1. Yes. For this reason, the adder / subtracter 72 executes the calculation of Z ′ = Y + X1 ′s + 1 and holds the calculation result in the destination register 74.

  In the next second cycle, the self-diagnosis controller 44 controls the decoder 50 by the control signal E1 to output the addition instruction ADD, and instructs the addition operation of the adder / subtractor 12 by the control signal E3. By the addition instruction ADD from the decoder 50, the multiplexer 80 selects the output of the destination register 34, and the multiplexer 82 selects the output of the destination register 32.

  Therefore, the adder / subtractor 12 receives the first operand Z ′, the second operand Z, and the carry input Cin = 0, performs the operation of Z ″ = Z ′ + Z, and holds it in the destination register 32. The value Z ″ of the destination register 32 is given as an operation result 40 to the all-zero detector 48 of the self-diagnosis controller 44.

Here, when the adder / subtracter 12 as the test object 10 is normal, Z ″ = Z + Z ′ = (X−Y) + (Y−X).
= X + Y2's + Y + X2's
= (X + X2's) + (Y + Y2's)
= 0 + 0
= 0 (11)
It becomes.

  For this reason, the all-zero detector 48 of the self-diagnosis controller 44 determines that the adder / subtractor 12 is normal if all the bits of the calculation result 40 are all zero, while it determines that the adder / subtractor 12 is abnormal if it is not all zero. The signal E4 is output to the outside.

  FIG. 13 is a circuit block diagram of a tenth embodiment of a processor with a self-diagnosis function according to the present invention. In the tenth embodiment, the adder / subtracter 36 provided in the output of the eighth embodiment of FIG. 11 is omitted, and the addition process is performed by the adder / subtractor 12 of the test object 10. Since the 11 adder / subtractors 36 are not provided, the circuit configuration can be simplified.

  In the tenth embodiment shown in FIG. 13, the arithmetic circuit 10-1 newly provides multiplexers 80 and 82 before the adder / subtractor 12 of the test object 10 in the eighth embodiment shown in FIG. 11. The output of the destination registers 34 and 38 can be selected and input to the adder / subtractor 12, and the other configuration is the same as that of the embodiment of FIG.

  The operation of the self-diagnosis process of the tenth embodiment of FIG. 13 will be described as follows. When the TAP controller 42 asserts the BIST START signal, the self-diagnosis controller 44 operates and a self-diagnosis test is started. First, arbitrary test data X and Y are read from the general-purpose register file 14 and held in the first and second source registers 24 and 26, respectively.

  At this time, the decoder 50 outputs the subtraction instruction SUB, and the multiplexers 68 and 28 select the outputs of the +1 increment circuits 78 and 61. The multiplexers 80 and 82 select the outputs of the first source register 24 and the multiplexer 28 based on the control signal E6.

  For this reason, the adder / subtracter 12 of the test object 10 is inverted by the inverter 30 as the first operand X and the second operand to be converted to 1's complement Y1's, and then added by 1 by the +1 increment circuit 61 to become 2's. The value converted to the complement Y2's is input. As a result, the adder / subtractor 12 performs an operation of Z = X + Y2's and holds it in the destination register 38.

  At the same time, the 2nd complement X2's obtained by adding 1 by the +1 increment circuit 78 to the 1's complement X1's obtained by inverting the first operand Y and the test data X by the inverter 76 is input to the adder / subtractor 72. As a result, the adder / subtracter 72 executes the calculation of Z ′ = Y + X2 ′s, and holds the calculation result Z ′ in the destination register 74.

  In the next second cycle, the self-diagnosis controller 44 outputs the addition instruction ADD under the control of the decoder 50, and switches the multiplexers 80 and 82 to the selected state of the destination registers 38 and 74 by the control signal E6. Therefore, the adder / subtractor 12 inputs the first operand Z ′ from the multiplexer 80 and also inputs the second operand Z from the multiplexer 82, thereby executing the subtraction Z ″ = Z ′ + Z, and obtaining the operation result Z ″. The result is held in the destination register 38 and is output as an operation result 40 to the all-zero detector 48 of the self-diagnosis controller 44.

Here, Z ″ as the final calculation result 40 is, if the adder / subtractor 12 is normal,
Z ″ = Z + Z ′ = (X−Y) + (Y−X)
= X + Y2's + Y + X2's
= (X + X2's) + (Y + Y2's)
= 0 + 0
= 0 (11)
It becomes.

  For this reason, the all-zero detector 48 of the self-diagnosis controller 44 determines that the adder / subtracter 12 as the test object 10 is normal if all-zero is detected, and determines that the adder / subtractor 12 is abnormal if it is not all-zero. An error signal E4 is output.

  FIG. 14 is a circuit block diagram showing an eleventh embodiment of a processor having a self-diagnosis function according to the present invention. The eleventh embodiment is characterized in that pseudorandom numbers are generated using a linear feedback shift register (LFSR) as test data for a self-diagnosis test.

  The eleventh embodiment shown in FIG. 14 has a configuration in which linear feedback shift registers 84 and 86 for generating pseudo-random numbers are added to the first embodiment shown in FIG. With the addition of the linear feedback shift registers 84 and 86, three-input multiplexers 88 and 90 are provided at the input stages of the first source register 24 and the second source register 26, and the register file 14, the source registers 24 and 26, or One of the linear feedback shift registers 84 and 86 can be selected. Other configurations of the arithmetic circuit 10-1 and the self-diagnosis processing unit 10-2 are the same as those in the first embodiment of FIG.

  FIG. 15 shows an example of the circuit configuration of the linear feedback shift register for generating pseudo-random numbers used in FIG. The linear feedback shift register 84 includes, for example, a 32-bit wide shift register 92 and an EX-OR circuit 94. The EX-OR circuit 94 inputs two bits at arbitrary positions out of 32 bits B0 to B31 in the shift register 92, for example, the 19th bit B18 and the 26th bit B25, and obtains the exclusive OR thereof, for example. A configuration is adopted in which shift input is performed to the most significant bit B31 (which may be input to the least significant bit B0).

  In FIG. 14, for example, arbitrary test data X read from the general-purpose register file 14 is loaded as an initial value into the shift register 92, and the output of the EX-OR 94 is shifted in by supplying a shift clock after loading. However, the test data is output as pseudorandom data as 32-bit shift data, and the self-diagnosis test is executed.

  Next, the operation of the self-diagnosis test will be described for the first embodiment of FIG. When the TAP controller 42 asserts the BIST START signal, the self-diagnosis controller 44 is activated and starts the operation of the self-diagnosis test of the arithmetic circuit 10-1. First, arbitrary test data X and Y are read from the general-purpose register file 14, selected by multiplexers 88 and 90, and the shift registers of the linear feedback shift registers 84 and 86 via the first source register 24 and the second source register 26. Is set as initial data.

  When the initial data set for the linear feedback shift registers 84 and 86 is ready in this way, the self-diagnosis controller 44 sets the multiplexers 88 and 90 to the selected state of the outputs of the linear feedback shift registers 84 and 86 by the control signal E2. The self-diagnosis operation using the pseudo random number test data output from the linear feedback shift registers 84 and 86 in synchronization with the shift clock is started. This self-diagnosis operation is the same as that of the first embodiment of FIG.

  FIG. 16 is a circuit block diagram of a twelfth embodiment of a processor having a self-diagnosis function according to the present invention. In the twelfth embodiment, linear feedback shift registers 84 and 86 for generating pseudo-random data are provided in the second embodiment for comparing the two subtraction results in FIG. 5 as in the eleventh embodiment in FIG. And the self-diagnosis test is repeatedly performed while generating pseudo-random number data by the multiplexers 88 and 90. Other points are the same as in the second embodiment of FIG.

  FIG. 17 is a circuit block diagram of a thirteenth embodiment of a processor having a self-diagnosis function according to the present invention. The thirteenth embodiment is characterized in that linear feedback shift registers 84 and 86 that generate pseudorandom data and multiplexers 88 and 90 that perform selection output are provided for the fourth embodiment of FIG. The point is the same as that of 4th Embodiment of FIG.

  FIG. 18 is a circuit block diagram of a fourteenth embodiment of a processor having a self-diagnosis function according to the present invention. This 14th embodiment is characterized in that, in the sixth embodiment of FIG. 9, linear feedback shift registers 84 and 86 for generating pseudo-random numbers and multiplexers 88 and 90 for selecting the outputs are provided. Is the same as in the sixth embodiment of FIG.

  FIG. 19 is a circuit block diagram of a fifteenth embodiment of a processor having a self-diagnosis function according to the present invention. The fifteenth embodiment is characterized in that the fifth embodiment of FIG. 8 is provided with linear feedback shift registers 84 and 86 for generating pseudo-random numbers and multiplexers 88 and 90 for selecting their outputs. Other configurations and operations are the same as those of the fifth embodiment shown in FIG.

  FIG. 20 is a circuit block diagram of a sixteenth embodiment of a processor having a self-diagnosis function according to the present invention. In the sixteenth embodiment, test data X is generated as a pseudorandom number from a single linear feedback shift register, and one test data X is inverted to obtain one's complement X1's, and subtraction Z = The calculation of XY is performed by generating the complement X2's. If the subtraction result Z is all zero, the adder / subtractor 12 of the test object 10 is normal, and if it is not all zero, the adder / subtractor 12 is determined to be abnormal.

  First, the arithmetic circuit 10-1 will be described. The multiplexer file 20 and 22, the first source register 24 and the second source register 26 are provided after the register file 14, and a linear feedback shift register 84 for generating a pseudo random number is further provided. ing.

  The multiplexer 20 selects and outputs either the source data 16 as the first operand from the general-purpose register file 14 or the test data from the linear feedback shift register 84. The multiplexer 22 selects and outputs the output obtained by inverting the test data of the second operand source data 18 from the general-purpose register file 14 or the test data of the linear feedback shift register 84 into the one's complement by the inverter 96.

  Here, assuming that the test data output from the linear feedback shift register 84 is X, the test data X is held in the first source register 24 during the self-diagnosis test, and at the same time, the second source register 26 is supplied with an inverter 96. Inverted and converted to 1's complement X1's is held.

  Following the first source register 24 and the second source register 26, a two-input adder / subtractor 12 with a carry input Cin is provided as the test object 10. The adder / subtractor 12 receives the first operand A and the second operand B, and the carry input Cin. When the decoder 50 outputs the addition instruction ADD, the adder / subtractor 12 executes the operation C = A + B + 0 = A + B. When SUB is output, the calculation of C ′ = A + B + 1 = A + B1 ′s is executed.

  At this time, when 1's complement B1's is input from the second source register 26 as the second operand, the operation of C '= A + B1's + 1 = A + B2's = AB is executed.

  The calculation result of the adder / subtracter 12 is held in the destination register 32, and is finally written and reflected in the general-purpose register file 14 by the data forward path 35 in normal calculation processing. On the other hand, in the self-diagnosis test according to the present invention, the calculation result 40 is output to the all-zero detector 48 of the self-diagnosis controller 44.

  Next, the operation of the self-diagnosis test in the sixteenth embodiment of FIG. 20 will be described. When the TAP controller 42 asserts the BIST START signal, the self-diagnosis controller 44 operates to read arbitrary test data X and Y from the general-purpose register file 14. Among these, the input data X as the first source data 16 is the multiplexer 20. The initial value is set in the linear feedback shift register 84 via the first source register 24.

  Thereafter, pseudo random number test data is generated for each processing cycle, selected by the multiplexers 20 and 22 and held as the first operand X in the first source register 24, while the second source register 26 is supplied with an inverter 96. It is held as the inverted second operand X1's.

The adder / subtractor 12 receives the first operand X, the second operand X1 ′s, and the carry input Cin = 1 because the decoder 50 outputs the addition instruction SUB under the control of the self-diagnosis controller 44.
Z = X + X1 ′s + 1 = X + X2 ′s = X−X
The operation result Z is executed, and the operation result Z is held in the destination register 32.

  The value held in the destination register 32 is output as an operation result 40 to the all-zero detector 48 of the self-diagnosis controller. If all bits are all 0, it is determined that the adder / subtractor 12 has operated normally, and if not all-zero. Since the adder / subtractor 12 is abnormal, an error execution E4 is output to the outside.

  In the sixteenth embodiment, when the first subtraction using the adder / subtractor 12 to be tested 10 is operating normally, an operation result of all 0 is obtained. Compared with the embodiment of FIG. 19, the circuit configuration of the arithmetic circuit 10-1 can be greatly simplified. In addition to the simplification of the configuration of the arithmetic circuit 10-1, the arithmetic processing cycle is short, so that higher-speed processing can be performed.

  In the sixteenth embodiment of FIG. 20, the calculation of the adder / subtractor 12 to be tested 11 is performed only once in one self-diagnosis test, and the test in the embodiments of FIGS. Compared to the case where the arithmetic operation of the adder / subtractor 12 serving as the object 10 is performed twice, the reliability of the evaluation of the self-diagnosis test is lowered accordingly. In order to solve this problem, the self-diagnosis test evaluation result equivalent to that of the embodiment shown in FIGS.

  FIG. 21 is a circuit block diagram of a seventeenth embodiment of a processor having a self-diagnosis function according to the present invention. In the seventeenth embodiment, the configuration of the same arithmetic circuit 10-1 as that in the sixteenth embodiment in FIG. 20 is basically simplified, and an adder / subtracter 65 having no carry input is used as the test object 10. The target points are different.

  By using the adder / subtractor 65 not having the carry input Cin as the test object 11, the test data X is inverted to the output line of the linear feedback shift register 84 for the multiplexer 22 on the second source register 26 side, and the one's complement is obtained. The +1 increment circuit 98 is provided following the inverter 96 for providing X1's, and 1 is added to the one's complement X1's to convert it to 2's complement X2's. The other configuration is the same as that of the sixth embodiment in FIG. The operation of the seventeenth embodiment is as follows.

  When the TAP controller 42 asserts the BIST START signal, the self-diagnosis controller 44 operates to set the first source data 16 read from the general-purpose register file 14 to the linear feedback shift register 84 via the multiplexer 20 and the first source register 24. Thereafter, the self-diagnosis operation is performed using the pseudo-random number from the linear feedback shift register 84 as test data.

  That is, during the self-diagnosis operation, the multiplexers 20 and 22 have selected the output on the linear feedback shift register 84 side by the control execution E2. If the linear feedback shift register 84 outputs the test data X at this time, the test data X is held as the first operand in the first source register 24, while the test data X is stored in the second source register 26 as an inverter. After being inverted at 96 and converted to 1's complement X1's, the +1 increment circuit 98 adds 1 to convert it to 2's complement X2's.

As a result, the adder / subtracter 65 as the test object 10 inputs the first operand X and the second operand Y2's,
Z = X + X2 ′s = X + X1 ′s + 1 = X−X
The above calculation is executed and held in the destination register 32.

  The value Z held in the destination register 32 is input as an operation result 40 to the all-zero detector 48 of the self-diagnosis controller 44. The all-zero detector 48 determines that the adder / subtracter 65 as the test object 10 is normal if the value Z of the operation result 40 is 0 in all bits. On the other hand, if the value Z as the calculation result 40 is not all 0 bits, the adder / subtracter 65 as the test object 10 determines that the error is abnormal, and outputs an error signal E4 to the outside.

  In the above embodiment, the arithmetic circuit is configured such that the calculation result in the self-diagnosis test is all zero, and the self-diagnosis process is performed as an example. In addition, the arithmetic circuit and the self-diagnosis processing unit may be configured so that all 1 that allows easy inspection of the operation result can be obtained without using the expected value.

  The configuration in which all 1 is obtained as a result of this calculation is the case where the negative logic configuration of each of the above embodiments is employed. Moreover, this invention is not limited to said embodiment, The appropriate deformation | transformation which does not impair the objective and advantage is included. Further, the present invention is not limited by the numerical values shown in the above embodiments.

  Although the embodiment of the present invention has been described above, the embodiment of the present invention similarly discloses the invention described below.

In a processor with a self-diagnosis function,
The arithmetic circuit
A first source register storing a first operand A;
A second source register storing a second operand B;
A pseudo-random number generator that generates a new operand and stores it in the first source register by a random number generation process for each operation period after inputting one of the first and second operands as an initial value;
A complement circuit for generating, for example, 2's complement B2's by inverting operand B output from the random number generator and adding 1 to the second source register;
A two-input adder / subtracter to be diagnosed without a carry input that adds the two's complement B2 ′s generated by the correction circuit to the first operand A when performing subtraction (A−B);
With
The self-diagnosis processing unit adds or subtracts the arbitrary self-diagnosis data X having a predetermined bit length stored in the first and second source registers from the pseudo random number generator and the two's complement X2 ′s of X generated by the complement circuit. Subtraction Z = (X−X) is executed as Z = (X + X2 ′s) = (X + X1 ′s + 1), and when the subtraction result Z is all 0 bits, it is determined to be normal, and all bits are not 0 In the case of, it is judged as abnormal.

(Appendix)
(Appendix 1)
An arithmetic circuit including an adder / subtracter to be diagnosed;
A data storage unit for storing self-diagnosis data;
A self-diagnosis processing unit that inputs the self-diagnosis data and causes the arithmetic circuit to execute a diagnostic process so that a calculation result is all 0 or all 1;
A processor comprising: (1)

(Appendix 2)
In the processor described in Appendix 1,
The arithmetic circuit is:
A first source register storing a first operand A;
A second source register storing a second operand B;
A complement circuit that inverts the second operand B and outputs a one's complement B1's;
The first operand A is input as a divisor, the output value B1's of the complement circuit is input as a reduction together with a carry, and a two's complement B2's obtained by adding 1 to the one's complement B1's is internally generated. A first adder / subtracter with a carry input to be diagnosed to perform subtraction C = (A−B) by adding to the first operand A,
A second adder / subtracter provided in a stage subsequent to the first adder / subtractor;
With
The self-diagnosis processing unit uses arbitrary self-diagnosis data X and Y having a predetermined bit length stored in the first and second source registers,
In the first cycle, using the complement circuit and the first adder / subtracter, the subtraction Z = (X−Y) is executed as Z = (X + Y2 ′s) = (X + Y1 ′s + 1),
In the second cycle, the attenuator X and the subtractor Y are exchanged and the subtraction Z ′ = (Y−X) is executed as Z ′ = (Y + X2 ′s) = (Y + X1 ′s + 1) using the complement circuit and the first adder / subtracter. And
In the third cycle, using the second adder / subtracter, the addition Z ″ = (Z + Z ′) = (X + X1 ′s + 1 + Y + Y1 ′s + 1) of the subtraction results Z and Z ′ of the first and second cycles is executed, and the addition result A processor characterized in that if all bits are 0, it is determined to be normal, and if all bits are not 0, it is determined to be abnormal. (2)

(Appendix 3)
In the processor described in Appendix 1,
The arithmetic circuit is:
A first source register storing a first operand A;
A second source register storing a second operand B;
A first complement circuit that inverts the second operand B and outputs a one's complement B1's;
The first operand A is input as a divisor, the output value B1's of the first complement circuit is input as a reduction together with a carry, and a two's complement B2's obtained by adding 1 to the one's complement B1's is internally stored. An adder / subtracter with carry to be diagnosed to generate and add to the first operand A to perform subtraction C = (A−B);
A second complement circuit that outputs 2's complement C2's by inverting the subtraction value C of the adder / subtractor and adding 1;
A comparator for comparing the output of the adder / subtractor and the second complement circuit;
With
The arithmetic circuit uses arbitrary self-diagnosis data X, Y having a predetermined bit length stored in the first and second source registers,
Subtract Z = (X−Y) using the first complement circuit and adder / subtracter in the first cycle as Z = (X + Y2 ′s) = (X + Y1 ′s + 1),
In the second cycle, the attenuator X and the subtractor Y are exchanged, and the subtraction Z ′ = (Y−X) is executed as Z = (Y + X2 ′s) = (Y + X1 ′s + 1) using the first complement circuit and the adder / subtracter. , The complement Z′2s = (Z1 ′s + 1) of the subtraction result Z ′ is output from the second complement circuit and compared with the subtraction result Z of the first cycle, and the two match (Z′2 ′s = Y2 ′). s−X2 ′s = X + Y2 ′s = Z), a processor is determined to be normal, and a mismatch is determined to be abnormal. (3)

(Appendix 4)
In the processor described in Appendix 1,
The arithmetic circuit is:
A first source register storing a first operand A;
A second source register storing a second operand B;
A complement circuit that outputs the 2's complement B2's by inverting the second operand B and adding 1;
The first operand A is input as an addend, and the output value B2's of the complement circuit is input as an addend and added to perform subtraction C = (A−B). And
A second adder / subtracter provided in a stage subsequent to the first adder / subtractor;
With
The self-diagnosis processing unit uses arbitrary self-diagnosis data X and Y having a predetermined bit length stored in the first and second source registers,
In the first cycle, using the complement circuit and the first adder / subtracter, the subtraction Z = (X−Y) is executed as Z = (X + Y2 ′s) = (X + Y1 ′s + 1),
In the second cycle, the attenuator X and the subtractor Y are exchanged, and subtraction Z ′ = (Y−X) is executed as Z = (Y + X2 ′s) = (Y + X1 ′s + 1) using the complement circuit and the first adder / subtractor. ,
In the third cycle, using the second adder / subtracter, the addition Z ″ = (Z + Z ′) = (X + X1 ′s + 1 + Y + Y1 ′s + 1) of the subtraction results Z and Z ′ of the first and second cycles is executed, and the addition result A processor characterized in that if all bits are 0, it is determined to be normal, and if all bits are not 0, it is determined to be abnormal. (4)

(Appendix 5)
In the processor described in Appendix 1,
The arithmetic circuit is:
A first source register storing a first operand A;
A second source register storing a second operand B;
A complement circuit that inverts the second operand B and outputs a one's complement B1's;
The first operand A is input as a divisor, the output value B1's of the complement circuit is input as a reduction together with a carry, and a two's complement B2's obtained by adding 1 to the one's complement B1's is internally generated. An adder / subtracter with carry input to be diagnosed to perform subtraction C = (A−B) by adding to the first operand A,
With
The self-diagnosis processing unit uses arbitrary self-diagnosis data X and Y having a predetermined bit length stored in the first and second source registers,
In the first cycle, the subtraction Z = (X−Y) is executed as Z = (X + Y2 ′s) = (X + Y1 ′s + 1) using the complement circuit and the adder / subtractor,
Subtract Z ′ = (Y−X) using the complement circuit and the adder / subtracter by exchanging the attenuator X and the subtractor Y in the second cycle, and execute Z = (Y + X2 ′s) = (Y + X1 ′s + 1).
In the third cycle, using the adder / subtracter, the addition of the subtraction results Z and Z ′ in the first and second cycles is performed as follows: Z ″ = (Z + Z ′) = (X + X1 ′s + 1 + Y + Y1 ′s + 1). A processor characterized in that when bit 0 is determined to be normal, all bits other than 0 are determined to be abnormal. (5)

(Appendix 6)
In the processor described in Appendix 1,
The arithmetic circuit is:
A first source register storing a first operand A;
A second source register storing a second operand B;
A complement circuit that outputs the 2's complement B2's by inverting the second operand B and adding 1;
An adder / subtracter to be diagnosed for performing subtraction C = (A−B) by inputting the first operand A as an addend and inputting and adding the output value B2 ′s of the complement circuit as an addend; ,
With
The self-diagnosis processing unit uses arbitrary self-diagnosis data X and Y having a predetermined bit length stored in the first and second source registers,
In the first cycle, the subtraction Z = (X−Y) is executed as Z = (X + Y2 ′s) = (X + Y1 ′s + 1) using the complement circuit and the adder / subtractor,
Subtract Z ′ = (Y−X) using the complement circuit and the adder / subtracter by exchanging the attenuator X and the subtractor Y in the second cycle, and execute Z = (Y + X2 ′s) = (Y + X1 ′s + 1).
In the third cycle, using the adder / subtracter, the addition of the subtraction results Z and Z ′ in the first and second cycles is performed as follows: Z ″ = (Z + Z ′) = (X + X1 ′s + 1 + Y + Y1 ′s + 1). A processor characterized in that when bit 0 is determined to be normal, all bits other than 0 are determined to be abnormal.

(Appendix 7)
In the processor described in Appendix 1,
The arithmetic circuit is:
A first source register storing a first operand A;
A second source register storing a second operand B;
A first complement circuit that inverts the second operand B and outputs a one's complement B1's;
A second complement circuit that inverts the first operand A and outputs a 1's complement A1's;
The first operand A is input as a divisor, the output value B1's of the second complement circuit is input as a reduction together with the carry, and a two's complement B2's obtained by adding 1 is internally generated to the first operand A. A first adder / subtracter with carry input to be diagnosed to perform subtraction C = (A−B) by adding,
The second operand B is input as a divisor, and the output value A1's of the first complement circuit is input as a reduction number together with a carry, and a two's complement A2's obtained by adding 1 is internally generated to generate a second operand B. A second adder / subtracter with carry input that performs subtraction C ′ = (B−A) by adding to
A third adder / subtracter for adding the outputs of the first adder / subtractor and the second adder / subtractor;
With
The self-diagnosis processing unit uses arbitrary self-diagnosis data X and Y having a predetermined bit length stored in the first and second source registers,
In the first cycle, using the first complement circuit and the first adder / subtracter, the subtraction Z = (X−Y) is executed as Z = (X + Y2 ′s) = (X + Y1 ′s + 1), and at the same time, the second complement circuit and Subtract Z ′ = (Y−X) using the second adder / subtracter in parallel as Z = (Y + X2 ′s) = (Y + X1 ′s + 1),
In the second cycle, the third adder / subtractor is used to perform the addition Z ″ = (Z + Z ′) = (X + X1 ′s + 1 + Y + Y1 ′s + 1) of the subtraction results Z and Z ′ of the first adder / subtracter and the second adder / subtracter. A processor characterized in that if the addition result is all 0 bits, it is determined to be normal, and if it is not all 0 bits, it is determined to be abnormal.

(Appendix 8)
In the processor described in Appendix 1,
The arithmetic circuit is:
A first source register storing a first operand A;
A second source register storing a second operand B;
A first complement circuit that inverts the second operand B and outputs a one's complement B1's;
A second complement circuit that inverts the first operand A and outputs a 1's complement A1's;
The first operand A is input as a divisor, the output value B1's of the second complement circuit is input as a subtract together with the carry, and a two's complement B2's obtained by adding 1 is internally generated to generate the first operand A. A first adder / subtracter with carry input to be diagnosed to perform subtraction C = (A−B) by adding to
The second operand B is input as a divisor, the output value A1's of the first complement circuit is input as a reduction together with a carry, and a two's complement A2's obtained by adding 1 is internally generated to be a second operand B. A second adder / subtracter with carry input to be diagnosed to perform subtraction C ′ = (B−A) by adding;
A third complement circuit that outputs 2's complement C'2's by inverting the subtraction value C 'of the second adder / subtracter and adding 1;
A comparator for comparing the output of the adder / subtractor and the third complement circuit;
With
The self-diagnosis processing unit uses arbitrary self-diagnosis data X and Y having a predetermined bit length stored in the first and second source registers, and uses the first complement circuit and the first adder / subtracter in a first cycle. The subtraction Z = (X−Y) is executed as Z = (X + Y2 ′s) = (X + Y1 ′s + 1), and at the same time, the subtraction Z ′ = (Y−X) using the second complement circuit and the second adder / subtractor. ) In parallel with Z = (Y + X2 ′s) = (Y + X1 ′s + 1)
In the second cycle, a complement Z′2 ′ = (Z1 ′s + 1) of the subtraction result Z ′ of the second adder / subtractor is output from the third complement circuit, and the subtraction result Z of the first adder / subtractor is output to the comparator. A processor characterized in that if both match (Z′2 ′s = Y2′s−X2 ′s = X + Y2 ′s = Z), it is determined to be normal, and if they do not match, it is determined to be abnormal.

(Appendix 9)
In the processor described in Appendix 1,
The arithmetic circuit is:
A first source register storing a first operand A;
A second source register storing a second operand B;
A first complement circuit that inverts the second operand B and adds 1 to output 2's complement B2's;
A second complement circuit that outputs 2's complement A2's by inverting the first operand A and adding 1;
A first adder / subtracter to be diagnosed that inputs the first operand A as a subordinate and inputs the output value B2 ′s of the first complement circuit as a subtract to execute subtraction C = (A−B);
A second adder / subtractor that inputs the second operand B as a subordinate and inputs the output value A2 ′s of the second complement circuit as a subtract to perform subtraction C ′ = (B−A);
A third adder / subtracter for adding the outputs of the first adder / subtractor and the second adder / subtractor;
With
The self-diagnosis processing unit uses arbitrary self-diagnosis data X and Y having a predetermined bit length stored in the first and second source registers,
In the first cycle, using the first complement circuit and the first adder / subtracter, the subtraction Z = (X−Y) is executed as Z = (X + Y2 ′s) = (X + Y1 ′s + 1), and at the same time, the second complement circuit and Subtract Z ′ = (Y−X) using the second adder / subtracter in parallel as Z = (Y + X2 ′s) = (Y + X1 ′s + 1),
In the second cycle, the third adder / subtractor is used to perform the addition Z ″ = (Z + Z ′) = (X + X1 ′s + 1 + Y + Y1 ′s + 1) of the subtraction results Z and Z ′ of the first adder / subtracter and the second adder / subtracter. A processor characterized in that if the addition result is all 0 bits, it is determined to be normal, and if it is not all 0 bits, it is determined to be abnormal.

(Appendix 10)
In the processor described in Appendix 1,
The arithmetic circuit is:
A first source register storing a first operand A;
A second source register storing a second operand B;
A first complement circuit that inverts the second operand B and outputs a one's complement B1's;
A second complement circuit that inverts the first operand A and outputs a 1's complement A1's;
The first operand A is input as a divisor, the output value B1's of the second complement circuit is input as a subtract together with the carry, and a two's complement B2's obtained by adding 1 is internally generated to generate the first operand A. A first adder / subtracter with carry input to be diagnosed to perform subtraction C = (A−B) by adding to
The second operand B is input as a divisor, the output value A1's of the first complement circuit is input as a reduction together with a carry, and a two's complement A2's obtained by adding 1 is internally generated to be a second operand B. A second adder / subtracter with carry input for performing subtraction C ′ = (B−A) by adding;
With
The self-diagnosis processing unit uses arbitrary self-diagnosis data X and Y having a predetermined bit length stored in the first and second source registers,
In the first cycle, using the first complement circuit and the first adder / subtracter, the subtraction Z = (X−Y) is executed as Z = (X + Y2 ′s) = (X + Y1 ′s + 1), and at the same time, the second complement circuit and Subtract Z ′ = (Y−X) using the second adder / subtracter in parallel as Z = (Y + X2 ′s) = (Y + X1 ′s + 1),
Using the first adder / subtracter in the second cycle, the addition of the subtraction results Z and Z ′ of the first adder / subtracter in the first cycle Z ″ = (Z + Z ′) = (X + X1 ′s + 1 + Y + Y1 ′) s + 1) is executed, and when the addition result is all bits 0, it is determined to be normal, and when it is not all bits 0, it is determined to be abnormal.

(Appendix 11)
In the processor described in Appendix 1,
The arithmetic circuit is:
A first source register storing a first operand A;
A second source register storing a second operand B;
A first complement circuit that inverts the second operand B and adds 1 to output 2's complement B2's;
A second complement circuit that outputs 2's complement A2's by inverting the first operand A and adding 1;
A first adder / subtracter to be diagnosed that inputs the first operand A as a subordinate and inputs the output value B2 ′s of the first complement circuit as a subtract to execute subtraction C = (A−B);
A second adder / subtractor that inputs the second operand B as a subordinate and inputs the output value A2 ′s of the second complement circuit as a subtract to perform subtraction C ′ = (B−A);
With
The self-diagnosis processing unit uses arbitrary self-diagnosis data X and Y having a predetermined bit length stored in the first and second source registers,
In the first cycle, using the first complement circuit and the first adder / subtracter, the subtraction Z = (X−Y) is executed as Z = (X + Y2 ′s) = (X + Y1 ′s + 1), and at the same time, the second complement circuit and Subtract Z ′ = (Y−X) using the second adder / subtractor Z = (Y + X2 ′s)
= (Y + X1's + 1)
Using the first adder / subtracter in the second cycle, the addition of the subtraction results Z and Z ′ of the first adder / subtracter in the first cycle Z ″ = (Z + Z ′) = (X + X1 ′s + 1 + Y + Y1 ′) s + 1) is executed, and when the addition result is all bits 0, it is determined to be normal, and when it is not all bits 0, it is determined to be abnormal.

(Appendix 11)
In the processor according to any one of appendices 2 to 10,
The arithmetic circuit further includes:
First pseudo-random number generation in which a new first operand is generated by random number processing and stored in the first source register every calculation cycle after the first operand A stored in the first source register is input as an initial value And
A second pseudo-random number generator that generates a new second operand by random number processing and stores it in the second source register every calculation cycle after the second operand B stored in the second source register is input as an initial value. When,
With
The self-diagnosis processing unit performs the first and second each time the self-diagnosis process using arbitrary self-diagnosis data X and Y having a predetermined bit length stored in the first and second source registers ends normally. A processor characterized by causing a pseudo-random number generator to generate new self-diagnosis data X and Y and repeatedly executing self-diagnosis processing.

(Appendix 12)
In the processor described in Appendix 1,
The arithmetic circuit is:
A first source register storing a first operand;
A second source register storing a second operand;
A pseudo-random number generator that generates a new operand A by a random number generation process for each operation cycle after inputting one of the first and second operands as an initial value and stores the new operand A in a first source register;
A complement circuit for storing one's complement A1's obtained by inverting operand A generated by the random number generator in the second source register;
Subtract C = (A−) by internally generating and adding two's complement A2 ′s obtained by inputting the first operand B as a divisor and inputting the two operands A1 ′s together with a carry as a subtract and adding 1. An adder / subtracter with carry input to be diagnosed to execute A);
With
The self-diagnosis processing unit inputs arbitrary self-diagnosis data X, X1 ′s having a predetermined bit length stored in the first and second source registers from the pseudo-random number generator to the adder / subtracter together with carry. Z = (X−X) is executed as Z = (X + X2 ′s) = (X + X1 ′s + 1). If the subtraction result is all 0 bits, it is determined to be normal, and if it is not all 0 bits, it is determined to be abnormal. A processor characterized by:

(Appendix 13)
In the processor described in Appendix 1,
The arithmetic circuit is:
A first source register storing a first operand;
A second source register storing a second operand;
A pseudo-random number generator that generates a new operand A by a random number generation process for each operation cycle after inputting one of the first and second operands as an initial value and stores the new operand A in a first source register;
A complement circuit that inverts operand A output by the random number generator and adds 1 to generate 2's complement A2's and store it in the second source register;
An adder / subtracter to be diagnosed, which inputs the first operand A as a divisor and inputs the second operand A2's as a subtract and executes subtraction C = (AA);
With
The self-diagnosis processing unit inputs arbitrary self-diagnosis data X, X1 ′s having a predetermined bit length stored in the first and second source registers from the pseudo-random number generator to the adder / subtractor and performs subtraction Z = (X−X) is executed as Z = (X + X2 ′s) = (X + X1 ′s + 1). When the subtraction result is all 0 bits, it is determined to be normal, and when it is not all 0 bits, it is determined to be abnormal. Processor.

Principle explanatory diagram of the present invention Block diagram showing the basic configuration of the present invention The circuit block diagram of 1st Embodiment of this invention Circuit diagram of 2-input adder / subtracter with carry input in FIG. The circuit block diagram of 2nd Embodiment of this invention Circuit block diagram of the third embodiment of the present invention The circuit block diagram of 4th Embodiment of this invention The circuit block diagram of 5th Embodiment of this invention Circuit block diagram of sixth embodiment of the present invention Circuit block diagram of seventh embodiment of the present invention Circuit block diagram of eighth embodiment of the present invention Circuit block diagram of ninth embodiment of the present invention Circuit block diagram of tenth embodiment of the present invention Circuit block diagram of eleventh embodiment of the present invention using pseudo-random number generation FIG. 14 is a circuit diagram of a linear feedback shift register that generates pseudo-random numbers. Circuit block diagram of the twelfth embodiment of the present invention using pseudo-random number generation Circuit block diagram of thirteenth embodiment of the present invention using pseudo-random number generation Circuit block diagram of fourteenth embodiment of the present invention using pseudo-random number generation Circuit block diagram of fifteenth embodiment of the present invention using pseudo-random number generation Circuit block diagram of sixteenth embodiment of the present invention using pseudo-random number generation Circuit block diagram of seventeenth embodiment of the present invention using pseudo-random number generation Block diagram of basic hardware configuration of conventional processor 22 is a block diagram of the basic configuration of an integer arithmetic unit including an instruction decoder in the processor of FIG. Block diagram of a conventional addition / subtraction circuit with a built-in self-diagnosis circuit

Explanation of symbols

10-1: Arithmetic circuit 10-2: Self-diagnosis processing unit 11: Test object 12, 72: Adder / subtracter (2-input adder / subtracter with carry input)
14: General-purpose register file 16: Source data (first operand)
18: Source data (second operand)
20, 22, 28, 64, 66, 68, 80, 82, 88, 90: selector 24: first source register 26: second source register 30, 56, 70, 76, 96: inverters 32, 34, 38, 74: Destination register 36: Adder / subtractor 40: Calculation result 42: Test access port controller (TAP controller)
44: Self-diagnosis controller (BIST controller)
48: all zero detector 50: decoder 52: opcode 54: comparators 58, 61, 78, 98: +1 increment 60: error detector 65: adder / subtracter (no carry input)
84, 88: Linear feedback shift register (LFSR)
92: Shift register 94: EX-OR

Claims (11)

An adder / subtracter to be diagnosed;
In the first cycle, the adder / subtracter subtracts the self-diagnosis subtract Y from the self-diagnosis subtracted number X as the first arithmetic processing, and in the second cycle, the adder / subtractor performs the diagnosis as the second arithmetic processing. A control unit that performs subtraction by exchanging the reduced number X and the diagnostic reduction number Y;
An adder that performs Z = X−Y as a result of the first arithmetic processing and Z ′ = Y−X as a result of the second arithmetic processing; and Z ″ = Z + Z ′;
A detector for detecting that all bits of the addition result Z ″ of the adder are 0;
An arithmetic processing apparatus comprising:
An adder / subtracter to be diagnosed;
In the first cycle, the adder / subtracter subtracts the self-diagnosis subtract Y from the self-diagnosis subtracted number X as the first arithmetic processing, and in the second cycle, the adder / subtractor performs the diagnosis as the second arithmetic processing. A control unit that performs subtraction by exchanging the reduced number X and the diagnostic reduction number Y;
An adder that performs Z = X−Y as a result of the first arithmetic processing and Z ′ = Y−X as a result of the second arithmetic processing; and Z ″ = Z + Z ′;
An inverter for inverting the addition result Z ″ of the adder;
A detector for detecting that all bits of the inversion result of the inverter are 1.
An arithmetic processing apparatus comprising:
The adder / subtractor has a complement circuit, an incrementer, and an adder,
The first arithmetic processing generates the Y's one's complement Y1's by the complement circuit, and adds 1 to the Y1's by the incrementer. The Y's two's complement Y2 ' subtracting the self-diagnosis subtract Y from the self-diagnostic divisor X by generating X and adding the X and Y2's using the adder,
In the second arithmetic processing, the one's complement X1 ′s of the X is generated by the complement circuit, and the two's complement X2 ′ of the X is a result of adding 1 to the X1 ′s by the incrementer. The s is generated, and the addition of the Y and the X2's using the adder is performed to perform subtraction by exchanging the diagnostic divisor X and the diagnostic subtraction Y. The arithmetic processing apparatus according to 1 or 2.
A complement circuit that inverts the self-diagnosis data X or Y to generate the inverted value X1 ′s of X or the inverted value Y1 ′s of Y;
In the first cycle, as the first calculation process, addition Z = (X + Y1 ′s + 1) for the self-diagnosis data X and the Y1 ′s generated by the complement circuit and the carry input 1 is performed, and the second cycle 1, the first carry that is the diagnosis target for performing addition Z ′ = (X1 ′s + Y + 1) for the self-diagnosis data X and the Y1 ′s generated by the complement circuit and the carry input 1 as the second arithmetic processing An adder with input;
A second adder for performing addition Z ″ = Z + Z ′ of Z that is the result of the first arithmetic processing and Z ′ that is the result of the second arithmetic processing;
A detector for detecting that all bits of the addition result Z ″ of the second adder are 0;
An arithmetic processing apparatus comprising:
A complement circuit that inverts the self-diagnosis data X or Y to generate the inverted value X1 ′s of X or the inverted value Y1 ′s of Y;
In the first cycle, as the first calculation process, addition Z = (X + Y1 ′s + 1) for the self-diagnosis data X and the Y1 ′s generated by the complement circuit and the carry input 1 is performed, and the second cycle 1, the first carry that is the diagnosis target for performing addition Z ′ = (X1 ′s + Y + 1) for the self-diagnosis data X and the Y1 ′s generated by the complement circuit and the carry input 1 as the second arithmetic processing An adder with input;
A second adder for performing addition Z ″ = Z + Z ′ of Z that is the result of the first arithmetic processing and Z ′ that is the result of the second arithmetic processing;
An inverter for inverting the addition result Z ″ of the second adder;
A detector for detecting that all bits of the inversion result of the inverter are 1.
An arithmetic processing apparatus comprising:
The arithmetic processing unit further includes a data storage unit,
6. The arithmetic processing apparatus according to claim 1, wherein the self-diagnosis subtraction number X and the self-diagnosis subtraction number Y are stored in the data storage unit.
The arithmetic processing unit further includes random number generating means,
6. The arithmetic processing unit according to claim 1, wherein the self-diagnosis subtraction number X and the self-diagnosis subtraction number Y are generated by the random number generation means.
In a self-diagnosis method of an arithmetic processing unit having an adder / subtracter to be diagnosed, an adder that performs addition, and a detector that detects that all bits are 0,
The adder / subtracter subtracts the self-diagnosis subtract Y from the self-diagnostic subtract X as the first arithmetic processing;
The subtractor performs subtraction by exchanging the diagnostic subtraction number X and the diagnostic subtraction number Y as a second calculation process;
The adder adds XY as a result of the first arithmetic processing and Y-X as a result of the second arithmetic processing; and
The detector detects that all bits of the addition result of the adder are 0;
A self-diagnosis method for an arithmetic processing unit, comprising:
In a self-diagnosis method of an arithmetic processing unit having an adder / subtracter to be diagnosed, an adder that performs addition, an inverter that inverts an input value, and a detector that detects that all bits are 1.
The adder / subtracter subtracts the self-diagnosis subtract Y from the self-diagnostic subtract X as the first arithmetic processing;
The subtractor performs subtraction by exchanging the diagnostic subtraction number X and the diagnostic subtraction number Y as a second calculation process;
The adder adds XY as a result of the first arithmetic processing and Y-X as a result of the second arithmetic processing; and
The inverter reverses the addition result of the adder; and
The detector detects that all bits of the inversion result of the inverter are 1, and
A self-diagnosis method for an arithmetic processing unit, comprising:
Computation having a complement circuit that inverts input data, a first adder with carry input to be diagnosed, a second adder that performs addition, and a detector that detects that all bits are 0 In the self-diagnosis method of the processing device,
The complement circuit inverts the self-diagnosis data Y to generate the inverted value Y1 ′s of Y;
The adder with the first carry input adds the self-diagnosis data X and the Y1's generated by the complement circuit and the carry input 1 Z = (X + Y1's + 1) as the first arithmetic processing. Steps to perform,
The complement circuit inverts the self-diagnosis data X to generate an inverted value X1's of the inverted value X of the X;
The first adder with carry input adds self-diagnosis data X and Y1 ′s generated by the complement circuit and carry input 1 Z ′ = (X1 ′s + Y + 1) as the second arithmetic processing. Steps to perform,
The second adder performs an addition Z ″ = Z + Z ″ of Z as a result of the first arithmetic processing and Z ′ as a result of the second arithmetic processing;
The detector detects that all bits of the addition result Z ″ of the adder are 0;
A self-diagnosis method for an arithmetic processing unit, comprising:
Complement circuit that inverts input data, first adder with carry input to be diagnosed, second adder that performs addition, inverter that inverts input value, and all bits are 1. In a self-diagnosis method of an arithmetic processing unit having a detector for detecting
The complement circuit inverts the self-diagnosis data Y to generate the inverted value Y1 ′s of Y;
The adder with the first carry input adds the self-diagnosis data X and the Y1's generated by the complement circuit and the carry input 1 Z = (X + Y1's + 1) as the first arithmetic processing. Steps to perform,
The complement circuit inverts the self-diagnosis data X to generate an inverted value X1's of the inverted value X of the X;
The first adder with carry input adds self-diagnosis data X and Y1 ′s generated by the complement circuit and carry input 1 Z ′ = (X1 ′s + Y + 1) as the second arithmetic processing. Steps to perform,
The second adder performs an addition Z ″ = Z + Z ′ of Z as a result of the first arithmetic processing and Z ′ as a result of the second arithmetic processing;
The inverter reverses the addition result Z ″ of the adder;
The detector detects that all bits of the inversion result of the inverter are 1, and
A self-diagnosis method for an arithmetic processing unit, comprising:

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