JP3889310B2 - Display device and driving method of display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a display device that receives a digital video signal and displays an image. In particular, the present invention relates to a display device having a light emitting element. Further, the present invention relates to an electronic device using the display device.
[0002]
[Prior art]
A display device that displays an image by arranging light emitting elements for each pixel and controlling light emission of these light emitting elements will be described below.
[0003]
In this specification, a light-emitting element is described as an element (OLED element) having a structure in which an organic compound layer that emits light when an electric field is generated is sandwiched between an anode and a cathode; however, the present invention is not limited to this. Any element that emits light by applying an electric field between the anode and the cathode can be used freely.
[0004]
A light emitting element uses both light emission (fluorescence) when transitioning from a singlet exciton to a ground state and light emission element (phosphorescence) when transitioning from a triplet exciton to a ground state. The description will be made assuming that
[0005]
Examples of the organic compound layer include a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer. The light emitting element is basically shown in a structure in which anode / light emitting layer / cathode is stacked in this order, but in addition to this, a structure in which anode / hole injection layer / light emitting layer / electron injection layer / cathode is stacked in order, There are structures in which an anode / hole injection layer / hole transport layer / light emitting layer / electron transport layer / electron injection layer / cathode are stacked in this order.
[0006]
Note that the organic compound layer is not limited to a layer in which a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer, and the like have a clearly distinguished laminated structure. That is, the organic compound layer may have a structure in which materials constituting the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, the electron injection layer, and the like are mixed.
[0007]
Moreover, the inorganic substance may be mixed.
[0008]
Further, the organic compound layer of the OLED element may be any material of a low molecular material, a high molecular material, and a medium molecular material.
[0009]
Note that in this specification, the term “middle molecular material” means that the number of molecules is 20 or less or the length of a chained molecule is 10 μm or less and has no sublimation property.
[0010]
The display device includes a display and a peripheral circuit that inputs a signal to the display.
[0011]
The configuration of the display will be described.
[0012]
The display includes a source signal line driver circuit, a gate signal line driver circuit, and a pixel portion. The pixel portion has a configuration in which pixels are arranged in a matrix.
[0013]
A thin film transistor (hereinafter referred to as TFT) is arranged in each pixel of the pixel portion. Here, a method of arranging two TFTs for each pixel and controlling light emission of the light emitting element of each pixel will be described.
[0014]
FIG. 7 shows a configuration of a pixel portion of the display device.
[0015]
In the pixel portion 700, source signal lines S1 to Sx, gate signal lines G1 to Gy, and power supply lines V1 to Vx are arranged, and pixels of x (x is a natural number) column y (y is a natural number) are arranged. Yes. Each pixel 800 includes a switching TFT 801, a driving TFT 802, a storage capacitor 803, and a light emitting element 804.
[0016]
FIG. 8 shows an enlarged view of one pixel in the pixel portion shown in FIG.
[0017]
The pixel includes one S of source signal lines S1 to Sx, one G of gate signal lines G1 to Gy, one V of power supply lines V1 to Vx, a switching TFT 801, A driving TFT 802, a storage capacitor 803, and a light emitting element 804 are included.
[0018]
The gate electrode of the switching TFT 801 is connected to the gate signal line G, one of the source region and the drain region of the switching TFT 801 is connected to the source signal line S, and the other is the gate electrode of the driving TFT 802 or the holding The capacitor 803 is connected to one electrode. One of a source region and a drain region of the driving TFT 802 is connected to the power supply line V, and the other is connected to an anode or a cathode of the light emitting element 804. Of the two electrodes of the storage capacitor 803, the side not connected to the driving TFT 802 and the switching TFT 801 is connected to the power supply line V.
[0019]
Here, in this specification, when the source region or the drain region of the driving TFT 802 is connected to the anode of the light-emitting element 804, the anode of the light-emitting element 804 is referred to as a pixel electrode and the cathode is referred to as a counter electrode. On the other hand, when the source region or the drain region of the driving TFT 802 is connected to the cathode of the light emitting element 804, the cathode of the light emitting element 804 is referred to as a pixel electrode and the anode is referred to as a counter electrode.
[0020]
In addition, a potential applied to the power supply line V is referred to as a power supply potential, and a potential applied to the counter electrode is referred to as a counter potential.
[0021]
The switching TFT 801 and the driving TFT 802 may be either a p-channel TFT or an n-channel TFT. However, when the pixel electrode of the light emitting element 804 is an anode, the driving TFT 802 is preferably a p-channel TFT, and the switching TFT 801 is An n-channel TFT is desirable. On the other hand, when the pixel electrode is a cathode, the driving TFT 802 is preferably an n-channel TFT, and the switching TFT 801 is preferably a p-channel TFT.
[0022]
Note that the storage capacitor 803 is not necessarily provided.
[0023]
For example, when an n-channel TFT used as the driving TFT 802 has an LDD region provided so as to overlap with the gate electrode through a gate insulating film, the overlapping region is generally referred to as a gate capacitance. Although a parasitic capacitance is formed, this parasitic capacitance can be positively used as a holding capacitor for holding a voltage applied to the gate electrode of the driving TFT 802.
[0024]
An operation of displaying an image in the pixel having the above configuration will be described below.
[0025]
When a signal is input to the gate signal line G, the potential of the gate electrode of the switching TFT 801 changes, and the gate voltage changes. A signal is input from the source signal line S to the gate electrode of the driving TFT 802 through the source and drain of the switching TFT 801 that is thus turned on. In addition, a signal is held in the holding capacitor 803. The gate voltage of the driving TFT 802 is changed by a signal input to the gate electrode of the driving TFT 802, and the source and the drain become conductive. The potential of the power supply line V is applied to the pixel electrode of the light emitting element 804 through the driving TFT 802. Thus, the light emitting element 804 emits light.
[0026]
A method for expressing gradation in a pixel having such a configuration will be described.
[0027]
Gradation expression methods can be broadly divided into analog methods and digital methods. Compared to the analog method, the digital method has advantages such as being suitable for multi-gradation.
[0028]
Here, attention is focused on a digital gradation expression method.
[0029]
An example of a digital gradation expression method is a time gradation method.
[0030]
The time gray scale driving method will be described in detail below.
[0031]
This type of driving method is a method of expressing gradation by controlling a period during which each pixel of a display device emits light.
[0032]
When a period for displaying one image is one frame period, one frame period is divided into a plurality of subframe periods.
[0033]
Each subframe period is turned on or off, that is, the light emitting element of each pixel is turned on or off to control the period during which the light emitting element emits light per frame period. Expressed.
[0034]
This time gray scale driving method will be described in detail with reference to the timing chart of FIG.
[0035]
Note that FIG. 5A shows an example in which gradation is expressed using a 4-bit digital video signal.
[0036]
Note that the configurations shown in FIGS. 7 and 8 are referred to for the configuration of the pixel and the pixel portion.
[0037]
Here, the counter potential is between the potential of the power supply lines V1 to Vx (power supply potential) or the potential of the power supply lines V1 to Vx by an external power supply (not shown). It can be switched so that 804 has a potential difference enough to emit light.
[0038]
One frame period F is divided into a plurality of subframe periods SF1 to SF4.
[0039]
In the first subframe period SF1, first, the gate signal line G1 is selected, and the digital video signals are input from the source signal lines S1 to Sx in the pixels having the switching TFT 801 whose gate electrode is connected to the gate signal line G1, respectively. Is done. By this input digital video signal, the driving TFT 802 of each pixel is turned on or turned off.
[0040]
Here, in this specification, the state in which the TFT is on indicates that the source and the drain are in a conductive state by the gate voltage. Further, the TFT is in an off state indicates that the gate voltage is in a non-conducting state between the source and the drain.
[0041]
At this time, since the counter potential of the light emitting element 804 is set to be substantially equal to the potentials (power supply potentials) of the power supply lines V1 to Vx, the light emitting element 804 emits light even in the pixel in which the driving TFT 802 is turned on. do not do.
[0042]
Here, FIG. 5B is a timing chart showing an operation of inputting a digital video signal to the driving TFT 802 of each pixel.
[0043]
In FIG. 5B, a period during which a source signal line driver circuit (not shown) samples a signal corresponding to each source signal line is indicated by S1 to Sx. The sampled signal is simultaneously output to all the source signal lines in the blanking period in the figure. The signal output in this way is input to the gate electrode of the driving TFT 802 in the pixel for which the gate selection line is selected.
[0044]
The above operation is repeated for all the gate signal lines G1 to Gy, and the writing period Ta1 ends.
[0045]
Note that the writing period of the first subframe period SF1 is referred to as Ta1. In general, a writing period of the j-th (j is a natural number) subframe period SFj is referred to as Taj.
[0046]
When the writing period Ta1 ends, the counter potential changes so as to have a potential difference with which the light emitting element 804 emits light with respect to the power supply potential. Thus, the display period Ts1 starts.
[0047]
Note that the display period of the first subframe period SF1 is referred to as Ts1. In general, the display period of the j-th (j is a natural number) subframe period SFj is referred to as Tsj.
[0048]
In the display period Ts1, the light-emitting element 804 of each pixel enters a light-emitting state or a non-light-emitting state according to the input signal.
[0049]
As shown in FIG. 5A, the above operation is repeated for all subframe periods SF1 to SF4, and one frame period F1 ends.
[0050]
Here, the lengths of the display periods Ts1 to Ts4 of the subframe periods SF1 to SF4 are set as appropriate, and the gray scale is expressed by the total display period of the subframe periods in which the light emitting element 804 emits light per frame period F. . In other words, the gradation is expressed by the total lighting time in one frame period.
[0051]
In general, an n-bit digital video signal is input and 2 ⁿ A method for expressing gradation will be described.
[0052]
At this time, for example, one frame period is divided into n subframe periods SF1 to SFn, and the ratio of the lengths of the display periods Ts1 to Tsn of the subframe periods SF1 to SFn is Ts1: Ts2:. Tsn-1: Tsn = 2 ⁰ : 2- ¹ : ...: 2- ^{n + 2} : 2- ^{n + 1} Set to be. The lengths of the writing periods Ta1 to Tan are the same.
[0053]
By calculating the sum of the display periods Ts in which the light emitting state is selected in the light emitting element 804 during one frame period, the gradation of the pixel in the frame period is determined. For example, when n = 8, assuming that the luminance when the pixel emits light in the entire display period is 100%, the luminance of 1% can be expressed when the pixel emits light at Ts8 and Ts7, and Ts6, Ts4, and Ts1. When is selected, a luminance of 60% can be expressed.
[0054]
A circuit for inputting a signal for performing the above-described time gray scale driving method to the source signal line driver circuit and the gate signal line driver circuit of the display will be described with reference to FIG.
[0055]
In this specification, a signal input to the display device is referred to as a digital video signal. Note that, here, a display device that displays an image by inputting an n-bit digital video signal will be described as an example.
[0056]
The display device includes a display 1100 including a source signal line driver circuit 1107, a gate signal line driver circuit 1108, and a pixel portion 1109, a signal control circuit 1101, and a display controller 1102.
[0057]
A digital video signal is read into the signal control circuit 1101, and the signal control circuit 1101 outputs a digital video signal (VD) to the display 1100.
[0058]
In this specification, a signal control circuit that edits a digital video signal and converts it into a signal to be input to the display 1100 is referred to as a digital video signal.
[0059]
Signals for driving the source signal line driver circuit 1107 and the gate signal line driver circuit 1108 of the display 1100 are input by the display controller 1102.
[0060]
The configurations of the signal control circuit 1101 and the display controller 1102 will be described.
[0061]
Note that the source signal line driver circuit 1107 of the display 1100 includes a shift register 1110, LAT (A) 1111, and LAT (B) 1112. In addition, although not shown, a level shifter, a buffer, or the like may be provided.
[0062]
The signal control circuit 1101 includes a CPU 1104, a memory A 1105, a memory B 1116, and a memory controller 1103.
[0063]
The digital video signal input to the signal control circuit 1101 is input to the memory A 1105 via the CPU 1104.
[0064]
That is, in the digital video signal, the digital signal of each bit for each pixel is input and stored in the memory A1105.
[0065]
Here, the memory A 1105 has a capacity capable of storing n-bit digital signals for all the pixels of the pixel portion 1109 of the display 1100.
[0066]
When a digital signal for one frame period is stored in the memory A 1105, the digital signal of each bit is sequentially read out by the memory controller 1103 and input to the source signal line driver circuit as a digital video signal VD.
[0067]
When reading of the signal stored in the memory A 1105 starts, a digital video signal corresponding to the next frame period is input to the memory B 1106 via the CPU 1104 and stored. Similarly to the memory A 1105, the memory B 1106 is assumed to have a capacity capable of storing n-bit digital signals for all the pixels of the display device.
[0068]
As described above, the signal control circuit 1101 includes the memory A1105 and the memory B1106 that can store n-bit digital signals for each frame period, and alternately uses the memory A1105 and the memory B1106. Sample a digital video signal.
[0069]
Here, the signal control circuit 1101 that stores signals by alternately using the two memories A 1105 and B 1106 has been shown. However, generally, the memory has a memory that can store information for a plurality of frames, and these memories Can be used alternately.
[0070]
The structure of the memory controller 1103 that controls the input of digital video signals and the reading of signals from each memory in the memory A 1105 and the memory B 1106 of the signal control circuit 1101 will be described with reference to FIG.
[0071]
In FIG. 11, the memory controller 1103 includes a memory read / write control (hereinafter referred to as memory R / W) circuit 1202, a reference oscillation circuit 1203, a variable frequency dividing circuit 1204, an x counter 1205a, a y counter 1205b, an x decoder 1206a, and a y decoder. 1206b.
[0072]
Hereinafter, both the memories A and B included in the signal control circuit described above are collectively referred to as a memory. The memory is composed of a plurality of storage elements, and these storage elements are selected by an address (x, y).
[0073]
A signal from the CPU 1104 is input to the reference oscillation circuit 1203. A signal from the reference oscillation circuit 1203 is input to the variable frequency dividing circuit 1204 and converted into a signal having an appropriate frequency. The signal from the variable frequency dividing circuit 1204 selects the x address of the memory via the x counter 1205a and the x decoder 1206a. Similarly, the signal from the variable frequency dividing circuit 1204 is input to the y counter 1205b and the y decoder 1206b to select the memory y address. Thus, the memory address (x, y) is selected. Further, a signal from the CPU 1104 is input to the memory R / W circuit 1202, and a memory R / W signal for selecting an operation for writing a signal to the memory or an operation for reading a signal from the memory is output.
[0074]
Thus, the memory address for writing or reading the digital signal is selected by the memory x address and the memory y address, and in the memory element selected by this address, the digital signal writing or the like can be performed by the memory R / W signal. A read operation is performed.
[0075]
Next, the configuration of the display controller 1102 in FIG. 10 will be described below.
[0076]
The display controller 1102 outputs signals such as a start pulse (S_SP, G_SP) and a clock pulse (S_CLK, G_CLK) to the source signal line driver circuit 1107 and the gate signal line driver circuit 1108.
[0077]
The configuration of the display controller 1102 will be described with reference to FIG.
[0078]
The display controller 1102 includes a reference clock generation circuit 1301, a horizontal clock generation circuit 1303, a vertical clock generation circuit 1304, and a light emitting element power supply control circuit 1305.
[0079]
The clock signal 31 input from the CPU 1104 is input to the reference clock generation circuit 1301 and generates a reference clock. This reference clock is input to the horizontal clock generation circuit 1303 and the vertical clock generation circuit 1304. The horizontal clock generation circuit 1303 receives a horizontal cycle signal 32 for determining a horizontal cycle from the CPU 1104, and outputs a clock pulse S_CLK and a start pulse S_SP for the source signal line driver circuit. Similarly, the vertical clock generation circuit 1304 receives a vertical cycle signal 33 for determining a vertical cycle from the CPU, and outputs a clock pulse G_CLK and a start pulse G_SP for the gate signal line driver circuit.
[0080]
Refer to FIG. 10 again.
[0081]
The source signal line driver circuit start pulse S_SP and the clock pulse S_CLK output from the display controller 1102 are input to the shift register 1110 of the source signal line driver circuit 1107 of the display 1100. In addition, the gate signal line driver circuit start pulse G_SP and the clock pulse G_CLK are input to the gate signal line driver circuit 1108 of the display 1100.
[0082]
Here, in the display controller 1102, the light-emitting element power supply control circuit 1305 maintains the potential of the counter electrode of the light-emitting element of each pixel of the display at the same potential as the power supply potential during the writing period, and during the display period. The power supply potential is controlled so as to change so as to have a potential difference that allows the light emitting element to emit light.
[0083]
Thus, the display device displays an image.
[0084]
Here, the display device is desired to reduce its power consumption as much as possible. In the case of being incorporated and used in a portable information device or the like, it is particularly desired to reduce power consumption.
[0085]
In view of this, there has been proposed a technique for reducing power consumption of a display device by reducing the number of gradations (number of gradations to be expressed) when displaying an image when multi-gradation display is not necessary.
[0086]
This method will be described in detail below with reference to the timing chart of FIG.
[0087]
Here, a 4-bit signal is input and 2 ^Four Attention is focused on a display device that expresses the gradation of the above. By means of the switching signal, gradation is expressed using only the upper 1 bit signal (digital signal). Thus, a method for reducing the power consumption of the display device will be described as an example.
[0088]
At this time, a 4-bit digital video signal is input and 2 ^Four A case where gradation is expressed is referred to as a first display mode, and a case where two gradations are expressed using only the upper 1-bit signal is referred to as a second display mode.
[0089]
In general, when an input digital video signal is an n-bit signal, a case in which gradation is expressed using an n-bit signal is referred to as a first display mode. The case where m is expressed using only a signal having a bit (a natural number smaller than n) bits is referred to as a second display mode.
[0090]
Of the n-bit digital video signal, the first bit is the most significant bit and the nth bit is the least significant bit.
[0091]
In the second display mode, gradation is expressed without using a signal corresponding to the lower bits of the digital video signal in the first display mode.
[0092]
One frame period is divided into four subframe periods SF1 to SF4. The subframe periods SF1 to SF4 represent the subframe periods corresponding to the lower bits in order from the subframe period for the upper bits, and appear in this order to constitute one frame period.
[0093]
In the first display mode, gradation is expressed using all the input 4-bit digital video signals, so that the signal input from the signal control circuit to the source signal line driver circuit is 4 bits as described above. This is the same as the case of expressing gradation using the digital video signal. In addition, the source signal line driver circuit clock pulse S_CLK and start pulse S_SP, and the gate signal line driver circuit clock pulse G_CLK and start pulse G_SP output from the display controller are also adjusted using a 4-bit digital video signal. It is expressed by the same signal as when expressing.
[0094]
A method for driving the display device in the second display mode will be described below.
[0095]
FIG. 9 shows a timing chart showing a method for driving the display device in the second display mode.
[0096]
In the first subframe period SF1, a signal is input to each pixel. When a signal is input to all pixels, the counter potential changes so as to have a potential difference with which the light emitting element emits light with respect to the power supply potential. Thus, the light emitting element of each pixel is in a light emitting state or a non-light emitting state.
[0097]
The operation in the first subframe period is the same as that in the first display mode.
[0098]
Next, also in the second subframe period, similarly, a digital video signal is written to all the pixels in the writing period. It does not change so as to have a potential difference enough to emit light. That is, in the display period of the second subframe period, the light emitting elements of all the pixels do not emit light uniformly regardless of the signal input to the pixels. This period is expressed as non-display.
[0099]
The same operation as the operation in the second subframe period is repeated for the third subframe period and the fourth subframe period, and one frame period is completed.
[0100]
Of the one frame period, the period during which the pixels display is only the first subframe period. Thus, in the second display mode, the number of times the light emitting elements of the pixels emit light can be reduced, and the power consumption of the display device can be reduced.
[0101]
[Problems to be solved by the invention]
In the conventional display device, when the display mode is switched to the second display mode that expresses gradation without using lower-bit information, each pixel of the display device displays during a period other than the subframe period corresponding to the upper bits. Not performed. However, in each driving circuit (source signal line driving circuit and gate signal line driving circuit), an operation of writing a digital video signal to each pixel is performed. At this time, a start pulse, a clock pulse, or the like is input to each drive circuit of the display device and continues to operate.
[0102]
Therefore, even when gradation display is performed with a small amount of information in the second display mode, each driving circuit performs the sampling operation of the digital video signal as much as the sampling operation in the driving of the first display mode. Will repeat. Therefore, there is a problem that power is consumed for sampling and power consumption cannot be reduced.
[0103]
In addition to the subframe period in which display is actually performed, in the subframe period in which display is not performed, the pixels are in a non-display state in which light emission is not performed uniformly, so that an effective display period per frame period There is a problem that the ratio of
[0104]
Accordingly, it is an object to provide a display device that consumes less power and has a large proportion of an effective display period per frame period and a driving method thereof when driving with a reduced number of gradations to be expressed. To do.
[0105]
[Means for Solving the Problems]
In the second display mode with respect to the first display mode, the memory controller of the signal control circuit included in the display device eliminates the writing of the low-order bit signal of the digital video signal to the memory. In addition, reading of the lower bit digital signal from the memory is eliminated. In this way, each drive circuit supplies a digital video signal (second digital video signal) with a reduced amount of information to the source signal line drive circuit with respect to the digital video signal (first digital video signal) in the first display mode. To enter. Corresponding to this operation, the display controller changes the frequency of the start pulse and the clock pulse input to each drive circuit (source signal line drive circuit and gate signal destination drive circuit) small. Accordingly, the writing period and the display period of the subframe period related to display are set long.
[0106]
With the above structure, a display device with low power consumption and a large proportion of an effective display period per frame period and a driving method thereof can be provided.
[0107]
The configuration of the present invention will be described below.
[0108]
According to the present invention,
One frame period is divided into a plurality of subframe periods;
In the display device that turns on or off the sub-frame period and expresses the gradation with the total lighting time in the one frame period,
The one frame period is divided into n (n is a natural number) subframe periods, the first display mode, and the one frame period is m (m is a natural number smaller than n) subframe periods. A display device having a second display mode to be divided is provided.
[0109]
According to the present invention,
A display and a display controller for supplying a clock signal;
One frame period is divided into a plurality of subframe periods;
In the display device that turns on or off the sub-frame period and expresses the gradation with the total lighting time in the one frame period,
According to the number of gradations to be expressed, the display controller supplies a clock signal having a different frequency to the display.
[0110]
According to the present invention,
A memory for storing a digital video signal for one frame period;
Dividing the one frame period into a plurality of subframe periods;
In the display device that turns on or off the sub-frame period and expresses the gradation with the total lighting time in the one frame period,
A display device is provided that reads out the digital video signal stored in the memory at different frequencies in accordance with the number of gradations to be expressed.
[0111]
According to the present invention,
A display and a display controller for supplying a clock signal;
A memory for storing a digital video signal for one frame period;
One frame period is divided into a plurality of subframe periods;
In the display device that turns on or off the sub-frame period and expresses the gradation with the total lighting time in the one frame period,
The display controller supplies a clock signal having a different frequency to the display according to the number of gradations to be expressed, and reads the digital video signal stored in the memory at a different frequency. Is provided.
[0112]
According to the present invention,
A display and a display controller for supplying a clock signal;
One frame period is divided into a plurality of subframe periods;
In the display device that turns on or off the sub-frame period and expresses the gradation with the total lighting time in the one frame period,
The one frame period is divided into n (n is a natural number) subframe periods, the first display mode, and the one frame period is m (m is a natural number smaller than n) subframe periods. A second display mode to be divided,
In the first display mode and the second display mode, a display device is provided in which the display controller supplies a clock signal having a different frequency to the display.
[0113]
According to the present invention,
A memory for storing a digital video signal for one frame period;
Dividing the one frame period into a plurality of subframe periods;
In the display device that turns on or off the sub-frame period and expresses the gradation with the total lighting time in the one frame period,
The one frame period is divided into n (n is a natural number) subframe periods, the first display mode, and the one frame period is m (m is a natural number smaller than n) subframe periods. A second display mode to be divided,
In the first display mode and the second display mode, a display device is provided that reads out the digital video signal stored in the memory at different frequencies.
[0114]
According to the present invention,
A display and a display controller for supplying a clock signal;
A memory for storing a digital video signal for one frame period;
One frame period is divided into a plurality of subframe periods;
In the display device that turns on or off the sub-frame period and expresses the gradation with the total lighting time in the one frame period,
The one frame period is divided into n (n is a natural number) subframe periods, the first display mode, and the one frame period is m (m is a natural number smaller than n) subframe periods. A second display mode to be divided,
In the first display mode and the second display mode, the display controller supplies a clock signal having a different frequency to the display, and reads the digital video signal stored in the memory at a different frequency. A display device is provided.
[0115]
The display device may be characterized in that the luminance at the time of lighting in the subframe period varies depending on the number of gradations to be expressed.
[0116]
In the first display mode and the second display mode, the display device may be characterized in that brightness at the time of lighting in the subframe period is different.
[0117]
According to the present invention,
A display and a memory;
The display has a plurality of pixels,
Each of the plurality of pixels has a light emitting element,
Write a digital video signal to the memory,
From the memory, output a digital video signal to the display,
One frame period is divided into a plurality of subframe periods, and in each of the plurality of subframe periods, the digital video signal is input to the plurality of pixels, and the plurality of pixels are input to the plurality of pixels in the writing period. A display period during which the light emitting element emits light or does not emit light according to the digital video signal,
A first display mode in which gradation is expressed using a signal from the first bit to the n-th bit (n is a natural number) of the digital video signal; , A display device that displays an image by switching to a second display mode that expresses gradation using a signal of a bit number (natural number smaller than n),
In the first display mode, the first to nth bit signals of the digital video signal are stored in the memory, and in the second display mode, the first bit to the nth bit of the digital video signal. The m-th bit signal is stored in the memory,
In the second display mode, the writing period and the display period of the subframe period corresponding to the t-th (t is a natural number less than or equal to m) -th bit are the t-th position in the first display mode. A display device is provided in which each of the writing period and the display period of a subframe period corresponding to a bit is longer.
[0118]
According to the present invention,
A display and a memory;
The display has a plurality of pixels,
The plurality of pixels include a plurality of light emitting elements,
Write a digital video signal to the memory,
From the memory, output a digital video signal to the display,
One frame period is divided into a plurality of subframe periods, and in each of the plurality of subframe periods, the digital video signal is input to the plurality of pixels, and the plurality of pixels are input to the plurality of pixels in the writing period. A display period during which the light emitting element emits light or does not emit light according to the digital video signal,
A first display mode in which gradation is expressed using a signal from the first bit to the n-th bit (n is a natural number) of the digital video signal; , A natural number smaller than n) and a second display mode that expresses gradation using a bit-order signal, and displays an image.
In the first display mode, there are n subframe periods,
The ratio of the lengths of the display periods Ts1 to Tsn included in each of the n subframe periods is 2 ⁰ : 2 ^-1 : 2 ^-(n-2) : 2 ^-(n-1) And
In the second display mode, there are m subframe periods,
The ratio of the lengths of the display periods Ts1 to Tsm included in each of the m subframe periods is 2 ⁰ : 2 ^-1 : 2 ^-(m-2) : 2 ^-(m-1) In the display device
A first display mode in which the first to nth bit signals of the digital video signal are stored in the memory, and a first to mth bit signal of the digital video signal is stored in the memory. Switch the second display mode to
In the second display mode, the writing period and the display period of the subframe period corresponding to the t-th bit (t is a natural number equal to or less than m) are the t-th bit in the first display mode. The display device is characterized in that each of the writing period and the display period of the subframe period corresponding to is longer.
[0119]
In the display period corresponding to the t-th bit of the second display mode, the light emission luminance of the light-emitting element whose light emission state is selected corresponds to the t-th bit of the first display mode. In the display period, the display device may be characterized in that the potential of the counter electrode of the light emitting element is changed so that the light emitting state is lower than the light emission luminance of the selected light emitting element.
[0120]
According to the present invention,
A signal control circuit, a display controller, and a display;
The display includes a source signal line driver circuit, a gate signal line driver circuit, and a plurality of pixels.
Each of the plurality of pixels has a light emitting element,
The signal control circuit includes a CPU, a memory, and a memory controller,
The display controller inputs a source signal line driver circuit clock pulse and a source signal line driver circuit start pulse to the source signal line driver circuit, and a gate signal line driver circuit clock pulse to the gate signal line driver circuit. And input the start pulse for the gate signal line drive circuit,
Write a digital video signal to the memory,
From the memory, output a digital video signal to the display,
One frame period is divided into a plurality of subframe periods, and in each of the plurality of subframe periods, the digital video signal is input to the plurality of pixels, and the plurality of pixels are input to the plurality of pixels in the writing period. A display period during which the light emitting element emits light or does not emit light according to the digital video signal,
A first display mode in which gradation is expressed using a signal from the first bit to the n-th bit (n is a natural number) of the digital video signal; , A display device that displays an image by switching to a second display mode that expresses gradation using a signal of a bit number (natural number smaller than n),
In the first display mode, the memory controller writes the digital video signal from the first bit to the nth bit from the CPU to the memory, and the digital video signal written to the memory, Output to the source signal line drive circuit as the digital video signal;
In the second display mode, the memory controller writes the digital video signal from the 1st bit to the mth bit into the memory from the CPU, and the digital video signal written into the memory. , Output to the source signal line drive circuit as the digital video signal,
In the second display mode, the display controller includes the source signal line driver circuit clock pulse, the source signal line driver circuit start pulse, and the gate signal line driver in comparison with the first display mode. A display device is provided in which the frequency of each of the clock pulse for the circuit and the start pulse for the gate signal line driving circuit is lowered.
[0121]
The display controller has a variable frequency dividing circuit,
A gradation control signal is input to the variable frequency dividing circuit,
In the second display mode, compared with the first display mode, the source signal line driver circuit clock pulse, the source signal line driver circuit start pulse, the gate signal line driver circuit clock pulse, and The display device may be characterized in that the frequency of the start pulse for the gate signal line driver circuit is lowered.
[0122]
The display controller has a light source power supply control circuit,
By the gradation control signal input to the light source power supply control circuit,
The light emitting element in which the light emitting state is selected in the display period corresponding to the t-th bit (t is a natural number equal to or less than m) in the second display mode by changing the potential of the counter electrode of the light emitting element. Of the counter electrode of the light emitting device so that the light emission luminance is lower than the light emission luminance of the selected light emitting device in the display period corresponding to the t-th bit of the first display mode. A display device characterized in that the potential is changed may be used.
[0123]
A video camera, a DVD playback device, a television receiver, a head-mounted display, a portable information terminal, or a personal computer using the display device may be used.
[0124]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described.
[0125]
A timing chart showing a method for driving the display device of the present invention is shown in FIG.
[0126]
In FIG. 1, attention is paid to a display device to which a 4-bit digital video signal is input. In the first display mode, a 4-bit digital video signal is input to the display to display an image. On the other hand, in the second display mode, gradation is expressed by a 1-bit digital video signal using only the upper 1-bit digital video signal among the 4-bit digital video signals. In this embodiment mode, an example of the above case is described, but the display device of the present invention is not limited to this case.
[0127]
In general, attention is focused on a display device that inputs a digital video signal of n (n is a natural number) bits. In the first display mode, an n-bit digital video signal is used, and 2 subframe periods SF1 to SFn are used. ⁿ Can be expressed. On the other hand, by the switching operation, in the second display mode, a digital video signal of m (m is a natural number smaller than n) bits is used, and 2 ^m Express gradation. Such cases can also be applied.
[0128]
More generally, attention is focused on a display device that inputs a digital video signal of n (n is a natural number) bits. In the first display mode, an n-bit digital video signal is input, and w (w is a natural number) gradation can be expressed using r (r is a natural number) subframe periods. On the other hand, by the switching operation, in the second display mode, a digital video signal of m (m is a natural number smaller than n) bits is used, and s (s is a natural number smaller than r) subframe periods, u (U is a natural number smaller than w) represents a gradation. Such cases can also be applied.
[0129]
Input a 4-bit signal and 2 ^Four A timing chart in the case of the first display mode for expressing gradation is shown in FIG.
[0130]
In each display period of the subframe periods SF1 to SF4 constituting one frame period, the light emission or non-light emission state of each pixel is selected. Here, the counter potential is set to be substantially the same as the power supply potential during the writing period, and changes so as to have a potential difference between the power supply potential and the light emitting element to emit light during the display period.
[0131]
Since this operation is the same as that of the conventional example, detailed description is omitted.
[0132]
FIG. 1B shows a timing chart in the case of the second display mode in which gradation is expressed using only the upper 1-bit signal.
[0133]
Compared to the case of the first display mode shown in FIG. 1A, the writing period and the display period are set longer, and one frame period substantially corresponds to the first subframe period.
[0134]
A configuration of a display device for performing the driving operation will be described below.
[0135]
4 and 6 are block diagrams of a display device that performs the above operation.
[0136]
The display device includes a signal line control circuit 101, a display controller 102, and a display 100.
[0137]
The display controller 102 supplies the display 100 with a start pulse SP and a clock pulse CLK.
[0138]
The signal control circuit 101 includes a CPU 104, a memory A 105, a memory B 106, and a memory controller 103.
[0139]
FIG. 4 shows an example of a display device that inputs a 4-bit digital video signal and expresses gradation using a 4-bit digital video signal in the first display mode. The memory A105 includes memories 105_1 to 105_4 that store signals of the first bit to the fourth bit of the digital video signal, respectively. Similarly, the memory B106 includes memories 106_1 to 106_4 that store signals of the first to fourth bits of the digital video signal, respectively. Each of the memories corresponding to the digital signals of each bit has a number of storage elements that can store one bit of signals for the number of pixels constituting one screen.
[0140]
In general, in a display device capable of expressing gradation using an n-bit digital video signal, the memory A includes memories 105_1 to 105_n that store information of first to nth bits, respectively. Composed. Similarly, the memory B is also configured by memories 106_1 to 106_n that store information of the first bit to the nth bit, respectively. A memory corresponding to each of these bits has a capacity capable of storing a signal for one bit for each pixel constituting one screen.
[0141]
The configuration of the memory controller 103 in FIG. 4 is shown in FIG.
[0142]
In FIG. 2, the memory controller 103 includes a gradation limiting circuit 201, a memory R / W circuit 202, a reference oscillation circuit 203, a variable frequency dividing circuit 204, an x counter 205a, a y counter 295b, an x decoder 206a, and a y decoder 206b. Has been.
[0143]
Both the above-described memories such as the memory A and the memory B are collectively referred to as a memory. Further, the memory is composed of a plurality of storage elements. These storage elements are selected by the address (x, y).
[0144]
A signal from the CPU 104 is input to the memory R / W circuit 202 via the gradation limiting circuit 201. The gradation limiting circuit 201 inputs a signal to the memory R / W circuit 202 in accordance with either the first display mode or the second display mode. The memory R / W circuit 202 selects whether to write each digital video signal corresponding to each bit in the memory according to the signal from the gradation limiting circuit 201. Similarly, an operation for reading a digital signal written in the memory is selected.
[0145]
A signal from the CPU 104 is input to the reference oscillation circuit 203. A signal from the reference oscillation circuit 203 is input to the variable frequency dividing circuit 204 and converted into a signal having an appropriate frequency. Here, a signal from the gradation limiting circuit 201 is input to the variable frequency dividing circuit 204 in accordance with either the first display mode or the second display mode. Based on this signal, the signal from the variable frequency dividing circuit 204 selects the x address of the memory via the x counter 205a and the x decoder 206a. Similarly, the signal from the variable frequency dividing circuit 204 is input to the y counter 205b and the y decoder 206b to select the memory y address.
[0146]
By using the memory controller 103 having such a structure, when high gradation display is not necessary, among digital video signals input to the signal control circuit, signals written to the memory and signals read from the memory (digital The amount of information (video signal) can be reduced. Further, the frequency for reading a signal from the memory can be changed.
[0147]
The above is the description of the memory controller 103.
[0148]
The configuration of the display controller 102 in FIG. 4 will be described below.
[0149]
FIG. 3 is a diagram showing the configuration of the display controller of the present invention.
[0150]
The display controller 102 includes a reference clock generating circuit 301, a variable frequency dividing circuit 302, a horizontal clock generating circuit 303, a vertical clock generating circuit 304, and a light emitting element power supply 305.
[0151]
The clock signal 31 input from the CPU 104 is input to the reference clock generation circuit 301 and generates a reference clock. This reference clock is input to the horizontal clock generation circuit 303 and the vertical clock generation circuit 304 via the variable frequency dividing circuit 302. The gradation control signal 34 is input to the variable frequency dividing circuit 302. The frequency of the reference clock is changed by this signal.
[0152]
The degree to which the frequency of the reference clock is changed in the variable frequency dividing circuit 302 can be determined as appropriate by the practitioner. This is because the sub-frame period in the first display mode corresponding to the bits involved in gradation expression in the second display mode differs depending on the ratio of one frame period.
[0153]
That is, in the second display mode, the subframe period in one frame period is reduced compared to the first display mode. Here, in the present invention, also in the second display mode, the variable frequency dividing circuit 302 changes the frequency of the reference clock in order to set a long effective display period in one frame period. The rate of changing the frequency can be changed according to the rate of reduction of the number of bits.
[0154]
The horizontal clock circuit 303 receives a horizontal cycle signal 32 that determines a horizontal cycle from the CPU 104, and outputs a clock pulse S_CLK for the source signal line driver circuit and a start pulse S_SP. Similarly, the vertical clock generation circuit 304 receives a vertical cycle signal 33 for determining a vertical cycle from the CPU 104, and outputs a clock pulse G_CLK and a start pulse G_SP for the gate signal line driving circuit.
[0155]
The above is the description of the display controller 102.
[0156]
Thus, in the display device of the present invention, in the second display mode, the memory controller of the signal control circuit does not read out the low-order bit signal from the memory. In addition, the frequency of reading signals from the memory is reduced. Corresponding to this operation, the display controller reduces the frequency of the sampling pulse SP and the clock pulse CLK input to each driving circuit (source signal line driving circuit and gate signal destination driving circuit), and subframe period for expressing an image. The writing period and display period are set longer.
[0157]
For example, in the first display mode, one frame period is divided into four subframe periods. Then, the ratio of the display periods Ts1: Ts2: Ts3: Ts4 of each subframe period is set to 2 ⁰ : 2 ^-1 : 2 ^-2 : 2 ^-3 As a 4 bit digital video signal, ^Four Consider a display device that expresses the gray scale of the image. For simplicity, the lengths of the display periods Ts1 to Ts4 of each subframe period are 8, 4, 2, 1. The length of the writing periods Ta1 to Ta4 in each subframe period is 1. In the second display mode, a case where gradation is expressed using a signal of upper 1 bit is considered.
[0158]
At this time, in the second display mode, the ratio of the sub-frame period in the first display mode corresponding to the bits related to the gradation expression to one frame period is 9/19.
[0159]
That is, the subframe period related to gradation expression in the second display mode is a subframe period (denoted as SF1) corresponding to the upper 1 bit. Here, in the first display mode, the ratio of SF1 per frame period is 9/19.
[0160]
When the configuration of the present invention is not used, for example, when the driving method as shown in FIG. 9 of the conventional example is used, 10/19 in one frame period is not involved in display in the second display mode. It will be a period.
[0161]
On the other hand, according to the present invention, in the second display mode, the present invention changes the frequency of the clock signal or the like input to each drive circuit of the display, and is 19/9 times longer than the writing period in the first display mode. Similarly, the display period is set to 19/9 times the display period Ts1 of the subframe period SF1 corresponding to the first bit of the first display mode. As a result, one frame period can be occupied by the subframe period SF1. Thus, in the second display mode, it is possible to reduce the period not involved in display during one frame period.
[0162]
In general, a first display mode that expresses gradation using a signal from the first bit to the nth (n is a natural number) bit, and the mth (m is a natural number smaller than n) from the first bit. Attention is paid to a display device having a second display mode in which gradation is expressed using a bit signal.
[0163]
When the ratio of the sub-frame period in the first display mode corresponding to the bit related to gradation expression in the second display mode to 1 frame period is 1 / q (q is a number greater than 1) think of.
[0164]
That is, in the first display mode, a case where the ratio of the subframe period corresponding to the 1st bit to the mth bit per frame period is 1 / q (q is a number greater than 1) is considered. .
[0165]
In the subframe period corresponding to the t-th bit (t is a natural number equal to or less than m) in the second display mode, it is input to each display drive circuit (source signal line drive circuit and gate signal line drive circuit). The frequency of each signal (clock pulse, start pulse, etc.) is changed to 1 / q times, and a writing period having a length q times the writing period of the subframe period corresponding to the t-th bit in the first display mode is set. Set. Similarly, the display period is set to a length of q times the display period of the subframe period corresponding to the t-th bit (t is a natural number equal to or less than m) in the first display mode. The image can be displayed with sufficient use.
[0166]
Thus, even in the second display mode, it is possible to increase the display period of the light emitting elements per frame period.
[0167]
Therefore, in the second display mode, the luminance of the light emitting element whose light emission state is selected in the display period of the subframe period corresponding to the first bit is the sub luminance corresponding to the first bit in the first display mode. Compared with the luminance of the light emitting element whose light emitting state is selected in the display period of the frame period, it can be reduced. Therefore, in the second display mode, the voltage applied between the anode and the cathode of the light emitting element can be set small during the display period.
[0168]
A method for changing the voltage applied between the anode and the cathode of the light emitting element in accordance with the display mode will be described.
[0169]
In FIG. 3, the light-emitting element power supply control circuit 305 maintains the potential of the counter electrode of the light-emitting element (counter potential) at substantially the same potential as the power supply potential during the writing period, The potential is controlled so that the light emitting element emits light during this period. Here, the gradation control signal 34 is also input to the light-emitting element power supply control circuit 305. Accordingly, in the pixel in which the light emitting state is selected, the potential of the counter electrode of the light emitting element is changed so that the voltage applied between both electrodes of the light emitting element is reduced by the length of the light emission period of the light emitting element.
[0170]
In general, in the subframe period corresponding to the t-th bit (t is a natural number equal to or less than m) in the second display mode, the display period is the sub-frame period corresponding to the t-th bit in the first display mode. Consider a case where the display period is set to q (q is a number greater than 1) times as long. The luminance of the light emitting element whose light emitting state is selected in the sub-frame period corresponding to the t-th bit in the second display mode is selected in the sub-frame period corresponding to the t-th bit in the first display mode. 1 / q times the luminance of the light emitting element.
[0171]
In the second display mode, the magnitude of the voltage applied between the two electrodes of the light emitting element can be reduced, so that the stress of the light emitting element due to the applied voltage can be reduced.
[0172]
Note that the display device that switches between the first display mode and the second display mode has been described. However, in addition to the first display mode and the second display mode, the number of gradations to be expressed in more detail. This can be applied to the case of setting a mode with different colors and switching between the plurality of display modes for display.
[0173]
Here, as a configuration of the pixel portion included in the display of the display device of the present invention, the pixel having the configuration shown in FIG. 8 can be used in the conventional example. In addition, other well-known pixels can be used freely.
[0174]
For example, the following two types of pixels can be applied. One is a pixel in which the luminance of the light emitting element is determined by determining the voltage applied between the anode and the cathode of the light emitting element. The pixel having the configuration shown in FIG. 8 corresponds to this type of pixel. The second type is a pixel that determines the luminance of the light emitting element by determining the current flowing through the light emitting element.
[0175]
A circuit having a known structure can be freely used for the source signal line driver circuit and the gate signal line driver circuit included in the display of the display device of the invention.
[0176]
Further, the present invention can be applied not only to a display device using an OLED element as a light-emitting element but also to other self-luminous display devices such as FDP and PDP.
[0177]
【Example】
Examples of the present invention will be described below.
[0178]
Example 1
In this embodiment, a configuration example of a source signal line driver circuit of a display device of the present invention will be described.
[0179]
A configuration example of the source signal line driver circuit is shown in FIG.
[0180]
The source signal line driver circuit includes a shift register, a scanning direction switching circuit, LAT (A), and LAT (B). In FIG. 15, only a portion 2612 of LAT (A) and a portion 2618 of LAT (B) corresponding to one of the outputs from the shift register are shown, but for all outputs from the shift register, FIG. Thus, LAT (A) and LAT (B) having the same configuration correspond to each other.
[0181]
The shift register 2601 includes clocked inverters 2602 and 2603, an inverter 2604, and a NAND 2607. The source register driver circuit start pulse S_SP is input to the shift register 2601, and the source signal driver circuit clock pulse S_CLK and the inverted signal pulse S_CLKB for the source signal driver circuit are inverted signals. When the inverters 2602 and 2603 change between a conductive state and a non-conductive state, sampling pulses are sequentially output from the NAND 2607 to the LAT (A).
[0182]
The scanning direction switching circuit includes a switch 2605 and a switch 2606, and functions to switch the operation direction of the shift register to the left and right as viewed in the drawing. In FIG. 15, when the left / right switching signal L / R corresponds to a Lo signal, the shift register sequentially outputs sampling pulses from left to right as viewed in the drawing. On the other hand, when the left / right switching signal L / R corresponds to a Hi signal, sampling pulses are output sequentially from right to left in the drawing.
[0183]
The LAT (A) 2613 of each stage includes clocked inverters 2614 and 2615 and inverters 2616 and 2617.
[0184]
Here, the LAT (A) of each stage indicates LAT (A) that captures a video signal input to one source signal line.
[0185]
Here, the VD of the digital video signal output from the signal control circuit described in the embodiment is input after being divided into p (p is a natural number). That is, signals corresponding to outputs to the p source signal lines are input in parallel. When the sampling pulse is simultaneously input to the clocked inverters 2614 and 2615 of the p stage LAT (A) 2612 via the buffers 2608 to 2611, the p-divided input signal is supplied to the p stage LAT ( A) At 2612, each is sampled simultaneously.
[0186]
Here, since the source signal line driver circuit 2600 that outputs a signal current to x source signal lines is described as an example, x / p sampling pulses are sequentially output from the shift register per horizontal period. . In response to each sampling pulse, the L stages (A) 2613 of p stages simultaneously sample digital video signals corresponding to outputs to the p source signal lines.
[0187]
In this specification, the method of dividing the digital video signal input to the source signal line driving circuit into the p-phase parallel signal and simultaneously taking in the p digital video signals by one sampling pulse is p-divided. This is called driving.
[0188]
By performing the divided driving, a margin can be given to sampling of the shift register of the source signal line driver circuit. Thus, the reliability of the display device can be improved.
[0189]
When all signals in one horizontal period are input to the LAT (A) 2613 of each stage, the latch pulse LP and the inverted latch pulse LPB whose polarity is inverted are input and input to the LAT (A) 2613 of each stage. These signals are output to the LAT (B) 2619 of each stage simultaneously.
[0190]
Here, the LAT (B) of each stage indicates a LAT (B) circuit that inputs a signal from the LAT (A) of each stage.
[0191]
Each stage 2619 of LAT (B) is constituted by clocked inverters 2620 and 2621 and inverters 2622 and 2623. The signal output from each stage 2613 of LAT (A) is held in LAT (B) and simultaneously output to each source signal line S1 to Sx.
[0192]
Although not shown here, a level shifter, a buffer, or the like may be provided as appropriate.
[0193]
The start pulse S_SP, the clock pulse S_CLK, and the like input to the shifter register and LAT (A) and LAT (B) are input from the display controller described in the embodiment of the invention.
[0194]
In the present invention, an operation of inputting a digital video signal having a small number of bits to the LAT (A) of the source signal line driver circuit is performed by the signal control circuit, and at the same time, a clock input to the shift register of the source signal line driver circuit. The display controller performs operations for reducing the frequency of the pulse S_CLK, the start pulse S_SP, and the like.
[0195]
In this manner, in the second display mode, the operation of sampling the digital video signal by the source signal line driver circuit can be reduced, and the power consumption of the display device can be suppressed.
[0196]
Note that the display device of the present invention is not limited to the configuration of the source signal line driver circuit of this embodiment, and a source signal line driver circuit having a known configuration can be freely used.
[0197]
(Example 2)
In this embodiment, a configuration example of a gate signal line driver circuit of a display device of the present invention will be described.
[0198]
The gate signal line driving circuit includes a shift register, a scanning direction switching circuit, and the like. Although not shown here, a level shifter, a buffer, or the like may be provided as appropriate.
[0199]
The shift register receives a start pulse G_SP, a clock pulse G_CLK, and the like, and outputs a gate signal line selection signal.
[0200]
A structure of the gate signal line driver circuit is described with reference to FIG.
[0201]
The shift register 3601 includes clocked inverters 3602 and 3603, an inverter 3604, and a NAND 3607. The start pulse G_SP is input to the shift register 3601, and the clocked inverters 3602 and 3603 are changed from a conductive state to a non-conductive state by an inverted clock pulse G_CLKB which is a signal obtained by inverting the polarity of the clock pulse G_CLK. Sampling pulses are output in order from the NAND 3607.
[0202]
The scanning direction switching circuit includes a switch 3605 and a switch 3606, and functions to switch the operation direction of the shift register to the left and right as viewed in the drawing. In FIG. 16, when the scanning direction switching signal U / D corresponds to a Lo signal, the shift register outputs sampling pulses sequentially from left to right as viewed in the drawing. On the other hand, when the scanning direction switching signal U / D corresponds to a Hi signal, sampling pulses are output sequentially from right to left in the drawing.
[0203]
The sampling pulse output from the shift register is input to NOR 3608 and is calculated as an enable signal ENB. This calculation is performed in order to prevent a situation in which adjacent gate signal lines are simultaneously selected due to the rounding of sampling pulses. The signal output from the NOR 3608 is output to the gate signal lines G1 to Gy via the buffers 3609 and 3610.
[0204]
Although not shown here, a level shifter, a buffer, or the like may be provided as appropriate.
[0205]
A start pulse G_SP, a clock pulse G_CLK, and the like input to the shifter register are input from the display controller described in the embodiment.
[0206]
In the present invention, in the second display mode, an operation for reducing the frequency of the clock pulse G_CLK, the start pulse G_SP, or the like input to the shift register of the gate signal line driver circuit is performed by the display controller.
[0207]
Thus, in the lower second display mode, the sampling operation of the gate signal line driver circuit can be reduced and the power consumption of the display device can be suppressed.
[0208]
Note that the display device of the present invention is not limited to the configuration of the gate signal line driving circuit of this embodiment, and a gate signal line driving circuit having a known configuration can be freely used.
[0209]
This embodiment can be implemented by freely combining with the first embodiment.
[0210]
(Example 3)
In this embodiment, a method for sealing a display device of the present invention will be described with reference to FIGS.
[0211]
13A is a top view of the display device, FIG. 13B is a cross-sectional view taken along the line AA ′ in FIG. 13A, and FIG. 13C is a cross-sectional view along B- in FIG. It is sectional drawing in B '.
[0212]
A sealant 4009 is provided so as to surround the pixel portion 4002 provided over the substrate 4001, the source signal line driver circuit 4003, and the first and second gate signal line driver circuits 4004a and 4004b. In addition, a sealing material 4008 is provided over the pixel portion 4002, the source signal line driver circuit 4003, and the first and second gate signal line driver circuits 4004a and 4004b. Therefore, the pixel portion 4002, the source signal line driver circuit 4003, and the first and second gate signal line driver circuits 4004a and 4004b are sealed with the filler 4210 by the substrate 4001, the sealant 4009, and the sealant 4008. ing.
[0213]
In addition, the pixel portion 4002, the source signal line driver circuit 4003, and the first and second gate signal line driver circuits 4004a and 4004b provided over the substrate 4001 include a plurality of TFTs. In FIG. 13B, typically, a driving TFT (here, an n-channel TFT and a p-channel TFT are illustrated) 4201 formed on the base film 4010 and included in the source signal line driver circuit 4003; A driving TFT 4202 included in the pixel portion 4002 is illustrated.
[0214]
In this embodiment, a p-channel TFT or an n-channel TFT manufactured by a known method is used for the driving TFT 4201, and a p-channel TFT manufactured by a known method is used for the driving TFT 4202. Further, the pixel portion 4002 is provided with a storage capacitor (not shown) connected to the gate of the driving TFT 4202.
[0215]
An interlayer insulating film (planarization film) 4301 is formed over the driving TFT 4201 and the driving TFT 4202, and a pixel electrode (anode) 4203 electrically connected to the drain of the driving TFT 4202 is formed thereon. As the pixel electrode 4203, a transparent conductive film having a large work function is used. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Moreover, you may use what added the gallium to the said transparent conductive film.
[0216]
An insulating film 4302 is formed over the pixel electrode 4203, and an opening is formed over the pixel electrode 4203 in the insulating film 4302. In this opening, an organic compound layer 4204 is formed on the pixel electrode 4203. A known organic material or inorganic material can be used for the organic compound layer 4204. In addition, organic materials include low molecular (monomer) materials and high molecular (polymer) materials, either of which may be used.
[0217]
As a method for forming the organic compound layer 4204, a known vapor deposition technique or coating technique may be used. The structure of the organic compound layer may be a stacked structure or a single layer structure by freely combining a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, or an electron injection layer.
[0218]
On the organic compound layer 4204, a cathode 4205 made of a light-shielding conductive film (typically a conductive film containing aluminum, copper, or silver as a main component or a laminated film of these with another conductive film) is formed. The In addition, it is desirable to remove moisture and oxygen present at the interface between the cathode 4205 and the organic compound layer 4204 as much as possible. Therefore, it is necessary to devise such that the organic compound layer 4204 is formed in a nitrogen or rare gas atmosphere and the cathode 4205 is formed without being exposed to oxygen or moisture. In this embodiment, the above-described film formation is possible by using a multi-chamber type (cluster tool type) film formation apparatus. The cathode 4205 is given a predetermined voltage.
[0219]
As described above, a light-emitting element 4303 including the pixel electrode (anode) 4203, the organic compound layer 4204, and the cathode 4205 is formed. A protective film 4209 is formed over the insulating film 4302 so as to cover the light emitting element 4303. The protective film 4209 is effective in preventing oxygen, moisture, and the like from entering the light emitting element 4303.
[0220]
Reference numeral 4005 a denotes a lead wiring connected to the power supply line, and is electrically connected to the source region of the driving TFT 4202. The lead wiring 4005 a passes between the sealant 4009 and the substrate 4001 and is electrically connected to the FPC wiring 4301 included in the FPC 4006 through the anisotropic conductive film 4300.
[0221]
As the sealing material 4008, a glass material, a metal material (typically a stainless steel material), a ceramic material, or a plastic material (including a plastic film) can be used. As the plastic material, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic resin film can be used. A sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can also be used.
[0222]
However, when the light emission direction from the light emitting element is directed toward the cover material, the cover material must be transparent. In that case, a transparent material such as a glass plate, a plastic plate, a polyester film or an acrylic film is used.
[0223]
As the filler 4103, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used. PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (Polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. In this example, nitrogen was used as the filler.
[0224]
In order to expose the filler 4210 to a hygroscopic substance (preferably barium oxide) or a substance capable of adsorbing oxygen, a recess 4007 is provided on the surface of the sealing material 4008 on the substrate 4001 side to adsorb the hygroscopic substance or oxygen. A possible substance 4207 is placed. In order to prevent the hygroscopic substance or the substance 4207 capable of adsorbing oxygen from scattering, the concave part cover material 4208 holds the hygroscopic substance or the substance 4207 capable of adsorbing oxygen in the concave part 4007. Note that the concave cover material 4208 has a fine mesh shape, and is configured to allow air and moisture to pass therethrough but not a hygroscopic substance or a substance 4207 capable of adsorbing oxygen. By providing the hygroscopic substance or the substance 4207 capable of adsorbing oxygen, deterioration of the light-emitting element 4303 can be suppressed.
[0225]
As shown in FIG. 13C, a conductive film 4203a is formed so as to be in contact with the lead wiring 4005a at the same time as the pixel electrode 4203 is formed.
[0226]
The anisotropic conductive film 4300 has a conductive filler 4300a. By thermally pressing the substrate 4001 and the FPC 4006, the conductive film 4203a on the substrate 4001 and the FPC wiring 4301 on the FPC 4006 are electrically connected by the conductive filler 4300a.
[0227]
This embodiment can be implemented by freely combining with Embodiments 1 and 2.
[0228]
Example 4
In this embodiment, electronic devices using the display device of the present invention will be described with reference to FIG.
[0229]
FIG. 14A is a schematic view of a portable information terminal using the display device of the present invention. The portable information terminal includes a main body 2701a, an operation switch 2701b, a power switch 2701c, an antenna 2701d, a display portion 2701e, and an external input port 2701f. The display device having the structure described in Embodiment Mode and Embodiments 1 to 3 can be used for the display portion 2701e.
[0230]
FIG. 14B shows a schematic diagram of a personal computer of the present invention. The personal computer includes a main body 2702a, a housing 2702b, a display portion 2702c, operation switches 2702d, a power switch 2702e, and an external input port 2702f. The display device having the structure described in any of Embodiments and Embodiments 1 to 3 can be used for the display portion 2702c.
[0231]
FIG. 14C shows a schematic diagram of the image reproducing apparatus of the present invention. The image reproducing device includes a main body 2703a, a housing 2703b, a recording medium 2703c, a display unit 2703d, an audio output unit 2703e, and an operation switch 2703f. The display device having the structure described in any of Embodiments and Embodiments 1 to 3 can be used for the display portion 2703d.
[0232]
FIG. 14D is a schematic diagram of the television of the present invention. The television set includes a main body 2704a, a housing 2704b, a display portion 2704c, and operation switches 2704d. The display device having the structure described in any of Embodiments and Examples 1 to 3 can be used for the display portion 2704c.
[0233]
FIG. 14E shows a schematic diagram of the head mounted display of the present invention. The head mounted display includes a main body 2705a, a monitor unit 2705b, a head fixing band 2705c, a display unit 2705d, and an optical system 2705e. The display device having the structure described in Embodiment Mode and Embodiments 1 to 3 can be used for the display portion 2705d.
[0234]
FIG. 14F is a schematic diagram of the video camera of the present invention. The video camera includes a main body 2706a, a housing 2706b, a connection unit 2706c, an image receiving unit 2006d, an eyepiece unit 2706e, a battery 2706f, an audio input unit 2706g, and a display unit 2706h. The display device having the structure described in Embodiment Mode and Examples 1 to 3 can be used for the display portion 2706h.
[0235]
The present invention is not limited to the above-described applied electronic devices, and can be applied to various electronic devices.
[0236]
【The invention's effect】
According to the present invention, the power consumption of the display device can be suppressed by the above configuration. In addition, in the second display mode, even when the number of subframes used to express gradation is reduced, the display period per frame period can be increased, and a clear image display is possible. It is possible to provide a display device and a driving method thereof.
[0237]
Further, since the display period of the light emitting element per frame period can be increased, the voltage applied between the anode and the cathode of the light emitting element can be set small when the same brightness is expressed per frame. . Thus, a highly reliable display device can be provided.
[0238]
The present invention can be applied not only to display devices using OLED elements as light emitting elements, but also to other self-luminous display devices such as FDP and PDP.
[Brief description of the drawings]
FIG. 1 is a timing chart showing a method for driving a display device of the present invention.
FIG. 2 is a diagram showing a configuration of a memory controller of a display device of the present invention.
FIG. 3 is a diagram showing a configuration of a display controller of the display device of the present invention.
FIG. 4 is a block diagram illustrating a configuration of a display device of the present invention.
FIG. 5 is a timing chart showing a time gray scale driving method;
FIG. 6 is a block diagram illustrating a configuration of a display device of the present invention.
FIG. 7 illustrates a structure of a pixel portion of a display device.
FIG. 8 illustrates a structure of a pixel of a display device.
FIG. 9 is a timing chart showing a conventional driving method of a display device.
FIG. 10 is a block diagram illustrating a configuration of a conventional display device.
FIG. 11 is a diagram showing a configuration of a memory controller of a conventional display device.
FIG. 12 is a diagram showing a configuration of a display controller of a conventional display device.
FIG 13 is a diagram showing a method for sealing a light emitting element of a display device of the present invention;
FIG 14 illustrates an electronic device of the invention.
FIG. 15 shows a structure of a source signal line driver circuit of a display device of the present invention.
FIG 16 is a diagram showing a structure of a gate signal line driver circuit of a display device of the present invention;

Claims (7)

Means for dividing one frame period into a plurality of subframe periods;
Means for selecting a light emitting state or a non-light emitting state of a light emitting element included in the pixel by inputting a digital signal to the corresponding pixel in each of the plurality of subframe periods ;
Means for selecting a first display mode or a second display mode;
In the first display mode, during the one frame period, a digital signal from the first bit to the nth bit (n is a natural number) is input to the pixel as a first digital video signal;
In the second display mode, the first bit to the m-th (m is a natural number smaller than n) among the digital signals of the first to n-th (n is a natural number) bits during the one frame period. ) Means for inputting a digital signal of a significant bit to the pixel as a second digital video signal;
The length of the subframe period corresponding to the digital signal of the first bit to the m-th bit of the second digital video signal in the second display mode is set as the length in the first display mode, respectively. Means for setting q (q is a number greater than 1) times the length of a subframe period corresponding to the digital signal of the first bit to the m-th bit of one digital video signal ;
The luminance of the light emitting element whose light emitting state is selected in the subframe period corresponding to the t th bit (t is a natural number less than or equal to m) in the second display mode is the t th in the first display mode. And a means for changing the potential of the electrode of the light emitting element so that the light emitting state is lower than the luminance of the selected light emitting element in the subframe period corresponding to the bit . In claim 1,
The pixel has a pixel portion arranged in a matrix,
In the second display mode with respect to the first display mode, the driving frequency of the driving circuit that inputs the digital signal to each pixel of the pixel portion is increased by 1 / q. Display device. In claim 1 or claim 2,
A pixel portion in which the pixels are arranged in a matrix and a memory;
In the memory, wherein in the first display mode to store the first order bit to a digital signal of the first n significant bits input to each pixel of the pixel portion, pixels of the pixel portion in the second display mode Means for reading out the digital signal of the first bit to the m-th bit among the digital signals of the first bit to the n-th bit for several minutes,
A display device comprising means for multiplying the frequency for reading the digital signal from the memory by 1 / q times in the second display mode with respect to the first display mode. An electronic apparatus using the display device according to any one of claims 1 to 3 . One frame period is divided into a plurality of subframe periods;
In each of the plurality of subframe periods, a light emission state or a non-light emission state of a light emitting element included in the pixel is selected by inputting a digital signal to the corresponding pixel ,
Select the first display mode or the second display mode,
In the first display mode, during the one frame period, a digital signal from the first bit to the n-th bit (n is a natural number) is input to the pixel as a first digital video signal,
In the second display mode, the digital signal of the 1st bit to the mth bit (m is a natural number smaller than n) of the digital signals of the 1st bit to the nth bit during the one frame period. A signal is input to the pixel as a second digital video signal;
The luminance of the light emitting element in which the light emitting state is selected in the subframe period corresponding to the t th bit (t is a natural number equal to or less than m) in the second display mode is the t th in the first display mode. The potential of the electrode of the light emitting element is changed so that the light emitting state is lower than the luminance of the selected light emitting element in the subframe period corresponding to the bit,
The length of the subframe period corresponding to the digital signal of the first bit to the m-th bit of the second digital video signal in the second display mode is respectively the first frame in the first display mode. Driving a display device, characterized in that it is q (q is a number greater than 1) times the length of a subframe period corresponding to the digital signal of the first to m-th bits of one digital video signal Method. In claim 5 ,
The pixel has a pixel portion arranged in a matrix,
In the second display mode with respect to the first display mode, a drive frequency of a drive circuit that inputs the digital signal to each pixel of the pixel portion is 1 / q times. Driving method. In claim 5 or claim 6 ,
A pixel portion in which the pixels are arranged in a matrix and a memory;
In the first display mode, the memory stores the first to n-th bit digital signals corresponding to the number of pixels in the first display mode , and in the second display mode , the number of pixels corresponding to the number of pixels in the pixel portion. Among the first to nth bit digital signals, the first to mth bit digital signals are read out,
In the second display mode, the frequency for reading the digital signal from the memory is 1 / q times in the second display mode with respect to the first display mode.

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