JP3882804B2 - Light emitting device - Google Patents

Description

  The present invention relates to a display device.

  An active matrix display device using a current-controlled light emitting element such as an EL element or an LED element has been proposed. Since all of the light emitting elements used in this type of display device self-emit, unlike a liquid crystal display device, there is an advantage that a backlight is not required and the viewing angle dependency is small.

  FIG. 31 is a block diagram of an active matrix display device using a charge injection type organic thin film EL element as an example of such a display device. In the display device 1A shown in this figure, on a transparent substrate, a plurality of scanning lines gate, a plurality of data lines sig extending in a direction intersecting with the extending direction of these scanning lines gate, and these A plurality of common power supply lines com parallel to the data lines sig and pixels 7 corresponding to the intersections of the data lines sig and the scanning lines gate are configured.

  Each of the pixels 7 is supplied with a scanning signal from the data line sig via the first TFT 20 through which the scanning signal is supplied to the gate electrode (first gate electrode) via the scanning line gate. A holding capacitor cap that holds an image signal, a second TFT 30 in which the image signal held by the holding capacitor cap is supplied to a gate electrode (second gate electrode), and a common power supply line via the second TFT 30 A light emitting element 40 (represented as a resistor) into which a drive current flows from the common power supply line com when electrically connected to the com is configured.

  In the display device 1A configured as described above, the first TFT 20 and the second TFT 30 are conventionally shown in FIG. 32 as equivalent circuits from the viewpoint of simplifying the manufacturing process when an N-channel type is taken as an example. As shown, both are configured as N-channel or P-channel TFTs. Therefore, taking the N-channel type as an example, as shown in FIGS. 33A and 33B, as shown in FIGS. 33A and 33B, the scanning signal Sgate supplied from the scanning line gatc becomes a high potential and the first TFT 20 is turned on. When the high potential image signal data is written from the data line sig to the storage capacitor cap, the second TFT 30 is held in the ON state. As a result, in the light emitting element 40, the drive current in the direction indicated by the arrow E continues to flow from the pixel electrode 41 toward the counter electrode op, and the light emitting element 40 continues to emit light (lighted bear). On the other hand, when the scanning signal Sgate supplied from the scanning line gate becomes a high potential and the first TFT 20 is turned on, the data line sig is opposed to the potential of the common power supply line com from the storage capacitor cap. When an image signal data having a potential lower than a certain potential between the potentials of the electrodes op is written, the second TFT 30 is turned off and the light emitting element 40 is turned off (light-off state).

In such a display device 1A, a semiconductor film, an insulating film, an electrode, and the like constituting each element are composed of a thin film deposited on the substrate, and this thin film is formed by a low-temperature process in consideration of the heat resistance of the substrate. Often done. Accordingly, the film quality is inferior because there are many defects due to the difference in physical properties between the thin film and the bulk, and problems such as dielectric breakdown and deterioration with time are easily surfaced in TFTs.

  A liquid crystal display device using liquid crystal as a light modulation element is also common in that a thin film is used. In this case, since the light modulation element is driven with an alternating current, not only the liquid crystal but also the deterioration with time of the TFT can be suppressed. On the other hand, in the display device 1A using the current-controlled light emitting element, the TFT is more likely to deteriorate with time than in the liquid crystal display device in that it must be DC-driven. In order to solve such a problem, although the display device 1A using the current-controlled light emitting element has been improved in the structure and process technology of the TFT, it cannot be said that it has been sufficiently improved.

  Further, when liquid crystal is used as a light modulation element, since the light modulation element is controlled by voltage, only a current flows instantaneously through each element, so that power consumption is small. On the other hand, in the display device 1A using the current control type light emitting element, since it is necessary to constantly drive the driving current in order to keep the light emitting element lit, the power consumption becomes high, and dielectric breakdown and deterioration with time are not caused. Easy to get up.

  Further, in the liquid crystal display device, the liquid crystal can be AC driven by one TFT per pixel, but in the display device 1A using a current control type light emitting element, the light emitting element 40 is DC-connected by two TFTs 20 and 30 per pixel. Since it is driven, the driving voltage becomes high, and the problems of the above-mentioned dielectric breakdown and large power consumption are remarkable.

  For example, as shown in FIG. 33A, the gate voltage Vgsw of the first TFT 20 at the time of selecting a pixel is a potential corresponding to the high potential of the scanning signal Sgate and the potential of the potential holding electrode st (of the holding capacitor cap). Therefore, the potential of the potential holding electrode st is increased to increase the gate voltage Vgcur of the second TFT 30 so that the light emitting element 40 is turned on with high luminance. When the voltage is increased, the gate voltage Vgsw of the first TFT 20 is lowered accordingly, so that it is necessary to increase the amplitude of the scanning signal Sgate, and the drive voltage of the display device 1A is increased.

  Further, in the display device 1A, when the light emitting element 40 is turned off, the potential of the image signal data is made lower than a certain potential between the potential of the common power supply line com and the potential of the counter electrode op. There is also a problem that the amplitude of the image signal data is large in order to turn it off. Therefore, in this type of display device 1A, it is necessary to pay particular attention to power consumption, the withstand voltage of TFT, and the like, compared with a liquid crystal display device, but in the conventional display device 1A, such consideration is not sufficiently taken. .

  Therefore, an object of the present invention is to adopt a driving method that takes into account the conductivity type of the TFT that controls the light emission operation of the current-driven light-emitting element, and reduces power consumption, dielectric breakdown, and deterioration over time due to lower driving voltage. An object of the present invention is to provide a display device that can achieve both reduction and improvement in display quality.

  In the present invention, on the substrate, a plurality of scanning lines, a plurality of data lines intersecting the scanning lines, a plurality of common power supply lines, and pixels formed in a matrix by the data lines and the scanning lines, Each of the pixels has a first TFT to which a scanning signal is supplied to the first gate electrode through the scanning line, and is supplied from the data line through the first TFT. A holding capacitor for holding an image signal, a second TFT in which the image signal held by the holding capacitor is supplied to a second gate electrode, and a pixel electrode formed for each pixel are the second TFT In the display device in which the light emitting thin film emits light by a driving current flowing between the pixel electrode and a counter electrode facing the light emitting thin film when electrically connected to the common power supply line through the second power supply, When TFT is N-channel type , The common feed line, characterized in that it is set to a potential lower than the counter electrode.

  In the display device according to the present invention, the gate voltage when the second TFT is on is the potential of one of the potential of the common power supply line and the potential of the pixel electrode and the potential of the gate electrode (the potential of the image signal). Since this corresponds to the difference, the relative level of the potential of the common feeder line and the potential of the counter electrode of the light emitting element is optimized according to the conductivity type of the second TFT, and the gate voltage of the second TFT is common. It is configured to correspond to the difference between the potential of the feeder line and the potential of the potential holding electrode. For example, if the second TFT is an N-channel type, the potential of the common power supply line is set lower than the potential of the counter electrode of the light emitting element.

  The potential of the common power supply line can be set to a sufficiently low value unlike the potential of the pixel electrode, so that a large on-current can be obtained by the second TFT and display can be performed with high luminance. it can. Further, when the pixel is turned on, if the high gate voltage can be obtained in the second TFT, the potential of the image signal can be lowered, so that the amplitude of the image signal is reduced and the driving voltage in the display device is reduced. Can be lowered.

  Therefore, there is an advantage that the power consumption can be reduced and the problem of withstand voltage, which has been a concern for each element composed of a thin film, does not become apparent.

  In the present invention, when the second TFT is an N-channel type, the potential of the image signal supplied from the data line to the pixel to be turned on is lower than the potential of the counter electrode. Or an equipotential. Even in such a configuration, the amplitude of the image signal can be reduced while the second TFT is kept on, and the driving voltage in the display device can be reduced.

  In the present invention, when the second TFT is an N-channel type, the potential of the image signal supplied from the data line to the pixel to be turned off is higher than the potential of the common power supply line. It is preferably a potential or an equipotential. That is, when the pixel is turned off, a gate voltage (image signal) is not applied so as to completely turn off the second TFT. Combined with the non-linear electrical characteristics of the light emitting element, the extinguished state can be realized. Therefore, the amplitude of the image signal can be reduced, the drive voltage in the display device can be lowered, and the frequency of the image signal can be increased.

  In the present invention, in contrast to the above-described configurations, when the second TFT is a P-channel type, the relative relationship between the potentials is reversed. That is, when the second TFT is a P-channel type, the common power supply line is set at a higher potential than the counter electrode. In this case, it is preferable that the potential of the image signal supplied from the data line to the pixel to be turned on is higher than or equal to the potential of the counter electrode. In addition, it is preferable that the potential of the image signal supplied from the data line to the pixel to be turned off is lower than or equal to the potential of the common power supply line.

  In the present invention, the first TFT and the second TFT are preferably composed of reverse conductivity type TFTs. That is, if the first TFT is an N-channel type, the second TFT is preferably a P-channel type, and if the first TFT is a P-channel type, the second TFT is preferably an N-channel type. . As will be described in detail later, with this configuration, the potential of the image signal for lighting is only changed within the range of the driving voltage range of the display device so that the resistance when the first TFT is turned on becomes smaller. Thus, the display operation can be speeded up.

  Further, at this time, since the potential of the image signal for lighting the pixel is changed in a direction in which the resistance when the second TFT is turned on is reduced, the luminance can be improved. Therefore, the drive voltage can be lowered and the display quality can be improved.

  In another embodiment of the present invention, a plurality of scanning lines, a plurality of data lines intersecting the scanning lines, a plurality of common power supply lines, and the data lines and the scanning lines are formed in a matrix on the substrate. Each of the pixels includes a first TFT to which a scanning signal is supplied to the first gate electrode through the scanning line, and the data line through the first TFT. A storage capacitor for holding an image signal supplied from the second TFT, a second TFT for supplying the image signal held by the storage capacitor to a second gate electrode, a pixel electrode formed for each pixel, and the pixel electrode A driving current that flows between the pixel electrode and the counter electrode when the pixel electrode is electrically connected to the common power supply line through the second TFT between the counter electrode and the counter electrode. Light emission comprising a light emitting thin film that emits light In the display device and a child, wherein the first TFT and the second TFT, characterized in that it consists of opposite conductivity type of the TFT.

  In the present invention, for example, if the first TFT is N-type, the first TFT and the second TFT are of the reverse conductivity type so that the second TFT is P-type. In order to increase the writing capability, the selection pulse height of the scanning signal is increased, and in order to increase the light emission luminance by decreasing the on-resistance of the second TFT, the potential of the image signal is decreased. Such optimization of the scanning signal and the image signal is performed as the image signal at a level for lighting the light emitting element is written to the storage capacitor during the pixel selection period with respect to the gate voltage of the first TFT. This is effective for shifting the on-current of the TFT to increase. Therefore, the image signal is smoothly written from the data line to the storage capacitor via the first TFT. Here, the gate voltage of the first TFT at the time of selecting a pixel is the potential corresponding to the high potential of the scanning signal and the potential of the potential holding electrode during lighting (the potential of the image signal for lighting, the potential of the holding capacitor). Or the potential of the gate electrode of the second TFT), and the gate voltage of the second TFT corresponds to the difference between the potential of the potential holding electrode during lighting and the potential of the common feeder line. When the potential of the potential holding electrode at that time is used as a reference, the potential corresponding to the high potential of the scanning signal and the potential of the common power supply line have the same polarity. Therefore, if the potential of the potential holding electrode during lighting (the potential of the image signal for lighting) is changed, the gate voltage of the first TFT and the gate voltage of the second TFT are the same in the same direction. Shift by minutes. Therefore, the display operation speed can be increased by shifting the potential of the image signal for lighting in the range of the driving voltage range of the display device in a direction in which the resistance when the first TFT is turned on is reduced. be able to. Further, at this time, the potential of the image signal for lighting is shifted in a direction in which the resistance when the second TFT is turned on becomes smaller, so that the luminance can be improved. Therefore, the drive voltage can be lowered and the display quality can be improved.

  In the present invention, the gate voltage applied to the second TFT in the pixel in the off state is the same as the polarity when the second TFT is turned on, and the threshold of the second TFT. A value that does not exceed the value voltage is preferred.

  That is, when the pixel is turned off, a gate voltage (image signal) is not applied so as to completely turn off the second TFT. Therefore, the amplitude of the image signal can be reduced, and the frequency of the image signal can be increased.

  In this configuration, if the first TFT is an N-channel type and the second TFT is a P-channel type, the scanning signal potential when the first TFT is turned on and the common are used. The potential of the gate electrode applied to the second TFT of the pixel that is equal to the potential of the power supply line and is in the extinguished state is determined based on the potential of the scanning signal when the first TFT is turned on. The potential is preferably lower than the potential obtained by subtracting the threshold voltage of one TFT. On the contrary, if the first TFT is a P-channel type and the second TFT is an N-channel type, the potential of the scanning signal when the first TFT is turned on and the common feed line The potential of the gate electrode applied to the second TFT of the pixel that is equal to the potential and is in the extinguished state is equal to the potential of the scanning signal when the first TFT is turned on. It is preferable that the potential be higher than the potential obtained by adding the threshold voltage.

  In this way, when the potential of the scanning signal when the first TFT is turned on and the potential of the common power supply line are equalized, the number of levels of each drive signal is reduced, so that the number of signal input terminals to the display device is reduced. The power consumption can be reduced and the number of power supplies can be reduced, resulting in low power consumption.

  In the present invention, among the electrodes of the storage capacitor, the electrode opposite to the electrode electrically connected to the second gate electrode of the second TFT is delayed from the selection pulse of the scanning signal. It is preferable that a pulse whose potential is reversed in the opposite direction to the selection pulse is supplied. With such a configuration, writing of the image signal to the storage capacitor can be supplemented, so that the potential of the image signal applied to the gate electrode of the second TFT is increased without increasing the amplitude of the image signal. Can be shifted in the direction of.

  In still another embodiment of the present invention, a plurality of scanning lines, a plurality of data lines intersecting the scanning lines, a plurality of common power supply lines, the data lines, and the scanning lines are formed in a matrix on the substrate. Each of the pixels includes a first TFT to which a scanning signal is supplied to the first gate electrode through the scanning line, and the first TFT through the first TFT. A storage capacitor for holding an image signal supplied from a data line, a second TFT for supplying the image signal held by the storage capacitor to a second gate electrode, and a pixel electrode formed for each pixel Driving between the pixel electrode and the counter electrode when the pixel electrode is electrically connected to the common power supply line through the second TFT between the counter electrode and the counter electrode facing the pixel electrode A light-emitting thin film that emits light by current In the display device including the light emitting element, the scanning signal is applied to an electrode on the opposite side to the electrode electrically connected to the second gate electrode of the second TFT among the two electrodes of the storage capacitor. This is characterized in that a pulse whose potential swings in a direction opposite to that of the selected pulse is supplied with a delay from the selected pulse.

  With such a configuration, writing of the image signal to the storage capacitor can be supplemented, so that the potential of the image signal applied to the gate electrode of the second TFT is increased without increasing the amplitude of the image signal. Can be shifted in the direction of.

  In any of the above inventions, for example, an organic semiconductor film can be used as the light-emitting thin film.

  In the present invention, in any of the above-described inventions, the second TFT operates in its saturation region, whereby an abnormal current flows in the light emitting element, and crosstalk or the like occurs in other pixels due to a voltage drop or the like. Can be prevented.

Further, by operating in the linear region, it is possible to prevent the variation in the threshold voltage from affecting the display operation.
Further, the light emitting device of the present invention is a light emitting device in which a transistor is arranged corresponding to a scanning line, a data line, and an intersection of the scanning line and the data line, and the first light emitting device connected to the transistor. One electrode; a second electrode formed above the first electrode; an interlayer insulating film covering the data line and the transistor; a bank layer disposed above the interlayer insulating film; and A light emitting thin film formed inside and disposed between the first electrode and the second electrode, wherein the first electrode and the transistor are connected via a relay electrode, and the bank layer is The first electrode and the relay electrode are arranged in an overlapping region.
In the above light-emitting device, the bank layer is preferably formed above the transistor.
In the light emitting device, the light emitting element preferably includes an organic thin film layer and a hole injection layer.
In the above light-emitting device, the transistor is preferably a P-channel type.

  Embodiments of the present invention will be described with reference to the drawings. Before describing each embodiment of the present invention, a configuration common to each embodiment will be described. Here, portions having a common function in each embodiment are given the same reference numerals to avoid duplication of explanation.

(Overall configuration of active matrix substrate)
FIG. 1 is a block diagram schematically showing the entire layout of a display device, and FIG. 2 is an equivalent circuit diagram of an active matrix configured therewith. As shown in FIG. 1, in the display device 1 of the present embodiment, the central portion of the transparent substrate 10 that is the base is the display unit 2. On the upper and lower sides of the outer peripheral portion of the transparent substrate 10, a data side drive circuit 3 and an inspection circuit 5 that output an image signal to the data line sig are respectively configured on the upper and lower sides toward the drawing. On the other side, a scanning side driving circuit 4 for outputting a scanning signal to the scanning line gate is configured. In these drive circuits 3 and 4, an N-type TFT and a P-type TFT constitute a complementary TFT, and this complementary TFT constitutes a shift register circuit, a level shifter circuit, an analog switch circuit, and the like. On the transparent substrate 10, a mounting pad 6 serving as a terminal group for inputting an image signal, various potentials, and a pulse signal is formed in an outer peripheral region of the data side driving circuit 3.

  In the display device 1, similarly to the active matrix substrate of the liquid crystal display device, a plurality of scanning lines gate and a plurality of data extended in a direction intersecting the extending direction of the scanning lines gate on the transparent substrate 10. Lines sig are formed, and as shown in FIG. 2, a large number of pixels 7 are formed in a matrix by the intersection of these data lines sig and scanning lines gate.

Each of these pixels 7 includes a first TFT 20 in which a scanning signal is supplied to the gate electrode 21 (first gate electrode) via the scanning line gate. One of the source / drain regions of the TFT 20 is electrically connected to the data line sig, and the other source / drain region is electrically connected to the potential holding electrode st.
In other words, the capacitance line “cline” is arranged in parallel to the scanning line “gate”, and the storage capacitance “cap” is formed between the capacitance line “cline” and the potential holding electrode st. Therefore, when the first TFT 20 is selected by the scanning signal and turned on, the image signal is written from the data line sig to the storage capacitor cap via the first TFT 20.

  A gate electrode 31 (second gate electrode) of the second TFT 30 is electrically connected to the potential holding electrode st, and one of the source / drain regions of the second TFT 30 is electrically connected to the common power supply line com. On the other hand, the other source / drain region is electrically connected to one electrode (a pixel electrode described later) of the light emitting element 40. The common power supply line com is held at a constant potential. When the second TFT 30 is turned on, the current of the common feeder line com flows through the light emitting element 40 through the second TFT 30 and causes the light emitting element 40 to emit light.

  In the display device 1 configured as described above, the driving current flows through a current path including the light emitting element 40, the second TFT 30, and the common power supply line com. Therefore, the driving current does not flow when the second TFT 30 is turned off. . However, in the display device 1 of the present embodiment, when the first TFT 20 is selected by the scanning signal and turned on, the image signal is written from the data line sig to the storage capacitor cap via the first TFT 20. Accordingly, the gate electrode of the second TFT 30 is held at the potential corresponding to the image signal by the storage capacitor cap even when the first TFT 20 is turned off, so that the second TFT 30 remains on. . Therefore, a driving current continues to flow through the light emitting element 40, and this pixel remains in a lighting state. This state is maintained until new image data is written into the storage capacitor cap and the second TFT 30 is turned off.

  In the display device 1, various arrangements are possible for the common power supply line com, the pixel 7, and the data line sig. In this embodiment, the common power supply line com is driven on both sides of the common power supply line com. A plurality of pixels 7 having light emitting elements 40 to which current is supplied are arranged, and two data lines sig pass through these pixels 7 on the side opposite to the common power supply line com. That is, a data line sig, a pixel group connected to the data line, a single common power supply line com, a pixel group connected to the data line sig, and a data line sig that supplies a pixel signal to the pixel group as one unit are used as a unit of the scanning line gate. It repeats in the extending direction, and the common power supply line com supplies a drive current to the pixels 7 for two columns. Therefore, in the present embodiment, between the two pixels 7 arranged so as to sandwich the common power supply line com, the first TFT 20, the second TFT 30, and the light emitting element 40 are arranged around the common power supply line com. They are arranged symmetrically to facilitate electrical connection between these elements and each wiring layer.

  As described above, in this embodiment, pixels for two columns are driven by one common power supply line com, and therefore, compared to the case where the common power supply line com is formed for each pixel group of one column, the common power supply line is used. The number of coms can be halved, and a gap secured between the common power supply line com and the data line sig formed between the same layers is unnecessary. Therefore, since the area for wiring on the transparent substrate 10 can be narrowed, display performance such as luminance and contrast ratio can be improved. Since two columns of pixels are connected to one common power supply line com in this way, two data lines sig are in parallel, and an image is applied to a pixel group in each column. A signal will be supplied.

(Pixel configuration)
The structure of each pixel 7 of the display device 1 configured as described above will be described in detail with reference to FIGS. FIG. 3 is an enlarged plan view showing three pixels 7 out of the plurality of pixels 7 formed in the display device 1 of the present embodiment, and FIGS. It is sectional drawing in the -A 'line, sectional drawing in the BB' line, and sectional drawing in the CC 'line.

  First, at a position corresponding to the line AA ′ in FIG. 3, as shown in FIG. 4, an island-like silicon film for forming the first TFT 20 on each pixel 7 on the transparent substrate 10. 200 is formed, and a gate insulating film 50 is formed on the surface thereof.

  A gate electrode 21 (a part of the scanning line gate) is formed on the surface of the gate insulating film 50, and source / drain regions 22 and 23 are formed in a self-aligned manner with respect to the gate electrode 21. A first interlayer insulating film 51 is formed on the surface side of the gate insulating film 50, and the data lines sig and the source / drain regions 22 and 23 are connected to the source / drain regions 22 and 23 through contact holes 61 and 62 formed in the interlayer insulating film. And the potential holding electrode st are electrically connected to each other.

  In each pixel 7, a capacitor line cline is formed between the scanning line gate and the gate electrode 21 (between the gate insulating film 50 and the first interlayer insulating film 51) so as to be in parallel with the scanning line gate. In addition, the extended portion st1 of the potential holding electrode st overlaps the capacitor line cline via the first interlayer insulating film 51. For this reason, the capacitor line cline and the extended portion st1 of the potential holding electrode st constitute a holding capacitor cap using the first interlayer insulating film 51 as a dielectric film. A second interlayer insulating film 52 is formed on the surface side of the potential holding electrode st and the data line sig.

  In the position corresponding to the line BB ′ in FIG. 3, each pixel 7 is formed on the surface of the first interlayer insulating film 51 and the second interlayer insulating film 52 formed on the transparent substrate 10 as shown in FIG. Two data lines sig corresponding to are in parallel. At the position corresponding to the line CC ′ in FIG. 3, as shown in FIG. 6A, the second substrate 7 extends across the two pixels 7 sandwiching the common power supply line com on the transparent substrate 10. An island-like silicon film 300 for forming the TFT 30 is formed, and a gate insulating film 50 is formed on the surface thereof. On the surface of the gate insulating film 50, a gate electrode 31 is formed in each of the pixels 7 so as to sandwich the common power supply line com, and source / drain regions 32 and 33 are self-aligned with the gate electrode 31. Is formed.

  A first interlayer insulating film 51 is formed on the surface side of the gate insulating film 50, and the relay electrode 35 is electrically connected to the source / drain region 62 through a contact hole 63 formed in the interlayer insulating film. ing.

  On the other hand, the common feeder line com is electrically connected to the portion that becomes the common source / drain region 33 in the two pixels 7 in the center of the silicon film 300 through the contact hole 64 of the first interlayer insulating film 51. Connected to. A second interlayer insulating film 52 is formed on the surfaces of the common power supply line com and the relay electrode 35.

  A pixel electrode 41 made of an ITO film is formed on the surface of the second interlayer insulating film 52. The pixel electrode 41 is electrically connected to the relay electrode 35 via a contact hole 65 formed in the second interlayer insulating film 52, and the source / drain region 32 of the second TFT 30 is connected via the relay electrode 35. Is electrically connected.

(Characteristics of light emitting element)
Since the present invention can be applied to the light emitting element 40 having any structure, a typical one will be described below. First, the pixel electrode 41 made of the ITO film constitutes one electrode (positive electrode) of the light emitting element 40 as shown in FIG. A hole injection layer 42 and an organic semiconductor film 43 as a light-emitting thin film are laminated on the surface of the pixel electrode 41. Further, on the surface of the organic semiconductor film 43, a counter electrode op (made of a metal film such as lithium-containing aluminum or calcium) is formed. Negative electrode) is formed. The counter electrode op is to be a common electrode formed on the entire surface of the transparent substrate 10 or in a stripe shape, and is held at a constant potential. On the other hand, when a driving current is passed in the direction opposite to that of the light emitting element 40 shown in FIG. 7A, the ITO film is moved from the lower layer side to the upper layer side as shown in FIG. 7B. A pixel electrode 41 (negative electrode) made of, a thin lithium-containing aluminum electrode 45 having light transmissivity, an organic semiconductor layer 43, a hole injection layer 42, an ITO film layer 46, and a metal film such as lithium-containing aluminum or calcium. The light emitting element 40 may be configured by stacking electrodes op (positive electrode) in this order.

  With this configuration, even when a driving current having a reverse polarity flows in each light emitting element 40 shown in FIGS. 7A and 7B, the hole injection layer 42 and the organic semiconductor layer 43 are directly in contact with the electrode layer. Since the configuration is the same, the emission characteristics are equivalent. Each of the light emitting elements 40 shown in FIGS. 7A and 7B has a pixel electrode 41 made of an ITO film on the lower layer side (substrate side), and the light is as indicated by an arrow hν. The light passes through the pixel electrode 41 and the transparent substrate 10 and is emitted from the back side of the transparent substrate 10.

  On the other hand, when the light emitting element 40 is configured as shown in FIGS. 8A and 8B, the light is transmitted through the counter electrode op and emitted to the surface side of the transparent substrate 10 as indicated by an arrow hν. Is done. That is, as shown in FIG. 8A, an organic semiconductor film 43 and a hole injection layer 42 are stacked on the surface of a pixel electrode 41 (negative electrode) made of a metal film such as lithium-containing aluminum, and further a hole injection layer. On the surface of 42, a counter electrode op (positive electrode) made of an ITO film is formed. The counter electrode op is also a single electrode on the entire surface or a common electrode formed in a stripe shape, and is held at a constant potential.

  On the other hand, in order to flow a driving current in the opposite direction to the light emitting element shown in FIG. 8A, as shown in FIG. A pixel electrode 41 (positive electrode) made of a metal film, an ITO film layer 46, a hole injection layer 42, an organic semiconductor layer 43, a lithium-containing aluminum electrode 45 that is thin enough to be translucent, and a counter electrode op (negative electrode) made of an ITO film. ) May be stacked in this order to form the light emitting element 40. In forming the light emitting element 40 having any structure, if the hole injection layer 42 and the organic semiconductor film 43 are formed on the inner side of the bank layer bank by an ink jet method as will be described later, they are manufactured even if the vertical positions are opposite. The process is not complicated. Further, even when the lithium-containing aluminum electrode 45 and the ITO film layer 46 that are thin enough to have translucency are added, the lithium-containing aluminum electrode 45 is displayed even if it is structured to be laminated in the same region as the pixel electrode 41. Even if the ITO film layer 46 has a structure in which the counter electrode op is laminated in the same region, the display is not hindered. Therefore, the lithium-containing aluminum electrode 45 and the pixel electrode 41 may be patterned separately, but may be patterned in a lump with the same resist mask. Similarly, the ITO film layer 46 and the counter electrode op may be patterned separately, but they may be patterned together with the same resist mask. Of course, the lithium-containing aluminum electrode 45 and the ITO film layer 46 may be formed only in the inner region of the bank layer bank.

  Further, the counter electrode op may be formed of an ITO film, and the pixel electrode 41 may be formed of a metal film. In either case, light is emitted from the transparent ITO film. A voltage is applied to the light emitting element 40 configured in this manner with the counter electrode op and the pixel electrode 41 as the positive electrode and the negative electrode, respectively, and the current of the light emitting element 40 shown in FIG. 9 (FIGS. 7A and 8B). -Voltage characteristics), as shown in FIG. 10 (current-voltage characteristics of the light emitting element 40 shown in FIGS. 7B and 8A), respectively, applied voltage (horizontal axis / of the counter electrode op with respect to the pixel electrode 41). In the region where the potential) exceeds the threshold voltage, an on state, that is, a low resistance state is entered, and the current (driving current) flowing through the organic semiconductor film 43 increases rapidly. As a result, the light emitting element 40 emits light as an electroluminescence element or an LED element, and light emitted from the light emitting element 40 is reflected by the counter electrode op and emitted through the transparent pixel electrode 41 and the transparent substrate 10. On the contrary, in the region where the applied voltage (horizontal axis / potential of the counter electrode op with respect to the pixel electrode 41) is lower than the threshold voltage, the organic semiconductor film 43 is turned into an off state, that is, a high resistance state and a current (drive current) ) Does not flow, and the light emitting element 40 is turned off. In the examples shown in FIGS. 9 and 10, the threshold voltages are near +2 V and −2 V, respectively.

  Here, although the light emission efficiency tends to slightly decrease, the hole injection layer 42 may be omitted. In some cases, the electron injection layer is provided at a position opposite to the position where the hole injection layer 42 is formed with respect to the organic semiconductor layer 43 without using the hole injection layer 42. In some cases, both the hole injection layer 42 and the electron injection layer are provided.

(TFT characteristics)
Current-voltage characteristics of N-channel and P-channel TFTs as TFTs (first TFT 20 and second TFT 30 in FIG. 2) for controlling light emission in the light-emitting element 40 configured as described above are shown in FIG. FIG. 12 and FIG. 12 (in both figures, examples of drain voltages of 4V and 8V are shown). As can be seen from these figures, the TFT is turned on and off by the gate voltage applied to the gate electrode. That is, when the gate voltage exceeds the threshold voltage, the TFT is turned on (low resistance state) and the drain current increases. In contrast, when the gate voltage falls below the threshold voltage, the TFT is turned off (high resistance state), and the drain current is reduced.

(Manufacturing method of display device)
In the manufacturing method of the display device 1 configured as described above, the steps until the first TFT 20 and the second TFT 30 are manufactured on the transparent substrate 10 are substantially the same as the steps of manufacturing the active matrix substrate of the liquid crystal display device 1. Therefore, the outline will be briefly described with reference to FIG.

  FIG. 13 is a process cross-sectional view schematically showing a process of forming each component of the display device 1 under a temperature condition of 600 ° C. or lower. That is, as shown in FIG. 13A, a thickness of about 2000 to 5000 angstroms is formed on the transparent substrate 10 by plasma CVD using TEOS (tetraethoxysilane), oxygen gas, or the like as a source gas, if necessary. A base protective film (not shown) made of a silicon oxide film is formed. Next, the temperature of the substrate is set to about 350 ° C., and a semiconductor film 100 made of an amorphous silicon film having a thickness of about 300 to 700 Å is formed on the surface of the base protective film by plasma CVD.

Next, a crystallization process such as laser annealing or solid phase growth is performed on the semiconductor film 100 made of an amorphous silicon film to crystallize the semiconductor film 100 into a polysilicon film. In the laser annealing method, for example, a line beam having a long beam shape of 400 mm is used with an excimer laser, and its output intensity is, for example, 200 mJ / cm ² . The line beam is scanned so that a portion corresponding to 90% of the peak value of the laser intensity in the short dimension direction overlaps for each region.

  Next, as shown in FIG. 13B, the semiconductor film 100 is patterned to form island-shaped semiconductor films 200 and 300, and TEOS (tetraethoxysilane), oxygen gas, or the like is used as a source gas on the surface. A gate insulating film 50 made of a silicon oxide film or nitride film having a thickness of about 600 to 1500 angstroms is formed by plasma CVD.

  Next, as shown in FIG. 13C, a conductive film made of a metal film such as aluminum, tantalum, molybdenum, titanium, or tungsten is formed by sputtering, and then patterned to form a gate as a part of the scan line gate. Electrodes 21 and 31 are formed. In this step, a capacitor line cline is also formed. In the figure, reference numeral 310 denotes an extended portion of the gate electrode 31. In this state, impurities such as high-concentration phosphorus ions or boron ions are implanted to form source / drain regions 22, 23, 32, 33 in the silicon thin films 200, 300 in a self-aligned manner with respect to the gate electrodes 21, 31. . Note that portions where impurities are not introduced become channel regions 27 and 37.

  In this embodiment, as will be described later, TFTs having different conductivity types may be manufactured on the same substrate. In this case, the impurity-conducting TFT formation region is covered with a mask in the impurity introduction step. The introduction of is recommended.

  Next, as shown in FIG. 13D, after forming the first interlayer insulating film 51, contact holes 61, 62, 63, 64, and 69 are formed, and the data line sig, the capacitor line cline, and the gate electrode are formed. The potential holding electrode st, the common power supply line com, and the relay electrode 35 including the extended portion st1 overlapping the 31 extended portion 310 are formed. As a result, the potential holding electrode st is electrically connected to the gate electrode 31 through the contact hole 69 and the extended portion 310. In this way, the first TFT 20 and the second TFT 30 are formed. In addition, the storage capacitor cap is formed by the capacitor line cline and the extended portion st1 of the potential holding electrode st.

  Next, as shown in FIG. 13E, a second interlayer insulating film 52 is formed, and a contact hole 65 is formed in the interlayer insulating film at a portion corresponding to the relay electrode 35.

  Next, after forming a conductive film on the entire surface of the second interlayer insulating film 52, patterning is performed, and the pixel electrode 41 electrically connected to the source / drain region 32 of the second TFT 30 through the contact hole 65 is formed. Form.

  Next, as shown in FIG. 13F, after forming a black resist layer on the surface side of the second interlayer insulating film 52, this resist is used as the organic semiconductor film 43 of the light emitting element 40 and the hole injection layer. The bank layer bank is formed while leaving the region to be formed to surround 42. Here, the organic semiconductor film 43 is bank-shaped in a shape corresponding to the case where it is formed in a box shape independently for each pixel or in the case of being formed in a stripe shape along the data line sig. The manufacturing method according to this embodiment can be applied only by forming the layer bank.

  Next, a liquid material (precursor) for forming the organic semiconductor film 43 is discharged from the inkjet head IJ to the inner region of the bank layer bank, thereby forming the organic semiconductor film 43 in the inner region of the bank layer bank. To do. Similarly, a liquid material (precursor) for forming the hole injection layer 42 is discharged from the inkjet head IJ to the inner region of the bank layer bank, and the hole injection layer 42 is injected into the inner region of the bank layer bank. Form. Note that, as described with reference to FIGS. 7A and 7B and FIGS. 8A and 8B, the structure of the light-emitting element 40 is described. Depending on the structure, the organic semiconductor film 43 and the hole injection layer may be used. The order of forming 42 may be changed. Here, since the bank layer bank is made of a resist, it is water repellent. On the other hand, since the precursor of the organic semiconductor film 43 and the hole injection layer 42 uses a hydrophilic solvent, the application region of the organic semiconductor film 43 is reliably defined by the bank layer bank, and is adjacent to the adjacent pixels. It does not protrude. If the bank layer bank is formed sufficiently high, the organic semiconductor film 43 and the hole injection layer 42 can be formed in a predetermined region even when a coating method such as a spin coating method is used without using the ink jet method. .

  In this embodiment, in order to increase the working efficiency when forming the organic semiconductor film 43 and the hole injection layer 42 by the ink jet method, as shown in FIG. The pitch P at the center of the region where the organic semiconductor film 43 is formed is also equal between the pixels 7. Therefore, as indicated by the arrow Q, there is an advantage that the material or the like of the organic semiconductor film 43 may be discharged from the inkjet head IJ to the positions at equal intervals along the extending direction of the scanning line gate. Further, since the movement at an equal pitch is sufficient, the moving mechanism of the ink jet head IJ is simplified, and the driving accuracy of the ink jet head IJ can be easily increased.

  Thereafter, as shown in FIG. 13G, the counter electrode op is formed on the surface side of the transparent substrate 10. Here, the counter electrode op is formed on the entire surface or in a stripe shape. When the counter electrode op is formed in a stripe shape, a conductive film is formed on the entire surface of the transparent substrate 10 and then patterned in a stripe shape. To do.

  Note that TFTs are also formed in the data side driving circuit 3 and the scanning side driving circuit 4 shown in FIG. 1, but these TFTs use all or part of the process of forming the TFTs on the pixels 7 described above. Done. Therefore, the TFT constituting the driving circuit is also formed between the same layers as the TFT of the pixel 7.

  In the present embodiment, since the bank layer bank is made of a black and insulating resist, it is left as it is and used as an insulating layer for reducing the black matrix BM and parasitic capacitance.

  That is, as shown in FIG. 1, the bank layer bank (formation area is hatched) is also formed in the peripheral area of the transparent substrate 10. Accordingly, since both the data side driving circuit 3 and the scanning side driving circuit 4 are covered with the bank layer bank, even if the counter electrode op overlaps the formation region of these driving circuits, the driving circuit The bank layer bank is interposed between the wiring layer and the counter electrode op. Therefore, parasitic capacitance can be prevented in the drive circuits 3 and 4, so that the load on the data side drive circuit 3 can be reduced, and power consumption can be reduced or display operation speed can be increased.

  In the present embodiment, as shown in FIGS. 3 to 5, the bank layer bank is formed so as to overlap the data line sig. Accordingly, since the bank layer bank is interposed between the data line sig and the counter electrode op, it is possible to prevent parasitic capacitance from occurring in the data line sig. As a result, the load on the drive circuit can be reduced, so that power consumption can be reduced or display operation can be performed at higher speed.

  Further, in the present embodiment, as shown in FIGS. 3, 4, and 6 (A), the bank layer bank may be formed also in a region where the pixel electrode 41 and the relay electrode 35 overlap. That is, as shown in FIG. 6B, when the bank layer bank is not formed in the region where the pixel electrode 51 and the relay electrode 35 overlap, a drive current flows between the pixel electrode and the counter electrode op. Even if the organic semiconductor film 43 emits light, the light is not emitted because it is sandwiched between the relay electrode 35 and the counter electrode op, and does not contribute to display. The driving current that flows in a portion that does not contribute to the display can be said to be a reactive current in terms of display. However, in this embodiment, since the bank layer bank is formed in a portion where such a reactive current should flow and the drive current is prevented from flowing therethrough, it is possible to prevent a wasteful current from flowing through the common feeder line com. . Therefore, the width of the common feeder line com may be reduced accordingly.

  If the bank layer bank made of black resist is left as described above, the bank layer bank functions as a black matrix, and the display quality such as luminance and contrast ratio is improved. That is, in the display device 1 according to the present embodiment, since the counter electrode op is formed in a stripe shape over the entire surface side of the transparent substrate 10 or over a wide region, reflected light from the counter electrode op decreases the contrast ratio. .

  However, in the present embodiment, since the bank layer bank having a function of suppressing the parasitic capacitance while defining the formation region of the organic semiconductor film 43 is configured by a black resist, the bank layer bank also functions as a black matrix, and is formed from the counter electrode op. Therefore, there is an advantage that the contrast ratio is high. In addition, since the light emitting region can be defined in a self-aligned manner using the bank layer bank, the light emission that causes a problem when another metal layer or the like is used as the black matrix without using the bank layer bank as the black matrix. No alignment margin with the area is required.

(Another configuration of active matrix substrate)
In addition, this invention is applicable not only to said structure but to various active matrix substrates. For example, as described with reference to FIG. 31, on the transparent substrate 1, the scanning line gate is extended with one data line sig, one common power supply line com, and one column of pixels 7 as one unit. The present invention can also be applied to the display device 1A having a configuration repeated in the installation direction.

  The storage capacitor cap may be configured between the common power supply line com and the potential holding electrode st without using the capacitor line. In this case, as shown in FIGS. 14A and 14B, the extended portion 310 of the gate electrode 31 for electrically connecting the potential holding electrode st and the gate electrode 31 is connected to the common power supply line com. A storage capacitor cap is formed which extends to the lower layer side and uses the first interlayer insulating film 51 located between the extended portion 310 and the common power supply line com as a dielectric film.

  Further, although not shown, the storage capacitor cap may be configured by using a polysilicon film for forming the TFT, and is not limited to the capacitor line or the common power supply line. It is also possible to configure between.

[Embodiment 1]
FIG. 15 is an equivalent circuit diagram illustrating a pixel configuration of the display device 1 of the present embodiment. FIGS. 16A and 16B are an explanatory diagram showing an electrical connection state of each element formed in each pixel and a waveform diagram showing a potential change such as a drive signal.

  As shown in FIGS. 15, 16A, and 16B, in the present embodiment, the first TFT 20 is an N-channel type. Accordingly, when the scanning signal Sgate supplied from the scanning line gate becomes a high potential, the first TFT 20 is turned on, and the image signal data is transferred from the data line sig to the storage capacitor cap via the first TFT 20. Is written and the second TFT 30 is driven and controlled by the image signal data held in the holding capacitor cap while the scanning signal Sgate supplied from the scanning line gate is at a low potential.

  In the present embodiment, the second TFT 30 is also an N-channel type. Therefore, from the data line sig, the image signal date on the high potential side is written to the holding capacitor cap of the pixel to be turned on, and the image signal date on the low potential side is written to the holding capacitor cap of the pixel to be turned off. Is written, and the potential of the potential holding electrode st changes accordingly.

  Here, the gate voltage of the second TFT 30, Vgcur, corresponds to the difference between the lower potential of the potential of the common power supply line com and the potential of the pixel electrode 30 and the potential of the potential holding electrode st. However, in the present embodiment, when the potential of the common feeder line com is lowered with respect to the potential of the counter electrode op of the light emitting element 40 and the second TFT 30 is turned on, as shown by the arrow F, the light emitting element A current flows from 40 toward the common feeder line com. For this reason, the gate voltage Vgcur of the second TFT 30 corresponds to the difference between the potential of the common feeder line com and the potential of the potential holding electrode st. The potential of the common power supply line com can be set to a sufficiently low value, unlike the potential of the pixel electrode 30 corresponding to the potential between the potential of the common power supply line com and the potential of the counter electrode op. . Therefore, in this embodiment, since the gate voltage Vgcur of the second TFT 30 can be set to a sufficiently high value, since the on-current of the second TFT 30 is large, display can be performed with high luminance. If a high value is obtained as the gate voltage Vgcur of the second TFT 30 when the pixel is turned on, the potential of the potential holding electrode st at that time, that is, the high potential of the image signal data. Since the potential on the side can be lowered, the amplitude of the image signal data can be reduced and the drive voltage in the display device 1 can be lowered.

  The on-state current of the second TFT 30 is not limited to the gate voltage Vgcur but also depends on the drain voltage, but the above conclusion does not change. In the present embodiment, the on-current of the second TFT 30 is defined by the difference between the potential of the common feeder line com and the potential of the potential holding electrode st, and is not directly affected by the potential of the counter electrode op. The potential on the high potential side of the image signal data for turning on the pixel is lowered to a potential lower than the potential of the counter electrode op, the amplitude of the image signal data is reduced, and the drive voltage in the display device 1 is reduced. It is intended to become. Note that the amplitude of the image signal data may be reduced by lowering the potential on the high potential side of the image signal data for turning on the pixel to the same potential as the counter electrode op.

  Furthermore, in the present embodiment, the potential of the image signal data supplied from the data line sig to the pixel to be turned off is slightly higher than the potential of the common power supply line com. Since the second TFT 30 is an N-channel type, in order to completely turn it off, the gate voltage Vgcur of the second TFT 30 is negative (potential lower than the common power supply line com). Alternatively, the potential on the low potential side of the image signal data is set so that the absolute value of the gate voltage Vgcur of the second TFT 30 is slightly lower than the level corresponding to the absolute value of the threshold voltage of the second TFT 30. Set higher. At this time, the gate voltage of the second TFT 30 in the pixel 7 in the unlit state is the same as the polarity when the second TFT 30 is turned on, and is lower than the threshold voltage of the second TFT 30. Set to. At this time, even when the potential on the low potential side of the image signal data is set higher as described above, the second TFT 30 is in a high resistance state and the on-state current is extremely small, so that the light emitting element 40 is turned off. . Note that the amplitude of the image signal data may be reduced by setting the potential of the image signal data supplied from the data line sig to the pixel to be turned off to the same potential as the common power supply line com.

  As described above, when the potential on the low potential side of the image signal data is set high enough not to exceed the threshold value of the second TFT 30, the amplitude of the image signal data can be reduced, so that the drive voltage of the image signal data is lowered. Can do. In addition, as described above, since the potential on the high potential side of the image signal data for turning on the pixel is lowered to a potential lower than the potential of the counter electrode op, the potential of the image signal data is equal to the counter electrode op. And the common feed line com. Therefore, the drive voltage in the display device 1 can be reduced, and the power consumption of the display device 1 can be reduced. Further, even if configured in this way, it does not cause a decrease in image quality, an abnormal operation, or a decrease in the operable frequency, and there is a concern about each element composed of a thin film because the drive voltage of the display device 1 is low. There is also an advantage that the problem of withstand voltage (insulation withstand voltage) does not become obvious.

[Modification of Embodiment 1]
FIG. 17 is an equivalent circuit diagram illustrating a pixel configuration of the display device 1 of the present embodiment. FIGS. 18A and 18B are an explanatory diagram showing an electrical connection state of each element formed in each pixel and a waveform diagram showing a potential change such as a drive signal. Note that, in this embodiment, contrary to the first embodiment, both the first TFT 20 and the second TFT 30 are configured by P-channel TFTs. However, in the present embodiment, each element is driven and controlled based on the same technical idea as in the first embodiment, and the polarity of the drive signal described in the first embodiment is merely inverted. Since other aspects have the same configuration, only the configuration will be briefly described.

  As shown in FIGS. 17, 18A, and 18B, in this embodiment, since the first TFT 20 is a P-channel type, the scanning signal Sgate supplied from the scanning line gate has a low potential. Sometimes, the first TFT 20 is turned on. In the present embodiment, the second TFT 30 is also a P-channel type. Therefore, from the data line sig, the low-potential-side image signal date is written to the holding capacitor cap of the pixel to be turned on, and the high-potential-side image signal date is written to the holding capacitor cap of the pixel to be turned off. Written.

  Here, the gate voltage Vgcur of the second TFT 30 corresponds to the difference between the higher potential of the potential of the common power supply line com and the potential of the pixel electrode 30 and the potential of the potential holding electrode st. However, in the present embodiment, when the potential of the common feeder line com is made higher than the potential of the counter electrode op of the light emitting element 40 and the second TFT 30 is turned on, as shown by the arrow E, the common supply An electric current flows from the electric wire com to the light emitting element 40. For this reason, the gate voltage Vgcur of the second TFT 30 corresponds to the difference between the potential of the common feeder line com and the potential of the potential holding electrode st. Unlike the potential of the pixel electrode 30 corresponding to the potential between the potential of the common power supply line com and the potential of the counter electrode op, the potential of the common power supply line com can be set to a sufficiently high value. . Therefore, in this embodiment, since the gate voltage Vgcur of the second TFT 30 can be set to a sufficiently high value, since the on-current of the second TFT 30 is large, display can be performed with high luminance. If a high value is obtained as the gate voltage Vgcur of the second TFT 30 when the pixel is turned on, the potential of the potential holding electrode st at that time, that is, the low potential of the image signal data. Since the potential on the side can be increased, the amplitude of the image signal data can be reduced.

  In the present embodiment, since the on-current of the second TFT 30 is not directly affected by the potential of the counter electrode op, the potential on the low potential side of the image signal data for turning on the pixel is The amplitude of the image signal data is reduced by raising the potential slightly higher than the potential of the counter electrode op. Note that the potential on the low potential side of the image signal data for turning on the pixel may be increased to the same potential as the counter electrode op, and the amplitude of the image signal data may be reduced.

  Furthermore, in the present embodiment, the potential of the image signal data supplied from the data line sig to the pixel to be turned off is lowered to a slightly lower potential than the potential of the common power supply line com. That is, the potential on the high potential side of the image signal data is set lower so that the absolute value of the gate voltage Vgcur of the second TFT 30 is slightly lower than the level corresponding to the absolute value of the threshold voltage of the TFT. It is. As a result, the on-current of the second TFT 30 becomes extremely small, and the light emitting element 40 is turned off. Note that the amplitude of the image signal data may be reduced by setting the potential of the image signal data supplied from the data line sig to the pixel to be turned off to the same potential as the common power supply line com.

  As described above, the low potential side potential of the image signal data is set high, and the high potential side potential of the image signal data for setting the pixel in a lighting state is set low. The potential falls within a range defined by the counter electrode op and the common power supply line com. Therefore, the driving voltage in the display device 1 can be reduced, and the power consumption of the display device 1 can be reduced.

[Embodiment 2]
FIG. 19 is an equivalent circuit diagram illustrating a pixel configuration of the display device 1 of the present embodiment.
20A and 20B are an explanatory diagram showing an electrical connection state of each element configured in each pixel and a waveform diagram showing a potential change such as a drive signal. As shown in FIGS. 19, 20A, and 20B, in this embodiment, the first TFT 20 is composed of an N-channel TFT, and the second TFT 30 is composed of a P-channel TFT. Since the second TFT 30 is a P-channel type, the image signal date on the low potential side is written from the data line sig to the storage capacitor cap of the pixel to be turned on, and the storage capacitor of the pixel to be turned off. In the cap, the image signal date on the high potential side is written. The gate voltage Vgcur of the second TFT 30 corresponds to the difference between the higher potential of the potential of the common power supply line com and the potential of the pixel electrode 30 and the potential of the potential holding electrode st.

  In the present embodiment, the potential of the common feed line com is made higher than the potential of the counter electrode op of the light emitting element 40, and the gate voltage Vgcur of the second TFT 30 is equal to the potential of the common feed line com and the potential holding electrode st. It is configured to correspond to the difference from the potential. Since the potential of the common power supply line com can be set to a sufficiently high value as compared with the pixel electrode 41, the on-current of the second TFT 30 is large and display can be performed with high luminance. In addition, since the potential of the potential holding electrode st at that time, that is, the potential on the low potential side of the image signal data can be increased, the amplitude of the image signal data can be reduced. In addition, since the on-current of the second TFT 30 is not directly affected by the potential of the counter electrode op, the potential on the low potential side of the image signal data for turning on the pixel is set to the potential of the counter electrode op. The amplitude of the image signal data is reduced by raising the potential to a higher or equal potential.

  Furthermore, in this embodiment, the image signal data potential supplied from the data line sig to the pixel to be turned off is set to a slightly lower potential or equal potential compared to the potential of the common power supply line com. The amplitude of data is reduced. Therefore, the potential of the image signal data is set within the range defined by the counter electrode op and the common power supply line com, and the drive voltage in the display device 1 is lowered, so that the power consumption of the display device 1 is reduced. The same effects as in the first embodiment or its modification can be obtained.

  In the present embodiment, since the first TFT 20 is an N-channel type and has a reverse conductivity type to the second TFT 30, the potential of the scanning line gate (scanning signal Sgate) when selecting a pixel is a high potential. The gate voltage Vgsw of the first TFT 20 at this time corresponds to the potential difference between the high potential of the scanning signal Sgate and the potential holding electrode st (the potential of the holding capacitor st, the potential of the gate electrode of the second TFT 30). . Here, since the second TFT 30 is a P-channel type, the image signal data for lighting the pixel 7 is on the low potential side, and the potential of the potential holding electrode st decreases during the selection period of the pixel 7. . Therefore, the gate voltage Vgsw of the first TFT 20 is shifted toward the increasing on-current.

  On the other hand, the gate voltage Vgcur of the second TFT 30 corresponds to the potential difference between the common power supply line com and the potential holding electrode st. When the selected pixel 7 is in the lighting state, the potential of the potential holding electrode st is set during the selection period. Since it tends to decrease, the gate voltage Vgcur of the second TFT 30 shifts toward an increase in on-current.

  Thus, in this embodiment, since the first TFT 20 and the second TFT 30 are of the reverse conductivity type, in order to increase the writing capability of the first TFT 20, the selection pulse height of the scanning signal Sgate is increased, In order to increase the luminance of the light emitting element 40, the image signal data is decreased in order to decrease the on-resistance of the second TFT 30. Such optimization with respect to the selection pulse height of the scanning signal Sgate and the image signal data is performed as the image signal data at a level for turning on the light emitting element 40 is written into the storage capacitor cap during the selection period of the pixel 7. This is effective for shifting the on-current of the TFT to the gate voltage of one TFT 20. Therefore, the image signal data is smoothly written from the data line sig to the storage capacitor cap via the first TFT 20.

  Here, the gate voltage Vgsw of the first TFT 20 when selecting the pixel 7 is the potential corresponding to the high potential of the scanning signal Sgate and the potential of the potential holding electrode st (the potential of the holding capacitor cap or the second TFT 30). The gate voltage Vgcur of the second TFT 30 corresponds to the difference between the potential of the common feeder line com and the potential of the potential holding electrode st, and the potential of the potential holding electrode st is used as a reference. In this case, the potential corresponding to the high potential of the scanning signal Sgate and the potential of the common power supply line com have the same polarity. Accordingly, if the potential of the potential holding electrode st is changed, both the gate voltage Vgsw of the first TFT 20 and the gate voltage Vgcur of the second TFT 30 are shifted by the same amount in the same direction.

  Therefore, the display operation speed can be increased by changing the potential of the image signal data for lighting within the range of the driving voltage range of the display device 1 in such a direction that the resistance when the first TFT 20 is on is reduced. At this time, since the potential of the image signal data for lighting is changed in a direction in which the resistance when the second TFT 30 is turned on becomes smaller, the luminance can be improved. Therefore, the drive voltage can be lowered and the display quality can be improved.

[Modification of Embodiment 2]
FIG. 21 is an equivalent circuit diagram showing a pixel configuration of the display device 1 of the present embodiment. FIGS. 22A and 22B are an explanatory diagram showing an electrical connection state of each element configured in each pixel and a waveform diagram showing a potential change such as a drive signal. In this embodiment, contrary to the second embodiment, the first TFT 20 is a P-channel type and the second TFT 30 is an N-channel TFT. However, in this embodiment, each element is driven and controlled based on the same technical idea as in the second embodiment, and the polarity of the drive signal described in the second embodiment is merely inverted. The configuration will be briefly described.

  As shown in FIGS. 21, 22A, and 22B, in the present embodiment, the second TFT 30 is an N-channel type as in the first embodiment, so that the data line sig is turned on. The high-potential-side image signal date is written to the storage capacitor cap of the power pixel, and the low-potential-side image signal date is written to the storage capacitor cap of the pixel to be turned off. Here, the gate voltage Vgcur of the second TFT 30 corresponds to the difference between the lower potential of the potential of the common feeder line com and the potential of the pixel electrode 30 and the potential of the potential holding electrode st. However, in this embodiment, since the potential of the common power supply line com is made lower than the potential of the counter electrode op of the light emitting element 40, the gate voltage Vgcur of the second TFT 30 is held at the potential of the common power supply line com. This corresponds to the difference from the potential of the electrode st. Since the potential of the common power supply line com can be set to a sufficiently low potential, the on-current of the second TFT 30 is large and display can be performed with high luminance. Alternatively, the amplitude of the image signal data can be reduced by increasing the potential of the potential holding electrode st at that time, that is, the potential on the high potential side of the image signal data, because the luminance is high. In addition, since the on-current of the second TFT 30 is not directly affected by the potential of the counter electrode op, the potential on the high potential side of the image signal data for turning on the pixel is set to the potential of the counter electrode op. The amplitude of the image signal data is reduced by lowering the potential to a lower potential or equipotential. Furthermore, in the present embodiment, the image signal data potential supplied from the data line sig to the pixel to be turned off is set to a slightly higher potential or equal potential compared to the potential of the common power supply line com. The amplitude of data is reduced. Therefore, the potential of the image signal data is kept within the range defined by the counter electrode op and the common feeder line com, and the drive voltage in the display device 1 is lowered, so that the power consumption of the display device 1 can be reduced. For example, the same effects as those of the first embodiment or its modification can be obtained.

  In the present embodiment, since the first TFT 20 is a P-channel type and has a conductivity type opposite to that of the second TFT 30, the potential of the scanning line gate (scanning signal Sgate) when selecting a pixel is a low potential. On the other hand, since the second TFT 30 is an N-channel type, the image signal data for lighting the pixel 7 is on the high potential side. Thus, in this embodiment, since the first TFT 20 and the second TFT 30 are of the reverse conductivity type, the potential of the selection pulse of the scanning signal Sgate is lowered in order to increase the writing capability of the first TFT 20. In order to increase the luminance of the light emitting element 40, the potential of the image signal data is lowered in order to reduce the on-resistance of the second TFT 30. Such optimization with respect to the selection pulse height of the scanning signal Sgate and the image signal data is performed as the image signal data at a level for turning on the light emitting element 40 is written into the storage capacitor cap during the selection period of the pixel 7. This is effective for shifting the on-current of the TFT to the gate voltage of one TFT 20.

Therefore, when the potential of the potential holding electrode st is used as a reference, the potential corresponding to the low potential of the scanning signal Sgate and the potential of the common power supply line com have the same polarity. Therefore, both the gate voltage Vgsw of the first TFT 20 and the gate voltage Vgcur of the second TFT 30 are shifted by the same amount in the same direction. Therefore, the display operation speed can be increased by changing the potential of the image signal data for lighting within the range of the driving voltage range of the display device 1 in such a direction that the resistance when the first TFT 20 is on is reduced. Can be planned. At this time, since the potential of the image signal data for lighting is changed in the direction in which the resistance when the second TFT 30 is turned on is reduced, the luminance can be improved. Therefore, similarly to the second embodiment, it is possible to achieve a reduction in driving voltage and an improvement in display quality.
In the second embodiment and the modification of the second embodiment, an optimal driving method will be described with reference to FIG.

  In Embodiment 2, the first TFT is an N-channel type, and the second TFT is a P-channel type. As shown in FIG. 25, when the light emitting element 40 is turned off, the potential of the image signal data is set higher than the potential of the common power supply line com to turn off the P-channel second TFT 30. In the present embodiment, as shown in FIG. 25, even when the light emitting element 40 is turned off, the second TFT 30 is not completely turned off. That is, in this embodiment, since the second TFT 30 is a P-channel type, in order to completely turn it off, the gate voltage Vgcur is set to 0 V (the same potential as the common power supply line com) or a positive potential (common supply). In this embodiment, the gate voltage Vgcur of the second TFT 30 is slightly higher than the level corresponding to the threshold voltage Vthp (cur) of this TFT. The potential when the image signal data is turned off is set low.

  Accordingly, the gate voltage applied to the second TFT 30 in the pixel 7 in the off state is the same as the polarity when the second TFT 30 is turned on, but the threshold voltage (Vthp of the second TFT 30). (cur)). For example, when the threshold voltage (Vthp (cur)) of the second TFT 30 is −4V, the gate voltage applied to the second TFT 30 in the unlit state is −3V.

As described above, when the first TFT is N-type and the second TFT is P-type, the amplitude of the image signal data can be reduced by setting the off-side potential of the image signal data lower than the conventional one. Can be reduced in voltage and frequency. Even when the off-side potential of the image signal data is set low in this way, the P-channel type second TFT 30 has a slightly higher potential than the level corresponding to the threshold voltage Vthp (cur). Therefore, the current that flows when the lamp is turned off is extremely small.
Further, if the voltage applied to the light emitting element 40 is low, only a very small driving current flows. Therefore, there is substantially no problem in turning off the light emitting element 40. In the present embodiment, the potential of the common power supply line com can be set relatively high unless the potential when the image signal data is turned off needs to exceed the potential of the common power supply line com.
Therefore, in this embodiment, the potential of the common power supply line com is set equal to the potential of the scanning signal Sgate when the first TFT 20 is turned on. Therefore, in the scanning side drive circuit, the signal level used as the high potential of the scanning signal Sgate may be supplied as it is to the common power supply line com. Therefore, in the display device 1 of the present embodiment, the number of levels of the driving signal to be used. The number of terminals for inputting drive signals to the display device 1 can be reduced. Further, since the number of power supplies can be reduced, the power consumption of the power supply circuit can be reduced and the space can be saved.

In this case, since the first TFT 20 is an N-channel type and the second TFT 30 is a P-channel type, the potential of the gate electrode applied to the second TFT 30 of the pixel 7 in the extinguished state is the first TFT 20. Is set to a potential lower than the potential obtained by subtracting the threshold voltage Vthn (sw) of the first TFT 20 from the potential of the scanning signal gate when turning on. That is, the absolute value of the potential difference Voff between the image signal data (potential of the potential holding electrode st) when the pixel 7 is turned off and the common power supply line com is expressed by the following formula Vthn (sw) <| Voff |
As shown in FIG. 6, it is only necessary to set the threshold voltage Vthn (sw) higher than the first TFT 20 to prevent troubles in the writing operation of the first TFT 20 when the pixel 7 is selected.

  In the case where the first TFT 20 of the modification of the second embodiment is a P-channel type and the second TFT 30 is an N-channel type, it will be described later with reference to FIGS. 26, 27A, and 27B. As described above, the polarities of the voltages applied to the first TFT 20 and the second TFT 30 are reversed by switching the relative levels of the signals described in this embodiment. Even in this case, if the second TFT 30 is not completely turned off when the light emitting element 40 is turned off as in the present embodiment, the voltage and frequency of the image signal data can be reduced. Further, the number of power supplies can be reduced by making the potential of the common power supply line com equal to the potential of the scanning signal Sgate when the first TFT 20 is turned on. In this case, the potential of the gate electrode applied to the second TFT 30 of the pixel 7 in the extinguished state is set so that the writing operation of the first TFT 20 when the pixel 7 is selected is not hindered. The potential is higher than the potential obtained by adding the threshold voltage Vthn (sw) of the first TFT 20 to the potential of the scanning signal gate when the TFT 20 is turned on.

[Embodiment 3]
In this embodiment, as shown in FIG. 23, an equivalent circuit thereof, as in the second embodiment, the first TFT 20 is an N-channel type and the second TFT 30 is a P-channel type in any pixel 7. It is an example. Also in the display device 1 according to the present embodiment, since the second TFT 30 is a P-channel type, the potential of the common power supply line com is set higher than the potential of the counter electrode op of the light emitting element 40. Therefore, when the second TFT 30 is turned on, a current flows from the common feeder line com to the light emitting element 40 as indicated by an arrow E.

  In addition, since it is the same as that of Embodiment 2, description is abbreviate | omitted about a common point and only a different point is described. Although the storage capacitor is provided in the second embodiment, the present embodiment is different in that there is no storage capacitor cap. With such a configuration, the change in potential of the holding electrode st can be increased.

  When the first TFT 20 is a P-channel type and the second TFT 30 is an N-channel type, as will be described later with reference to FIGS. 26, 27A, and 27B, The polarity of the voltage applied to the first TFT 20 or the second TFT 30 is inverted by switching the relative levels of the signals described. Even in this case, the potential of the selection pulse of the scanning signal is lowered in order to increase the writing capability of the first TFT 20, and the potential of the image signal is increased in order to increase the light emission luminance by lowering the on-resistance of the second TFT 30. It will be.

[Modification of Embodiment 3]
In Embodiment 3 described above, in any pixel 7, the first TFT 20 is an N-channel type and the second TFT 30 is a P-channel type. However, as shown in FIG. 26, an equivalent circuit is shown. The first TFT 20 may be a P-channel type, and the second TFT 30 may be an N-channel type. In the example shown in this figure, when the potential of the common feeder line com is lowered with respect to the potential of the counter electrode op of the light emitting element 40 and the second TFT 30 is turned on, as shown by an arrow F, light emission is performed. A current flows from the counter electrode op of the element 40 to the common power supply line com.

  When the pixel 7 is configured in this way, as shown in FIGS. 27A and 27B, the polarity of each drive signal having the waveform shown in FIG. 24A is inverted. In the third embodiment, when the first TFT 20 is an N-channel type and the second TFT 30 is a P-channel type, the potential of the common power supply line com is set lower than the potential of the counter electrode op of the light emitting element 40. When the second TFT 30 is turned on, the current may flow from the counter electrode op of the light emitting element 40 to the common power supply line com. However, the effect of having the first TFT 20 and the second TFT 30 of the reverse conductivity type can be obtained. On the contrary, when the first TFT 20 is a P-channel type and the second TFT 30 is an N-channel type, the potential of the common feeder line com is made higher than the potential of the counter electrode op of the light emitting element 40, When the second TFT 30 is turned on, the first TFT 20 and the second TFT 30 are made to have the reverse conductivity type even when the current flows from the common feeder line com to the light emitting element 40. You can get that effect.

[Embodiment 4]
In any of the first, second, and third embodiments, as described with reference to FIGS. 28A and 28B, the gate electrode of the second TFT 30 is electrically connected to both electrodes of the storage capacitor cap. The electrode on the side opposite to the electrode connected to may be configured to be supplied with a pulse whose potential swings in the direction opposite to that of the selection pulse delayed from the selection pulse of the scanning signal gate.

  In the example shown here, as shown in FIG. 28A, of the two electrodes of the storage capacitor cap, the side opposite to the electrode electrically connected to the gate electrode of the second TFT 30 via the potential holding electrode st. These electrodes are constituted by a capacitance line “cline” extending in parallel with the scanning line “gate”.

  As shown in FIG. 28B, the capacitance line cline is supplied with a potential stg including a pulse signal Pstg that is delayed from the selection pulse Pgate of the scanning signal Sgate and whose potential swings in the opposite direction to the selection pulse Pgate. It is comprised so that. The pulse signal Pstg shifts the potential of the image signal data by using the capacitive coupling of the storage capacitor cap after the selection pulse Pgate is not selected. Therefore, a signal corresponding to the potential of the image signal data added to the potential of the pulse signal Pstg is held in the holding capacitor cap in which the pixel 7 is turned off. A signal on the high potential side of the image signal data has a high on-resistance of the first TFT 20, and thus it is difficult to sufficiently perform writing in a limited time. In this example, if the writing is not sufficient, it cannot be lit. However, by using the example of this embodiment, writing of the image signal data to the storage capacitor cap can be supplemented. Nevertheless, the maximum range of the potential of the drive signal does not expand.

  In this way, when the pulse signal Pstg is put on the capacitor line cline, as shown in FIG. 29, the capacitor line cline is pulled out from the scanning side drive circuit 4, and in the scanning side drive circuit 4, any gate stage In addition, the output signal from the shift register 401 is output as a scanning signal Sgate to the scanning line gate via a NAND gate circuit and an inverter, while the output signal from the shift register 401 is delayed via a NAND gate circuit and a two-stage inverter. However, as shown in FIG. 30, the power level on the high potential side may be shifted from Vdd to the potential Vccy and output to the capacitor line cline.

  In the above-described embodiments and their modifications, the description has been given of the type of light emitting element provided with the capacitor line cline when the storage capacitor is added. However, the present embodiment is not limited to the configuration in which the capacitor line cline is provided, and one electrode of the storage capacitor may be configured by an adjacent gate line. FIG. 34A shows an example of such a structure, and FIG. 34B shows a voltage waveform of the gate electrode with respect to the scanning direction of the gate line. In this manner, by forming the adjacent gate line as one electrode of the storage capacitor for the pixel, there is an effect that it is not necessary to provide the capacitor line cline.

[Other embodiments]
In any of the above-described embodiments, the region in which the current-voltage characteristics of the second TFT 30 are operated is not described. However, if the second TFT 30 is operated in the saturation region, the TFT is weakly defined. It is possible to prevent an abnormal current from flowing through the light emitting element 40 using current characteristics. For example, a pinhole defect may occur in the organic semiconductor film or the like constituting the light emitting element 40. Even in this case, the current flowing through the defective light emitting element is limited, and a complete short circuit between the electrodes of the light emitting element 40 occurs. Never become.

  On the other hand, if the second TFT 30 is operated in the linear region, it is possible to prevent the variation in threshold voltage from affecting the display operation. The TFT structure is not limited to the top gate type, and may be a bottom gate type, and the manufacturing method is not limited to the low temperature process.

(Applicability of invention)
As described above, in the above display device, the gate voltage when the second TFT is turned on is one of the potential of the common power supply line and the potential of the pixel electrode, and the potential of the gate electrode (the image signal). Therefore, according to the conductivity type of the second TFT, the relative level between the potential of the common power supply line and the potential of the counter electrode of the light emitting element is set to determine the gate of the second TFT. The voltage is configured to correspond to the difference between the potential of the common power supply line and the potential of the potential holding electrode. For example, if the second TFT is an N-channel type, the potential of the common power supply line is set lower than the potential of the counter electrode of the light emitting element. The potential of the common power supply line can be set to a sufficiently low value unlike the potential of the pixel electrode, so that a large on-current can be obtained by the second TFT and display can be performed with high luminance. it can. Further, when the pixel is turned on, if the high gate voltage of the second TFT can be obtained, the potential of the image signal at that time can be lowered accordingly, so that the amplitude of the image signal is reduced. In addition, the driving voltage in the display device can be lowered. Therefore, there is an advantage that the power consumption can be reduced and the problem of withstand voltage, which has been a concern for each element composed of a thin film, does not become apparent.

  In the display device of the present invention, since the first TFT and the second TFT are of the reverse conductivity type, a pulse of a scanning signal for selecting a pixel and an image signal for lighting a light emitting element It is in a relationship that is opposite to the potential of. Therefore, when the potential of the potential holding electrode at the time of lighting (the potential of the image signal for lighting) is used as a reference, the potential corresponding to the high potential of the scanning signal and the potential of the common power supply line have the same polarity. If the potential of the potential holding electrode (the potential of the image signal for lighting) is changed, both the gate voltage of the first TFT and the gate voltage of the second TFT are shifted by the same amount in the same direction. . Therefore, the display operation speed can be increased by shifting the potential of the image signal for lighting in the range of the driving voltage range of the display device in a direction in which the resistance when the first TFT is turned on is reduced. In addition, at this time, the potential of the image signal for lighting is shifted in the direction in which the resistance when the second TFT is turned on is reduced, so that the luminance can be improved. Therefore, the drive voltage can be lowered and the display quality can be improved.

  Further, in the above display device, of the two electrodes of the storage capacitor, the electrode opposite to the electrode electrically connected to the second gate electrode of the second TFT is delayed from the selection pulse of the scanning signal. Thus, since a pulse whose potential is reversed in the direction opposite to the selection pulse is supplied, writing of the image signal to the storage capacitor can be supplemented. Therefore, the potential of the image signal applied to the gate electrode of the second TFT can be shifted in the direction of increasing brightness without increasing the amplitude of the image signal.

It is a top view which shows typically the display apparatus to which this invention is applied. It is a block diagram which shows the basic composition of the display apparatus to which this invention is applied. It is a top view which expands and shows the pixel of the display apparatus shown in FIG. It is sectional drawing in the AA 'line of FIG. It is sectional drawing in the BB 'line | wire of FIG. 6A is a cross-sectional view taken along the line CC ′ of FIG. 3, and FIG. 6B is an explanatory diagram for explaining an effect obtained when the structure shown in FIG. 6A is configured. 7A and 7B are cross-sectional views of light-emitting elements used for the display device illustrated in FIG. 8A and 8B are cross-sectional views of light-emitting elements each having a structure different from that of the light-emitting element illustrated in FIG. FIG. 9 is a graph showing current-voltage characteristics of the light-emitting elements shown in FIGS. 7 (A) and 8 (B). FIG. 9 is a graph illustrating current-voltage characteristics of the light-emitting element illustrated in FIGS. 7B and 8A. It is a graph which shows the current-voltage characteristic of N channel type TFT. It is a graph which shows the current-voltage characteristic of P channel type TFT. It is process sectional drawing which shows the manufacturing method of the display apparatus to which this invention is applied. FIGS. 14A and 14B are a plan view and a cross-sectional view, respectively, of a pixel having a different structure from the pixel of the display device illustrated in FIGS. 2 is an equivalent circuit diagram illustrating a pixel configuration of the display device according to Embodiment 1 of the present invention. FIG. FIGS. 16A and 16B are an explanatory diagram illustrating an electrical connection state of each element included in the pixel illustrated in FIG. 15 and a waveform diagram illustrating a potential change such as a drive signal. It is an equivalent circuit diagram which shows the pixel structure of the display apparatus which concerns on the modification of Embodiment 1 of this invention. 18A and 18B are an explanatory diagram illustrating an electrical connection state of each element included in the pixel illustrated in FIG. 17 and a waveform diagram illustrating a potential change such as a drive signal. FIG. 5 is an equivalent circuit diagram showing a pixel configuration of a display device according to Embodiment 2 of the present invention. 20A and 20B are an explanatory diagram illustrating an electrical connection state of each element included in the pixel illustrated in FIG. 19 and a waveform diagram illustrating a potential change such as a drive signal. It is an equivalent circuit diagram which shows the pixel structure of the display apparatus which concerns on the modification of Embodiment 2 of this invention. 22A and 22B are an explanatory diagram illustrating an electrical connection state of each element included in the pixel illustrated in FIG. 21 and a waveform diagram illustrating a change in potential of a drive signal or the like. It is an equivalent circuit diagram which shows the pixel structure of the display apparatus which concerns on Embodiment 3 of this invention. FIGS. 24A and 24B are waveform diagrams of signals for driving the pixels shown in FIG. 23, and are explanatory diagrams showing correspondence between these signals and equivalent circuits. It is a wave form diagram of the signal for driving the pixel of the display apparatus which concerns on Embodiment 2 of this invention. It is an equivalent circuit diagram which shows the pixel structure of the display apparatus which concerns on the modification of Embodiment 3 of this invention. 27A and 27B are waveform diagrams of signals for driving the pixels shown in FIG. 26, and are explanatory diagrams showing correspondence between these signals and equivalent circuits. FIGS. 28A and 28B are an equivalent circuit diagram of a pixel of a display device according to Embodiment 4 of the present invention and a waveform diagram of a signal for driving the pixel. FIG. 29 is a block diagram of a scanning side drive circuit for generating the signal shown in FIG. 28. It is a wave form diagram of each signal output from the scanning side drive circuit shown in FIG. It is a block diagram of a display apparatus. FIG. 32 is an equivalent circuit diagram showing a conventional pixel configuration in the display device shown in FIG. 31. 33A and 33B are waveform diagrams of signals for driving the pixels shown in FIG. 32, and are explanatory diagrams showing correspondence between these signals and equivalent circuits. 34A and 34B are a block diagram of a structure in which a capacitor is formed using adjacent gate lines and a signal waveform of the gate voltage, respectively.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Display apparatus 2 Display part 3 Data side drive circuit 4 Scan side drive circuit 5 Inspection circuit 6 Mounting pad 7 Pixel 10 Transparent substrate 20 1st TFT
21 Gate electrode 30 of the first TFT Second TFT
31 Gate electrode 40 of second TFT Light emitting element 41 Pixel electrode 42 Hole injection layer 43 Organic semiconductor film 50 Gate insulating film bank Bank layer cap Retention capacitor line Capacitor line com Common feed line gate Scan line op Counter electrode sig Data line st Potential holding electrode

Claims (3)

A light emitting device in which a transistor is arranged corresponding to a scanning line, a data line, and an intersection of the scanning line and the data line,
A first electrode formed above the transistor formed on a substrate;
A relay electrode connecting the transistor and the first electrode;
A second electrode formed above the first electrode;
An interlayer insulating film covering the data line and the transistor;
A bank layer disposed above the interlayer insulating film and in a region where the first electrode and the relay electrode overlap in plan view;
A light emitting device disposed inside the bank layer and in a layer between the first electrode and the second electrode;
The light emitting element is disposed in a region where the first electrode and the relay electrode overlap in a plan view and a region in which both of the transistors do not overlap in a plan view,
The light emitted from the light emitting element is emitted through the first electrode;
A light emitting device characterized by the above.   The light emitting device according to claim 1, wherein the light emitting element includes an organic thin film layer and a hole injection layer.   The light-emitting device according to claim 1, wherein the transistor is a P-channel type.

Images